JP2537549B2 - Dialer - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dialer which is built into a telephone and controls dialing of the telephone, and more particularly to a dialer for regulating specific dialing.

[Prior Art] In recent years, semiconductor technology has made dramatic progress, and ICs and LSIs have been used in various devices to achieve multi-functionality. Telephones are not an exception, and a dialer that controls the dialing of a telephone by incorporating an IC makes it possible, for example, to call one telephone number from a plurality of pre-stored telephone numbers and dial it. There is.

Hereinafter, the configuration and operation of the conventional dialer will be described with reference to FIG.

FIG. 5 is a block diagram of a conventional dialer 5,
When the telephone operator operates the keyboard 22, the keyboard interface 10 outputs a dial signal to the system controller 12 according to this dialing. The system controller 12 includes a PLA (programmable logic array) that determines whether or not the transmitted dial signal is valid, a key sequence data latch that encodes and holds the dial signal together with the dialing order, and key sequence data for each block. It consists of an instruction decoder that outputs to the keyboard interface
The dial signal from 10 is determined by the system controller 12 whether it is valid, and if it is valid, the memory 14
Is output to

The dial data input to the memory 14 is sent to each output circuit as dial data corresponding to a predetermined telephone number under the control of the system controller 12. As the output circuit, a DTMF generator 16 that sends a DTMF (Dual Tone Multi Frequency) signal to the telephone line and a pulse generator 18 that sends a dialing pulse to the telephone line are used. Either one is selected by the output controller 20 to achieve the desired dialing. A corresponding signal can be transmitted from the telephone line.

[Problems to be Solved by the Invention] However, it may be necessary to regulate certain dialing depending on the usage of the telephone. For example, if there are a large number of specified users other than the owners who are subscribers in the subscriber telephone, if one example is given, the employee starts dialing at zero at the beginning of the dialing at a business operator having migrant workers from afar. It is possible to make high-priced international calls and long-distance calls freely, so that the owner of the telephone may have a desire to regulate the leading zero dialing in order to avoid accidentally high telephone charges.

However, the conventional dialer has the above-mentioned configuration, and the configuration that regulates a certain specific dialing is not adopted, and there is a problem that the above-mentioned leading zero transmission regulation must be left to the self-restraint of the subscriber. there were.

Of course, even in the conventional dialer, it is possible to apply a predetermined program to the PLA in the system controller to regulate the leading zero transmission, but the user, that is, the owner of the telephone, can easily allow the leading zero transmission or enter the regulation mode. Difficult to set and impractical.

The present invention has been made in view of the above conventional problems,
An object of the present invention is to provide a dialer capable of restricting a predetermined head transmission of dialing, for example, zero transmission with a simple configuration.

[Means for Solving the Problem] In order to achieve the above object, the present invention includes a keyboard interface, a system controller, a memory, a DTMF generator, a pulse generator, an output controller, and a head transmission regulating means. A dialer built into a telephone equipped with the system controller, wherein the system controller has a data latch circuit for presetting a predetermined initial value and latching a dial signal from the keyboard interface. And a system controller, and has a first logic gate, a second logic gate, and a third logic gate. The first logic gate inputs the first data signal from the data latch circuit of the system controller, and outputs the data. If the signal is the initial value, The second logic gate inputs the dial signal from the keyboard interface, outputs the recognition signal indicating that the dial signal is a predetermined signal, and outputs the third logic signal. The gate is a data latch when the latch trigger signal from the keyboard interface, the regulation mode signal from the mode changeover switch, the head detection signal from the first logic gate, and the recognition signal from the second logic gate are input. When the latch trigger signal output to the circuit is prohibited and the dialing start value is the specified signal and the mode changeover switch is in the regulation mode, the dial signal of the data latch circuit is prohibited from latching and the specified dialing start number is set. It is characterized by restricting outgoing calls.

[Operation] That is, the head detecting means detects whether or not the key sequence data signal held in the key sequence data latch of the system controller is the head of dialing.

The head detection signal from the head detection means is input to the head transmission regulation means together with the dial data from the keyboard interface.

The head transmission control means has a first logic gate, a second logic gate, and a third logic gate. The first logic gate detects that it is the head of dialing, and the second logic gate detects that dialing is being performed. It detects that it is a predetermined number.
Then, the third logic gate inputs the signals from the first and second logic gates and further inputs the signal from the external mode changeover switch, and the dialing head has a predetermined number and the mode is the regulation mode. Only when, the output of the latch trigger signal from the keyboard interface to the data latch circuit is prohibited. As a result, it is possible to prohibit the transmission of a predetermined leading number for dialing.

[Embodiment] Hereinafter, a preferred embodiment of a head transmission restriction dialer according to the present invention will be described with reference to the drawings by taking a case where head zero transmission is restricted as an example.

FIG. 1 shows a configuration block diagram of the embodiment. The keyboard interface 10 is a key data decoder 10a that outputs a dial signal corresponding to dialing.
And a debounce counter 10b for preventing chattering, and a key data decoder when the keyboard 22 is operated.
Dial data 100 from 10a is system controller 12
It is output to PLA (programmable logic array) 12a.

The PLA 12a judges whether or not the transmitted dial signal is valid, for example, whether or not the dial signal at the head of the dialing is a numeric keypad signal, and includes the dialing sequence information.
Key sequence data latch 1 as digitized binary signal 102
Sent to 2b.

The characteristic of this embodiment is that the conventional keyboard interface 10 and system controller 12 are
In between, one end is "Hi level" for permitting transmission of leading zero,
Two-terminal mode changeover switch 24 whose other end is a "Low level" for controlling leading zero transmission, and leading detecting means for detecting that the key sequence data signal 114 from the key sequence data latch 12b is the beginning of dialing. As a first OR gate 26c and a NAND gate 26b for extracting the zero of the dial data 100 from the key data decoder 10a.
And a zero signal judged by the NAND gate 26b as zero from the switching signal 104 from the mode changeover switch 24, the head signal 106 from the first OR gate 26c, and the dial data 100 from the key data decoder 10a in the keyboard interface 10. The second OR gate 26a to which the signal 112 is input, and the debounce signal 108 from the second OR gate 26a and the debounce counter 10b in the keyboard interface 10 are input.
A new AND gate 26d is added to the system controller 12
The key sequence data latch 12b is controlled. The first OR gate 26c functions as a first logic gate, the NAND gate 26b functions as a second logic gate, and the second
The OR gate 26a and the AND gate 26d will function as the third logic gate. Further, in this embodiment, the debounce signal 108 from the keyboard interface 10 functions as a latch trigger signal, and the transmission of this latch trigger signal to the key sequence data latch 12b is controlled to prohibit the transmission of a predetermined leading number.

The operation of this embodiment will be described below with reference to the timing charts of FIG. 2, FIG. 3 and FIG.

In Fig. 2, the mode selector switch 24 is on the "Low level" side,
That is, it shows a timing chart of each signal in the leading zero transmission restriction mode, and at this time, the switching signal
104 is "restricted", that is, at a low level, as shown in FIG. When the dial zero key is operated in this state, the dial data 100 changes from the Hi level to the Low level in response to the zero key, and the zero recognition signal 112 output from the NAND gate 26b is changed as shown in FIG. 2 (B). Hi
The level changes from the low level to the low level, and after the elapse of the prescribed debounce time, the debounce signal 108 is generated as shown in FIG. 2 (A). On the other hand, since the initial value of the key sequence data 114 output from the key sequence data latch is set to “0” in advance, the head detection signal output from the first OR gate 26c is output.
106 becomes Low level as shown in FIG. 2 (D). Here, when the dial signal 100 is not the head of dialing, all 6 digits of the key sequence data 114 are not "0", and therefore the head detection signal from the first OR gate 26c is
It becomes Hi level, and it is possible to judge whether it is the beginning or not.

Zero press determination signal 112, switching signal 104 and head detection signal
When 106 is input to the second OR gate 26a of the head transmission regulation means 26, all the signals are at the low level, so the regulation signal 116 which is the output thereof is at the low level as shown in FIG. 2 (E). AND gate 26d keeps the above-mentioned debounce signal 10
8 is prevented from being transmitted to the sequence data latch 12b, the latch timing signal 110 shown in FIG.
Latch trigger does not occur at ow. Therefore, the key sequence data does not change and the leading zero transmission is restricted.

FIG. 3 shows a timing chart of each signal when the zero transmission is input second, for example, not at the beginning of dialing. At this time, the head detection signal 106 from the first OR gate 26c is the key sequence data signal 114 as described above.
Since all 6 digits of the above are not "0", they become Hi level as shown in FIG. 3 (D).

Then, when the dial data 100, the switching signal 104, and the head detection signal 106 are input to the second OR gate 26a of the head transmission restricting means 26, the output of the restriction signal 116 is as shown in FIG. 2 (E). Hi level. Therefore AND gate 2
6d is the sequence data latch 1 for the debounce signal 108 described above.
2b, and a latch trigger is generated in the latch timing signal 110 shown in FIG. 3 (F).
Then, this pulse is input to the key sequence data latch 12b as a trigger, and the key sequence data latch 1
Since the key sequence data is input to the instruction decoder 12c from 2b, the second zero transmission is possible.

Next, FIG. 4 shows a timing chart of each signal when the mode changeover switch 24 is set to the power supply terminal side, that is, the leading zero transmission permission mode. At this time, the switching signal 104 is "permitted", that is, at the Hi level, as shown in FIG. When the zero key on the dial is operated in this state, the mode change switch 24 causes the zero recognition signal 1 which is the output of the NAND gate 26b, as in the case of the leading zero oscillation regulation mode.
12 changes from the Hi level to the Low level as shown in FIG. 4 (B), the debounce signal 108 is generated as shown in FIG. 4 (A), and the head detection signal 106 output from the first OR gate 26c is Although it becomes Low level as shown in FIG. 4 (D), since the switching signal 104 is at Hi level by the mode selector switch 24, as shown in FIG. 4 (F), the regulation signal 116 which is the output of the second OR gate 26a. Becomes Hi level. Therefore NAND gate 26d
Is the sequence data latch 12b which is the aforementioned debounce signal 108.
Then, the latch trigger is generated in the latch timing signal 110 shown in FIG. 4 (F). Then, this pulse is input to the key sequence data latch 12b as a trigger, and the key sequence data latch 12b
Since the key sequence data signal is input from the instruction decoder 12c to the instruction decoder 12c, the leading zero can be transmitted.

As described above, the present invention provides a heading detection means for dialing,
A permission / restriction mode changeover switch and a leading transmission regulation means are newly provided, and by skillfully controlling the key sequence data latch of the system controller, it is possible to easily regulate or permit transmission of a prescribed leading number. Needless to say, when the changeover switch is set to the permission mode, it has the same function as a conventional dialer.

It is also possible to use a switch with a key as the mode changeover switch, or to take the mode changeover switch itself into the inside of the telephone so that it cannot be freely changed by anyone other than the owner of the telephone.

Further, in the present embodiment, the OR gate, the AND gate and the NAND gate are used for the head detecting means and the head transmission restricting means, but of course the invention is not limited to this, and for example,
A combination of AND gate and NOT gate is also possible.

Further, in the present embodiment, the case where the leading zero transmission is restricted has been exemplified, but the present invention is not limited to this, and can be applied to any leading number restriction.

[Advantages of the Invention] As described above, according to the head transmission restriction dialer according to the present invention, it is possible to restrict the predetermined head transmission of dialing with a simple configuration.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of a dialer according to the present invention, FIGS. 2, 3, and 4 are timing charts of the dialer according to the present invention, and FIG. 5 is a block diagram of a conventional dialer. is there. 10 …… Keyboard interface 12 …… System controller 22 …… Keyboard 24 …… Changeover switch 26 …… First transmission restriction means 26a …… Second OR gate 26b …… NAND gate 26c …… First OR gate 26d …… AND gate

 ─────────────────────────────────────────────────── ─── Continuation of the front page (56) Reference JP-A-64-25643 (JP, A) JP-A-56-89160 (JP, A) Practical application Sho-57-113565 (JP, U)

Claims (1)

(57) [Claims] 1. A keyboard interface (10), a system controller (12), a memory (14), a DTMF generator (16), a pulse generator (18), an output controller (20), and a head transmission control means. (26) is a dialer built in a telephone set including: a system controller (12), which has a predetermined initial value set in advance and which latches a dial signal from the keyboard interface (10) ( 12b), the head transmission control means (26) is connected to the keyboard interface (10) and the system controller (12),
First logic gate (26c), second logic gate (26b) and third
A first logic gate (26c) has a logic gate (26e) and a system controller (1
The head data signal is input from the data latch circuit (12b) of 2), and when the data signal is the initial value, the head detection signal indicating that the predetermined value is output is output, and the second logic The gate (26b) inputs the dial signal from the keyboard interface (10) and outputs a recognition signal to that effect when the dial signal is a predetermined signal, and the third logic gate (26e) is the keyboard interface. The latch trigger signal (108) from (10), the regulation mode signal from the mode changeover switch (24), the head detection signal from the first logic gate (26c), and the second logic gate (2
When the recognition signal from 6b) is input, the latch trigger signal (108) is prohibited from being output to the data latch circuit (12b), the dialing start value is a predetermined signal, and the mode switch (24) is regulated. In the mode, a dialer that prohibits the dial latching of the data latch circuit (12b) and restricts the dialing of the specified leading number.