JP2537180B2 - Method for manufacturing semiconductor device - Google Patents

Description

Description: TECHNICAL FIELD OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device, and more particularly to an ion implantation method.

[Technical Background of the Invention] Recently, in manufacturing a semiconductor device, an ion implantation method has been mainly used when impurities are to be introduced into a semiconductor substrate with precision.

When impurities are introduced into a semiconductor substrate by an ion implantation method, if ion implantation is performed in parallel with the atomic sequence of the substrate (that is, perpendicular to the substrate surface having a plane orientation index <100>), so-called channeling phenomenon occurs and ions are A deep source / drain junction is formed in the case of a MOS structure, etc. as a result of being deeply implanted into the substrate, but a deep source / drain junction causes a short channel effect and a large parasitic capacitance. This is an obstacle to increasing the density and speed of the device. Therefore, it is necessary to make the source / drain junction shallow in order to enable a high-density integrated circuit.
In order to make this possible, it is necessary to tilt the ion implantation direction with respect to the crystal axis so as not to cause the channeling phenomenon in the ion implantation process (G. Dearnaley et al.
al.: Can. J. Phys. 46 (1968) p587).

Therefore, conventionally, when performing ion implantation into a semiconductor substrate in the process of manufacturing a semiconductor device, the ion implantation is performed at an incident angle which is inclined by about 8 ° with respect to the normal direction of the substrate surface. In this case, as is well known, a resist film having a thickness of 1 μm or more is formed on a semiconductor substrate according to the acceleration voltage of ions, and a mask is formed by selectively opening the resist film, The tilted ion beam is scanned over the entire surface of the substrate to implant impurity ions into the substrate in the opening.

FIG. 2 shows such a conventional ion implantation method. In FIG. 2, 1 is a semiconductor substrate, 2 is a resist film, 2a is an opening formed in the resist film, and 3 is an ion beam. The ion beam 3 is applied at an incident angle which is inclined by about 8 ° ± 3 ° with respect to the normal line direction of the substrate surface.

As a method of scanning the tilted ion beam on the surface of the semiconductor substrate, a method of electrostatically scanning the ion beam with the semiconductor substrate stationary, and a method of scanning the semiconductor substrate with the tilted ion beam stationary One of the methods of scanning by moving the one up, down, left, and right has been implemented.

[Problems of the Background Art] However, according to the conventional ion beam irradiation method, as is apparent from FIG. 2, a shadowed portion is generated due to the opening edge of the resist, and therefore, after the ion implantation step is completed, In the resist opening 2a, as shown in FIG. 2B, an ion non-implanted region 5 is formed adjacent to the ion implanted region 4.

Conventionally, when the cell size of the device is also considerably large according to the design rule, even if the ion non-implanted region 5 exists in the ion implantation opening, the non-implanted region may not deteriorate the electrical characteristics of the device. It could be ignored because it was scarcely present, but the width W of one side of the ion implantation opening (resist opening 2a) has been reduced to about 1 μm due to the recent progress in miniaturization of integrated circuits. The existence of such an ion non-implanted region 5 cannot be ignored because it adversely affects the device electrical characteristics such as the threshold voltage of the device. For example, if the resist film thickness is 1.5 μm
In this case, the width w of one side of the non-ion-implanted region 5 is w = 1.5 μm × tan8 ° = 2100Å, and the width W of one side of the resist opening 2a is 1 μm, as is clear from FIG. Since the area of the non-implanted region 5 reaches a little over 20% of the total area of the opening 2a, it cannot be ignored.

In particular, as shown in FIG. 3, exactly the same elements 6 and 7
Are arranged on the substrate in directions perpendicular to each other and the distances d between them are close to each other by about 10 μm, the shapes of the ion non-implanted regions 6a and 7a of both are also different, so that the electrical conductivity of both There is a big difference in the characteristic characteristics, and in order to use them as elements with the same characteristics, it is necessary to precisely control the threshold voltage of both elements, which is very important for circuit design and element formation. Will be complicated.

[Object of the Invention] An object of the present invention is to provide an improved semiconductor device manufacturing method which does not cause the above problems. More specifically, an object of the present invention is to provide an ion implantation method that does not cause an impurity non-implanted region in the impurity introduction opening in the ion implantation step.

SUMMARY OF THE INVENTION According to the present invention, first, an ion beam tilted at a predetermined angle with respect to a crystal axis of a semiconductor substrate is scanned on a surface of the semiconductor substrate, and then the semiconductor substrate is substantially rotated about its axis.
Rotate each by 90 ° by 180 °, 180 °, 270 °, and sequentially incline the region at which ion implantation was performed by the previous scan and the adjacent region shaded by the previous scan at an equal dose amount. It is characterized in that the ion beam is scanned four times or more. As described above, according to the method of the present invention in which an equal dose is injected by rotating by 90 °, the dose of the shadowed area along each side of the opening is no matter which direction the pattern shape is oriented. All the doses are 3/4 or more of the central non-shadowed area, and a constant ion implantation concentration distribution can be obtained for patterns oriented in any direction, giving constant electrical characteristics to each semiconductor element. You can Thus, the element characteristics do not depend on the layout (direction) of the pattern, so that the degree of freedom in circuit design and element formation is increased.

Embodiment of the Invention FIG. 1 shows an embodiment of the method of the present invention.

In this embodiment, after the resist film 2 is formed on the surface of the semiconductor substrate 1, two resist films 2 are formed at right angles to each other.
A plurality of resist openings 2a having the same area are formed, and the ion beam 3 is irradiated into the resist opening 2a from a direction inclined by 8 ° with respect to the normal line of the substrate 1, and the ion beam 3 is applied to the surface of the semiconductor substrate 1. The whole surface was scanned along. The ion current was set so that the dose amount at this time was 0.25 × 10 ¹³ cm ^-2 .

Next, the semiconductor substrate 1 is rotated by 90 ° about its central axis in a plane, and then the ion current is set so that the same dose amount is obtained again, so that the ion beam 3 is entirely spread along the surface of the semiconductor substrate 1. Scanned.

Then, the above operation in the 90 ° rotation is performed even when the semiconductor substrate is rotated by 180 ° and 270 ° from the initial position of the semiconductor substrate, and two ion implantation regions 8 having different directions are formed as shown in FIG. 1 (b). And 9 were formed in the semiconductor substrate 1.
When the ion concentration in the region was examined, it was found that in each region 8 and 9, a predetermined dose amount (1 × 10 ¹³ cm
^-2 ) regions 8a and 9a are formed while each region 8 and 9a
Along the outer peripheral edge of the regions 8b and 9 having a dose amount (0.75 × 10 ¹³ cm ⁻² ) lower than a predetermined dose amount (3/4 in this embodiment).
It was confirmed that b was formed, and no ion non-implanted region was not formed in each of the regions 8 and 9.

[Effects of the Invention] As described above, according to the method of the present invention, since an ion non-implanted region is not generated in the ion implantation planned region in the ion implantation step, an element having excellent electrical characteristics can be obtained. It is possible to manufacture a high-density semiconductor device integrated with high density. Further, as shown in FIG. 1 (b), the ion-implanted region formed by the method of the present invention has the same impurity distribution in all directions, so that the same element is formed regardless of the orientation of the element on the semiconductor substrate. Since they have the same characteristics, the difficulty and complexity in circuit design and element formation are eliminated as a result.

In the embodiment, only the case where the semiconductor substrate is sequentially rotated by 90 ° is shown, but how to change the posture of the semiconductor substrate on the plane is not limited to the case of the embodiment. Further, it goes without saying that the scanning method may be either a method of electrostatically scanning an ion beam or a method of moving a semiconductor substrate for scanning.

[Brief description of drawings]

FIG. 1 (a) is a diagram showing a case where ions are implanted into a semiconductor substrate by the method of the present invention, and FIG. 1 (b) is a plane of an ion implantation region formed in the state shown in FIG. 1 (a). FIG. 2, FIG. 3 and FIG. 3 are views showing a state in which an ion non-implanted region is generated when ions are implanted by a conventional method, and FIGS. 2 (a) and 3 (a) are semiconductor substrates. 2B and 3B are plan views of the semiconductor substrate after ion implantation. 1 ... semiconductor substrate, 2 ... resist film, 2a ... opening, 3
…… Ion beam, 4 …… Ion implantation area, 5 …… Ion non-implantation area, 6,7 …… Element, 6a, 7a …… Ion non-implantation area, 8,9 …… Ion implantation area.

Claims (1)

(57) [Claims] 1. A method of manufacturing a semiconductor device by ion-implanting impurities into a semiconductor substrate, comprising scanning an ion beam tilted at a predetermined angle with respect to a crystal axis of the semiconductor substrate, and then scanning the surface of the semiconductor substrate. The semiconductor substrate is rotated substantially 90 ° about its axis, and an ion beam of equal dose at least four times is sequentially applied to the region where the ion implantation was performed by the previous scan and its adjacent region. A method for manufacturing a semiconductor device, which comprises scanning in a stack.