JP2536652B2 - Printed circuit board for SRAM - Google Patents
Printed circuit board for SRAMInfo
- Publication number
- JP2536652B2 JP2536652B2 JP2047879A JP4787990A JP2536652B2 JP 2536652 B2 JP2536652 B2 JP 2536652B2 JP 2047879 A JP2047879 A JP 2047879A JP 4787990 A JP4787990 A JP 4787990A JP 2536652 B2 JP2536652 B2 JP 2536652B2
- Authority
- JP
- Japan
- Prior art keywords
- sram
- terminal hole
- terminal
- capacity
- capacity sram
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0286—Programmable, customizable or modifiable circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
Landscapes
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Structure Of Printed Boards (AREA)
Description
【発明の詳細な説明】 ［産業上の利用分野］ この発明は小容量SRAMの代りに大容量SRAMを装着可能
とするSRAM共用化プリント基板に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Industrial field of use] The present invention relates to an SRAM common printed circuit board on which a large capacity SRAM can be mounted instead of a small capacity SRAM.
［従来の技術］ 一般の電子機器、システムにおいて多数のSRAMを装着
したプリント基板が多用されている。[Prior Art] Printed boards on which a large number of SRAMs are mounted are often used in general electronic devices and systems.
第４図〜第６図はそれぞれプリント基板上に装着され
る16Kビット（2048語×８ビット構成）、64Kビット（81
92語×８ビット構成）および256Kビット（32768語×８
ビット構成）のSRAM（スタテックランダムアクセスメモ
リ）を上側面から見た端子（ピン）の配置図であり、各
端子には端子番号を書き込み、その機能を添書きした。
第４〜第６図において、（１）は16KビットSRAM（以
下、16KSRAMと記す）、（２）は64KビットSRAM（以下、
64KSRAMと記す）、（３）は256KビットSRAM（以下、256
KSRAMと記す）、（４）は端子であり、16KSRAM（１）の
場合は24本の端子を、64KSRAM（２）および256KSRAM
（３）の場合は28本の端子を有する。（５）は電源（バ
ッテリバックアップ電源）、（６）はGND（接地）、
（７）はコンデンサを示す。Figures 4 to 6 show 16K bits (2048 words x 8 bits) and 64K bits (81 bits) mounted on the printed circuit board, respectively.
92 words x 8 bits configuration and 256K bits (32768 words x 8)
It is a layout view of terminals (pins) when the SRAM (Static Random Access Memory) of bit configuration) is viewed from the upper side. Each terminal has a terminal number written and its function is added.
4 to 6, (1) is a 16 Kbit SRAM (hereinafter referred to as 16K SRAM), and (2) is a 64 Kbit SRAM (hereinafter, referred to as 16 Kbit SRAM).
64KSRAM), (3) is a 256Kbit SRAM (hereinafter 256
KSRAM), (4) are terminals, and 16KSRAM (1) has 24 terminals, 64KSRAM (2) and 256KSRAM
In the case of (3), it has 28 terminals. (5) is the power supply (battery backup power supply), (6) is the GND (ground),
(7) shows a capacitor.
次に、各端子（10）に端子番号と共に併記された役割
（機能）を示す記号について説明する。A0〜A15はアド
レスバス端子、I/O1〜I/O8はデータ入出力用のデータバ
ス端子OEは読出し指令信号端子、WEは書込み指令信号端
子、CSはチップセレクト端子であり、第５図におけるCS
1、CS2はそれぞれ第１および第２のチップセレクト端
子、Vccは電源端子、Vssは接地端子を示す。16KSRAM
（１）と64KSRAM（２）および256KSRAM（３）とは端子
数が異なり、64KSRAM（２）と256KSRAM（３）とは端子
の数は28本で同じであるが、端子の役割が、例えば端子
番号1,20、26番について異なっている。ただし端子およ
び端子間寸法は各SRAM共同一に標準化されており、例え
ば256KSRAM（３）装着用のプリント基板の端子穴には64
KSRAM（２）および16KSRAM（１）の装着を可能とする。Next, the symbols indicating the roles (functions) that are written together with the terminal numbers on the terminals (10) will be described. A0 to A15 are address bus terminals, I / O1 to I / O8 are data input / output data bus terminals OE is a read command signal terminal, WE is a write command signal terminal, and CS is a chip select terminal. CS
Reference numerals 1 and CS 2 are first and second chip select terminals, Vcc is a power supply terminal, and Vss is a ground terminal. 16K SRAM
The number of terminals is different between (1) and 64KSRAM (2) and 256KSRAM (3), and the number of terminals is the same as 64KSRAM (2) and 256KSRAM (3), but the role of terminals is, for example, The numbers 1, 20, and 26 are different. However, the terminals and the terminal-to-terminal dimensions are standardized for each SRAM jointly, for example, 64K for the terminal holes of the printed circuit board for mounting 256K SRAM (3).
KSRAM (2) and 16KSRAM (1) can be installed.
［発明が解決しようとする課題］ SRAMの端子数および各端子の役割が一般にそのメモリ
容量にて異なるので、プリント基板への上記SRAMの装着
工程において、必要とするメモリ容量のものが入手でき
ない場合には、よりメモリ容量の大きな大容量SRAMで代
用したくとも従来のプリント基板では装着することがで
きず、メモリ容量や端子数の異なる各SRAMに合わせて複
数種類のプリント基板を準備しなければならないなどの
問題点があった。[Problems to be Solved by the Invention] Since the number of SRAM terminals and the role of each terminal generally differ depending on the memory capacity, when the required memory capacity cannot be obtained in the process of mounting the SRAM on the printed circuit board. However, even if you want to substitute a large-capacity SRAM with a larger memory capacity, you cannot install it with a conventional printed circuit board, and you must prepare multiple types of printed circuit boards according to each SRAM with different memory capacity and number of terminals. There was a problem such as not becoming.
この発明は、上記のような問題点を解消するためにな
されたもので、小容量SRAMの代りに大容量SRAMを装着可
能とするSRAM共用化プリント基板を得ることを目的とす
る。The present invention has been made to solve the above problems, and an object of the present invention is to obtain an SRAM shared printed circuit board on which a large capacity SRAM can be mounted instead of a small capacity SRAM.
［課題を解決するための手段］ この発明に係るSRAM共用化プリント基板は、小容量SR
AMの代りに端子数の異なる大容量SRAMを装着可能に大容
量SRAMの端子数の端子穴を形成し、小容量SRAMと大容量
SRAMとの接地端子穴を共用すると共にそれぞれの電源端
子穴間を接続し、小容量SRAMのWE端子穴は第１の抵抗器
または短絡片を介して大容量SRAMのWE端子穴に接続する
と共に小容量SRAMを装着時に誤装着を防止すべく不要と
なる端子穴近傍に第１の抵抗器または短絡片を装着し、
小容量SRAMのWE端子穴は第２の抵抗器を介して論理レベ
ル一定のラインに接続されるべくプリント配線を形成す
るようにしたものである。[Means for Solving the Problems] The SRAM shared printed circuit board according to the present invention has a small capacity SR.
A large-capacity SRAM with a different number of terminals can be mounted in place of the AM, by forming a terminal hole with the number of terminals of the large-capacity SRAM, and a small-capacity SRAM and a large capacity
The ground terminal hole with SRAM is shared, and each power supply terminal hole is connected, and the WE terminal hole of the small capacity SRAM is connected to the WE terminal hole of the large capacity SRAM via the first resistor or the shorting piece. Install the first resistor or shorting piece near the unnecessary terminal hole to prevent incorrect installation when installing a small capacity SRAM,
The WE terminal hole of the small-capacity SRAM forms a printed wiring so as to be connected to a line having a constant logic level through the second resistor.
また、小容量SRAMの代りに小容量SRAMと端子数の等し
い大容量SRAMを装着可能に小容量SRAMと大容量SRAMとの
接地端子穴および電源端子穴を共用すると共に、大容量
SRAMのCS端子穴になると共に小容量SRAMの第１のCS端子
穴になる端子穴をCS信号が供給される端子穴とし、小容
量SRAMの第２のCS端子穴にはCS信号の働きを阻害しない
論理レベル一定の電圧を与え、小容量SRAMのNC端子穴に
なると共に大容量SRAMのアドレス端子穴になる端子穴に
は論理レベル一定電圧を与えるべくプリント配線を形成
するようにしたものである。Also, instead of a small capacity SRAM, a large capacity SRAM with the same number of terminals as a small capacity SRAM can be mounted. The small capacity SRAM and the large capacity SRAM share the ground terminal hole and the power supply terminal hole, and the large capacity
The CS hole is used as the CS terminal hole of the SRAM and the first CS terminal hole of the small-capacity SRAM is used as the terminal hole to which the CS signal is supplied, and the second CS terminal hole of the small-capacity SRAM functions as the CS signal. A printed wiring is formed so as to give a constant logic level voltage by applying a voltage with a constant logic level that does not hinder and becomes an NC terminal hole of a small capacity SRAM and an address terminal hole of a large capacity SRAM. is there.
［作用］ この発明によるSRAM共用化プリント基板は、小容量SR
AMの代りに端子数の異なる大容量SRAMを装着可能に大容
量SRAMの端子数の端子穴が形成され、小容量SRAMと大容
量SRAMとの接地端子穴が共用されると共にそれぞれの電
源端子穴間が接続され、小容量SRAMのWE端子穴は第１の
抵抗器または短絡片を介して大容量SRAMのWE端子穴に接
続されると共に小容量SRAMを装着時に誤装着を防止すべ
く不要となる端子穴近傍に第１の抵抗器または短絡片が
装着され、小容量SRAMのWE端子穴は第２の抵抗器を介し
て論理レベル一定のラインに接続されるべくプリント配
線が形成される。[Operation] The SRAM shared printed circuit board according to the present invention has a small capacity SR.
Instead of AM, large-capacity SRAMs with different numbers of terminals can be mounted, and terminal holes for the large-capacity SRAM terminals are formed, and ground terminal holes for small-capacity SRAMs and large-capacity SRAMs are shared, and power-supply terminal holes for each. The WE terminal hole of the small capacity SRAM is connected to the WE terminal hole of the large capacity SRAM via the first resistor or the short-circuit piece, and it is unnecessary to prevent the incorrect mounting when mounting the small capacity SRAM. A first resistor or a short-circuit piece is mounted in the vicinity of the terminal hole, and a printed wiring is formed so that the WE terminal hole of the small capacity SRAM is connected to a line having a constant logic level via the second resistor.
また、小容量SRAMの代りに小容量SRAMと端子数の等し
い大容量SRAMを装着可能に小容量SRAMと大容量SRAMとの
接地端子穴および電源端子穴が共用されると共に、大容
量SRAMのCS端子穴になると共に小容量SRAMの第１のCS端
子穴になる端子穴をCS信号が供給される端子穴とし、小
容量SRAMの第２のCS端子穴にはCS信号の働きを阻害しな
い論理レベル一定の電圧が与られ、小容量SRAMのNC端子
穴になると共に大容量SRAMのアドレス端子穴になる端子
穴には論理レベル一定電圧を与えるべくプリント配線が
形成される。Also, instead of the small-capacity SRAM, the large-capacity SRAM with the same number of terminals as the small-capacity SRAM can be mounted, the ground terminal hole and the power supply terminal hole of the small-capacity SRAM are shared, and the large-capacity SRAM CS Logic that does not interfere with the CS signal function in the second CS terminal hole of the small capacity SRAM, with the terminal hole that becomes the terminal hole and the first CS terminal hole of the small capacity SRAM as the terminal hole to which the CS signal is supplied A voltage is applied at a constant level, and a printed wiring is formed to give a constant logic level voltage to the terminal hole that becomes the NC terminal hole of the small capacity SRAM and the address terminal hole of the large capacity SRAM.
［発明の実施例］ この発明の一実施例を第１図〜第３図により説明す
る。図中、従来例と同じ符号で示されたものは従来例の
それと同一もしくは同等なものを示す。[Embodiment of the Invention] An embodiment of the present invention will be described with reference to Figs. In the figure, those denoted by the same reference numerals as those of the conventional example indicate the same or equivalent parts as those of the conventional example.
第１図は16KSRAM（１）の代りに256KSRAM（３）を装
着するSRAM共用化のためのプリント基板（11）の回路
図、第２図は16KSRAM（１）の実装状態を示す外観の一
部を示す図である。第１図において（８）は後述のプリ
ント基板（11）に形成されたSRAM装着のための端子穴で
あり、各端子穴に付した記号T1〜T28は256KSRAM（３）
装着時の端子番号を示し、例えばT3（１）のごとく
（ ）内に付された数字は16KSRAM（１）装着時の端子
番号を示す。（９）は16Kと256KSRAM（１）、（３）の
書込指令信号を切替えるための抵抗器、（10）は256KSR
AM装着時A11端子を“Ｈレベル”に確定させるためのプ
ルアップ抵抗器である。Fig. 1 is a circuit diagram of a printed circuit board (11) for sharing SRAM, in which 256KSRAM (1) is replaced with 256KSRAM (3), and Fig. 2 is a part of the appearance showing the mounting state of 16KSRAM (1). FIG. In FIG. 1, (8) is a terminal hole for mounting SRAM, which is formed on a printed circuit board (11) described later, and symbols T1 to T28 attached to each terminal hole are 256K SRAM (3).
Indicates the terminal number at the time of mounting. For example, the number in parentheses like T3 (1) indicates the terminal number at the time of mounting 16K SRAM (1). (9) is a resistor for switching 16K and 256K SRAM (1), (3) write command signal, (10) is a 256KSR
This is a pull-up resistor for fixing the A11 terminal to "H level" when AM is installed.
次に16Kと256KSRAM（１）、（３）の共用回路と実装
方式について説明する。16KSRAM（１）はその１、12、1
3、24番ピンが256KSRAM（３）の３、14、15、26番ピン
に対応するように実装させる。この場合、ピンアサイン
が一致しない256KSRAM（３）のA14、A12についてはGND
（６）へ接続することによりアドレスを確定させる。書
込指令信号端子であるWE端子については16KSRAM（１）
の装着時に抵抗器（９）を実装し、256KSRAM（３）実装
時には抵抗器（９）を実装しないことにより書込指令信
号の入力先を切替えることにする。抵抗（10）は256KSR
AM装着時、抵抗器（９）が実装されないため端子A11が
不安定となるのを避けるために挿入したものである。ま
た、抵抗器（９）の実装位置を第２図に示すように256K
SRAMの１、２番ピンと27、28番ピンの間にすることによ
り、16Kと256KSRAMとも誤実装の防止、例えば16KSRAM
（１）の装着端子穴の間違防止、又は16KSRAM（１）の
代りに256KSRAM（３）の誤装着の防止、および抵抗器
（９）を実装する。しないによる書込指令信号の切替え
間違いを防止する。例えば、16KSRAM実装時に抵抗器
（９）が無いと動作せず、出荷時に確認可となる。ま
た、抵抗器（９）があると256KSRAMは実装することがで
きず組立時に誤実装を防止することができる。Next, a shared circuit of 16K and 256K SRAM (1) and (3) and a mounting method will be described. 16KSRAM (1) is 1, 12, 1
Mount pins so that pins 3 and 24 correspond to pins 3, 14, 15, and 26 of 256K SRAM (3). In this case, GND is used for A14 and A12 of 256K SRAM (3) whose pin assignments do not match.
The address is fixed by connecting to (6). 16K SRAM (1) for the WE terminal which is the write command signal terminal
The input destination of the write command signal is switched by mounting the resistor (9) at the time of mounting and not mounting the resistor (9) at the time of mounting 256KSRAM (3). Resistance (10) is 256KSR
This is inserted to prevent the terminal A11 from becoming unstable because the resistor (9) is not mounted when the AM is mounted. Also, the mounting position of the resistor (9) is 256K as shown in FIG.
Preventing erroneous mounting of both 16K and 256K SRAMs by placing it between pins 1 and 2 and 27 and 28 pins of SRAM, for example 16K SRAM
Prevent the wrong mounting terminal hole of (1) or prevent wrong mounting of 256KSRAM (3) instead of 16KSRAM (1), and mount a resistor (9). Prevents mistaken switching of the write command signal due to not doing so. For example, when the 16K SRAM is mounted, it does not work without the resistor (9) and can be confirmed at the time of shipment. Further, if the resistor (9) is provided, the 256K SRAM cannot be mounted and erroneous mounting can be prevented during assembly.
第３図は64KSRAM（２）の代りに256KSRAM（３）を装
着するSRAM共用化のためのプリント基板の回路図であ
る。図において、（12）は64KSRAM（２）を装着の場合
に第１および第２のチップセレクト信号のいずれかを選
択するようにチップセレクト信号を制御するためのNAND
ゲート、（13）は入力信号を反転するインバータであ
る。FIG. 3 is a circuit diagram of a printed circuit board for sharing SRAM in which 256K SRAM (3) is mounted instead of 64K SRAM (2). In the figure, (12) is a NAND for controlling the chip select signal so as to select either the first or second chip select signal when the 64K SRAM (2) is mounted.
The gate, (13) is an inverter that inverts the input signal.
次に、64Kと256KSRAM共用回路について説明する。一
例の64KSRAMと一例の256KSRAMとは、第５図および第６
図に示すように端子数はともに28であり接地端子および
電源端子のピン番号は同一である。64KSRAMの１番ピン
はIC内部で接続のないNCピンであり、26番ピンはCS2ピ
ンである。そして、256KSRAMの１番ピンはアドレス選択
信号じゃ14のピンであり、26番ピンはアドレス選択信号
A13のピンである。この実施例によれば、64KSRAM（２）
と256KSRAM（３）の相違点である１番ピンと26番ピン
は、第３図に示すように、それぞれGND（６）と電源
（５）に接続することによりアドレスを確定させる。な
お、この例では１番ピンは64KSRAMの場合はNCピンであ
り256KSRAMの場合はA14のアドレス選択信号ピンになる
ので、１番ピンおよび26番ピンを接地すると256KSRAMを
装着した場合はA14のアドレス選択信号およびA13のアド
レス選択信号がＬレベルに固定される。256KSRAMであっ
ても64Kとして使用するのでA14のアドレス端子およびA1
3のアドレス選択端子は使用しなくてもよく、特定の理
論レベルに固定されるだけでよい。64KSRAMの選択をチ
ップセレクト信号１と２の両方で行っている場合、20番
ピンにはチップセレクト信号１をインバータ（13）によ
り反転させチップセレクト信号２とのNANDをとって入力
させることによりSRAMが選択されるようにする。Next, a 64K and 256K SRAM common circuit will be described. An example of 64K SRAM and an example of 256K SRAM are shown in FIG. 5 and FIG.
As shown in the figure, the number of terminals is 28, and the pin numbers of the ground terminal and the power supply terminal are the same. Pin 64 of the 64K SRAM is an NC pin that has no connection inside the IC, and pin 26 is the CS2 pin. And the 1st pin of 256K SRAM is the 14th pin for the address selection signal and the 26th pin is the address selection signal
A13 pin. According to this embodiment, 64K SRAM (2)
As shown in FIG. 3, pins 1 and 26, which are the differences between the 256K SRAM (3) and the 256K SRAM (3), are connected to the GND (6) and the power supply (5), respectively, to fix the address. In this example, pin 1 is the NC pin for 64K SRAM and the address selection signal pin of A14 for 256K SRAM, so if pin 1 and pin 26 are grounded, the address of A14 will be displayed when 256K SRAM is installed. The selection signal and the address selection signal of A13 are fixed to the L level. Even if 256K SRAM is used as 64K, address pin of A14 and A1
The address selection terminal of 3 does not have to be used and need only be fixed at a particular theoretical level. When 64K SRAM is selected by both chip select signals 1 and 2, SRAM is created by inverting the chip select signal 1 by the inverter (13) and inputting NAND with the chip select signal 2 at pin 20. To be selected.
上記実施例において、アドレスを確定させるために、
第１図に示した16K/256KSRAM共用回路ではA14（256KSRA
Mの１番ピン）、A12（256KSRAMの２番ピン）をそれぞれ
GNDに接続し、第３図に示した64K/256KSRAM共用回路で
はA14（256KSRAMの１番ピン）をGNDに接続したが、上記
A12、A14アドレス端子2.2〔Ｖ〕以上の電位にプルアッ
プしてアドレスを確定することも可能である。In the above embodiment, in order to fix the address,
In the 16K / 256K SRAM shared circuit shown in Fig. 1, A14 (256KSRA
Pin 1 of M) and A12 (pin 2 of 256K SRAM) respectively
Connected to GND, and in the 64K / 256K SRAM shared circuit shown in Fig. 3, A14 (Pin 1 of 256KSRAM) was connected to GND.
It is also possible to determine the address by pulling up to a potential of A12, A14 address terminal 2.2 [V] or higher.
また、16K/256KSRAM共用回路では書込み指令信号の入
力先を変え、なおかつ、16KSRAMの誤実装を防止するた
めに抵抗（９）を使用しているが、これを短絡片等の部
品に変えることも可能である。さらに、64K/256KSRAM共
用回路では、SRAMの選択チップセレクト信号１または２
のどちらか一方のみで行っている場合には、26番ピンを
電源に接続し、制御を行っているチップセレクト信号を
20番ピンに接続することも可能である。Also, in the 16K / 256KSRAM shared circuit, the input destination of the write command signal is changed, and the resistor (9) is used to prevent erroneous mounting of the 16KSRAM. However, this can be changed to a part such as a shorting piece. It is possible. Furthermore, in the 64K / 256K SRAM shared circuit, SRAM select chip select signal 1 or 2
If only one of the two is used, connect pin 26 to the power supply and send the chip select signal
It is also possible to connect to pin 20.
［発明の効果］ 以上のように本発明によれば、小容量SRAMの代りに端
子数の異なる大容量SRAMを装着可能に大容量SRAMの端子
数の端子穴が形成され、小容量SRAMと大容量SRAMとの接
地端子穴が共用されると共にそれぞれの電源端子穴間が
接続され、小容量SRAMのWE端子穴は第１の抵抗器または
短絡片を介して大容量SRAMのWE端子穴に接続されると共
に小容量SRAMを装着時に誤装着を防止すべく不要となる
端子穴近傍に第１の抵抗器または短絡片が装着され、小
容量SRAMのWE端子穴は第２の抵抗器を介して論理レベル
一定のラインに接続されるべくプリント配線が形成され
るようにしたので、また、小容量SRAMの代りに小容量SR
AMと端子数の等しい大容量SRAMを装着可能に小容量SRAM
と大容量SRAMとの接地端子穴および電源端子穴が共用さ
れると共に、大容量SRAMのCS端子穴になると共に小容量
SRAMの第１のCS端子穴になる端子穴をCS信号が供給され
る端子穴とし、小容量SRAMの第２のCS端子穴にはCS信号
の働きを阻害しない論理レベルの一定の電圧が与えら
れ、小容量SRAMのNC端子穴になるとともに大容量SRAMの
アドレス端子穴になる端子穴には論理レベル一定電圧を
与えるべくプリント配線が形成されるようにしたので、
メモリ容量や端子数の異なる各SRAMに合わせて複数種類
のプリント基板を準備する必要のないものが得られる効
果がある。[Effects of the Invention] As described above, according to the present invention, a terminal hole having the number of terminals of a large capacity SRAM is formed so that a large capacity SRAM having a different number of terminals can be mounted in place of the small capacity SRAM, and a large capacity SRAM The ground terminal hole with the capacity SRAM is shared and the power supply terminal holes are connected together, and the WE terminal hole of the small capacity SRAM is connected to the WE terminal hole of the large capacity SRAM via the first resistor or short-circuit piece. The first resistor or shorting piece is installed near the terminal hole that is unnecessary to prevent incorrect installation when installing the small capacity SRAM, and the WE terminal hole of the small capacity SRAM is connected via the second resistor. Since the printed wiring is formed so as to be connected to a line with a constant logic level, small capacity SR is used instead of small capacity SRAM.
Large capacity SRAM with the same number of terminals as AM can be mounted Small capacity SRAM
The ground terminal hole and the power supply terminal hole are shared between the large capacity SRAM and the large capacity SRAM, and it becomes the CS terminal hole of the large capacity SRAM and the small capacity
The terminal hole that becomes the first CS terminal hole of the SRAM is the terminal hole to which the CS signal is supplied, and the second CS terminal hole of the small capacity SRAM is given a certain voltage with a logic level that does not disturb the function of the CS signal. The printed wiring is formed to give a constant logic level voltage to the terminal hole which becomes the NC terminal hole of the small capacity SRAM and the address terminal hole of the large capacity SRAM.
There is an effect that it is not necessary to prepare a plurality of types of printed circuit boards according to the SRAMs having different memory capacities and the number of terminals.
第１図はこの発明の一実施例による16KSRAMの代りに256
KSRAMを装着可能にするSRAM共用化プリント基板の回路
図、第２図は第１図に示した回路図の実体配線図、第３
図は64KSRAMの代りに256KSRAMを装着可能にするSRAM共
用化プリント基板の回路図、第４図〜第６図は従来のプ
リント基板におけるSRAMの回路図であり、それぞれ16
K、64K、256KSRAMの回路図である。 図において、（１）〜（３）はそれぞれ16K、64K、256K
SRAM、（４）は各SRAMの端子、（８）はプリント基板
（10）の端子穴、（９）、（10）は抵抗器、（12）はNA
NDゲート素子、（13）はインバータ素子を示す。 なお、図中、同一符号は同一、または相当部分を示す。FIG. 1 shows that 256K SRAM is used instead of 16K SRAM according to one embodiment of the present invention.
Circuit diagram of an SRAM shared printed circuit board on which KSRAM can be mounted. Fig. 2 is a physical wiring diagram of the circuit diagram shown in Fig. 1.
The figure is a circuit diagram of an SRAM common printed circuit board that allows 256K SRAM to be installed instead of 64K SRAM, and FIGS. 4 to 6 are SRAM circuit diagrams of conventional printed circuit boards.
It is a circuit diagram of K, 64K, 256K SRAM. In the figure, (1) to (3) are 16K, 64K, and 256K, respectively.
SRAM, (4) is a terminal of each SRAM, (8) is a terminal hole of a printed circuit board (10), (9) and (10) are resistors, and (12) is NA.
ND gate element, (13) indicates an inverter element. In the drawings, the same reference numerals indicate the same or corresponding parts.
Claims (2)
SRAMを装着可能に上記大容量SRAMの端子数の端子穴を形
成し、上記小容量SRAMと上記大容量SRAMとの接地端子穴
を共用すると共にそれぞれの電源端子穴間を接続し、上
記小容量SRAMのWE端子穴は第１の抵抗器または短絡片を
介して上記大容量SRAMのWE端子穴に接続すると共に上記
小容量SRAMを装着時に誤装着を防止すべく不要となる端
子穴近傍に上記第１の抵抗器または短絡片を装着し、か
つ、上記小容量SRAMのWE端子穴は第２の抵抗器を介して
論理レベル一定のラインに接続されるべくプリント配線
を形成したことを特徴とするSRAM共用化プリント基板。1. A large capacity having a different number of terminals instead of a small capacity SRAM
Forming terminal holes for the number of terminals of the large-capacity SRAM so that SRAM can be mounted, sharing the ground terminal holes of the small-capacity SRAM and the large-capacity SRAM, and connecting the power supply terminal holes to each other The WE terminal hole of the SRAM is connected to the WE terminal hole of the large-capacity SRAM via the first resistor or the shorting piece, and the small-capacity SRAM is installed near the unnecessary terminal hole to prevent erroneous mounting when mounting. The first resistor or the short-circuit piece is mounted, and the WE terminal hole of the small capacity SRAM is formed with a printed wiring so as to be connected to a line having a constant logic level through the second resistor. An SRAM shared printed circuit board.
数の等しい大容量SRAMを装着可能に上記小容量SRAMと上
記大容量SRAMとの接地端子穴および電源端子穴を共用す
ると共に、上記大容量SRAMのCS端子穴になると共に上記
小容量SRAMの第１のCS端子穴になる端子穴をCS信号が供
給される端子穴とし、上記小容量SRAMの第２のCS端子穴
には上記CS信号の働きを阻害しない論理レベル一定の電
圧を与え、上記小容量SRAMのNC端子穴になるとともに上
記大容量SRAMのアドレス端子穴になる端子穴には論理レ
ベル一定電圧を与えるべくプリント配線を形成したこと
を特徴とするSRAM共用化プリント基板。2. A ground terminal hole and a power supply terminal hole are shared between the small capacity SRAM and the large capacity SRAM so that a large capacity SRAM having the same number of terminals as the small capacity SRAM can be mounted instead of the small capacity SRAM. The terminal hole that becomes the CS terminal hole of the large capacity SRAM and becomes the first CS terminal hole of the small capacity SRAM is the terminal hole to which the CS signal is supplied, and the second CS terminal hole of the small capacity SRAM is Print a wiring to give a constant logic level voltage to the terminal holes that will be the NC terminal holes of the small capacity SRAM and the address terminal holes of the large capacity SRAM by applying a voltage of a constant logic level that does not disturb the function of the CS signal. A printed circuit board for shared use with SRAM, characterized in that
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2047879A JP2536652B2 (en) | 1990-02-28 | 1990-02-28 | Printed circuit board for SRAM |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2047879A JP2536652B2 (en) | 1990-02-28 | 1990-02-28 | Printed circuit board for SRAM |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH03250784A JPH03250784A (en) | 1991-11-08 |
| JP2536652B2 true JP2536652B2 (en) | 1996-09-18 |
Family
ID=12787672
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2047879A Expired - Lifetime JP2536652B2 (en) | 1990-02-28 | 1990-02-28 | Printed circuit board for SRAM |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2536652B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04109568U (en) * | 1991-03-11 | 1992-09-22 | 株式会社ケンウツド | Structure to prevent incorrect insertion of printed circuit boards |
| US20230066238A1 (en) * | 2020-01-31 | 2023-03-02 | Fanuc Corporation | Motor drive device and method for manufacturing same |
-
1990
- 1990-02-28 JP JP2047879A patent/JP2536652B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH03250784A (en) | 1991-11-08 |
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