JP2532082B2 - Thin film transistor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial application] The present invention relates to an improvement in a thin film transistor.

[Conventional technology]

In recent years, thin film transistors have been vigorously developed as switch elements for liquid crystal display or fax image sensors. As a typical structure of this thin film transistor, the structure shown in FIG. 8 is known. FIG. 8 shows an inverted staggered MISFET (hereinafter abbreviated as FET).
This type is currently the main development goal. (1) is the substrate, (20) is the gate metal of the FET, and (3) is the gate insulating film. (21) and (22)
A metal film corresponding to the source and drain of the FET.
(4) is a semiconductor film typified by amorphous silicon or the like, and (5a) and (5b) are semiconductor films 4 and metal films (21) and (2).
2) A semiconductor film that reduces the contact resistance with it, and usually amorphous silicon doped with phosphorus is used.

The FET operates by applying the voltage V _DS between the drain (22) and the source (21) and applying the voltage V _GS to the gate (20). When the gate voltage V _GS is equal to or higher than the threshold voltage V _TH , an electron channel is formed at the interface between the semiconductor film (4) and the gate insulating film (3). Since the resistance of this channel portion is small, the current I _DS between the source (21) and the drain (22) increases. The relationship between the current I _DS and the gate voltage V _G drain voltage V _D and source voltage V _S is expressed by the following equation.

Here, μeff is the effective mobility, W is the effective gate width, L is the effective gate length, ε _G is the dielectric constant of the gate insulating film, and T _G is the gate insulating film thickness. Since a large I _DS, usually a gate insulating film as a plasma nitride layer: uses a _{(ε G ≒ 6.4ε O, ε} O permittivity of vacuum), the thickness thereof in the production limit
It is taken from 200 to 300 nm. The gate length L is approximately 5 μm due to the processing accuracy, and μeff is 0.1 to 1.0 cm ² / V · S in the case of amorphous silicon, although it depends on the semiconductor film. The gate width W is designed appropriately.

[Problems to be solved by the invention]

The conventional thin film transistor described above has the problems that the operation speed is slow and the change over time is large. First, the operating speed is slow, but the main reason for this is that the mobility is small, so the ON resistance is large and the RC time constant cannot be kept small. In order to reduce the ON resistance, the gate width W may be increased, but the element size is increased and the parasitic capacitance is increased accordingly, so that the operation speed is not improved so much. In the currently reported amorphous silicon type thin film transistor (hereinafter abbreviated as a-Si TFT), the maximum propagation delay time is 210 ns. (K.Hir
anaka et al: IEEE Electron Device Letters. VoL EDL−
5, No.7 1984 pp224-225) However, this is an operation as a ring oscillator and does not always match the operation speed of a normal logic circuit. Considering the case where it is applied to a TV display, it is necessary to operate at 4MHz or higher as a logic circuit that combines TFTs. On the other hand, 20 kHz is the highest shift register reported so far (Okada et al., Technical Report of the Institute of Electronics and Communication Engineers, 1984 ED84-9), and a-Si TFT logic circuit cannot be used for TV. is the current situation.
Next, there is a large change over time, which appears as a change in the threshold voltage V _TH . This occurs because carriers are driven into the gate insulating film during the operation of the TFT, and the insulating film is charged accordingly. In order to improve this, research has been conducted on the two points of the film quality of the insulating film and the interface with the semiconductor film, but a V _TH fluctuation of several volts is inevitable. This also makes it difficult to put the TFT logic circuit into practical use.

[Means for solving problems]

The present invention has been made to solve the above-mentioned problems, and is provided on the collector electrode made of the first high conductive film A, and is provided on the first high conductive film A so as to have an intrinsic or low concentration of impurities. A semiconductor film B having the introduced first conductivity type, a base electrode made of a second high conductive film C provided on the semiconductor film B and having holes or grooves, and a base electrode on the base electrode. An insulating film G provided; a semiconductor film D having a first conductivity type, which is provided on the insulating film G and in the holes or grooves and has an intrinsic or low concentration impurity introduced; A semiconductor film F provided on the semiconductor film D and having a second conductivity type in which a high concentration of impurities is introduced; and an emitter electrode formed on the semiconductor film F and formed of a third high conductive film J, Thin film transistor having There is a semiconductor film K having a second conductivity type provided on the first high conductive film A between the first high conductive film A and the semiconductor film B, or the first high conductive film A. A semiconductor film M having a first conductivity type, which is provided on the high conductive film A and has an intrinsic or low concentration of impurities, and a semiconductor film M, which is provided on the semiconductor film M and has a second conductivity type. A thin film transistor characterized in that a composite film N, which is a combination of L and L, is provided.

Further, the present invention provides a collector electrode made of a first high conductive film A, and a semiconductor provided on the first high conductive film A and having a first conductivity type with impurities introduced at an intrinsic or low concentration. A film B, a base electrode formed on the semiconductor film B and formed of a second high conductive film C having holes or grooves, and an insulating film E formed on the base electrode and on the side wall.
A semiconductor film F having a second conductivity type, which is provided on the insulating film E and in the holes or grooves and has a high concentration of impurities, and is provided on the semiconductor film F. A thin film transistor comprising: an emitter electrode made of a high conductive film J, and a second thin film transistor provided on the first high conductive film A between the first high conductive film A and the semiconductor film B. A semiconductor film K having a second conductivity type, or a semiconductor film M having a first conductivity type provided on the first high conductive film A and having an impurity introduced at an intrinsic or low concentration; A thin film transistor, comprising: a composite film N, which is provided on M and is combined with a semiconductor film L having a second conductivity type.

[Work]

The present inventor has previously found that the first high conductive film A, the semiconductor film B having the first conductivity type with intrinsic or low-concentration impurities introduced, and the second high conductive film having holes or vacancies. C and a semiconductor film F having a second conductivity type in which impurities are introduced at a high concentration are stacked in a normal order or a reverse order,
A thin film transistor in which carriers can be injected from the semiconductor film F to the semiconductor film B through the holes or groove portions provided in the high conductive film C was newly prepared and a patent application was filed.
(Japanese Patent Laid-Open No. 61-97556) The present invention has been made to solve the problems of the conventional FET described above. Like the conventional FET, a voltage is applied to the gate metal to form a channel, and a current is generated by the channel. Instead of using a flowing structure, two electrodes for turning on and off are provided in the semiconductor and another electrode for injecting carriers is provided outside the semiconductor, and one or a plurality of electrodes for passing the carriers through the electrode on the carrier injection side are provided. A hole is provided and the amount of injected carriers is controlled to change the resistance between the two electrodes to realize functions such as ON / OFF.
It is possible to suppress the N resistance to be small to increase the operation speed and to suppress the change with time in the threshold voltage V _TH to the ON state.

An embodiment of the invention will be described below with reference to sectional views. In FIG. 5, (1) is a substrate, and (60) (61
a) (61b) (61c) (61d) (61e) (62) is a high conductive film [J, C, A] of metal or the like, (9) is a P-type semiconductor film [F],
(8) the n ^- in the form semiconductor films or intrinsic (undoped) semiconductor film (B). Also (71a) (71b) (71
c) (71d) and (72) are high conductive films (61a) such as metal.
d) An n ^{+ type} semiconductor film provided for ohmic contact between (62) and the semiconductor film (8) [H, I]. (63a)
(63b) (63c) (63d) are insulating films [G] provided so that the hole current injected from the P-type semiconductor film (9) does not flow into the high conductive film (61a). is there.

Further, in the transistor structure, the types of the semiconductor films (8) and (9) do not matter. Amorphous, polycrystalline, or crystalline silicon may be used, and compound semiconductors other than silicon operate in exactly the same manner. However, as the semiconductor film used for the thin film transistor is improved mainly in the present technological development, amorphous silicon is mainly used. Therefore, the following description will be made with this semiconductor film in mind.

High conductive film (62) and (61a) (61b) (61c) (61d)
(61e) has ohmic contact with the semiconductor film (8), and also has ohmic contact with the high conductive film (60) and the P-type semiconductor film (9). Also, a high conductive film (61
Although not shown in the figure, a) (61b) (61c) (61d) (61e) are connected at the periphery. The P-type semiconductor film (9) has a function of injecting holes, and is called an emitter, and (60) is called an emitter electrode. (62) is a collector electrode, (61a) to (61e)
Is called a base electrode.

As a concrete example of the material and dimensions of the above parts, the thickness is approximately
1mm glass substrate (1), Cr film (60) about 100nm thick, about 10
0 nm thick P-type silicon layer (9), about 5 μm at intervals of about 5 μm
50-100 nm thick Cr film (61) with slits of m width,
An i-type silicon layer (8) provided with a thickness of about 100 nm above and below the slit hole of the r film (61), C with a thickness of about 100 nm
The r film (62) and the like can be mentioned, and these can be formed by a vacuum deposition method, a photolithography method or the like.

The base electrode is not limited to the slit shape, and can be used as long as it is a perforated electrode having at least one hole or groove, and the holes and grooves may have any shape. . Further, it is preferable to use a metal or the like having a low electric resistance value for the base electrode. The holes or grooves provided in the base electrode are preferably provided in large numbers because the number of injected carriers increases. When a large number of vacancies or vacancies are provided, the distance between the vacancies or vacancies is the diffusion length L _D of the injected carriers (electrons ≈ 1 μm, holes ≈ 0.2 to 0.3 μm for amorphous silicon semiconductors).
m) less than twice the base electrode (6
2) It is preferred because it increases the number of carriers acting on the area. Further, the thickness (P
Type semiconductor (8) of thickness = base electrode (61a) thickness + base electrode and the collector electrode (62) between the n ^- type the thickness of the semiconductor (8) + base electrode and P-type semiconductor film (9) between n of ^- form the thickness of the semiconductor (8)) is thinner than the diffusion length L _D of carriers injected is preferred. To operate the thin film transistor, the collector electrode (62) is set to the lowest potential, and the voltage V _BC is applied to the base electrodes (61a) to (61e). In this state, the control on whether to apply a diffusion voltage Vdiff more than the voltage V _BC to the emitter electrode (60). If the voltage of the emitter electrode (60) is set lower than V _BC + V diff, P
Hole injection from shaped semiconductor (9) into (8) does not occur. In this case, the OFF current between the base and collector is determined by the resistance of the semiconductor film (8) sandwiched between the base electrode and the collector electrode. When the resistivity of the semiconductor film (8) is Pi, the base electrode-collector electrode facing area is S _BC , and the base electrode-collector electrode distance is L _BC , the OFF electrode I _OFF is I _OFF = V _BC · S _BC / ( Pi ・ L _BC ) (2) Suppose now that V _BC = 10v, Pi = 10 ⁹ Ωcm, L _BC = 200n
m, S _BC = 5 × 10 ³ μm ² . Here, S _BC is because the collector size is 100 μm square and the effective area of the base is 1/2 of that. In this case, I _OFF is 2.5 μA.

Next, when the voltage of the emitter electrode (60) is set to V _BC + Vdiff or higher, holes are injected from the P-type semiconductor (9) and the semiconductor film (8) is filled with carriers composed of holes and electrons. . Assuming that the injection carrier concentration is 10 ¹⁶ cm ^-3 and the mobility is 1 cm ² / V · S, the resistivity in the injected state is about 600 Ωcm. Therefore, the ON current IoN can be calculated using the same form of equation (2), and IoN of 40 mA is obtained.

However, these figures are for the ideal case, and are actually slightly lower than the above figures. One of the causes is that the carrier diffusion length is very short in amorphous silicon. The actual carrier diffusion length L _D is considered to be approximately 1 μm, and therefore the P-type semiconductor (9)
The holes injected from pass through the hole portion or groove portion of the base electrode and do not completely wrap around to the collector electrode side (between the base electrode and the collector electrode), and a region like a shadow of the base electrode is formed. This is a phenomenon in which the carrier concentration decreases in the shaded area. In order to reduce this phenomenon, it is necessary to make the semiconductor film (8) thinner than the carrier diffusion length as described above, and to keep the width of each base electrode to be less than twice the carrier diffusion length, which requires a certain degree of fine processing. To be done. However, even if the width of the base electrode is designed to be 5 μm as in the above embodiment, this phenomenon causes the IoN to be 15 m.
It only deteriorates to about A level. Another cause is that the emitter electrode has a higher potential than the base electrode, so that part of the emitter current flows into the base electrode, and eventually the current value flowing from the base electrode to the collector electrode appears to decrease. If the width and spacing of the base electrode are designed to be the same, about half of the emitter electrode will flow into the base. Now the distance between the base electrode and the P-type semiconductor is 100 nm,
If the base-to-base voltage is 2V, the emitter current is about 16mA, so about 8mA flows into the base. This results in an IoN of approximately 7mA.

For comparison, a-Si TF with a gate length of 5 μm within 100 μm square
Trial calculation of ON current when T is created is V _D = 10v
It is about 0.2 mA as μeff = 1 cm ² / VS.

Therefore, the thin film transistor of the embodiment of the invention is
The result is that the ON current is about 30 times higher than that of the TFT. That is, the effect is remarkably improved by the RC time constant which is a factor that determines the transistor operation speed. If IoN = 8mA
The ON resistance is about 1200Ω, and the time constant is as fast as 60ns even when driving a 50pF load. Another factor that determines the operating speed of the transistor of the invention is the carrier generation / annihilation speed, which is about 200 ns.
I know from the experiment of in diode. From the above, it can be seen that the speed of the transistor of the present invention is 260 ns in amorphous silicon, and therefore a logic circuit operation of 2 MHz or higher can be expected. This is 50 times faster than the conventional 20kHz operation. Next, regarding the change over time, the transition to the ON state occurs when the voltage of the emitter electrode is V _BC + Vdi
It is determined whether it is above or below ff, and it is determined from the band gap of the semiconductor itself, so it does not change unless the semiconductor changes. Therefore, the threshold voltage as in the conventional example
No major fluctuations in V _TH occur.

FIG. 6 shows another example of the invention which performs the same operation as described above.

In this example, the side walls of the base electrodes (61a) to (61d) are also covered with the insulating films (63a) to (63d), so that the hole current injected from (9) is prevented from flowing into the base. The structure is such that the contribution to the degree modulation region is not impaired.

The thin film transistor that the present inventor previously applied is ON
Although the thin film transistor is improved in that it can take a large current, is fast, and has little change over time, it has a problem that the transition voltage to the ON state of the device is not always determined by V _BC + V diff. This is the base (61a) ~ (6
Current is flowing from 1d) to the collector (62) even when it is OFF, and this is because a potential distribution is generated inside the n ^{− type} semiconductor (8). FIG. 7 shows this state. (The potential inside the n ^{− type} semiconductor (8) is shown in the broken lines (100a) and (100b).) Assuming that 10 V is applied as V _BC , the broken line (100a) is 3.3 V and the broken line (100 b is 100 b). ) Corresponds to an equipotential line of 6.7V.

From this, the central portion of the P-type semiconductor (9) feels a potential of about 5V in this figure. For this reason, the ON transition voltage of this device is a value obtained by adding the diffusion potential Vdiff to this 5V, which is the original V _BC + Vdiff and is decreasing. The amount of ON voltage drop from V _BC + V diff changes considerably depending on the size and shape of the hole. In particular, the smaller the hole, the smaller the drop.

This phenomenon indicates that when the device is actually manufactured, if the width of the hole varies from device to device due to variations in etching and the like, this appears as a change in ON voltage. Further, if the ON voltage drop is to be suppressed to a small level, it is necessary to make the hole small, that is, to perform finer processing, which is more difficult in manufacturing.

The present invention relates to, for example, the n ^{− type} semiconductor layer (8) and the n ^{+ type} semiconductor layer (72) of the thin film transistor shown in FIGS. 5 and 6 above.
Be implemented in the form of such sandwiching the P-type semiconductor layer (110) between, according to the present invention can be extremely small OFF current, thereby the n ^- type semiconductor layer (8) inside the potential Can be almost uniformly V _BC . As a result, it is possible to eliminate the ON voltage drop that was a problem in the past.
Between devices due to variations in device etching
ON voltage variations can be reduced.

Hereinafter, the present invention will be described in more detail based on examples.

〔Example〕

Example 1 In FIG. 1, (1) is a substrate (62), (61
a) to (61d) and (60) are wiring metal films (72) and (71a)
To (71d) are n ^{+ type} semiconductor films, (8) and (111) are n ^{− type} or intrinsic type semiconductor films, (9) and (110) are P type semiconductor films, and (63a) to (63d) are insulating films. Is.

This example is different from the thin film transistor of FIG.
The feature is that a P-type semiconductor (110) [L] and an intrinsic semiconductor (111) [M] are added. Object n of the P-type semiconductor (110) ^- in eliminating the OFF current between the type semiconductor (8) to reverse bias. The intrinsic layer (111) is a P-type semiconductor film (110) and an n ⁺ layer (11).
The Pn junction with 1) is provided to reduce the leak current, and is not always necessary.

The operation of this embodiment will be described below. Base electrode (61a)
Voltage (V _BC) is applied between (61d) and collector electrode (62) to control the voltage of the emitter electrode (60) to turn ON / OFF between the base and collector. This is basically the same as the operation described above. However, since the P-type semiconductor film (110) is included as compared with the thin film transistor of the prior application, the P-type semiconductor film (110) and the n ⁻ -type or intrinsic-type semiconductor film (8) are reverse-baked, and the electron current is It is stopped at the P-type semiconductor film (110). As a result, in the OFF state, the base (61a) to (61d) to the collector (6
Almost no current flows in 2). Semiconductor film (110) (11
1) Since only the reverse leakage current of the pn junction formed in (72) flows, the OFF current can be kept extremely small. On the other hand, in the ON state, holes are injected from the P-type layer (9), but since the P-type layer (110) does not serve as a barrier against holes, the injected holes are N-type layers (72). ) Is reached. On the other hand, electrons are back-injected from the N-type layer (72) by the amount that cancels the positive charges of the injected holes. Therefore, both electrons and holes are accumulated in the three layers of the semiconductor films (8) (110) (111), and the resistivity is extremely reduced. This is exactly the same as the operation described in the conventional example. The ON current is the same as in the conventional example. That is, since the OFF current can be suppressed to almost zero, the ON / OFF ratio can be considerably increased.

On the other hand, the hole current injectable voltage from the P-type layer (90) of the emitter does not fluctuate inside the device because the OFF current is almost zero and becomes V _B + V diff.

Therefore, the problem in the thin film transistor of the prior application is solved.

Another example of the present invention is shown in FIG. This corresponds to FIG. 6 of the conventional example, and the operation is exactly the same as above.

A manufacturing process for actually realizing the structure described in the present invention will be described.

FIG. 3 shows the manufacturing process of the embodiment shown in FIG. First, a metal film (62) is deposited on the substrate (1) and a pattern is formed by photoetching. (Fig. 3 (a)) After this, n ⁺ a-Si layer (72), ia-Si layer (111), P ⁺ a-Si
The layer (110) and the ia-Si layer (8) are sequentially formed. (FIG. 3 (b)) Further, an n ⁺ a-Si layer, a metal film, and an insulating film are formed, and these three layers are patterned by photoetching. Now (71
a) A plurality of sets of (61a) and (63a) are formed (3rd
(Fig. (C)) On top of this, ia-Si (8), P ⁺ a-Si (9), metal film (6
0) is formed and finally photo-etched to form a device. (FIG. 3 (d)) Next, FIG. 4 shows a manufacturing process of the embodiment shown in FIG.
The processes up to (a), (b) and (c) are as described in FIG. An insulating film (63e) is formed on the state of FIG. 4 (c) (FIG. 4 (d)), and only the flat portion of this film is removed by anisotropic etching such as reactive ion etching. As a result, (63e) remains only on the side walls of (63a), (61a), (71a), etc., and is combined with (63a) to (63d).
a) It will be shaped to cover (61a) etc. After this, P ⁺ a−Si
(9), a metal film (60) is formed, and finally photoetching is performed to form a device (FIG. 4 (e)).

As described above, whichever structure is adopted, it can be manufactured by a relatively simple process.

The description so far has been made with the a-Si semiconductor in mind, but the present invention can obtain exactly the same operation even if not only this semiconductor but also polycrystalline Si crystalline Si or a compound semiconductor is used.

The above-described embodiments have been described with respect to the case where the P-type semiconductor film is set on the substrate side or the case where the collector electrode is set to the substrate side, but the same applies to the case where they are set oppositely.

Further, the P-type semiconductor film of the hole injection source is used as the emitter electrode, but the same is true even if the n-type semiconductor film of the electron injection source is used as the emitter electrode. However, in this case, the semiconductor film (8) is a P-type semiconductor film or an intrinsic semiconductor film, and the bias voltage is also reversed, so care must be taken.

Further, in the above embodiment, the semiconductor film D, the insulating film E, the insulating film G, the intermediary films H and I for ohmic contact, the high conductive film J, etc. are provided, but they are omitted depending on the required characteristics and material of the thin film transistor. It is also possible to do this. In particular, as the high conductive film (61) (base electrode), the n ^{− type} semiconductor film (8) can be ohmic contacted, and the P type semiconductor film (9) can be made of a high conductive film capable of Schottky junction to simplify the structure. You can

〔The invention's effect〕

According to the present invention, it is possible to eliminate the variation in the transition voltage to the ON state of a device, which is a problem in a thin film transistor that performs ON / OFF switching operation using injected carriers, and accurately set the voltage to V _BC + V diff. it can.
At the same time, the OFF current can be extremely reduced and the ON / OFF ratio can be made sufficiently large.

[Brief description of drawings]

FIG. 1 is a schematic sectional view showing the structure of a thin film transistor of the present invention prepared in an embodiment, FIG. 2 is a schematic sectional view of another embodiment, and FIGS. 3 and 4 are the aforementioned FIG. 1 and FIG. Sectional drawing showing the manufacturing process of the thin film transistor of the example shown in FIG.
FIGS. 5 and 6 are schematic cross-sectional views showing the structure of the thin film transistor previously applied, FIG. 7 is a diagram showing potential distribution of the thin film transistor shown in FIG. 5, and FIG. 8 is a schematic structure of a conventional TFF. FIG.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI technical display location H01L 29/786

Claims (10)

(57) [Claims] 1. A collector electrode made of a first high conductive film A, and a semiconductor having a first conductivity type provided on the first high conductive film A and having an impurity introduced at an intrinsic or low concentration. A film B; a base electrode made of a second high conductive film C provided on the semiconductor film B and having holes or grooves; an insulating film G provided on the base electrode; and an insulating film G A semiconductor film D having a first conductivity type, which is provided above and in the holes or trenches and has an intrinsic or low concentration impurity introduced; and a semiconductor film D provided on the semiconductor film D and having a high concentration impurity A thin film transistor comprising: a semiconductor film F having the introduced second conductivity type; and an emitter electrode provided on the semiconductor film F and made of a third high conductive film J, comprising: Membrane A and the semiconductor A semiconductor film K having a second conductivity type provided on the first high conductive film A between the first and second conductive films B, or an intrinsic or low concentration film provided on the first high conductive film A. A semiconductor film M having a first conductivity type into which impurities are introduced; and a semiconductor film M provided on the semiconductor film M.
And a semiconductor film L having a conductivity type of 1. 2. A gap between voids or grooves in the high conductive film C is set to be smaller than twice the extension length LD of carriers injected from the semiconductor film F into the semiconductor film B. 1. The thin film transistor according to item 1. 3. The semiconductor film B has a thickness equal to that of the semiconductor film F.
The thin film transistor according to claim 1, wherein the thin film transistor has a diffusion length LD thinner than that of carriers injected into the semiconductor film B. 4. The thin film transistor according to claim 1, further comprising an intermediary film H for ohmic contact provided between the high conductive film C and the semiconductor film B. 5. An intermediary film I for ohmic contact is provided between the first high conductive film A and the semiconductor film K, or between the first high conductive film A and the semiconductor film M. The thin film transistor according to any one of claims 1 to 4 of the appended claims. 6. A collector electrode made of a first high conductive film A, and a semiconductor having a first conductivity type provided on the first high conductive film A and having an impurity introduced at an intrinsic or low concentration. A film B; a base electrode made of a second high conductive film C provided on the semiconductor film B and having holes or grooves; an insulating film E provided on the base electrode and on the side wall; A semiconductor film F provided on the film E and in the holes or grooves and having a second conductivity type in which impurities are introduced at a high concentration; and a third high conductive film provided on the semiconductor film F. A thin film transistor comprising: an emitter electrode made of J; and a second conductivity type provided on the first high conductive film A between the first high conductive film A and the semiconductor film B. Or a semiconductor film K having: A semiconductor film M provided on the film A and having a first conductivity type into which impurities are introduced intrinsically or at a low concentration; and a semiconductor film M provided on the semiconductor film M and a second film
And a semiconductor film L having a conductivity type of 1. 7. A gap between voids or trenches in the high conductive film C is set to be smaller than twice an extension length LD of carriers injected from the semiconductor film F into the semiconductor film B. 6. A thin film transistor according to item 6. 8. The thickness of the semiconductor film B is equal to that of the semiconductor film F.
The thin film transistor according to claim 6 or 7, which is thinner than a diffusion length LD of carriers injected from the semiconductor film to the semiconductor film B. 9. The thin film transistor according to claim 6, wherein an ohmic contact mediating film H is provided between the high conductive film C and the semiconductor film B. 10. The first high conductive film A and the semiconductor film K.
Or between the first high conductive film A and the semiconductor film M.
The thin film transistor according to any one of claims 6 to 9, wherein an intermediary film I for ohmic contact is provided between and.