JP2529650B2 - camera - Google Patents

Description

Description: FIELD OF THE INVENTION The present invention relates to an improvement in a camera capable of issuing an instruction to start charging a strobe in advance when the release button is unlocked.

(Background of the Invention) In a conventional camera that automatically charges a strobe, a distance measurement operation and a photometry operation are performed when an actual release operation is performed, and charging is started after determining the result, so charging is completed. There was a problem such as a long release time lag until the release.

In consideration of this point, there is also a system that starts strobe charging at the moment when a release lock switch such as a barrier switch or a main switch is switched from an off state to an on state. Each time the battery is charged, the battery is charged each time, which causes inconvenience such that the battery is consumed quickly.

(Object of the Invention) An object of the present invention is to solve the above-mentioned problems and to provide a camera capable of preventing a long release time lag and wasteful power consumption. .

(Characteristics of the Invention) In order to achieve the above object, the present invention according to claim 1 has a releasing means for releasing a release lock state and a measuring means for measuring a signal related to a distance to a subject. By the flash photography preparation means for controlling the charging of the flash and the release lock release operation of the release means,
An operation control unit that operates the measurement unit and operates the strobe photographing preparation unit according to the measurement result,
Therefore, when the release lock state is released, the signal related to the distance to the subject is measured regardless of the release operation, and the flash is charged when the measurement result indicates the flash shooting conditions. It is characterized by doing so.

Further, in order to achieve the above object, the present invention according to claim 2 performs a release means for releasing the release lock state, a photometric means for measuring the brightness of an object, and a strobe charge control. It has a strobe photographing preparation means and an operation control means for operating the photometric means by a release lock releasing operation of the releasing means and operating the strobe photographing preparation means according to the measurement result, whereby the state of the release lock When is released, the brightness of the subject is measured irrespective of the release operation, and the strobe is charged when the measurement result indicates the strobe photographing condition.

(Embodiment of the Invention) FIG. 1 is a block diagram showing an embodiment of the present invention.

Switch means 101 having the function of releasing the locked state of the release button such as the main switch or barrier switch
When the operation is detected, the operation control means 102
First, the battery check means 103 is operated in order to guarantee the power supply voltage for the subsequent operation.
If it is determined that the power supply voltage level is sufficient, the distance measuring means is immediately irrespective of the operation of the release button.
104 and the photometric means 105 are operated to obtain the distance information to the subject and the luminance (EV value) information of the subject, and whether or not the photographing that requires stroboscopic light, that is, the macro photographing or the low luminance photographing is performed. Make a distinction. As a result, when it is determined that it is during macro photography or low-luminance photography, a strobe charging preparation unit 106 is instructed to charge the strobe, and the strobe photography associated with the subsequent release button operation can be immediately performed.

FIG. 2 is a block diagram showing a concrete configuration example of the camera of the embodiment. In the figure, 1 is a CPU, 2 is a switch interface, 3 to 18 are various mechanical switches in the camera, 19 is a strobe control circuit, 20 is a flash discharge tube, and 21 is a flash discharge tube.
A / D converter, 22 is an analog multiplexer, 23 is a photometric circuit, 24 is a photometric sensor, 25 to 28 are adjustment volume resistors, 29, 31 are current limiting resistors, 30, 32 are LEDs, 33 is a distance measuring circuit, 34 is iRED (infrared light emitting diode), 35 is a light receiving element (distance measuring sensor), 36 is a film counter driver, 37 is a film counter, 38 is a motor driver, 39 is a motor,
40 is a plunger driver, 41 is a plunger, 42 is a photocoupler detection circuit, 43 is a photocoupler light receiving element, 44
Is a photocoupler LED, 45 is a pulse plate, and 46 is a battery check circuit.

3 to 7 show the inside of each circuit shown in FIG. 2, and FIG. 3 shows the motor driver 38, the plunger driver 40, the photocoupler detection circuit 42, and the battery check circuit 46. FIG. 4 shows the switch interface 2 for transmitting the inputs of the mechanical switches 13 to 18 used in this camera to the CPU 1, FIG. 5 shows the distance measuring circuit 33, and FIG. 6 shows the A / D converter 21 and photometry. FIG. 7 of the circuit 23 shows a specific configuration example of each strobe control circuit 19. Further, FIGS. 8 and 9 show a basic flowchart of this system, and FIG. 10 shows a timing chart at the time of the distance measuring operation.

The operation will be described below with reference to the flowcharts of FIGS. 8 and 9.

First, in step 680, the state of the flag MAINONL that stores the state before the main switch is checked. This flag is set to "1" at the time of initial reset.
In this initial stage, proceed to step 685 and select the main switch (M
AINSW) status detection. Here, the main switch corresponds to the switch 3 in FIG. 4, and the CPU 1 proceeds to step 685 for detecting its state via the switch input circuit 80 in the switch interface 2.

If it is determined in step 685 that the main switch is off, the release operation is prohibited, so the flag MAINONL is reset to "0", and a fixed time for absorbing chattering of the main switch is set. After waiting in step 687, the process proceeds to step 691. Steps 691 to 702 detect the conditions of film rewinding (MRSWON) and idle feeding (ALEND). If neither condition is satisfied, the process returns to SWWAIT again (detailed description is omitted). On the other hand, if it is determined that the main switch is on, the release operation is not prohibited, so the state of SW1, the self switch (SELFSW) is checked next. Here, the SW1 and the self-switch correspond to the switches 4 and 6 in FIG. 4, and the CPU 1 takes in the state through the switch input circuit 80. However, when the SW1 is on, the process immediately proceeds to step 703. If the self-switch is on, set the flag SELFL to "1" and step 7
If the switch SW03 and the self switch are both turned off in step 03, the process proceeds to step 691. In steps 703 to 708, the state of the valve switch (BULBSW) and the tele wide switch (T / WSW) is latched as a release preparation operation. Here, the valve switch and the tele wide switch correspond to the switches 11 and 12 in FIG. 4, and the CPU 1 takes in the state through the switch input circuit 82. If the valve switch is turned on in step 703, the flag BULBL is set to "1" as the valve mode is set, and if it is turned off, it is reset to "0". or,
If the tele / wide switch is on, the tele state is set, and the flag T / WL is set to "1". If the tele / wide switch is off, the wide state is set. Reset to "0".

Next, in step 720 (see FIG. 9), a battery check operation is performed to guarantee the voltage level of the entire system. The operation at this time will be briefly described with reference to FIG. 3. When the PLG output of the CPU1 becomes H level (meaning high level), the transistor 285 is turned off via the inverter 286 and the resistor 287, and the operational amplifier 280, Resistance 282
~ 284, transistor 281 and other plunger driver 40 (see FIG. 3) is enabled, and energization of plunger 41 is started. Since a large current flows through the plunger 41, the power supply voltage drops, but this power supply voltage can be detected to detect whether or not it has a level value equal to or higher than a predetermined level. FIG. 3 shows a configuration example for realizing this. Battery check circuit 46
Then, a value obtained by dividing the power supply voltage VCC by the resistors 320 and 321 is compared with the reference level VC by the comparator 322, and when it becomes lower than the reference level VC, an H-level output BCNG indicating that it is below a predetermined level is generated. Therefore, the CPU 1 determines the power supply voltage state at this time from the output. If an H-level output BCNG input is detected during the specified period, CP
U1 sets the output PLG to L level (meaning low level), immediately stops energizing the plunger 41, prohibits the subsequent sequence from proceeding, and detects that SW1 is off (step 722). Return to SWWAIT. When the input of the H-level output BCNG is not detected even after the lapse of a predetermined period, the energization of the plunger 41 is similarly stopped, and then the process proceeds to step 723 to start the distance measuring operation.

Regarding the distance measuring operation performed in step 723,
This will be described with reference to the distance measuring circuit 33 shown in the figure and the timing chart of FIG. CPU1 and distance measuring circuit 33 have four signal lines AFE,
Communication is performed through SCK, SDO, and SDI, and the H level is first input from the CPU 1 through the signal line AFE, so that the AF control logic 150 in the distance measuring circuit 33 starts the distance measuring operation. While the L level is being input through the signal line AFE, the AF control logic 150 is in the reset state, and each signal processing system is set to the initial state. next
A serial synchronization clock is input from the CPU 1 through the signal line SCK, and at the same time, the first status data (4 bit data in FIG. 10) is input through the signal line SDO in synchronization with the falling edge thereof. Normally, the H level is input through the signal line SDO, and the first 2 bits of the status data transferred thereafter represent the start bit at the L level and the remaining 2 bits represent the status contents. When a signal as shown in FIG. 10 is input through the signal line SCK and the signal line SDO, the AF control logic 15
0 generates an iRON signal obtained by dividing the serial synchronous clock by 1, and outputs the iRON signal to the operational amplifier 151, the transistor 152,
Output to the iRED driver composed of resistors 153 and 154. As a result, the iRED34 is AC-driven at a constant cycle (iRED34 lights up when the iRON signal is at the H level, iRED34 goes out when the iRON signal is at the L level). When all 4-bit status data has been input, the output SPL1 goes high in synchronization with the lighting state of the iRED34 in order to set the rising integration status.
To level.

Here, the infrared light emitted from the iRED 34 is reflected by the object surface and enters the light receiving element 35, where it is converted into a signal current and becomes Ia and Ib. Based on the principle of triangulation, the position of incident light on the light receiving element 35 differs depending on the distance from the camera body to the subject, and the current distribution ratio of Ia and Ib changes depending on this incident light position, so (Ia-Ib) / ( The value of (Ia + Ib) has a one-to-one correspondence with the distance from the camera body to the subject. The signal current Ia generated by the light receiving element 35 is converted into a signal voltage Va by a current-voltage converter composed of an operational amplifier 155 and a resistor 156, and a direct current component is further cut by a capacitor 157, and then a subtraction circuit 161, It is input to the adder circuit 162. Similarly, the signal current Ib is converted into a signal voltage Vb by a current-voltage converter composed of an operational amplifier 158 and a resistor 159, and the direct current component is further cut by the capacitor 160, and then input to the subtraction circuit 161 and the addition circuit 162. To be done. The value of (Va-Vb) is calculated in the subtraction circuit 161, and this output is input to the integrator composed of the resistor 165, the operational amplifier 166, and the capacitor 167 through the analog switch 163. On the other hand, in the addition circuit 162, (Va + V
The value of b) is calculated and this output is input to the integrator through the analog switch 164. Since the analog switch 163 is turned on by the H level of the output SPL1, the subtraction circuit 161
Output is integrated in synchronism with the H level signal of the output SPL1, and as shown in FIG. 10, the output of the integrator iN
TOUT rises above the reference level KVC. At this time, the CPU 1 measures the integration time by an internal timer (not shown), and when the predetermined time is reached, the next status data is transferred again through the signal line SDO. The status data at this time indicates the interval mode setting. Therefore, in this case, the AF control logic 150 outputs the outputs SPL1, SPL2.
Are both fixed at the L level to form an integration stop time (interval period).

If the above status continues for a predetermined time, the signal line from CPU1
The next 4-bit status data, that is, the data for setting the status of falling integration is transferred through SDO. As a result, the AF control logic 150 sets the output SPL2 to the H level in synchronization with the extinguished state of the iRED34 (see FIG. 10). Therefore, the output of the adder circuit 162 is integrated by the integrator. However, since the output SPL2 is 180 ° out of phase with the output SPL1, the output of the integrator i
NTOUT falls. When the integration in this direction proceeds and the output iNTOUT of the integrator becomes lower than the reference level KVC, the output AFCOMP of the comparator 168 becomes H level, and this signal is output to the CPU1 side through the AF control logic 150 and the signal line SD1. The CPU1 stops the internal timer started at the start of the falling integration and stores the contents in an internal register (not shown), and at the same time, sends the next status data (data indicating the end of integration) to the AF control logic 150 through the signal line SDO. Transfer. AF control logic
At the same time that the 150 receives this status data, iRON
Stops signal output to stop driving iRED34 and then outputs
Both SPL1 and SPL2 are set to the L level to complete the integration operation.
Further, the CPU 1 uses the value (fall integration time) stored in the internal register as described above to specify the tooth information for actually controlling the lens (for example, the maximum integration time of the down integration is 20 ms.
c is “1” when the actual integration time is 0 to 2 ms, 2 to 4
In msc, it is converted to "2" and stored in RAM (not shown). At this time, the CPU 1 outputs the L level through the signal line AFE, and ends the distance measuring operation (and the AF control based on the distance measuring result) in step 723 of FIG.

When the distance measuring operation in step 723 is completed, the process proceeds to step 724 to start the photometric operation. This photometric operation will be described with reference to FIG. First, the photometric circuit 23 is a photometric sensor 24 that is converted into photocurrent according to subject brightness information.
The output of the above is converted into a voltage by a compression circuit composed of an operational amplifier 180 and a compression diode 181, and then this output is canceled by a diode 182 and a constant current source 184 due to the reverse saturation current. Temperature-sensitive resistance 185, resistance 18
Input to the non-inverting amplifier composed of 6 to obtain the photometric output AEOUT that has no temperature coefficient. On the other hand, when the ADE output from the L level to the H level is input from the CPU 1 to the A / D converter 21, the latch circuit 198 and the counter 20 are passed through the inverter 199.
0, the reset state of the shift register 203 is released, the counter 200 starts the counting operation of the CLOCK input, and the output of the counter 200 is passed through the decoder 201, the latch circuit 198, and the inverters 190 to 197 to the analog switch and the ladder. Input to the D / A converter 188 composed of resistors
The analog signal D / AOUT based on the value of 198 is output.
Further, when the MLSELECT signal is applied from the CPU 1 to the analog multiplexer 22, the analog multiplexer 22 transmits the photometric output AEOUT to the non-inverting input of the comparator 189.
The comparison result of the comparator 189 is successively input to the latch circuit 198 and the shift register 203. After that, when the counter 200 counts 8 pulses of the CLOCK input, the value obtained by A / D converting the photometric output AEOUT is shifted. It is stored in the register 203. The shift register 203 sets the ADEND output to H level when all the 8-bit data is set.

The CPU 1 detects the output, captures A / DDATA as a photometric output, returns the ADE output to the L level, and ends the A / D operation. The CPU 1 converts this A / D conversion data into EV information (for example, classifies every 0.25 steps, EV40 "40", 10.25 "41", etc.) and stores it in the internal RAM.

When the photometric operation is completed, the routine proceeds to step 725, where it is judged whether or not the valve mode is set. If the flag BULBL is set to "1", then the routine proceeds to step 726 and whether a film is loaded or not. Make a decision. If the film is loaded normally and the specified number of blank feed operations are completed, the flag FSETL is set to "1" and the internal state of the film is set. Although the process proceeds to step 733, if the film is not loaded or the specified number of blank feed operations are not completed, the flag FSETL is reset to "0", and thus the distance measurement result obtained in step 723 is It becomes invalid, and the value "f" in the tele state and the value "g" in the wide state are written in the RAM storing the designated AF tooth in step 729 or step 728. In the above valve operation, the AF control differs depending on whether or not there is a film, but in these cases, the process proceeds to step 733, so charging of the strobe and light emission are prohibited, and the flag FAL is reset to "0".

If it is not in the bulb mode, the process proceeds to step 730. Here, if the AF distance measurement result is closer than a predetermined distance, it is determined to be macro photography, and strobe photography mode is set. When not macro shooting, next is the actual photometric value, DX code value, T / W
From the state of (3), it is determined whether or not stroboscopic photography is necessary at a low alarm level. Hereinafter, the time of determination of the low alarm level will be described. The content of the RAM stored in advance is the value of photometric data = photometric value × 4. For example, if EV = 9, 36 (9 ×
It becomes the value of 4). To simplify the ISO value of the DX code, only the upper 3 bits are read and stored every other row,
For example, when ISO = 50, the value is “1”, and when ISO = 100, the value is “2”, which is the value of ISO data = ISO × 4. The T / W data is expressed in the form of a shift in the number of steps due to the difference in aperture F-number between tele and wide. For example, if the wide is 1.5 steps brighter than the tele, then T / W data = 1.5 x 4 = 6 (wide Time) T / W data = 0 (when tele). Therefore, these values are added to calculate AE data = photometric data + ISO data + T / W data. If this value is smaller than the specified value, it is determined that the alarm is low and the flash photography mode is set. For example, EV = 9,
If the low alarm level is set at ISO = 100, wide, this value becomes 9 × 4 + 2 × 4 + 6 = 50. Therefore, if the calculated AE data result is “50” or less, the flag FAL is set to “1” in step 734. And set the flash mode, and if it is larger than "50", step 733.
Reset the flag FAL to "0" with and set to AE shooting mode. When the flash shooting mode is set, the flash charging is started as a preparatory operation.

Next, the operation during the strobe charge control performed in steps 735 to 738 will be described with reference to FIG. When the FLBiT terminal of the CPU1 changes from the on state to the off state, this terminal becomes high impedance, and the oscillation stop circuit formed by the transistor 223 and the resistors 224 and 225 is turned off. Here, when the CGCOM terminal of CPU1 is turned on, oscillation transformer 229, transistor 220, resistor 221, capacitor 222
The oscillating circuit constituted by is brought into an enabled state, and the charging of the main capacitor 243 is started via the smoothing diode 228. The CPU 1 starts an internal timer simultaneously with the start of charging, and determines whether or not the main capacitor 243 reaches a predetermined level until this timer reaches a predetermined time. The charging level of the main capacitor 243 is higher than the Zener voltage of the Zener diode 233 and the resistance 232,234,235
When the CGUP pin reaches a predetermined voltage level from the GND level through, the CPU1 detects that the charge has reached a predetermined level, stops the oscillation by setting the CGCOM pin to high impedance and the FLBiT pin to the ON state. If the internal timer of the CPU1 reaches the predetermined time (the longest charging time) even though the charge has not reached the predetermined level, the CGCOM pin is immediately set to high impedance and the FLBiT pin is turned on to oscillate. Stop and stop strobe charging. The transistor 23
1 is an overcharge protection circuit for automatically stopping charging when the voltage reaches a predetermined level.

When the charging of the strobe is completed, the process proceeds to step 739, and the state of the flag SPCHL is determined. This flag SPCHL is set to "1" by turning the main switch from off to on.
Is set to, so if this is set,
It is assumed that the sequence has not advanced due to the normal release operation, the flag SPCHL is immediately reset to "0", and the process returns to SWWAIT. Also, the flag SPCHL
Is reset to “0”, it is determined that SW1 or the self switch is turned on while the main switch is already turned on, and the sequence is advanced without returning to SWWAIT.

According to this embodiment, when the main switch is turned on from off, the flag SPCHL is set to "1" to perform the battery check, and then the distance measuring operation and photometry are performed regardless of the release button operation (SW1 operation). By performing the operation, it is judged whether the result is a flash shooting condition, and the flash charging operation is started only when the flash shooting condition is satisfied, so that unnecessary charging is prevented and the time lag at the actual release is set. It is possible to provide a camera that can satisfy both requirements such as shortening the length.

(Correspondence between Invention and Embodiment) In the embodiment shown in FIG. 2, the main switch (switch 3) serves as the releasing means of the present invention, the distance measuring circuit 33, iRED34, and the light receiving element 35 serve as the measuring means, and the A / D converter 21 Photometric sensor 34
Up to the photometry means, the flash control circuit 19 corresponds to the flash photographing preparation means, and the CPU 1 corresponds to the operation control means.

(Effects of the Invention) As described above, according to the present invention as set forth in claim 1, the releasing means for releasing the state of the release lock, and the measuring means for measuring the signal related to the distance to the subject. By the flash photography preparation means for controlling the charging of the flash and the release lock release operation of the release means,
An operation control unit that operates the measurement unit and operates the strobe photographing preparation unit according to the measurement result,
Therefore, when the release lock state is released, the signal related to the distance to the subject is measured regardless of the release operation, and the flash is charged when the measurement result indicates the flash shooting conditions. As a result, it is possible to prevent the release time lag from becoming long and useless power consumption.

According to the present invention described in claim 2,
Release means for releasing the state of the release lock, photometric means for measuring the brightness of the subject, strobe shooting preparation means for charging control of the strobe, and release lock release operation of the release means to operate the photometric means, It has an operation control means for operating the stroboscopic photographing preparation means according to the measurement result, so that when the release lock state is released, the luminance of the subject is measured regardless of the release operation, and the measurement is performed. When the result indicates the conditions for stroboscopic photography, the strobe is charged, so that it is possible to prevent the release time lag from becoming long and useless power consumption.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a concrete block diagram for realizing the camera shown in FIG. 1, and FIG. 3 is a motor driver, a plunger driver shown in FIG. FIG. 4 is a circuit diagram showing a configuration example of a photocoupler detection circuit and a battery check circuit, FIG. 4 is a circuit diagram showing a configuration example of a switch interface shown in FIG. 2, and FIG. 5 is a configuration example of a distance measuring circuit shown in FIG. Circuit diagram, Figure 6 is the second
FIG. 7 is a circuit diagram showing a configuration example of an A / D converter and a photometric circuit shown in FIG. 7, FIG. 7 is a circuit diagram showing a configuration example of a strobe control circuit shown in FIG. 2, and FIGS. 8 and 9 are embodiments shown in FIG. The flowchart of the camera and FIG. 10 are timing charts during the distance measuring operation. 1 …… CPU, 3,4 …… Switch, 19 …… Strobe control circuit, 20 …… Flash discharge tube, 21 …… A / D converter, 32 ……
Analog multiplexer, 23 ... Photometric circuit, 24 ... Photometric sensor, 33 ... Distance measuring circuit, 34 ... iRED, 35 ... Photodetector, 101 ... Switch means, 102 ... Operation control means, 104
...... Distance measuring means, 105 ...... Photometric means, 106 ...... Strobe shooting preparation means.

Claims (2)

(57) [Claims] 1. A release means for releasing a release lock state, a measuring means for measuring a signal related to a distance to a subject, a strobe photographing preparation means for controlling strobe charging, and a release lock for the releasing means. A camera comprising: an operation control unit that operates the measurement unit by operation and operates the strobe photographing preparation unit according to a measurement result. 2. A release means for releasing the release lock state, a photometric means for measuring the brightness of an object, a strobe photographing preparation means for controlling the charging of a strobe, and a release lock release operation for the release means to perform the photometry. And an operation control unit that operates the strobe photographing preparation unit according to the measurement result.