JP2522293Y2 - Vertical deflection circuit - Google Patents

Description

[Detailed description of the invention] [Industrial applications]

The present invention relates to a vertical deflection circuit in a video display system such as a television receiver and a display monitor using a cathode ray tube (hereinafter referred to as CRT) and a deflection coil.

[Prior art]

FIG. 3 is a block diagram showing a conventional vertical deflection circuit, wherein 1 is a vertical synchronization signal processing section, 2 is an oscillation section to which an output signal of the vertical synchronization signal processing section 1 is supplied, and 3 is an output of the oscillation section 2. Wave generating circuit for generating a sawtooth wave synchronized with the
A vertical output amplifier for amplifying the output of the sawtooth wave generating circuit 3 using the output of the pump-up circuit 4 as a power supply, and one end connected to the output terminal of the vertical output amplifier 5 Vertical deflection coil, 7a is a capacitor directly connected to the vertical deflection coil 6, 8a is a capacitor
7a is a resistor connected between ground and 8b is a vertical deflection coil 6
8c is a resistor connected between the output terminal of the vertical output amplifier 5 and the ground via a capacitor 7b. Reference numeral 9 denotes a vertical deflection integrated circuit portion. Next, the operation will be described. When the vertical synchronizing signal is input, the oscillating unit 2 synchronizes with the vertical synchronizing signal.
Its oscillating frequency is the same as the vertical synchronizing signal. Further, the oscillating unit 2 outputs a signal with a fixed phase, and the saw-wave generating circuit 3 and the pump-up circuit 4 operate by this output. The sawtooth wave voltage generated in the sawtooth wave generating circuit 3 is converted into a current in the vertical output amplifier 5, and the converted current is supplied to the vertical deflection coil 6. Will flow to On the other hand, the pump-up circuit 4 serves as a power supply for the vertical output amplifier 5, and raises the power supply voltage Va as shown in FIG. 4 during a vertical blanking period (T _{R in} FIG. 4). As a result, as shown in FIG. 4, the level of the output voltage Vb of the vertical output amplifier 5 is greatly increased in the vertical blanking period. As a result, the charging current for the capacitor 7a during the vertical blanking period is increased, and the vertical deflection current waveform flowing through the vertical deflection coil 6 becomes stable. Here, a capacitor 7a for blocking DC and a resistor 8a for feedback are connected in series to the vertical deflection coil 6, and feedback and AC level, that is, peak value and waveform linearity for stabilizing the DC level are corrected from this portion. Feedback is supplied to the sawtooth wave generating circuit 3 to stabilize the vertical deflection current. The vertical deflection circuit thus configured includes a vertical synchronization signal processing unit 1, an oscillation unit 2, a sawtooth wave generation circuit 3, a pump-up circuit 4, and a vertical output amplifier 5.
Is integrated as a semiconductor integrated circuit 9,
It is a one-chip IC.

[Problems to be solved by the invention]

The conventional vertical deflection circuit is organized as described above,
Most are all built into one-chip ICs. As a result, although space can be saved, IC
For example, there is a problem that it is difficult to shorten the retrace period due to, for example, increasing the breakdown voltage and the limit of the output current. The present invention has been made to solve the above-mentioned problems, and uses an integrated vertical deflection circuit,
It is an object of the present invention to obtain a vertical deflection circuit having a short retrace period.

[Means for Solving the Problems]

In the vertical deflection circuit according to the present invention, a power MOSFET is provided between a vertical output amplifier and a vertical deflection coil, and the power MOSFET is turned off at the beginning of a retrace period to reduce this power
When the current flowing through the OSFET becomes zero, the power MOS
Controls FET ON.

[Action]

The vertical deflection circuit in this invention is a power MOSFET provided between the vertical output amplifier and the vertical deflection coil.
Is turned off at the beginning of the vertical retrace period, the vertical retrace current rapidly changes toward zero, and the vertical retrace current changes by the amount of the rapid retrace current. Can be shortened.

[Example of the invention]

An embodiment of the present invention will be described below with reference to the drawings. In FIG. 1, reference numeral 10 denotes an enhanced channel power MOSFET as a switching element, which is connected between the output terminal of the vertical output amplifier 5 and the vertical deflection coil 6. Reference numeral 11 denotes a DC power supply connected between the gate of the power MOSFET 10 and the ground to apply a bias voltage to the gate of the power MOSFET 10. Reference numeral 12 denotes a parasitic diode that is parasitic inside the power MOSFET 10. Therefore, the difference between the circuit thus configured and the conventional circuit is that the power MOSFET
10 is provided between the vertical output amplifier 5 and the deflection coil 6. Next, the operation will be described. The gate voltage of the power MOSFET 10 is set lower than the voltage in the vertical blanking period shown in FIG. 4 and slightly higher than the vertical scanning start voltage Vc.
Therefore, the power MOSFET 10 is turned on during the scanning period, and the vertical deflection circuit performs the same operation as the conventional circuit. Next, in the retrace period, since the source of the power MOSFET 10 is connected to the output terminal of the vertical output amplifier 5,
The power MOSFET 10 is turned off. Power MOSFET10
Is turned off, the current flowing in the deflection coil 6 flows in a loop of the damping resistors 8b and 8c, the capacitor 7c, the resistor 8a, and the capacitor 7a, and the current rapidly becomes zero.
Then, when this current becomes zero, the vertical output amplifier 5 is driven by a parasitic diode 12 that is parasitic inside the power MOSFET 10.
And the deflecting coil 6 become conductive, so that the operation returns to the operation in the conventional circuit. That is, as shown in FIG. 2 (a), in the conventional vertical deflection circuit, the current Ia which varies uniformly during the retrace period of the output voltage Vb of the vertical output amplifier 5 flows. In the case of (2), when the power MOSFET 10 is turned off at the beginning of the retrace period, the deflection retrace current rapidly changes to zero as indicated by _{Ib in} FIG. 2 (b). After the deflection retrace current reaches zero, the power MOSFET 10 continues to be in the OFF state, but has a forward potential state with respect to the parasitic diode 12 that is parasitic inside the power MOSFET 10. , The deflection return current flows. Therefore, during the period from the start of the deflection retrace period to the time when the deflection retrace current reaches zero, the power MOSFET 10 is turned off, so that the deflection retrace current rapidly changes toward zero. The period is shorter in the case of the present invention shown in FIG. 2 (b) than in the conventional case shown in FIG. 2 (a).
The capacitor 7b and the resistor 8c are provided to prevent the power MOSFET 10 from being damaged by the back electromotive force of the vertical deflection coil 6, and are set in consideration of the withstand voltage of the power MOSFET 10. In the above embodiment, only the case where a power MOSFET is used as a switching element has been described. However, the present invention is not limited to this case. A switching element having any configuration may be used as long as it is controlled to be turned on when the current reaches zero.

[Effect of the invention]

As described above, according to the present invention, the gate of the power MOSFET provided between the vertical output amplifier and the vertical deflection coil is higher than the sawtooth vertical scanning start voltage output by the vertical output amplifier, The power MOSFET is turned off at the same time as the start of the vertical flyback period, and the vertical MOSFET is turned off by the generation of the back electromotive force of the vertical deflection coil. Since the voltage on the primary side of the deflection coil can be significantly increased, the time required for the current flowing through the vertical deflection coil to change from negative to zero can be extremely short, and the vertical flyback period can be extremely short. Further, since the forward deflection return current flows through the parasitic diode of the power MOSFET until the current flowing in the vertical deflection coil goes from zero to positive and reaches the peak of the sawtooth wave, no operational problem occurs. . Furthermore, there is an effect that the vertical flyback period can be shortened without adding any load to the vertical deflection circuit by adding only one power MOSFET.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a vertical deflection circuit according to an embodiment of the present invention. FIGS. 2 (a) and 2 (b) show conventional deflection voltage / current waveforms and deflection voltage / current waveforms in the circuit shown in FIG. FIG. 3 is a circuit diagram showing a conventional vertical deflection circuit, and FIG. 4 is an operation waveform diagram of each part of the circuit shown in FIG. 5 is a vertical output amplifier, 6 is a vertical deflection coil, 10 is power
MOSFET (switching element). In the drawings, the same reference numerals indicate the same or corresponding parts.

Claims (1)

(57) [Scope of request for utility model registration] In a vertical deflection circuit, a vertical output amplifier used in an image system using a cathode ray tube and outputting a sawtooth wave having an increased voltage only during a vertical retrace period is integrally formed as a semiconductor integrated circuit. A power MOSFET provided between the output amplifier and the vertical deflection coil, and a voltage set higher than the sawtooth vertical scanning start voltage output by the vertical output amplifier and lower than the voltage of the vertical flyback period. And a DC power supply for supplying the power to the gate of the power MOSFET.