JP2520148B2 - Transversal automatic equalizer and cross polarization interference canceller shared circuit - Google Patents

Description

The present invention relates to a combination circuit of an adaptive automatic equalizer and a cross polarization interference canceller in a receiver of a digital wireless communication system, and a transversal automatic equalizer TEQL and a cross polarization interference canceler. For the purpose of facilitating the manufacture and maintenance of XPIC, a common circuit consisting of the circuit parts common to the transversal automatic equalizer and the cross polarization interference compensator, and a unique circuit part consisting of different circuit parts, According to the function to be realized, a connecting portion for connecting the circuit portion corresponding to the specific circuit portion and the common circuit portion to each other, a signal means for indicating the type of the function realized as a result of the connection of the connecting portion, and an external circuit. A bidirectional bus for transmitting or receiving a signal between the two, and controlling the directivity by the signal means indicating the type of the function to be realized. , It constitutes a transversal automatic equalizer and cross polarization interference compensator shared circuit.

[Industrial applications]

The present invention relates to a combination circuit of an adaptive automatic equalizer and a cross polarization interference canceller in a digital wireless communication system.

[Conventional technology]

Most of the recent wired or wireless communication systems have an adaptive automatic equalizer in the receiving device in order to automatically correct the variation in the characteristics of the transmission line. Particularly in the case of digital wireless communication systems, the intersymbol interference component is removed using a digitalized transversal filter (DTF) type adaptive automatic equalizer (hereinafter referred to as transversal automatic equalizer TEQL).

Similarly, the receiver of a QAM (Quadrature Amplitude Modulation) type digital wireless communication system is equipped with a transversal film type cross polarization interference compensator (hereinafter referred to as XPIC) to eliminate intersymbol interference components between polarizations. are doing.

FIG. 9 shows a simplified configuration of a receiving device having both such TEQL and XPIC.

In Fig. 9, 1 and 2 are antennas for separately receiving radio waves of two systems of horizontal polarization and vertical polarization, and 3 and 4 are demodulators.
DEM, 5 and 6 are TEQL, 7 and 8 are XPIC, 9 to 12 are adders, I and Q and XI and XQ are two orthogonal channels Ch output from DEM3 and DEM4, respectively.

With such a configuration, the radio signal received by the system of the antenna 1 is demodulated by the DEM3, equalized and compensated by TEQL5, and then the compensating signals of the XPIC8 output are added by the adders 9 and 10,
It is output after cross-polarization interference compensation with the system of the antenna 2 is performed.

Similarly, in the system of antenna 2, the received radio signal is demodulated by DEM4 and equalized and compensated by TEQL6, and then the adder 11, 12 adds the compensation signal of XPIC7 output, and the system of antenna 1 It is output after cross-polarization compensation between and is performed.

Generally, TEQL or XPIC in the receiving device
Can be arbitrarily selected and inserted into the circuit only when necessary.

Figures 10 and 11 show TEQL and XPI in 16QAM, respectively.
A concrete example of C is shown. It is assumed that TEQL and XPIC are selected for simultaneous use.

The circuit elements shown in FIGS. 10 and 11 are as follows.

13: Element transversal automatic equalizer TEQL (Ich → Ich
Intersymbol interference compensation) 14: Transversal element equalizer TEQL (Ich → Qch)
Intersymbol interference compensation) 15: Transversal element equalizer TEQL (Qch → Ich)
Intersymbol interference compensation) 16: Element transversal automatic equalizer TEQL (Qch → Qch
Intersymbol interference compensation) 17: Digital adder (for Ich) 18: Digital adder (for Qch) 19: Digital adder (for XPIC compensation signal addition, Ich) 20: Digital adder (for XPIC compensation signal addition, Qch) 21: Polarity signal generation circuit (Ich) 22: Polarity signal generation circuit (Qch) 23: Error signal generation circuit (Ich) 24: Error signal generation circuit (Qch) 25: XPIC compensation signal input buffer (Ich) 26: XPIC compensation signal input buffer (Qch) 27: Error signal output buffer (Ich) 28: Error signal output buffer (Qch) 29: XPIC compensation signal output buffer (Ich) 30: XPIC compensation signal output buffer (Qch) 31: Error signal Input buffer (Ich) 32: Error signal input buffer (Qch) SI: Polarity signal (Ich) SQ: Polarity signal (Qch) EI: Error signal (Ich) EQ: Error signal (Qch) CI: Compensation signal (Ich) CQ : Compensation signal (Qch) The TEQL shown in Fig. 9 is a composite configuration of four TEQLs 13 to 16. The control method of each TEQL is as follows. Sex signal SI, SQ
Modified zero forcing (MZ
F) method is used. By using these polarity signals SI and SQ and the error signals EI and EQ, the gain of each variable tap (not shown) in each of TEQL 13 to 16 is coded by the signal at the time corresponding to the distance from the center tap. The inter-symbol interference is adjusted so that it is canceled, and automatic control is performed so that the sum of absolute values of inter-symbol interference becomes zero. For this, SI, SQ indicating the signal polarity and EI, EQ indicating the error amount are used. As a result, in each of TEQL 13 to 16, I-I, I-Q, Q
Optimal intersymbol interference cancellation characteristics for -I and Q-Q are dynamically realized.

XPIC in Fig. 10 is also composed of TEQL13 to 16, but
The output compensation signals CI and CQ are added to the I and Q channels of the other system (FIG. 9). Therefore, the polar signals SI and SQ are those of the own system (FIG. 10), but the error signals EI and EQ are those extracted by the other system (FIG. 9). As a result, the TEQLs 13 to 16 in FIG. 10 are arranged between the I (represented by XI) and Q (represented by XQ) channels of the own system and the I and Q channels of the other system, that is, XI-I, XI-. In Q, XQ-I, and XQ-Q, optimum intersymbol interference cancellation characteristics are dynamically realized.

[Problems to be Solved by the Invention]

In a conventional receiver equipped with a transversal automatic equalizer TEQL and a cross polarization interference canceller XPIC, each circuit and board are designed separately, which increases man-hours and causes price increase. Was there. Also, the maintenance burden was heavy. In addition, if the two are designed differently, the respective delay amounts will be different, and there has been a problem that a device for matching the delay amounts is required.

The present invention solves the above problems, and a transversal automatic equalizer TEQL and a cross polarization interference compensator in a receiver are provided.
It is intended to facilitate the manufacturing and maintenance of XPIC.

[Means for solving the problem]

In the present invention, many common parts are used between the transversal automatic equalizer TEQL and the cross polarization interference canceller XPIC, but TEQL and XPIC set the initial setting of the DTF center tap to "1". Paying attention to the method of setting to “0”, the destination of the error signal, and the difference in the input / output directions of the error signal and the compensation signal, the common circuit part of TEQL and XPIC and both It is intended to solve the problems of the present invention by providing a TEQL / XPIC shared circuit in which the unique circuit part is divided and the unique circuit parts of both can be configured to be switched according to the purpose of use.

FIG. 1 shows the basic configuration of a TEQL / XPIC shared circuit according to the present invention.

In the figure, 101 is a common circuit part, which is composed of common circuit parts for TEQL and XPIC.

Reference numeral 102 denotes a unique circuit section, which includes unique circuits 102a and 102b of TEQL and XPIC, respectively.

Reference numeral 103 denotes a connection unit, which has a function of selectively connecting the common circuit unit 101 and a corresponding specific circuit in the specific circuit unit 102 depending on whether TEQL or XPIC is intended. In the figure, for convenience
It shows a state in which the TEQL-specific circuit 102a is connected.

Further, if necessary, a signal means indicating the type of the function realized as a result of the circuit connection, and a bidirectional bus for controlling the directionality by the signal means indicating the type and transmitting or receiving a signal to or from an external circuit. And a center tap control mode / initial setting value generation circuit for performing center tap control by a signal indicating the type.

[Action]

The common circuit section 101 of the TEQL / XPIC shared circuit in FIG.
It consists of input side circuit part including TEQL element in each of XPIC and XPIC. On the other hand, the TEQL proper circuit 102a and the XPIC proper circuit 102b of the proper circuit unit 102 are composed of different output side circuit portions in TEQL and XPIC, respectively.

When the TEQL / XPIC shared circuit of the present invention is incorporated in the receiving device as TEQL, the TE of the common circuit unit 101 and the unique circuit unit 102
Connect the QL specific circuit 102a to the connection part as shown in FIG. 2 (A).
Connect together at 103. When incorporating as an XPIC, the XPIC specific circuit 102b of the common circuit unit 101 and the specific circuit unit 102
And are integrally connected by the connecting portion 103 as shown in FIG. 2 (B).

In this way, either TEQL or XPIC function can be easily realized simply by preparing a single TEQL / XPIC shared circuit.

Further, if the type of the function realized by the signal means for indicating the type is determined, the directivity of the bidirectional bus and the center tap control mode / initial setting value generation circuit can be controlled, for example.

〔Example〕

An embodiment of the present invention will be described with reference to FIGS.

3 and 4 show a first embodiment in which the connecting portion 103 in FIG. 1 is realized by terminal connection, and FIGS. 5 and 6 show a case in which the connecting portion 103 is realized by a connector. Second Embodiment FIG. 7 shows a third embodiment in which the connecting portion 103 is realized by a switch. Fig. 8 shows TE
It is a control table about the center tap of the TEQL element in each of QL and XPIC.

Since most of the circuit elements shown in FIGS. 3 to 7 are the same as those described in the conventional circuit of FIGS. 10 and 11, they are designated by the same reference numerals. It will be used as it is, and only new circuit elements will be described.

 3 to 7, 33: XPIC compensation signal bidirectional buffer (Ich) 34: XPIC compensation signal bidirectional buffer (Qch) 35: Error signal bidirectional buffer (Ich) 36: Error signal bidirectional buffer (Qch) 37: Center tap control mode / initial setting value generation circuit 38: 1st terminal group 39: 2nd terminal group 40a: TEQL specific circuit 40b: XPIC specific circuit 41: Pull-up Resistor 42: Connector CN1 43: Connector CN2 44: Connector CN11 45: Connector CN12 46: Switch SW1 47 to 50: Analog switch.

First, the first using the terminal connection shown in FIG. 3 and FIG.
An example will be described.

FIG. 3 is a circuit diagram of the first embodiment of the TEQL configuration incorporating the TEQL specific circuit 40a, and FIG. 4 is a circuit diagram of the first embodiment of the XPIC configuration incorporating the XPIC specific circuit 40b.

The TEQL peculiar circuit 40a in FIG. 3 and the XPIC peculiar circuit 40b in FIG. 4 are, for example, printed circuits in parallel on the board, and if necessary, one of them, the first terminal group 38 and the second terminal. The actual wiring is made between the group 39 and the group 39 so that the connection is made.
However, it is not always necessary to prepare the XPIC specific circuit 40b in the form of a printed circuit, and when the XPIC is manufactured, the wiring as shown in the figure is provided between the first terminal group 38 and the second terminal group 39. You may connect directly.

Also, a circuit is provided to detect whether the TEQL-specific circuit 40a is connected, and whether the circuit functions as TEQL XP
It is desirable to be able to identify whether it is functioning as an IC. The lowermost terminal 38X of the first terminal group 38 is used for this purpose. This terminal 38X is connected to a pull-up resistor 41 as shown in FIG. 3 to give an H level of a logical value "1", and when the TEQL specific circuit 40a is used, the H level is maintained as it is, When using the XPIC specific circuit 40b or directly connecting the first terminal group and the second terminal group as shown in Fig. 4, connect to the ground terminal 39X which gives the L level of the logical value "0" in the second terminal group. Thus, the H level of the terminal 38X changes to the L level so that the two can be distinguished.

It is assumed that the TEQL elements 13 to 16 are capable of controlling the presence / absence of the center tap control and the initial setting value from the outside, respectively, and the center tap control mode / initial setting value generating circuit 37 is arranged in the first terminal group 38. TEQL / XP IC identification terminal 3
It is connected to 8X and generates an output value based on the control table of Fig. 8 according to its logical value. In this control table, when the level of terminal 38X is H (logical value "1"), the TEQL column is read and L
When it is (logical value "0"), the XPIC column is read.

For XPIC compensation signal (CI, CQ) and error signal (EI, EQ)
The bidirectional buffers 33 to 36 are used as buffers for input, and the input / output direction is switched by the TEQL / XPIC identification signal of the terminal 38X (when TEQL, the bidirectional buffers 33 and 34 for XPIC compensation signals are The input buffer and the error signal bidirectional buffers 35 and 36 are output buffers, and vice versa for XPIC).

Next, a second embodiment using the connector connection shown in FIGS. 5 and 6 will be described.

FIG. 5 is a circuit diagram of the second embodiment of the TEQL configuration incorporating the TEQL specific circuit 40a, and FIG. 6 is a circuit diagram of the second embodiment of the XPIC configuration incorporating the XPIC specific circuit 40b.

In the second embodiment, a connection mechanism using the first terminal group 38 and the second terminal group 39 in the first embodiment is used as a connector.
It is replaced with the connection mechanism of CN1-CN11, CN2-CN12, and the TEQL and XPIC are easier to assemble and the configuration can be easily changed as compared with the first embodiment.

In the second embodiment as well, in order to enable the identification of TEQL / XPIC
CN1 pin 42X and CN2 pin 43X are used. Pin 42X
Is connected to the pull-up resistor 41, and the pin 43X is grounded. And in the TEQL configuration of FIG. 5, pin 42X is pin 43X.
Is not connected to the H level logic value "1" and XP in Fig. 6
When the IC is configured, the pin 42X is connected to the pin 43X so that the L-level logic value becomes "0".

The third embodiment using the switch shown in FIG.
In this embodiment, the connectors CN1-CN11, CN2-CN12 in the above embodiment are replaced with a switch 46 and analog switches 47 to 50.

Switching of TEQL / XPIC is performed by the switch SW1, and thereby the logical value "1" or "0" is obtained. Further, the analog switches 47 to 50 are switched according to the value (contact a is TE
Controls the output of the center tap control mode / initial setting value generation circuit 37 when QL, when the contact b is XPIC). Further, the input / output directions of the bidirectional buffers 33 to 36 are also switched.

This makes it possible to switch between TEQL and XPIC easily and quickly.

〔The invention's effect〕

The TEQL / XPIC shared circuit of the present invention can be shared with XPIC by slightly increasing the circuit size of the conventional TEQL, so the number of steps such as circuit design, board design, and testing can be halved from the conventional one. be able to.

In addition, when TEQL and XPIC are used in combination, the physical characteristics of the circuit related to the delay are exactly the same for each, so the delay amount is also the same and no special means for adjusting the delay amount is needed. The number of circuits and man-hours can be reduced.

[Brief description of drawings]

FIG. 1 is a diagram showing the principle of the present invention, FIG. 2 is a diagram for explaining the operation of the present invention, FIG. 3 is a circuit diagram of the TEQL configuration of the first embodiment of the present invention, and FIG. FIG. 5 is a circuit diagram of the XPIC configuration of the first embodiment, FIG. 5 is a circuit diagram of the TEQL configuration of the second embodiment of the present invention, and FIG. 6 is a circuit diagram of the XPIC configuration of the second embodiment of the present invention. FIG. 7 is a circuit diagram of a third embodiment of the present invention, FIG. 8 is an explanatory diagram of a control table of a center tap, FIG. 9 is a block diagram of a receiver having conventional TEQL and XPIC, and FIG. Te
The QL circuit diagram and Fig. 11 are conventional XPIC circuit diagrams. In Fig. 1, 101: Common circuit section 102: Specific circuit section 103: Connection section

Continuation of the front page (56) References JP-A-61-105543 (JP, A) Actual development: S58-196867 (JP, U)

Claims (2)

(57) [Claims] 1. A common circuit section (101) composed of circuit sections common to a transversal automatic equalizer and a cross-polarization interference compensator configured by using a digital transversal filter, and different circuit sections from each other. And the common circuit section (101) corresponding to the specific circuit section (102) depending on which function of the transversal automatic equalizer and the cross polarization interference canceller is realized. In the shared circuit of the transversal automatic equalizer and the cross polarization interference canceller, which comprises a connection part (103) for connecting the circuit and the circuit), the type of function realized as a result of the circuit connection of the connection part (103) is shown. A signal means and a bidirectional bus for transmitting or receiving a signal to / from an external circuit are provided, and the directionality is controlled by the signal means indicating the type of the function to be realized. A circuit for shared use of a transversal automatic equalizer and a cross polarization interference compensator, which is characterized by. 2. A center tap control mode / initial setting value generating circuit having a control table for controlling center taps of a transversal automatic equalizer and a cross polarization interference canceller according to claim 1, A transversal automatic equalizer and cross-polarization interference compensator shared circuit, characterized in that a corresponding means tap control is performed by referring to a control table by a signal means indicating the type of function to be realized.