JP2519114B2 - Data transmission equipment - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transmission device, and more particularly to a data transmission device that is most suitable for fetching data from an external circuit connected to the microprocessor into the microprocessor.

[Prior Art] When data from an external circuit is taken into a microprocessor and serial data is transmitted using a conventional data transmission device, three lines for transmitting a clock signal, a latch signal, and a data signal are used. Is used for data transmission. When data transmission is performed using such three lines, as shown in FIG. 4, the external circuit is surely initialized at the rising edge of the latch signal (FIG. 4 (a)), and the clock signal is generated. Of the data signals D0, D1, in synchronization with the clock signal (FIG. 4 (b)).
..., D11 (Fig. 4 (c)) is transmitted in sequence,
After that, the data is latched at the falling edge of the latch signal.

[Problems to be Solved by the Invention] When serially transmitting data, as described above, three lines for transmitting the clock signal, the latch signal, and the data signal are required. Of these, if the transmission of the latch signal is omitted and the data is transmitted by two lines of the clock signal and the data signal, the external circuit cannot be initialized at the rising or falling of the latch signal.
The operation of latching the data signal becomes uncertain, and a malfunction occurs easily.

The present invention has been made in view of the above problems, and an object of the present invention is to accurately transmit data by two lines of a clock signal and a data signal.

[Means for Solving the Problem] In order to achieve this object, a data transmission device of the present invention is configured so that data stored in a storage means is stored in a clock line for transmitting a clock signal and a data line for transmitting a data signal. In a data transmission device that transmits data by two lines, first level changing means for setting one of a clock line and a data line to a predetermined level and changing the other level, and a level change of the clock line or the data line And a level detection means for detecting the clock signal, an initialization means for initializing the storage means when one of the clock line and the data line is at a predetermined level and the other level is changed, and the storage means is initialized. And a second level changing means for changing the level of the clock line or the data line. .

[Operation] In the data transmission device having the above configuration, for example, by using the first and second level changing means for changing the level of the data line so that the data line is used bidirectionally, the latch signal is generated. The transmission line can be omitted, and data can be accurately transmitted by the two lines of the clock signal and the data signal.

[Embodiment] An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of a data transmission device according to the present invention.

In FIG. 1, the CPU circuit 1 is connected to a data input circuit 2 by a clock line 11 and a data line 12. That is, the clock signal (CLK) output terminal of the CPU circuit 1 is connected to the input terminal of the shift register 3 of the data input circuit 2. In addition, the data signal of the CPU circuit 1 (DAT
A) The output terminal is connected to the input terminal of the falling differential circuit 7 of the data input circuit 2 via the resistor R1. The data line 12 is pulled up to the power supply voltage by the resistor R2.

The clock signal CLK is also supplied to the AND gate 4 of the data input circuit 2 and an AND gate 5 described later. The output of the falling differential circuit 7 is also supplied to the AND gate 4. The "H" level pulse output when the falling differential circuit 7 detects the falling of the data signal DATA is the AND gate 4 when the clock signal CLK is at the "H" level.
To the shift register 3 to clear the shift register 3. The output of the AND gate 4 is also supplied to the falling differentiation circuit 10, and the output of the falling differentiation circuit 10 loads the data signals D0, D1, ..., Dn into the shift register 3. Further, the output of the AND gate 4 is also supplied to the clear terminal (CLR) of the n-ary counter 6 to clear the count content of the n-ary counter 6.

The output of the n-ary counter 6 is supplied to the inverter 8, and the inverter 8 controls on / off of the analog switch 9 according to the output of the n-ary counter 6. When the AND gate 4 clears the count content of the n-ary counter 6,
The carry output (CARRY) of the n-ary counter 6 changes from the "H" level to the "L" level, and the output of the inverter 8 becomes the "H" level to turn on the analog switch 9.

As a result, the data signals D0, D1, ..., Dn loaded by the shift register 3 can be transmitted and output to the data line 12 in synchronization with the clock signal CLK. CPU circuit 1
The data signals D0, D1, ..., Dn are fetched from the data line 12.

On the other hand, the clock signal CLK is supplied to the n-ary counter 6 via the AND gate 5, and the AND gate 5 gates the clock signal CLK by the output of the inverter 8. Therefore, when n clock signals CLK are supplied to the n-ary counter 6, the carry output CARRY of the n-ary counter 6 changes from "L" level to "H" level. As a result, the output of the inverter 8 becomes "L" level and the analog switch 9 is turned off.

When the n clock signals CLK are supplied to the n-ary counter 6, the shift register 3 also receives the n clock signals.
CLK is being supplied. Therefore, at this point, the data signal D
The transmission of 0, D1, ..., Dn is completed, the analog switch 9 is turned off, and the shift register 3 is disconnected from the data line 12.

When it is unclear which data signal D0, D1, ..., Dn is currently being transmitted due to power-on or noise, send n or more clock signals CLK to the data input circuit 2 for certain. The data input circuit 2 can be initialized.
After that, when the CPU circuit 1 supplies the "L" level data signal to the falling differentiation circuit 7, the data transmission operation is restarted in the sequence described above.

In the above embodiment, the CPU circuit 1 serves as the first level changing means, the falling differentiating circuit 7 serves as the level detecting means, the AND gate 4 serves as the initializing means, the n-ary counter 6, the analog switch 9 and the resistor R1. , R2 is the second level changing means,
Each is configured.

The above operation will be further described with reference to the waveform chart of FIG. 2 and the flowchart of FIG.

First, the CPU circuit 1 temporarily sets its data line 12 (Fig. 2 (b)) to high impedance (Hi-Z) and sets the clock signal CLK (Fig. 2 (a)) to "H" level. (Step 21). Next, at that time, it is determined whether the data line 12 is at "H" level or "L" level (step 22).

When it is determined in step 22 that the data line 12 is at the "H" level, the following two states are possible. The first state is a state in which the analog switch 9 is off. At this time, since the data line 12 is pulled up by the resistor R2, the data line 12 becomes "H" level. The second state is when the analog switch 9 is turned on and the shift register 3 outputs "H" data.

In order to determine which state this is, next, as shown at time t1 in FIG. 2, the CPU circuit 1 once sets the data line 12 to the “L” level and further sets it to high impedance (step twenty four).

In the first state in which the analog switch 9 is off, the operation of changing the data line 12 to the "L" level is detected by the falling differential circuit 7, and the differential pulse of "H" (see FIG. 2 (d )) Is output from the falling differential circuit 7 through the AND gate 4. As a result, the shift register 3 is cleared and its output becomes "L". Further, the n-ary counter 6 is cleared, its carry output (CARRY) changes from "H" level to "L" level, the output of the inverter 8 becomes "H" level, and the analog switch 9 is turned on. To do.

As a result, in the following step 25, when the level of the data line 12 is determined again as shown at time t2,
Since the output of the cleared shift register 3 is output via the analog switch 9, its level becomes “L” (FIG. 2 (c)). Then, the clock CLK is "L"
The level is set (step 26), and thereafter, the clocks are sequentially inverted and the data signals D0, D1, ...
., Dn is read by the CPU circuit 1 through the analog switch 9 and the data line 12.

In this data, the falling edge of the pulse of the AND gate 4 is detected by the falling edge differentiating circuit 10,
When the pulse (FIG. 2 (e)) is output from 10, it is loaded in the shift register 3.

On the other hand, in the second state in which the analog switch 9 is turned on and the "H" level data is output from the shift register 3, the input of the falling differentiating circuit 7 is clamped to the "H" level. Regardless of the processing of step 24, in the determination of step 25, the level of the data line 12 does not change and remains “H”. In this case, since it means that the initialization of the input circuit 2 has not been completed yet, as described below, the same processing as when the data line 12 is determined to be the “L” level in step 22 is performed. To be executed.

In step 22, when the data line 12 is at "L" level, it is determined that the analog switch 9 is on and the shift register 3 is outputting "L" data. This means that the initialization of the input circuit 2 has not been completed yet. Therefore, in this case, the CPU circuit 1 repeats the operation of setting the clock signal CLK to the "L" level and then returning it to the "H" level until the data line 12 becomes the "H" level (step 23). By this operation, when the "H" level data is output from the shift register 3, the processing from step 24 onward is executed as described above.

When the "H" level data is not output from the shift register 3, when the count value of the n-ary counter 6 counting clock pulses input via the AND gate 5 reaches n, the n-ary counter The carry output of 6 is inverted from "L" to "H". As a result, the analog switch 9 is turned off, and the data line 12 changes to "H" level. Therefore, hereinafter, as described above, the processing from step 24 onward is executed.

It should be noted that the data line and the clock line described above can be used in reverse.

According to the embodiment described above, the following effects can be obtained.

Since the clock signal CLK can be shared with the clock signal CLK for other serial access, it is practically 1
Serial data can be captured simply by adding lines.

Since it corresponds with hardware and software, there is no mistake in data acquisition.

Even if there is noise in the clock signal CLK on the way, it can be surely initialized from the next access and accurate data acquisition.

By further increasing the number of lines, the input port can be expanded infinitely.

By reducing the number of transmission lines from three to two, it is possible to reduce costs.

[Effects of the Invention] As described above, according to the data transmission device of the present invention, the level of the data line or the clock line is bidirectionally used by using the first and second level changing means. Therefore, the transmission line of the latch signal can be omitted, and the data can be accurately transmitted by the two lines of the clock signal and the data signal.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of a data transmission apparatus according to the present invention, FIG. 2 is a timing chart explaining an operation of an embodiment of a data transmission apparatus according to the present invention, and FIG. FIG. 4 is a flow chart for explaining the operation of the embodiment of the data transmission apparatus according to the present invention, and FIG. 4 is a timing chart for explaining the operation of the example of the conventional data transmission apparatus. 1 ... CPU circuit, 2 ... data input circuit, 3 ... shift register, 4 ... AND gate, 5 ... AND gate,
6 ... n-ary counter, 7,10 ... falling differentiation circuit, 8 ...
Inverter, 9 ... Analog switch, 11 ... Clock line, 12 ... Data line.

Claims (1)

(57) [Claims] 1. A data transmission device for transmitting data stored in a storage means by two lines of a clock line for transmitting a clock signal and a data line for transmitting a data signal, wherein one of the clock line or the data line Is set to a predetermined level and the other level is changed, first level changing means, level detecting means for detecting a change in the level of the clock line or the data line, and one of the clock line or the data line is set to a predetermined level. When the level detection means detects a change in the other level, the initialization means initializes the storage means; and when the storage means is initialized, the clock line or the data. And a second level changing means for changing the level of the line.