JP2517999B2 - Logical operation unit - Google Patents

Description

The present invention relates to a logical operation device, and more particularly to a logical operation device in an information processing device such as a logic simulation / functional level simulation device.

[Conventional technology]

In the logic simulation / functional level simulation device, particularly when simulating a signal of a control system, it is necessary to evaluate a complicated logical operation expression as shown in Expression (1) to obtain a 1-bit signal.

Such an expression can be regarded as a binary tree in which the output of another signal (A, B, and CD in the expression 1) corresponds to a leaf, each operation corresponds to an intermediate node, and the desired signal corresponds to a root. .

In the conventional logic level logic simulation / function level simulation apparatus, in order to evaluate such an expression, a stack is used to perform an operation while tracing a binary tree corresponding to the expression.

[Problems to be Solved by the Invention]

However, when a conventional logical operation device advances an operation while tracing a binary tree, if there are n operators in an expression, m times of operations and a maximum of m times of access to the stack are required, which is very large. When performing a simulation of a device of a large scale, there is a drawback that the total simulation time increases.

The purpose of the present invention is to eliminate such conventional defects,
An object of the present invention is to provide a high-speed logical operation device by suppressing the number of operations for a complicated arithmetic expression to the depth of an arithmetic tree (logM times in the best case) and eliminating the need to access the stack.

[Means for solving the problem]

The logical operation device of the present invention is a combinational circuit that realizes a parallel logical operation unit using n 2-input 1-output operation units that perform n sets of logical operations on 2n-bit data. A multiplexer and a result holding register are provided to enable data transfer to and from the arithmetic logic unit of the microprogram control computer, and one input of the multiplexer is connected to an external bus of the arithmetic logic unit, The output of the multiplexer is connected to the input of the result holding register, the output of the result holding register is connected to the external bus of the arithmetic logic unit and the input of the parallel logic unit, and the output of the parallel logic unit is connected to the multiplexer. Connect to the other input.

[Action]

In the present invention, under the control of the microprogram, the binary corresponding to the leaves of the binary tree (in the case of the expression (1), the values of A, B, C, D) are transferred from the arithmetic logic unit to the result holding register via the multiplexer. Later stored in the result holding register
The n logical operations designated by the microinstruction are performed on the 2n-bit data by the parallel logical operation unit, and the result is stored in the lower n bits of the result holding register via the multiplexer. This means that operations that are equidistant from the root of the binary tree are executed simultaneously within one microinstruction. Therefore, it becomes possible to execute an operation with the number of times of the depth of the binary tree (logm in the best case) for an expression including m operations. Further, during this operation, since the intermediate result of the operation is always held in the result holding register, it is not necessary to access the external memory such as the stack, so that the system throughput is further improved.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 shows an embodiment of the present invention. In FIG.
An embodiment of the present invention has a multiplexer 2 connected to an external bus 1 of an arithmetic logic unit 5 of a micro program control computer, and a result holding register 3 connected to this multiplexer 2, and controls a micro instruction 6. Under 2
The data corresponding to the leaves of the tree is transferred from the arithmetic logic unit 5 to the result holding register 3 via the external bus 1 and the multiplexer 2.

Further, this embodiment has an output of the result holding register 3 and a parallel logical operation unit 4 connected to the other input of the multiplexer 2, and 2n held in the result holding register 3
N specified by microinstruction 6 for bit data
It is configured to perform a number of logical operations and store the operation result in the lower n bits of the result holding register via the multiplexer 2. Furthermore, the result holding register 3 is connected to the external bus 1, and under the control of the micro instruction 6,
It is configured to transfer the held operation result to the arithmetic logic operation unit 5.

FIG. 2 shows a parallel logic operation unit 4 in one embodiment of the present invention.
FIG. In FIG. 2 (a), the parallel logical operation unit 4 is composed of n 2-input 1-output logical operation units 7. These two-input one-logical operation unit 7 performs the operation 12 designated by the corresponding operation field 8 of the microinstruction 6 on the left input 9 and the right input 10, and outputs the result to the output 11. In FIG. 2B, each calculation 12 in each calculation designation field 8 is, for example, a designated field.
00 for NOP, 01 for NOT, 11 for AND, 10
In the case of, an operation such as OR is specified.

FIG. 3 shows an example when the formula (1) is evaluated by the present invention.
In FIG. 3A, the binary tree 13 corresponding to the equation (1) is a binary tree having a depth of 3. In the present invention, this expression is evaluated according to the microprogram 14. In FIG. 3B, the value corresponding to the leaf of the binary tree is transferred from the arithmetic and logic unit 5 to the result holding register 3 by the first microinstruction 15. The second micro instruction 16 causes the binary tree 13
The operation of the deepest stage (two negations) is executed.
The third microinstruction 17 performs the operation of the second deepest stage (logical sum and logical product), the fourth microinstruction 18 performs the operation of the shallowest stage, and the fifth microinstruction 19 the third. The value 20 of the result holding register is transferred to the arithmetic logic operation unit 5 as shown in FIG.

〔The invention's effect〕

As described above, according to the present invention, it is possible to perform an operation on an expression including m operations by the number of times of the depth of the binary tree (logm in the best case). Further, during this operation, since the intermediate result of the operation is always stored in the result holding register, it is not necessary to access the external memory such as the stack, so that the system throughput is further improved.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a diagram showing an embodiment of the present invention, FIGS. 2 (a) and 2 (b) are diagrams showing a parallel logical operation unit and microinstructions in this embodiment, and FIG. FIG. 4 is a diagram showing an example when evaluated in the present invention. 1 ... External bus, 2 ... Multiplexer, 3 ... Result holding register, 4 ... Parallel logic operation unit, 5 ... Arithmetic logic operation unit, 6 ... Micro instruction, 7 ... 2-input one logic operation unit, 8 ... Calculation specification field, 9 ... Left input, 10 ...
Right input, 11 …… output, 12 …… math, 12 …… binary tree, 14…
… Micro programs, 15 …… Micro instructions 1, 16 ……
Micro-instruction 2, 17 ... Micro-instruction 3, 18 ... Micro-instruction 4, 19 ... Micro-instruction 5, 20 ... Result holding register value.

Claims (1)

(57) [Claims] 1. A multiplexer for inputting data connected to an arithmetic logic unit of a microprogram control computer via an external bus, and a data stored in the arithmetic logic unit via the multiplexer. , A result holding register for sending data to the arithmetic and logic unit via the external bus and n 2-input 1-output logical operation units to obtain 2n-bit wide data held in the result holding register And a parallel logical operation unit that performs n logical operations according to the control signal and transfers the resulting n-bit width data to the lower n bits of the result holding register via the multiplexer. Logical operation device.