JP2517152B2 - Voltage application method for scanning circuit for photo diode array - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application The present invention inputs a photodiode array constituting a contact-type image sensor used in an optical image reading apparatus such as a facsimile machine or an image scanner. The present invention relates to a voltage application method for a scanning circuit for a photodiode array for scanning with one sawtooth voltage.

(B) Conventional Technology Conventionally, this type of photodiode array scanning circuit is
As shown in FIG. 10, diodes D _{W1 to} D _W10 having the same forward characteristic are connected in series, and each diode D _W1
~ D _W10 cathode to ground GND, resistors R _W1 ~ R
It is configured by connecting _W10 and a series circuit of resistors R _{T1 to} R _T10 and diodes D _{T1 to} D _T10 . Then, the scanning voltage is output from the anodes of the respective diodes D _{T1 to} D _T10 to the respective photodiodes PD _{1 to} PD ₁₀ of the photodiode array. BD _{1 to} BD ₁₀ are blocking diodes for preventing crosstalk.

In such a circuit configuration, for example, a sawtooth voltage Vdr is applied to the anode of the diode D _W1 (at T = 0 in FIG. 11). A voltage appearing at the cathode side of the diode D _W1 when the sawtooth voltage Vdr exceeds the threshold voltage V _F of the diode D _W1. Next, when the sawtooth voltage Vdr reaches twice the threshold voltage 2V _F, the voltage appearing at the cathode side of the diode D _W2. The voltage appearing on the cathode side of the subsequent diode D sequentially diode D _W3 to D _W10 to _W10.

The voltage appearing on the cathode side of the diode D _W1 increases as the sawtooth voltage Vdr increases. At this time, the voltage at the connection point tp1 on the anode side of the diode D _T1 also gradually rises, but when it reaches the threshold voltage V _F of the diode D _T1 , it becomes almost saturated, and thereafter the voltage rises very slowly. It will be Therefore, a voltage sequentially appears at the output terminals tp1 to tp10 due to the threshold V _F of the diodes D _{W1 to} D _W10 , and the voltage is saturated by the diodes D _{T1 to} D _T10 and becomes as shown in FIG.

(C) Problems to be Solved by the Invention However, in the photodiode array scanning circuit described above, the voltage output to each photodiode does not exceed the threshold value of the diode D _T. In the photodiode array including the scanning circuit and the blocking diode, it is assumed that the blocking diode has the same characteristics as the diodes of the scanning circuit. In this case, when charging the capacitance of the photodiode through the blocking diode, the blocking diode is used in a region having a very high resistance equal to or lower than the threshold voltage V _F of the blocking diode. At this time, the nth (n = 1,2,
3 ...) is charged to the photodiode and the charging current flowing at that time is detected as an optical signal. Time until the nth photodiode is charged
The charging is not completely performed within T _C (FIG. 12), and the charging current flowing after the time T _C is added as a residual current amount when charging the (n + 1) th photodiode. Since this residual current is not constant depending on the amount of light incident on the photodiode, the n-th detection is performed during the (n + 1) th detection.
The state of the second photodiode causes the signal to be non-uniform. Due to this non-uniformity, the variation in signal output becomes a non-negligible value within the dynamic range determined by the saturated exposure amount and the minimum detectable exposure amount. Will not be able to get.

Further when the current through the internal resistance R _S of the diode D _T through the diode D _T is increased, since the voltage on the anode side of the diode D _T will continue to slowly rise to reach the threshold voltage V _F, in FIG. 12 to the voltage V _F to detect the output as shown, the voltage for charging the capacitor to the photodiode (V _F + delta
V) becomes large. If the amount of charge charged by the voltage ΔV of this difference is ΔQ, unless the amount of charge discharged by the photocurrent of the photodiode exceeds ΔQ, the photodiode is not recharged at the time of output detection, so that an output is obtained. I can't. Also connection point tp1 to connection point tp10
Since the value of the voltage difference ΔV is different, the output at low illuminance cannot be obtained for each bit, and the minimum illuminance value for output by each bit also differs.

The present invention has been made in view of the above circumstances, and an object thereof is to provide a voltage applying method for a scanning circuit for a photodiode array, which can increase the scanning voltage supplied to the photodiode.

(D) Means for Solving the Problems The present invention is directed to a first diode group in which n: n ≧ 2 diodes are connected in series, and a cathode of each diode of the first diode group and a first common group. A resistor group W consisting of n resistors connected to the path, a second diode group consisting of n: n ≧ 2 diodes, and a series connection to the anode of each diode of this second diode group. A resistor group T composed of n resistors connected to each other, wherein the cathodes of the diodes of the second diode group are connected to a second common path, and the second group of resistors of the resistor group T is The side of the diode group not connected to the anode of the diode is connected to the cathode of each diode of the first diode group, and the photodiode array is composed of n photodiodes. To the photodiode array scanning circuit for sequentially scanning the respective photodiodes, the sawtooth voltage is applied to the anode of the diode having the anode to which the resistor of the resistor group W is not connected among the first diode group. When the scanning voltages of the photodiodes are sequentially output from the anode side of the diodes of the second diode group by, the zero voltage is applied to the first common path and the positive voltage is applied to the second common path. This is a voltage application method for a scanning circuit for a photodiode array.

Applying the positive voltage in this invention may be applying a constant bias voltage continuously while the sawtooth voltage is being applied.

In addition, applying a positive voltage means that the first bias is applied to each diode of the second diode group that is sequentially switched in synchronization with the switching of each diode of the second diode group while the sawtooth voltage is applied. It may be to apply a voltage.

Further, applying a positive voltage means applying a constant first bias voltage until each diode of the second diode group switches while the sawtooth voltage is applied, and then applying the second diode group. Alternatively, the second bias voltage may be applied to each diode of the second diode group that is sequentially switched in synchronization with the switching of each diode.

(E) Action In the above configuration, since a positive voltage is applied to the cathode of the second diode, the voltage value of the sawtooth voltage gradually increases, and the voltage value on the anode side of the second diode becomes the second value. The voltage on the anode side of the second diode is not saturated even if the threshold voltage of the diode is exceeded. When the voltage value obtained by adding the threshold voltage and the positive voltage becomes saturated, the scanning voltage applied to the photodiode can be made equal to or higher than the threshold voltage.

(F) Embodiments Embodiments of the present invention will be described in detail below with reference to the drawings, but the present invention is not limited to the following embodiments.

In FIG. 1, PD _{1 to} PD ₁₀ are photodiodes, and each cathode has a blocking diode BD.
The cathodes _{1 to} BD ₁₀ are connected. The anodes of the photodiodes PD _{1 to} PD ₁₀ are connected to the output common path 1. The photodiode array 2 is composed of the photodiodes PD _{1 to} PD ₁₀ and the blocking diodes BD _{1 to} BD ₁₀ .

Reference numeral 3 denotes a photodiode array scanning circuit, which includes first diodes D _{W1 to} D _W10 and resistors R _{W1 to} R _W10 , R _T1 to which are connected in series.
It is composed of R _T10 and the second diodes D _{T1 to} D _T10 . The resistor R _Wi (i = 1,2,3 ...) Is connected between the cathode of the first diode D _Wi and the first common path. The first common path 4 is connected to the ground GND which is zero voltage. A resistor R _Ti is connected in series to the anode of the second diode D _Ti , its cathode is connected to the second common path 5, and the resistor R _Ti is connected to the cathode of the first diode D _Wi. .
The cathode of the photodiode PD _i is connected to the connection point tpi between the anode of the second diode D _Ti and the resistor R _Ti .

In the above configuration, when scanning the photodiode array 2, a constant bias voltage V _B that is a positive voltage is applied to the second common path 5. Then, the sawtooth voltage Vdr is applied to the anode of D _W1 of the first diode.

When the sawtooth voltage Vdr rises, the first diode D _W1
The voltage on the cathode side of the second diode D _T1 increases, and the voltage on the anode of the second diode D _T1 , that is, the scanning voltage also gradually increases.
At this time, since the positive constant bias voltage V _B is applied to the cathode of the second diode D _T1 , the second diode D _T1
The voltage of the anode of _T1 , that is, the voltage Vtp1 of the connection point tp1
As shown in FIG. 2, even if the threshold voltage V _F of the second diode D _T1 is exceeded, it does not saturate and rises up to the voltage value of the sum of those voltages (V _F + V _B ). . And the second
The voltage value of the anode of the diode D _T1 is the sum voltage (V _F + V _B ).
After that, the voltage Vtp1 rises very slowly, and when the sawtooth voltage Vdr turns off (V _F
It rises to + V _B + ΔV ₁ ) and turns off.

Thereafter, similarly, the scanning voltage applied to each of the photodiodes PD ₂ to PD ₁₀ is sequentially output to the anode side of each of the second diodes D _{T2 to} D _T10 . At this time, the photodiode PD
_The scanning voltage applied to _n (n = 1,2,3 ...) is the bias voltage V _B.
As shown in FIG. 3, the maximum value of the signal current I _OUT obtained increases as compared with the conventional case. In addition, when charging the photodiode capacitance, the low resistance region of the blocking diode can be used at a voltage higher by the bias voltage V _B , and charging is performed rapidly in that region, so that the maximum value of the signal current I _OUT remains. The ratio of the current becomes smaller,
The influence of the residual current can be reduced as compared with the conventional case. Further, since the saturated exposure amount increases by the bias voltage V _{B, the} minimum detectable exposure amount determined by ΔV due to the voltage difference between the reset time and the read time and the dynamic range determined by the saturated exposure amount increase.

The second embodiment is shown in FIGS. In this example,
The cathode of each of the second diodes D _{T1 to} D _T10 is
Unlike the first embodiment, the switch circuit 6a of the voltage generator 6 that generates the first bias voltage is normally connected to the ground. Then, when the corresponding switch of the switch circuit 6a is switched in synchronization with the switched second diode, the voltage generator 6 applies the first bias voltage only to the cathode of the switched second diode.

In this embodiment, as the sawtooth voltage Vdr rises, the anode voltage Vrp1 of the second diode D _T1 also gradually rises and reaches saturation when the threshold voltage V _F is reached (see FIG. 5). ), The first bias voltage V from the voltage generator 6 in synchronization with the timing shown in FIG. 6, that is, the threshold voltage V _F being reached and the second diode D _T1 switching.
Output _P1 (= V _F + ΔV ₁ ). This first bias voltage V
The application of _P1 to the cathode of the second diode D _T1, the anode voltage Vtp1 of the second diode D _T1 is (V _F + ΔV ₁₎
Rise to. When the first bias voltage V _P1 is turned off,
The anode voltage Vtp1 of the second diode D _T1 decreases to almost the threshold voltage V _F, and follows the increase of the voltage after being saturated at the threshold voltage V _F. After that, the scanning voltages applied to the second diodes D _{T2 to} D _T10 are sequentially output to the photodiodes. At this time, the voltage value applied to the cathode of the second diode D _Tn is (V _F + ΔVn), where ΔVn is the difference between the reset voltage and the read voltage of the nth bit (n = 1,2,3 ...). .

As described above, since the voltage at the time of completing the charging of the photodiode and the voltage at the time of reading are equal to each other, the minimum detectable exposure amount becomes small, so that the dynamic range can be expanded.

A third embodiment is shown in FIGS. In this example,
Different from the second embodiment, the second diodes D _{T1 to} D _T10
A constant bias voltage V _B is always applied to each of the cathodes by the switch circuit 7a of the voltage generating circuit 7. Then, when the corresponding switch of the switch circuit 7a is switched in synchronization with the switched second diode in that state, the second bias voltage is applied by the voltage generator 7 only to the cathode of the switched second diode. Is.

In this embodiment, as the sawtooth voltage Vdr rises, the anode voltage Vtp1 of the second diode D _T1 rises. In this case the cathode of the second diode D _T1, since the applied positive bias voltage V _B, the anode voltage of the second diode D _T1 is gradually increased beyond the threshold voltage V _F, switching i.e. saturated with the sum voltage (V _F -V _B) (Figure 8). And the second diode D _T1
The second bias voltage V _P12
Since (= V _B + ΔV ₁ ) is applied (FIG. 9), the voltage Vtp1 of the anode of the second diode D _T1 rises to (V _F + V _B + ΔV ₁ ). When the second bias voltage _P12 is turned off, the voltage of the anode of the second diode D _T1 becomes a value that coincides with the voltage waveform when only the bias voltage V _B is applied in the first embodiment. Thereafter, similarly, the scanning voltage applied to the photodiodes is sequentially output from each of the second D _{T2 to} D _T10 . At this time the first
As in the above embodiment, the maximum value of the output increases because the voltage applied to the photodiode increases. Further, since the low resistance region of the blocking diode is used when the voltage applied to the photodiode is increasing, the ratio of the residual current to the maximum value of the signal current becomes small. Therefore, the non-uniformity in each photodiode is reduced and the voltage at the time of reading is the same as that at the time of resetting, so that an output can be obtained even at low illuminance. This indicates that both the effect obtained only in the first embodiment and the effect obtained in the second embodiment can be obtained.

In each of the above embodiments, the photodiode is 10
Although the scanning circuit for scanning one photodiode array has been described, for example, if the number of photodiodes is 1728, ten photodiode arrays are regarded as one block, and the scanning circuit shown in each embodiment is connected to each of them. You should take. And one of each scanning circuit
A sawtooth voltage may be sequentially applied to the first diode of the bit in a time division manner.

(G) Effect of the Invention According to the present invention, since the scanning voltage applied to the photodiode is increased, the maximum value of the signal current output from the photodiode array can be increased. This reduces the non-uniformity between photodiodes,
Also, the dynamic range of the photodiode array can be increased.

[Brief description of drawings]

FIG. 1 is an electric circuit diagram of a photodiode array and a photodiode array scanning circuit for explaining the first embodiment of the present invention, and FIG. 2 is each connection point tp1 of the photodiode array scanning circuit in the first embodiment. ~ A graph showing the relationship between the output voltage of tp10 and the signal current I _OUT , Fig. 3 shows the n-th graph
A graph showing the relationship between the output voltage of the connection point tpn of the bit and the signal current I _{OUT in} the bright state and the dark state at that time, FIG. 4 is a diagram corresponding to FIG. 1 of the second embodiment, and FIG. 2 of the second embodiment, and FIG. 6 shows the output voltage and the bias voltage of the connection point tpn of the nth bit in the second embodiment and the signal current I _{OUT in} the bright state and the dark state at that time. FIG. 7 is a graph showing the relationship, FIG. 7 is an equivalent view of FIG. 1 of the third embodiment, FIG. 8 is an equivalent view of FIG. 2 of the third embodiment, and FIG. 9 is FIG. 6 of the third embodiment. Equivalent diagram, FIG. 10 is an electric circuit diagram in the conventional example, FIG.
The drawing corresponds to FIG. 2 of the conventional example, and FIG. 12 corresponds to FIG. 3 of the conventional example. 2 ... Photodiode array, 3 ... Scanning circuit for photodiode array, 4 ... 1st common path, 5 ... 2nd common path, D _{W1 to} D _W10 ... 1st diode, D _{T1 to} D _T10 ... Second diode, R _{W1 to} R _W10 , R _{T1 to} R _T10 ... resistance.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Mitsuhiko Yoshikawa 22-22 Nagaike-cho, Abeno-ku, Osaka-shi, Osaka Within Sharp Corporation (72) Inventor Hiromi Kakinuma 6-16-20 Ueno, Taito-ku, Tokyo Sun-inducted stock In-house (72) Inventor Kazuyuki Hirooka 6-16-20 Ueno, Taito-ku, Tokyo Sun Induction Co., Ltd. (72) Inventor Sadaaki Kurata 6-16-20 Ueno, Taito-ku, Tokyo In Sun Induction Co., Ltd.

Claims (4)

(57) [Claims] 1. A first diode group in which n: n ≧ 2 diodes are connected in series, and n connected between a cathode of each diode of the first diode group and a first common path. A resistor group W consisting of a number of resistors, a second diode group consisting of n: n ≧ 2 diodes, and n resistors connected in series to the anodes of the diodes of this second diode group. A resistor group T, wherein the cathodes of the diodes of the second diode group are connected to a second common path, and the resistors of the resistor group T are connected to the anodes of the diodes of the second diode group. Each photodiode of the photodiode array, which is connected to the cathode of each diode of the first diode group and which is composed of n photodiodes, is A second diode by applying a sawtooth voltage to the anode of a diode having an anode to which the resistance of the resistor group W is not connected, of the first diode group, for the next scanning photodiode array scanning circuit. Scanning circuit for photodiode array that applies a zero voltage to the first common path and a positive voltage to the second common path when sequentially outputting the scanning voltages of the photodiodes from the anode side of each diode of the group Voltage application method. 2. The voltage application method for a photodiode array scanning circuit according to claim 1, wherein applying the positive voltage is applying a constant bias voltage continuously while the sawtooth voltage is applied. 3. A positive voltage is applied to the second diode group while the sawtooth voltage is applied to the second diode group.
2. The voltage applying method for a photodiode array scanning circuit according to claim 1, wherein the first bias voltage is applied to each diode of the diode group. 4. Applying a positive voltage comprises applying a constant first bias voltage until each diode of the second diode group switches while the sawtooth voltage is applied, and then applying a second bias voltage. 2. The voltage application method for a photodiode array scanning circuit according to claim 1, wherein the second bias voltage is applied to each diode of the second diode group which is sequentially switched in synchronization with the switching of each diode of the diode group.