JP2516501Y2 - Signal processing circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Outline] In a signal processing circuit for processing positive and negative signals from a signal source, a buffer amplifier for a reference voltage and a capacitive means for removing a residual voltage included in an input signal from the signal source are provided. One operational amplifier is also used as a buffer amplifier to reduce the number of operational amplifiers.

[Industrial applications]

The present invention relates to a processing circuit for a signal given from a sensor or the like.

[Conventional technology]

When a signal output from the sensor is amplified and signal processing is performed using the amplified signal, there is a case where only a signal having one polarity is necessary.

Generally, the output signal of the amplifier circuit is regulated by its power supply voltage. Therefore, a signal processing circuit performs processing such as unipolarizing and amplifying the signal to greatly amplify only a necessary portion of the output signal of the sensor and accurately process it.

For example, in an airbag device or the like that protects an occupant when a vehicle collides, an acceleration sensor is provided in the vehicle to inflate the airbag when the deceleration of the vehicle exceeds a predetermined value. In this device, in order to detect the deceleration of the vehicle with high accuracy, a signal processing circuit is used that amplifies a portion corresponding to acceleration and greatly amplifies a portion corresponding to deceleration in the output signal of the acceleration sensor.

 FIG. 3 is a circuit diagram showing a conventional signal processing circuit.

The sensor unit 1 is, for example, an acceleration sensor, and is configured such that the resistance values of the resistors R11 to R14 forming a bridge change according to the detected acceleration, and a voltage corresponding to the acceleration is generated between the terminals Tm1 and Tm2. . In the following description, the resistance value of the resistor is expressed by its lower case (for example, the resistance value of the resistor R11 is r11).

The voltage difference of the terminal Tm1 with respect to the terminal Tm2 (hereinafter referred to as the output signal of the sensor unit 1) produces both positive and negative values according to the detected acceleration, but the circuit shown in FIG. In, a single-pole power supply Vcc is used as a power supply, and a negative voltage cannot be output as an output signal. Therefore, in this circuit, the reference voltage VR that is half the voltage of the power supply Vcc is supplied to the line 1 as a virtual ground voltage, and a voltage centered on the reference voltage VR is generated according to the output voltage of the sensor unit 1. Is performing negative signal processing.

The reference voltage generation unit 5 obtains the reference voltage VR by dividing the power supply Vcc with the resistors R1 and R2, and supplies the reference voltage VR to the line 1 through the operational amplifier 51 that constitutes the buffer amplifier for impedance conversion. is there.

The differential amplifier section 2 amplifies the output signal of the sensor section 1, and is composed of operational amplifiers 21 and 22 and resistors R21 to R24. If the ratio of the resistance r22 to the resistance r21 is n times, the ratio of the resistance r24 to the resistance r23 is also set to n times. Then, the output signal of the differential amplifier section 2 is given to the DC blocking section 3. The gain of the differential amplifier 2 is the sensor 1
When the output signal is amplified, the output signal of the differential amplifier 2 is selected to be large in a range in which the output signal is not saturated.

The DC cutoff unit 3 removes a DC component from the output signal of the differential amplification unit 2, and includes a capacitor C1 and a resistor R31 that form a high pass filter, and an operational amplifier 31 that forms a buffer amplifier. The resistor R31 has one end connected to the capacitor C1 and the other end connected to the line 1. Therefore, a voltage obtained by adding the voltage VR to the output signal of the high-pass filter formed by the resistor R31 and the capacitor C1 is output via the operational amplifier 31. The operational amplifier 31 is for preventing the capacitor C1 from being unnecessarily charged by the output signal of the offset adder 4 described later.

The offset adder 4 is composed of resistors R41 to R43 and an operational amplifier 41, and is an inverting adder that adds the offset voltage VF, the amplified output signal of the DC cutoff unit 3, and the offset voltage VF. The output voltage of the offset addition unit 4 is not 0 V when acceleration is not applied to the sensor unit 1. This prevents the output signal of the offset addition unit 4 from being cut off due to disconnection or the like. Since it is 0V, it can be detected.

Although the offset adder 4 is supplied with the offset voltage VF in FIG.
By supplying the power supply Vcc in place of the offset voltage VF, and by attenuating the power supply Vcc by the resistors R42 and R43,
It is also possible that the offset voltage VF is apparently supplied.

Next, the operation of the circuit shown in FIG. 3 will be described. Figure 4 is the third
FIG. 4 (a) is a waveform diagram showing the operation of the circuit shown in FIG.
Is the output voltage of the sensor unit 1, and FIG. 4 (b) is the differential amplifier unit 2.
Output waveform, FIG. 4 (c) shows the output waveform of the DC cutoff unit 3,
FIG. 4 (d) shows the output waveform of the offset adder.

In FIG. 4 (a), the solid line 10 shows the voltage of the terminal Tm1 based on the voltage of the terminal Tm2, and the broken line 11 shows the voltage of the terminal Tm2. Further, in FIG. 4 (b), the solid line 12 shows the output signal of the differential amplifier 2, and the broken line 13 shows the reference voltage VR. Further, in FIG. 4 (c), the solid line 14 shows the output signal of the DC blocking unit 4, and the broken line 15 shows the reference voltage VR. Further, in FIG. 4 (d), the broken line 16 indicates the addition result of the output signal of the DC blocking unit 4 and the offset voltage, the solid line 17 indicates the output signal of the offset adder 4, and the broken line 18 indicates the reference voltage VR.

If acceleration is not applied until time t11, the voltage between the terminals Tm1 and Tm2 in the sensor unit 1 should originally be 0, but in reality, as shown by the solid line 10 in FIG. ~ Residual voltage VS is generated due to variations in R14. The residual voltage VS is amplified by the differential amplifier 2 and output as shown by the solid line 12 in FIG. 4 (b).

Then, the output signal of the differential amplifier 2 is given to the inverting amplifier via the capacitor C1, but the residual voltage VS is removed, so that the direct current cutoff unit 3 is as shown by the solid line 14 in FIG. 4 (c). , Output reference voltage VR.

The output signal of the DC cutoff unit 3 is given to the offset addition unit 4 and added with the offset voltage VF. However, since the offset addition unit 4 is an inverting type adder, the addition result of both shown by the broken line 16 is the reference voltage. The signal is inverted by VR (see dashed line 18) (see solid line 17).

At time t11, when acceleration is applied to the sensor unit 1, the output signal of the sensor unit 1 starts to fluctuate as shown by the solid line 10 in FIG. 4 (a), and the fluctuation is amplified and output by the differential amplifying unit 2. . That is, the differential amplifier 7 outputs a value corresponding to the acceleration with reference to the voltage obtained by adding the residual voltage VS to the reference voltage VR shown by the broken line 13.

When the output signal of the differential amplification unit 2 is given to the DC cutoff unit 3, the DC cutoff unit 3 removes the residual voltage VS from the output signal of the differential amplification unit 2 with reference to the reference voltage VR (see broken line 15). Output signal (see solid line 14).

Then, the offset addition unit 4 adds the output signal of the DC cutoff unit 3 and the offset voltage VF (see broken line 16),
It outputs a signal with the reference voltage VR inverted around the axis (see solid line 17).

Since the range of the output signal of the offset addition unit 4 is from 0 to the power supply Vcc, the offset addition unit is added during the period in which the result of addition and inversion is negative (the period from time t12 to t13 and time t14 to 15). The output signal of 4 is 0.

In this way, among the output signals of the sensor unit 1, only the negative voltage corresponding to the deceleration is output.

[Problems to be solved by the device]

In order to configure the circuit shown in FIG. 3, five operational amplifiers are required, and there is a problem that the cost is high.

An object of the present invention is to provide a signal processing circuit in which the number of operational amplifiers is reduced while maintaining the same function.

[Means for solving the problem]

In order to solve the above-mentioned problems, the present invention provides a signal processing circuit for amplifying an AC component of an output signal from a signal source, wherein the voltage dividing means divides the voltage of the power source to generate a reference voltage, and the voltage dividing means. An adder for adding a reference voltage generated by the means and an input signal given from an input terminal to output an addition signal; and amplifying the output signal and giving the addition signal as a ground potential to the addition signal. An amplifier whose output signal is suppressed by itself, and a capacitance means for passing an AC component contained in the output signal of the amplifier to the input terminal of the adder, the addition signal of the signal processing circuit being provided. It is characterized in that it is used as an output signal.

[Action]

Since the capacitive means is connected to the input terminal of the adder,
This adder works as a buffer, and the circuit (3rd
The offset adder 4) in the figure prevents unnecessary charging.

Further, the adder adds the output signal of the amplifier and the reference voltage from the voltage dividing means and supplies the ground potential to the amplifier to form a negative feedback, so that the amplifier and the adder operate based on the reference voltage. However, as a result, the adder functions as a buffer for the voltage dividing means and prevents the reference voltage generated by the voltage dividing means from fluctuating by other circuits.

In this way, since the buffer of the capacity means and the buffer of the voltage dividing means are shared by the adder, the cost can be reduced.

[Example of device]

 Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a circuit diagram showing an embodiment of the present invention. The same parts as those in FIG. 3 are designated by the same reference numerals, and detailed description thereof will be omitted.

The output signal of the sensor unit 1 is amplified by the differential amplification unit 7 which constitutes an amplifier, and is given to the inverting amplification unit 6 via the capacitor C2.

In FIG. 1, the differential amplifier 7 and the sensor terminal Tm1,
The connection relationship with Tm2 is different from that in FIG. 3, and the terminal Tm1 is connected to the operational amplifier 71 of the differential amplifier 7 and the terminal Tm2 is connected to the operational amplifier 71. That is, in FIGS. 1 and 3, the positive and negative signs of the output signal of the sensor unit 1 are inverted.

The inverting amplification unit 6 is composed of an operational amplifier 61 and resistors R61 and R62, and inverts the output signal of the differential amplification unit 7 given via the capacitor C2 which is a capacitance means with reference to the reference voltage VR. It amplifies. The inverting amplification unit 6 corresponds to the adder in the present invention, and includes a resistor R71,
The gain (for example, 1) is determined by R72. The reference voltage VR is obtained by dividing the power supply Vcc by the resistors R1 and R2, and the resistors R1 and R2 form a voltage dividing means.

Further, the output signal of the inverting amplification section 6 is given to the above-mentioned differential amplification section 7 as its reference voltage, and when the output signal of the differential amplification section 7 increases, the output signal of the inverting amplification section 6 decreases. A negative feedback loop is formed so as to suppress an increase in the output signal of the differential amplifier 7.

That is, the output signal of the differential amplifier 7 which has amplified the voltage difference between the terminals Tm1 and Tm2 of the sensor unit 1 is obtained when the voltage difference between the terminals Tm1 and Tm2 is amplified by the gain of the differential amplifier 7 alone. With respect to the output signal, the change in the output signal is reduced by the amount attenuated by the output signal from the inverting amplifier 6.

Note that the resistance of the resistors R71 to R74 is set so that the gain of the differential amplifier 7 alone becomes larger than the gain of the differential amplifier 2 in FIG. 3 in anticipation of the negative feedback by the inverting amplifier 6. Is set.

The output signal of the inverting amplification unit 6 is the offset addition unit 4
Given to. The offset adding unit 4 has resistors R1 and R2.
The reference voltage VR is given from the offset voltage VF to the output signal of the inverting amplifier 6 and the result is added to the resistance R
It is configured to invert with respect to a reference voltage VR given by 1, R2.

Next, the operation of this embodiment will be described. First, the differential amplifier 7
The operation of the inverting amplifier 6 will be described.

Considering the signals of each part in terms of AC, the output signal of the sensor unit 1 based on the voltage of the terminal Tm1 is V1, the output signal of the operational amplifier 71 is V2, the output signal of the operational amplifier 72 is V3, the operational amplifier 71.
The output signal of V4 is V4, and the gain of the operational amplifier 72, that is, r74 / r7
When 3 is G1 and the gain of the inverting amplifier 6, that is, r72 / r71 is G2, the following equation is obtained.

V3 = G1 ・ (V1−V2) ＋ V1 ・ ・ ・ (1) V4 ＝ －G2 ・ V3 ・ ・ ・ (2) V2 ＝ －V4 / G1 ・ ・ ・ (3) And if the first formula is substituted into the second formula, become that way.

V4 = -G2 ・ {G1 ・ (V1-V2) + V1} = -G1 ・ G2 ・ (V1-V2) -G2 ・ V1 = -G1 ・ G2 ・ V1−G2 ・ V1 + G1 ・ G2 ・ V2 ＝ − (G1 + 1) G2 ・ V1 ＋ G1 ・ G2 ・ V2 (4) Substituting the third equation into the fourth equation gives the following.

V4 =-(G1 + 1) G2 * V1 + G1 * G2 * (-V4 / G1) =-(G1 + 1) G2 * V1-G2 * V4 (5) The output signal V4 of the inverting amplifier 6 When asked, it becomes as follows.

V4 = {-(G1 + 1) G2 / (G2 + 1)} × V1 (6) Here, the gain G1 of the operational amplifier 71 allows for negative feedback,
Since it is set to be sufficiently larger than 1 (for example, twice the gain of the differential amplifier section 2 in FIG. 3), the output signal V4 of the inverting amplifier section 6 is an amplified signal of the output signal V1 of the sensor section 1. .

Since the inverting amplifier 6 is supplied with the reference voltage VR, its output signal V4 becomes an AC signal based on the reference voltage VR.

FIG. 2 is a waveform diagram showing the operation of the circuit shown in FIG. 1. FIG. 2 (a) is an output signal of the sensor unit 1, FIG. 2 (b) is an output signal of the differential amplifier unit 7, and FIG. 2C shows the output signal of the inverting amplifier 6, and FIG. 2D shows the output signal of the offset adder 4.

In FIG. 2 (a), the solid line l20 shows the voltage of the terminal Tm2 with reference to the voltage of the terminal Tm1, and the broken line l21 shows the voltage of the terminal Tm1. Further, in FIG. 2 (b), the solid line l22 shows the output signal of the differential amplifier 7, and the broken line l23 shows the reference voltage VR. Further, in FIG. 2 (c), the solid line l24 shows the output signal of the inverting amplifier 6 and the broken line l25 shows the reference voltage. Further, in FIG. 2 (d), a broken line l26 shows the addition result of the output signal of the inverting amplifier 6 and the offset voltage, a solid line l27 shows the output signal of the offset addition part 4, and a broken line l28 shows the reference voltage VR.

If acceleration is not applied until time t1, the voltage between the terminals Tm1 and Tm2 in the sensor unit 1 should originally be 0, but actually the resistances R11 to R14 as shown by the solid line l20.
The residual voltage VS is generated due to variations in the voltage. The residual voltage VS is amplified by the differential amplifier 7 and output as shown by the solid line 122 in FIG. 2 (b).

Then, the output signal of the differential amplifier 7 is given to the inverting amplifier via the capacitor C2, but the residual voltage VS is removed, so that the inverting amplifier 6 is set as shown by the solid line l24 in FIG. 2 (c). , Output reference voltage VR.

The output signal of the inverting amplifier 6 is given to the offset adder 4 and added with the offset voltage VF. However, since the offset adder 4 is an inverting adder, the addition result of the two shown by the broken line l26 is the reference voltage. The signal is inverted by VR (see the broken line l28) (see the solid line l27).

At time t1, when acceleration is applied to the sensor unit 1, the second
The output signal of the sensor unit 1 starts to fluctuate as shown by the solid line l20 in FIG. 9A, and the fluctuation is amplified and output by the differential amplifier 7. That is, the differential amplifier 7 outputs a value according to the acceleration with reference to the voltage obtained by adding the residual voltage VS to the reference voltage VR shown by the broken line l23.

When the output signal of the differential amplifier 7 is applied to the inverting amplifier 6 after the residual voltage VS is removed by the capacitor C2, the inverting amplifier 6 uses the reference voltage VR (see the broken line l25) as a reference.
A signal having a phase opposite to the output signal of the differential amplifier 7 is output (see the solid line l24).

Then, the offset addition unit 4 adds the output signal of the inverting amplification unit 6 and the offset voltage VF (see the broken line l26),
Outputs a signal that is the reference voltage VR inverted with respect to the axis (see the solid line l27).

Since the range of the output signal of the offset addition unit 4 is from 0 to the power supply Vcc, the output signal of the offset addition unit 4 is not changed during the period in which the result of addition and inversion is negative (the period from time t2 to t3). It is 0.

In this way, of the output signals of the differential amplifier section 7, the section corresponding to the signal higher than the reference voltage VR, that is, the sensor section 1
Among the voltages at the terminal Tm1 with respect to the terminal Tm2 at, the negative voltage is output.

As described above, in this embodiment, the DC cutoff unit 3 shown in FIG.
Since the operational amplifier 31 for the buffer amplifier and the operational amplifier 51 for the buffer amplifier in the reference voltage generation unit 5 in FIG. 2 are configured to be shared by the inverting amplification unit 6, the number of operational amplifiers is reduced by one compared with the conventional circuit shown in FIG. However, the cost can be reduced.

[Effect of device]

As described above in detail, according to the present invention, since the adder also serves as the buffer amplifier of the capacitance means and the voltage dividing means, the buffer amplifiers are separately provided, but the operational amplifier for the buffer amplifier is provided. The number can be reduced and the cost can be reduced.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, FIG. 2 is a waveform diagram showing the operation of the circuit shown in FIG. 1, FIG. 3 is a circuit diagram showing a conventional signal processing circuit, and FIG. FIG. 4 is a waveform chart showing the operation of the circuit shown in FIG. 3. In the figure, 1: sensor part, 2: differential amplifier part, 6 ... inverting amplifier part,
R1, R2: resistance, C2: capacitor

Claims (1)

(57) [Scope of utility model registration request] 1. In a signal processing circuit for amplifying an AC component of an output signal from a signal source, a voltage dividing means for dividing a voltage of a power source to generate a reference voltage, and a reference voltage generated by the voltage dividing means and an input. An adder that adds an input signal given from a terminal and outputs an added signal; and an amplifier that amplifies the output signal, and that the added signal is given as a ground potential, and the added signal suppresses its own output signal. And an AC component contained in the output signal of the amplifier,
A signal processing circuit, comprising: a capacitance means applied to an input terminal of the adder, wherein the addition signal is an output signal of the signal processing circuit.