JP2515459B2 - Method of forming multilayer wiring - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming multi-layer wiring.

[0002]

2. Description of the Related Art In a large-scale semiconductor integrated circuit (LSI), multi-layered wiring is frequently used to give a degree of freedom to coupling between respective elements arranged in a semiconductor substrate and to form a high density and high speed device. ing.

Conventionally, in a multilayer wiring, as shown in FIG. 9, first, an insulating film 2 is formed on a surface 1 of a semiconductor substrate, the insulating film in a portion necessary for connection with a substrate is removed, and then an aluminum film is formed on the entire surface. Is vapor-deposited, and the aluminum film is patterned to form two or more first lower layer wirings 3a and second lower layer wirings 3b adjacent to each other. Next, in order to form an upper layer wiring, an interlayer insulating film 4 is formed on the insulating film 2 and the first and second lower layer wirings 3a and 3b, and this interlayer insulating film is formed by a known resist etch back method. 4 is flattened. Further, as shown in FIG. 10, after forming a resist 5 on the interlayer insulating film 4, the resist 5 is formed into a predetermined pattern by a well-known photolithography technique. Then, as shown in FIG. 11, the interlayer insulating film on the first and second lower layer wirings 3a and 3b is formed by a well-known reactive ion etching technique (hereinafter referred to as RIE) using the resist 5 having the predetermined pattern as a mask. Openings 6a and 6b for contacts are formed in a part of 4 and the resist 5 is removed as shown in FIG. 12, and then lower layer wirings 3a and 3b in the openings are included as shown in FIG. An aluminum film 7 for upper wiring is formed on the interlayer insulating film 4. Next, as shown in FIG.
A resist 5 is formed on the resist 5 and formed into a predetermined pattern by a well-known photolithography technique. Then, as shown in FIG. 15, the aluminum film 7 is partially removed on the interlayer insulating film 4 existing between the lower layer wirings 3a and 3b by using RIE by using the resist 5 having a predetermined pattern as a mask to mutually Separately and independently, each lower layer wiring 3a, 3
Upper layer wirings 7a and 7b electrically connected to b are formed.
After that, as shown in FIG. 16, the resist 5 is removed by a known resist stripping method, and thereafter, if necessary,
An interlayer insulating film and wiring are alternately formed to obtain a multilayer wiring structure.

However, in these methods, as the space between the lower layer wirings becomes narrower, as shown in FIG.
The resist 5 formed on the interlayer insulating film 4 between a and 3b has an extremely thin pattern. For example, in the case of forming an opening having a width of 1.2 μm between two lower layer wirings and a taper of 75 degrees with respect to an interlayer insulating film having a thickness of 1 μm, a dimension conversion difference of 0.1 μm is considered. The size of the resist 5 formed on the interlayer insulating film 4 between the lower layer wirings 3a and 3b is a thin pattern of 0.57 μm or less, and when the opening is formed,
The resist floats or peels off, and the openings 6a and 6b having a stable shape cannot be obtained. Therefore, patterning of the upper layer wirings 7a and 7b cannot be performed stably, and a short circuit between the upper layer wirings, a disconnection, or the like occurs. Also,
If the mask alignment is deviated during the patterning of the resist, a groove 8 is formed on the side wall of the lower layer wiring as shown in FIG. 11 due to over-etching when the opening is formed, and an aluminum film as the upper layer wiring is deposited. Since the groove width is narrow, it cannot be completely covered, and as shown in FIG. 16, there is a problem that a nest 9 is formed and the yield and reliability of the wiring are lowered.

[0005]

As described above, in the conventional method for forming a multi-layer wiring, as the space between the lower layer wirings is narrowed, the upper layer wirings are disconnected, or the upper layer wirings are short-circuited, or the trenches on the lower layer wiring side wall are formed. However, there is a drawback that the yield and reliability of the wiring are reduced due to the nest of the wiring and the like. Therefore, an object of the present invention is to eliminate the above-mentioned drawbacks and to provide a method for forming a multilayer wiring with high yield and high reliability.

[0006]

In order to achieve the above object, according to the present invention, a first lower layer wiring planned region, a second lower layer wiring planned region and a separation planned region between the lower layer wirings are formed on a semiconductor substrate. A step of forming a conductive film for the lower layer wiring, a step of forming an interlayer insulating film on the semiconductor substrate including the conductive film, and an opening for partially removing the interlayer insulating film to expose the conductive film A step of forming an upper layer wiring on the surface of the conductive film and the interlayer insulating film exposed in the opening, and a conductive film and an upper layer wiring on the separation planned region between the lower layer wirings at the same time. And selectively removing the first and second lower layer wirings and the upper layer wirings from each other. Further, it is characterized in that the distance between the regions to be separated between the lower layer wirings is about 2 microns or less. The opening is characterized by including at least two or more lower layer wiring regions.

[0007]

In the multi-layer wiring forming method configured as described above, the conductive is formed on the first lower layer wiring planned region, the second lower layer wiring planned region, and the separation planned region between the first and second lower layer wirings. A film is formed, and an opening having a size that can include this conductive film is formed. Further, an upper layer wiring is deposited on the interlayer insulating film including the opening, and the conductive film on the separation planned region between the lower layer wirings and the upper layer wiring portion located on this conductive film are selectively removed at the same time to form the upper layer. The wiring and the conductive film are separated and independent from each other.

Therefore, since there is no thin resist pattern portion as in the conventional method and a predetermined opening shape can be obtained, the upper wiring can be reliably separated and isolated, and the yield and reliability of wiring can be improved.

Further, the upper layer wiring and the lower layer wiring can be processed by self-alignment using the same mask. Therefore, there is no pattern shift between the upper layer wiring and the lower layer wiring, and the lower layer wiring is not abnormally etched by over-etching when processing the upper layer wiring. As a result, the yield and reliability are improved without the formation of cavities during the upper layer wiring.

Further, since the opening area of the opening is large and the aspect ratio in the opening is small, the coverage of the upper wiring is improved, the opening resistance is stabilized, the yield is improved, and the electromigration resistance in the opening is improved. Heightened and improved in reliability. From the above, according to the present invention, a multilayer wiring with high yield and high reliability can be obtained.

[0011]

EXAMPLE First, as shown in FIG. 1, a semiconductor substrate surface 1
After forming the insulating film 2 on the upper part and removing the part of the insulating film necessary for connection with the substrate, an aluminum film is vapor-deposited on the entire surface, and the aluminum film is patterned to form the first and second lower wiring planned regions. The conductive film 3 is formed on the regions 10a, 10b and the planned isolation region 10c between the lower layer wirings. Next, in order to form an upper layer wiring, the insulating film 2 and the conductive film 3 are formed.
An interlayer insulating film 4 is formed on the interlayer insulating film 4, and the interlayer insulating film 4 is flattened by a known resist etch back method. Next, as shown in FIG. 2, after forming a resist 5 on the interlayer insulating film 4, the resist 5 is formed into a predetermined pattern by a well-known photolithography technique. The opening 5a of the resist 5 is formed to have a size including the conductive film 3. next,
As shown in FIG. 3, by well-known tapered reactive ion etching (hereinafter, referred to as tapered RIE), the interlayer insulating film 4 exposed from the opening 5a of the resist is uniformly formed using the resist 5 having the predetermined pattern as a mask. And is removed until the conductive layer 3 is reached, and an opening 6c for contact is formed. Next, as shown in FIG.
Is removed by a well-known resist stripping method, as shown in FIG. 5, an aluminum film 7 for an upper wiring is formed on the interlayer insulating film 4 including the conductive layer 3 in the opening 6c. Further, as shown in FIG. 6, a resist 5 is formed in a predetermined pattern having an opening above the conductive film and the aluminum film 7 on the separation planned region 10c between the first and second lower layer wirings by a photography technique. Then, as shown in FIG. 7, the aluminum film 7 existing on the planned separation region 10c between the first and second lower layer wirings is partially removed by RIE using the resist 5 having a predetermined pattern as a mask. Then, they are separated from each other to form upper wirings 7a and 7b. At the same time, by using the resist 5 having a predetermined pattern as a mask, the conductive film 3 existing on the separation planned region 10c between the first and second lower layer wirings is partially removed until it reaches the insulating film 2 so as to be separated and independent from each other. Wirings 11a and 11b are used. Then, the separate and independent conductive films, that is, the separate and independent lower layer wirings 11a and 11b and the upper layer wirings 7a and 7b are electrically connected. Then, as shown in FIG.
Is removed by a well-known resist stripping method, and thereafter, an interlayer insulating film and wiring are alternately formed as needed to obtain a multilayer wiring structure.

[0012]

As described above, according to the method for forming a multilayer wiring, an ideal opening shape can be obtained without requiring a thin resist pattern portion as in the conventional method, and the upper layer wiring can be separated. Independence is ensured. The lower layer wiring and the upper layer wiring of the opening can be processed by self-alignment using the same mask. Therefore, there is no pattern shift between the upper layer wiring and the lower layer wiring, and the lower layer wiring is not abnormally etched by over-etching when processing the upper layer wiring. As a result, no nests or grooves are formed during the upper layer wiring.
Further, since the opening area is large, the coverage of the aluminum film is improved, and the aluminum film on the side wall of the opening is thickened. Therefore, the cross-sectional area of the wiring is increased and the current density is not increased,
Electromigration resistance is improved. Therefore, it is possible to obtain a multilayer wiring with high yield and high reliability.

[Brief description of drawings]

FIG. 1 is a diagram showing a process of forming a multilayer wiring in an example of the present invention.

FIG. 2 is a diagram showing a process of forming a multilayer wiring according to an embodiment of the present invention.

FIG. 3 is a diagram showing a process of forming a multilayer wiring according to an example of the present invention.

FIG. 4 is a diagram showing a process of forming a multilayer wiring according to an example of the present invention.

FIG. 5 is a diagram showing a process of forming a multilayer wiring according to an example of the present invention.

FIG. 6 is a diagram showing a process of forming a multilayer wiring according to an example of the present invention.

FIG. 7 is a diagram showing a process of forming a multilayer wiring according to an example of the present invention.

FIG. 8 is a diagram showing a step of forming a multilayer wiring in the example of the present invention.

FIG. 9 is a diagram showing a conventional multi-layer wiring forming process.

FIG. 10 is a diagram showing a conventional multi-layer wiring forming process.

FIG. 11 is a diagram showing a conventional process of forming a multilayer wiring.

FIG. 12 is a diagram showing a conventional process of forming a multilayer wiring.

FIG. 13 is a diagram showing a conventional multi-layer wiring forming process.

FIG. 14 is a diagram showing a conventional multi-layer wiring forming process.

FIG. 15 is a diagram showing a conventional process of forming a multilayer wiring.

FIG. 16 is a diagram showing a conventional multilayer wiring forming process.

[Explanation of symbols]

 1 semiconductor substrate 2 insulating film 3a, 3b lower layer wiring 3 conductive film 4 interlayer insulating film 5 resist 5a opening 6a opening 6b opening 6c opening 7 aluminum film 7a upper layer wiring 7b upper layer wiring 8 groove 9 nest 10a first lower layer wiring Planned area 10b Second lower layer wiring planned area 10c Planned separation area between lower layer wirings 11a First lower layer wiring 11b Second lower layer wiring

Claims (3)

(57) [Claims] 1. A step of forming a conductive film for a lower layer wiring on a first lower layer wiring planned region, a second lower layer wiring planned region and a planned separation region between the lower layer wirings on a semiconductor substrate, and the conductive film. A step of forming an interlayer insulating film on the semiconductor substrate including: a step of partially removing the interlayer insulating film to form an opening exposing the conductive film; and the conductive film exposed in the opening. And a step of forming an upper layer wiring on the surface of the interlayer insulating film, and selectively removing the conductive film and the upper layer wiring on the separation planned region between the lower layer wirings at the same time, And a step of separating upper layer wirings from each other to be independent of each other. 2. The method for forming a multi-layer wiring according to claim 1, wherein an interval between the regions to be separated between the lower layer wirings is about 2 μm or less. 3. The method for forming a multilayer wiring according to claim 1, wherein the opening includes at least two or more lower layer wiring planned regions.