JP2504153B2 - Signed digit number sign judgment circuit - Google Patents

Description

The present invention relates to a signed digit number positive / negative determination circuit used in a digital calculator.

[Conventional technology]

The number of digits with a sign is a number expression in which each digit has a weight of a power of 2 and takes any one of -1, 0, and +1. For example, a 4-digit signed digit number (0,
The value of -1, 0, +1) is 0x2 ³ + (-1) x2 ³ + 0x2 ¹
+ (+ 1) × 2 ³ = −3, and similarly (0, + 1, −1, −
The value of 1) is 0 × 2 ³ + (+ 1) × 2 ² + (− 1) × 2 ¹ +
(−1) × 2 ³ = 1. As can be seen from these examples, whether the signed digit number is positive or negative is determined to be negative or positive depending on whether the most significant non-zero digit is -1 or +1. As described above, the signed digit number cannot be determined as positive or negative by a specific bit (most significant bit) like a two's complement binary number.

Therefore, conventionally, the positive / negative determination of the number of signed digits is, as in the example shown in FIG. 5, a binary number in which only the digit that is +1 is 1 and a digit in which only the digit that is -1 is 1. Significance was determined by performing subtraction with a base number and converting into a normal two's complement display binary number. The binary subtraction can be realized by addition of 2's complement as is well known. That is, the conversion from a signed digit number to a two's complement binary number can be realized by using an adder circuit.

[Problems to be Solved by the Invention]

In this conventional method, an addition circuit is required to convert a signed digit number into a two's complement display binary number, resulting in a large amount of hardware.

SUMMARY OF THE INVENTION An object of the present invention is to provide a signed digit number positive / negative determination circuit configured by a simple unit circuit repeating structure composed of a switch means and a delay means.

[Means for solving the problem]

According to the configuration of the present invention, an n (n is a positive integer) bit register, n switch means connected to input each bit output of the n bit register, and a logic for inputting each output of the switch means. Summing means, each of the n-1 sets of switching control signal terminal pairs consisting of switching control signal terminals of adjacent ones of the n switch means are connected by delay means, and the n-1 sets Of the two switching control signal terminals of each of the switching control signal terminals, the switching control signal terminal of the switch means connected to the higher-order bit output of the n-bit register is input to the respective delay means. A first circuit obtained by being connected, and a second circuit which is equal to the first circuit.
And a circuit of.

[Action]

It is assumed that one digit of the number of signed digits is represented by the same bit pair of the n-bit registers of the first circuit and the second circuit. For example, -1, 0, +1 of each digit of the number of signed digits is (1, 0), (0, 0),
Expressed as (0, 1). Here, the first and second bits in parentheses are bits held by the n-bit registers of the first circuit and the second circuit, respectively.

The bits of these two n-bit registers are sequentially read from the most significant bit and simultaneously with respect to the same bit by the delay means and the switch means. Then, the output of the logical sum means of the circuit to which the n-bit register having the non-zero bit in the higher order belongs becomes 1 before the output of the other logical sum means. By detecting this, it is determined whether the bit pair is (1, 0) or (0, 1), that is, as the number of signed digits, the highest non-zero digit is -1 or +1. Can be determined.

〔Example〕

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of an embodiment showing the configuration of the present invention. An embodiment using a concrete circuit as the delay means, the switch means, and the logical sum means will be described below.

FIG. 2 is a circuit diagram showing the first embodiment of the present invention. In this embodiment, an 8-bit register is used with n = 8. Further, AND gates 31 to 38 and AND gates 71 to 78 are used as the switch means described in the claims of the claims.
Inverter pairs 81-87 of inverter pairs 41-47 connected in series are used as delay means, and 8-input OR gate 21 and OR gate 61 are used as OR means.

Each of the signed digit numbers -1, 0, +1 is represented as a bit pair by (1, 0), (0, 0), (0, 1). Here, the first bit in the parentheses is represented by each bit of the 8-bit register 11 of the second first circuit 1, and the second bit in the parenthesis is the 8 bits of the second circuit 2 in FIG. It shall be expressed by each bit of the register 51. As an example, first
When 00101000 is held in the 8-bit register 11 of the circuit 1 and 00010101 is held in the 8-bit register 51 of the second circuit 2, that is, 8 bits are held by these two 8-bit register pairs. A case will be described in which the number of digits with signed digits is (0, 0, -1, +1, -1, +1, 0, +1) and the value as a decimal number is -19.

Also, inverter pair 41-47 and inverter pair 81-87
The delay time of t _pd1 , AND gates _31-38 and AND gate 71
The delay time of _~ 78 is t _pd2 , the delay time of the OR gate 21 and the OR gate 61 is t _pd3, and a pulse is applied to the switching control signal terminal 150 at time t = 0.

In the first circuit 1, the most significant 1 is located in the third bit from the most significant bit of the 8-bit register 11. In this case, the pulse applied to the switching control signal terminal 150 propagates through the upper two inverter pairs 47 and 46, the third AND gate 36 from the left, and the OR gate 21, and the output becomes 1. Therefore, its propagation time is 2t _pd1 + t _pd2 + t _pd3
After, that is, t = t ₁ = 2t _pd1 + t _pd2 + t _pd3 , the OR gate 21
Output becomes 1. On the other hand, in the second circuit 2, 8
Since there is a most significant 1 from the most significant bit to the 4th bit of the bit register 51, the switching control signal terminal 150
Pulse propagates through the upper three inverter pairs 87, 86 and 85, the fourth AND gate 75 and OR gate 61 from the left, and the output becomes 1. Therefore, after the propagation time of 3t _pd1 + t _pd2 + t _pd3 , that is, t = t ₂ = 3t _pdn1 + t
The output of the OR gate 21 becomes 1 when _pd2 + _tpd3 . As a result, the output of the OR gate 21 of the first circuit 1 becomes
It becomes 1 earlier than the output of the OR gate 61 by t ₂ −t ₁ = t _pd 1. From the above, the 8-bit register having the most significant 1 at the higher order is the 8-bit register 11 of the first circuit 1, which is the most significant as the number of signed digits from the above-described representation method of the number of signed digits. It can be seen that non-zero is -1. That is, it can be determined that the number of signed digits is negative.

An example of a circuit for determining which of the two OR gates 21 and 61 outputs 1 first, that is, a circuit for detecting which of the two inputs becomes 1 will be described below.

FIG. 3 (a) is a circuit diagram of a circuit for detecting which of the two inputs becomes 1 first, and FIG. 3 (b) is a known RS flip-flop used in FIG. 3 (a). It is a truth table of the type.

First, 1 is input to the reset terminal 209 to enter the initial state and the Q outputs 204 and 208 of the RS flip-flops 202 and 206 are input.
Is reset to 0. S input 2 of RS flip-flop 202
Assuming that 01 is input to the former at 01 and the S input 205 of the RS flip-flop 206, the Q output 204 thereof becomes 1. R
Q output even if 1 is input to the S input 205 of the RS flip-flop 206 after the S input 201 of the S flip-flop 202
Since 204 is input to the reset terminal of the RS flip-flop 206 through the OR gate 207, it is forcibly reset. As a result, the Q output 204 of the RS flip-flop 202
Holds 1 and the Q output 208 of the RS flip-flop 206 is 0
Will be held.

FIG. 4 is a circuit diagram showing a second embodiment of the present invention. In this embodiment, an 8-bit register is used with n = 8. Further, as the switch means described in the claims, the transfer gates 131 to 138 and the transfer gates 171 to 178 are connected in series as delay means to form an inverter pair 141 to 147 and an inverter pair 181-187.
Is used as the logical sum means, and the wire doors 121 and 161 are used. The present embodiment is different from the embodiment shown in FIG. 2 only in the method of implementing the switch means and the logical sum means, and the operation of determining the sign of the number of signed digits is the same as that of the embodiment shown in FIG. Is.

〔The invention's effect〕

As described above, the present invention provides a circuit that can determine the sign of a signed digit number without converting it to a two's complement binary number. Moreover, since it is configured by repeatedly connecting a simple unit circuit composed of a switch means and a delay means, even if the number of digits of the number of signed digits to be handled changes, the circuit can be easily designed. Have.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of the present invention, FIG. 2 is a diagram showing a first embodiment of the present invention, and FIG. 3 is a circuit for detecting which of two inputs is 1 first. Circuit diagram of example circuit,
FIG. 4 is a circuit diagram showing a second embodiment of the present invention, and FIG. 5 is a diagram for explaining a method of converting a signed digit number into a two's complement display binary number. 1 ... First circuit, 2 ... Second circuit, 3 ... Switch means, 4 ... First circuit, 10 ... n bit register, 20
... OR means, 50 ... Switching control signal terminal.

Claims (1)

(57) [Claims] 1. An n-bit register (n is a positive integer), n switch means connected so as to input each bit output of the n-bit register, and a logical sum for inputting each output of the switch means. Means, each of n-1 sets of switching control signal terminal pairs consisting of switching control signal terminals of adjacent ones of the n switch means is connected by delay means, and the n-1 sets of switching control signal terminals are connected. Of the two switching control signal terminals of each switching control signal terminal pair,
The switching control signal terminal of the switch means connected to the higher-order bit output of the n-bit register is
A signed digit number plus / minus determination circuit comprising a first circuit obtained by being connected to an input of each of the delay means and a second circuit equal to the first circuit.