JP2502296B2 - Bias application method - Google Patents

Bias application method

Info

Publication number
JP2502296B2
JP2502296B2 JP61264481A JP26448186A JP2502296B2 JP 2502296 B2 JP2502296 B2 JP 2502296B2 JP 61264481 A JP61264481 A JP 61264481A JP 26448186 A JP26448186 A JP 26448186A JP 2502296 B2 JP2502296 B2 JP 2502296B2
Authority
JP
Japan
Prior art keywords
developing
roller
voltage
bias
electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP61264481A
Other languages
Japanese (ja)
Other versions
JPS63118169A (en
Inventor
雄一 小林
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ricoh Co Ltd
Original Assignee
Ricoh Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ricoh Co Ltd filed Critical Ricoh Co Ltd
Priority to JP61264481A priority Critical patent/JP2502296B2/en
Publication of JPS63118169A publication Critical patent/JPS63118169A/en
Application granted granted Critical
Publication of JP2502296B2 publication Critical patent/JP2502296B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Classifications

    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02PCLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P10/00Technologies related to metal processing
    • Y02P10/20Recycling

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  • Developing For Electrophotography (AREA)
  • Wet Developing In Electrophotography (AREA)

Description

【発明の詳細な説明】 (技術分野) 本発明は複写機等に用いられる現像装置におけるバイ
アス印加方法に関する。
TECHNICAL FIELD The present invention relates to a bias applying method in a developing device used in a copying machine or the like.

(従来技術) 複写機等の画像形成装置においては感光体又は誘電体
からなる記録媒体上に静電潜像を形成してこれを現像す
ることにより顕像化し、この顕像を転写紙に転写させる
と共に記録媒体上に残った像をクリーニングし、このよ
うな行程をくり返して行なっている。この画像形成装置
では記録媒体上の静電潜像を現像部において現像して顕
像化する行程で現像電極に電圧を印加して現像時に記録
媒体上の非画像部にトナーが付着することを防止する方
法が採られており、この現像電極に電圧を印加すること
をバイアスをかけると言っている。バイアスをかける方
法には現像電極に常に一定の電圧を印加する固定バイア
ス方式、記録媒体より現像電極に電圧が誘起されてこれ
が常に変化するフロートバイアス方式、このフロートバ
イアス方式と固定バイアス方式の特性を組合せたセミフ
ロートバイアス方式、記録媒体上の電位を検出してその
電位に応じたバイアスを現像電極に印加するオートバイ
アス方式等がある。
(Prior Art) In an image forming apparatus such as a copying machine, an electrostatic latent image is formed on a recording medium made of a photoconductor or a dielectric, and the latent image is developed to be visualized, and the visualized image is transferred to a transfer paper. Then, the image remaining on the recording medium is cleaned, and such a process is repeated. In this image forming apparatus, a voltage is applied to the developing electrode in the process of developing and visualizing the electrostatic latent image on the recording medium in the developing section to prevent toner from adhering to the non-image area on the recording medium during development. A method of preventing is adopted, and applying a voltage to this developing electrode is said to apply a bias. The biasing method includes a fixed bias method in which a constant voltage is always applied to the developing electrode, a float bias method in which a voltage is induced from the recording medium to the developing electrode, and this always changes, and characteristics of the float bias method and the fixed bias method. There are a combined semi-float bias system, an auto bias system in which a potential on a recording medium is detected and a bias corresponding to the potential is applied to a developing electrode.

オートバイアス方式では通常、記録媒体上に静電潜像
を形成した後この静電潜像を現像する直前に記録媒体の
表面電位を検出してその検出電位に応じた電圧を現像電
極に印加している。この現像電極に印加する電圧は通
常、バイアス印加が画像の地肌部を現像させない目的を
持っているので、上記検出電圧の最低値に所定の電圧、
例えば+40V〜100V位の電圧を付加したものとしてい
る。
In the auto-bias method, usually, after the electrostatic latent image is formed on the recording medium, immediately before the electrostatic latent image is developed, the surface potential of the recording medium is detected and a voltage corresponding to the detected potential is applied to the developing electrode. ing. Since the voltage applied to the developing electrode usually has the purpose of not applying a bias to develop the background portion of the image, a predetermined voltage is applied to the minimum value of the above detection voltage,
For example, it is assumed that a voltage of about + 40V to 100V is added.

現像電極としては従来は面状のものを記録媒体に近接
させて現像を行う皿現像方式が一般的に採用されてい
た。この方式では現像効果が安定している反面、現像電
極をドラム状等の記録媒体に接近させて配置するので、
部品精度,組付精度が必要になり、又そのことと関連し
て現像に一定の時間が必要になる。さらに、現像時に現
像電極側に付着したトナーを何らかの方法で取り去る必
要があり、その方法として現像電極に逆バイアスを印加
して現像電極の付着トナーを記録媒体側に吸引させてク
リーニングを行う等の方法が採られている。又皿現像方
式とは別にローラ現像方式というものが最近採用される
ようになった。このローラ現像方式は従来より知られて
いる方式であるが、現像電極としての現像ローラが現像
時に記録媒体上の静電潜像に近接する時間が非常に短い
ので、良好な現像が行なえない。そこでこのローラ現像
方式を採用する場合には多段の現像が必要とされたが、
反面、ローラ現像方式は皿現像方式で行なった現像電極
のクリーニングに関しては現像電極の機械的クリーニン
グが行えるので、特別のクリーニング工程を必要としな
いという利点がある。又最近のトナーの改良により現像
ローラを必ずしも上述の如く多段にする必要がなくな
り、現像ローラが1〜4本程度でも十分に良好な現像が
行えるようになって最近改めて見直されるようになっ
た。さらにローラ現像方式は記録媒体に対する現像部の
位置がある程度自由に選択できる(皿現像方式では現像
の性質上記録媒体の下側という条件がついてしまう)と
いう利点があり、この点からも最近改めて注目されるよ
うになった。
Conventionally, as a developing electrode, a plate developing method has been generally adopted in which a planar electrode is brought close to a recording medium for developing. In this method, the developing effect is stable, but on the other hand, since the developing electrode is arranged close to the drum-shaped recording medium,
Part accuracy and assembly accuracy are required, and in connection with that, a certain time is required for development. Further, it is necessary to remove the toner adhering to the developing electrode side at the time of development by some method, and as a method for that, a reverse bias is applied to the developing electrode to attract the adhering toner on the developing electrode to the recording medium side for cleaning. The method is adopted. In addition to the plate developing system, a roller developing system has recently been adopted. This roller developing system is a conventionally known system. However, since the developing roller as a developing electrode is very close to the electrostatic latent image on the recording medium at the time of development, good developing cannot be performed. Therefore, when adopting this roller development method, multi-stage development was required.
On the other hand, the roller developing method has an advantage that no special cleaning process is required because the developing electrode can be mechanically cleaned with respect to the cleaning of the developing electrode performed by the plate developing method. Further, due to recent improvements in toner, it is not always necessary to provide the developing roller in multiple stages as described above, and sufficient development can be performed even with one to four developing rollers, which has recently been reviewed again. Further, the roller developing method has an advantage that the position of the developing portion with respect to the recording medium can be freely selected to some extent (the dish developing method has a condition of being under the recording medium due to the nature of development), and from this point, attention has been paid again recently Came to be.

しかしローラ現像方式では記録媒体の電位をどのよう
にして検出するかが問題となる。従来の皿現像方式では
皿の先端の一部を検出電極として利用できるが、ローラ
現像方式ではそのようなことができず、現像装置の一部
を検出電極に利用するということにより、最初の現像ロ
ーラに検出電極と現像電極を兼ねさせるという方式が提
案されている。この方式は記録媒体上の静電潜像の先端
が最初の現像ローラを通過してある一定の距離を進む時
に最初の現像ローラに誘起された電圧を検出し、この検
出電圧に応じたバイアス電圧を最初の現像ローラ及びそ
れ以後の現像ローラに印加するものである。
However, in the roller developing method, how to detect the potential of the recording medium becomes a problem. In the conventional dish developing method, a part of the tip of the dish can be used as a detection electrode, but in the roller developing method, this cannot be done. A method has been proposed in which the roller also serves as a detection electrode and a development electrode. This method detects the voltage induced on the first developing roller when the leading edge of the electrostatic latent image on the recording medium passes a certain distance after passing the first developing roller and detects the bias voltage corresponding to this detected voltage. Is applied to the first developing roller and the subsequent developing rollers.

しかしこの方式では静電潜像の先端部が最初の現像ロ
ーラを通過する時にこの現像ローラに誘起された電圧を
検出して最初の現像ローラ及びそれ以外の現像ローラに
バイアスを印加するので、静電潜像の先端部は最初の現
像ローラにおけるバイアス印加が不足し、他の部分に比
べて地肌が出てしまう。
However, in this method, when the leading edge of the electrostatic latent image passes the first developing roller, the voltage induced on this developing roller is detected and a bias is applied to the first developing roller and the other developing rollers. At the leading end of the latent electrostatic image, the bias application at the first developing roller is insufficient, and the background is exposed as compared with other portions.

(目的) 本発明は上記欠点を除去し、画像先端部の地肌汚れを
なくすことができるバイアス印加方法が提供することを
目的とする。
(Object) It is an object of the present invention to provide a bias applying method capable of eliminating the above-mentioned drawbacks and eliminating the background stain on the image front end portion.

(構成) 本発明は、複数の現像ローラにより静電潜像を現像す
る現像装置におけるバイアス印加方法において、前記複
数の現像ローラのうちの検出電極として用いられる現像
ローラを通過する像により該検出電極用現像ローラに誘
起した電圧を検出し、この検出電圧に応じて前記複数の
現像ローラにバイアス電圧を印加し、且つ、前記検出に
用いた像領域が前記複数の現像ローラのうちの前記検出
電極用現像ローラ以降の他の現像ローラを通過する間は
前記他の現像ローラに印加するバイアス電圧を補正す
る。
(Structure) The present invention provides a bias applying method in a developing device for developing an electrostatic latent image by a plurality of developing rollers, wherein the detection electrode is detected by an image passing through a developing roller used as a detection electrode among the plurality of developing rollers. The voltage induced on the developing roller is detected, a bias voltage is applied to the plurality of developing rollers according to the detected voltage, and the image area used for the detection is the detection electrode of the plurality of developing rollers. The bias voltage applied to the other developing roller is corrected while passing the other developing roller after the developing roller for use.

以下図面を参照しながら本発明の実施例について説明
する。
Embodiments of the present invention will be described below with reference to the drawings.

第3図は複写機の一例における現像装置を示す。この
複写機においては感光体ドラム1はモータにより矢印方
向へ回転駆動されてコロナ放電器で一様に帯電された後
に露光装置により原稿像が露光されて静電潜像が形成さ
れ、この静電潜像が現像装置2により現像されて給紙装
置からの転写紙に転写される。現像装置2は現像ローラ
3,4及びスクイズローラ5が感光体ドラム1の周囲に微
小間隔をおいてその回転方向に沿って配置され、駆動装
置により現像ローラ3,4が感光体ドラム1と逆の方向に
回転してスクイズローラ5が感光体ドラム1と同じ方向
に回転する。現像液はタンクからポンプにより汲上げら
れてノズル6より感光体ドラム1と現像ローラ3,4の間
に供給され、感光体ドラム1上の静電潜像が現像され
る。スクイズローラ5は感光体ドラム1上の余分な現像
液を除去し、現像ローラ3,4及びスクイズローラ5上の
現像液はスクレーパ7〜9により除去されて現像容器10
を介してタンクに回収される。感光体ドラム1上の静電
潜像が最初に通過する現像ローラ3は検出電極として用
いられ、かつ現像ローラ3,4が現像電極として用いられ
る。
FIG. 3 shows a developing device in an example of a copying machine. In this copying machine, the photosensitive drum 1 is rotationally driven in the direction of the arrow by the motor and uniformly charged by the corona discharger, and then the original image is exposed by the exposure device to form an electrostatic latent image. The latent image is developed by the developing device 2 and transferred to the transfer paper from the paper feeding device. The developing device 2 is a developing roller
3, 4 and the squeeze roller 5 are arranged around the photosensitive drum 1 with a minute interval along the rotation direction thereof, and the developing rollers 3, 4 are rotated in the opposite direction to the photosensitive drum 1 by the driving device. The squeeze roller 5 rotates in the same direction as the photosensitive drum 1. The developer is pumped up from the tank by a pump and supplied from the nozzle 6 between the photosensitive drum 1 and the developing rollers 3 and 4, so that the electrostatic latent image on the photosensitive drum 1 is developed. The squeeze roller 5 removes the excess developer on the photosensitive drum 1, and the developer on the developing rollers 3, 4 and the squeeze roller 5 is removed by scrapers 7 to 9 to remove the developer.
It is collected in the tank via. The developing roller 3 through which the electrostatic latent image on the photosensitive drum 1 first passes is used as a detection electrode, and the developing rollers 3 and 4 are used as developing electrodes.

第1図は本発明の実施回路例を示し、第2図はそのタ
イミングチャートである。第1図においてRA1,RA2はリ
レー、CVはDC−DCコンバータ、D1〜D4はダイオード、Z1
〜Z4はツェナーダイオード、FETは電界効果トランジス
タ、Q1〜Q4はトランジスタ、C1〜C3はコンデンサ、RA11
はリレーRA1の常閉接点、RA12,RA13はリレーRA1の常開
接点、RA21はリレーRA2の常開接点、R1〜R9の抵抗、A
〜Cは複写機の制御部よりタイミング信号が印加される
端子、D,Eは現像ローラ3,4にそれぞれ接続される端子で
ある。また電界効果トランジスタFET、トランジスタQ1,
Q2、ダイオードD3,D4、コンデンサC1,C2、接点RA12,RA1
3、抵抗R3〜R6は検出回路VDを構成し、コンデンサC3及
び抵抗R8,R9は記憶回路Mを構成し、トランジスタQ3,Q
4、ツェナーダイオードZ3,Z4、接点RA11,RA21、抵抗R7
は出力回路OCを構成する。
FIG. 1 shows an example of an embodiment circuit of the present invention, and FIG. 2 is a timing chart thereof. In Fig. 1, RA1 and RA2 are relays, CV is a DC-DC converter, D1 to D4 are diodes, and Z1.
~ Z4 is a Zener diode, FET is a field effect transistor, Q1 to Q4 are transistors, C1 to C3 are capacitors, RA11
Is a normally closed contact of relay RA1, RA12 and RA13 are normally open contacts of relay RA1, RA21 is a normally open contact of relay RA2, resistances of R1 to R9, A
˜C are terminals to which a timing signal is applied from the control section of the copying machine, and D and E are terminals connected to the developing rollers 3 and 4, respectively. In addition, field effect transistor FET, transistor Q1,
Q2, diodes D3, D4, capacitors C1, C2, contacts RA12, RA1
3, the resistors R3 to R6 constitute the detection circuit VD, the capacitor C3 and the resistors R8 and R9 constitute the memory circuit M, and the transistors Q3 and Q
4, Zener diode Z3, Z4, contact RA11, RA21, resistor R7
Constitutes the output circuit OC.

リレーRA1,RA2及びDC−DCコンバータCVは制御部から
端子A〜Cを介して第2図に示すように制御され、すな
わちDC−DCコンバータCVは感光体ドラム1上の静電潜像
が現像部を通過する時T1にオンして高電圧を出力し、リ
レーRA1は感光体ドラム1の表面電位を検出すべき時
間、つまり感光体ドラム1上の静電潜像の先端部が現像
ローラ3を通過する時間T2にオンして常閉接点RA11を開
き常開接点RA12,RA13を閉じる。そしてリレーRA2はこの
表面電位検出時間T2と、静電潜像の上記先端部の後縁が
現像ローラ3,4間を通過する時間T3とからなる時間T4
オンして常開接点RA21を閉じる。
The relays RA1 and RA2 and the DC-DC converter CV are controlled by the control section via terminals A to C as shown in FIG. 2, that is, the DC-DC converter CV develops the electrostatic latent image on the photosensitive drum 1. When passing through the section, it is turned on at T 1 to output a high voltage, and the relay RA1 detects the surface potential of the photosensitive drum 1, that is, the tip of the electrostatic latent image on the photosensitive drum 1 is the developing roller. At time T 2 when passing through 3, the normally closed contact RA11 is opened and the normally open contacts RA12, RA13 are closed. The relay RA2 and the surface potential detection time T 2, the normally open contact is turned on to the time T 4 consisting of time T 3 Metropolitan the trailing edge of the leading end portion of the electrostatic latent image passes between the developing roller 3, 4 Close RA21.

まず表面電位検出時間T2ではリレーRA1がオンした状
態で現像ローラ3に誘起された電圧が検出回路VDにおけ
る電界効果トランジスタFETのゲートに入力される。電
界効果トランジスタFETを用いたのは現像ローラ3に誘
起される電圧が微小であるから検出回路VDの入力インピ
ーダンスを高抵抗にして誘起電圧への影響をなくすため
であり、検出回路VDは電界効果トランジスタFETの入力
を電流増幅して記憶回路Mへ出力する。記憶回路Mは検
出回路VDの出力によりコンデンサC3が充電されてその電
圧を少なくとも現像時T1は記憶し、出力回路OCはコンデ
ンサC3の電圧に応じてバイアス電圧を決定する。出力回
路OCは入力に対してトランジスタQ4のコレクタ出力が1
対1の形で出てこれに+αの電圧を上乗せする。この+
αは通常+40V〜+80V位である。高い電圧(+100V〜+
200V)をツェナーダイオードZ3,Z4により上記時間T4
上乗せして現像ローラ4に印加する。したがって現像ロ
ーラ4に印加されるバイアス電圧は静電潜像の先端部が
現像ローラ4を通過するまで高く補正され、静電潜像の
先端部による現像ローラの誘起電圧を検出するために静
電潜像の先端部の現像でバイアスが不足するということ
がなくなって画像先端部の地肌汚れが解消する。上記時
間T4か経過して静電潜像の先端部が現像ローラ4を通過
すると、リレーRA2がオンしてその常開接点RA21により
ツェナーダイオードZ3が短絡され、+αがツェナーダイ
オードZ4による通常の電圧となって通常のバイアス電圧
が現像ローラ4に印加される。現像ローラ3は表面電位
検出時間T2にはリレーRA1のオンで上述の如く検出電極
として用いられ、この後はリレーRA1のオフで現像電極
として出力回路OCから通常のバイアス電圧が印加され
る。
First surface potential detection time T 2 the relay RA1 is the voltage induced in the developing roller 3 in a state of ON is input to the gate of the field effect transistor FET in the detection circuit VD. The field effect transistor FET is used because the voltage induced in the developing roller 3 is very small and the input impedance of the detection circuit VD is made high to eliminate the influence on the induced voltage. The input of the transistor FET is current-amplified and output to the memory circuit M. The storage circuit M stores the voltage of the capacitor C3 charged by the output of the detection circuit VD and stores the voltage at least during development T 1 , and the output circuit OC determines the bias voltage according to the voltage of the capacitor C3. In the output circuit OC, the collector output of the transistor Q4 is 1 with respect to the input.
It comes out in the form of 1 and adds a voltage of + α to it. This +
α is usually around + 40V to + 80V. High voltage (+ 100V to +)
(200 V) is applied to the developing roller 4 by adding the time T 4 with the Zener diodes Z3 and Z4. Therefore, the bias voltage applied to the developing roller 4 is highly corrected until the leading edge of the electrostatic latent image passes the developing roller 4, and the electrostatic voltage is detected in order to detect the induced voltage of the developing roller by the leading edge of the electrostatic latent image. There is no shortage of bias in the development of the leading edge of the latent image, and the background stain on the leading edge of the image is eliminated. When the leading edge of the electrostatic latent image passes the developing roller 4 after the time T 4 has passed, the relay RA2 is turned on, the Zener diode Z3 is short-circuited by the normally open contact RA21, and + α is the normal value by the Zener diode Z4. A normal bias voltage is applied to the developing roller 4 as a voltage. During the surface potential detection time T2, the developing roller 3 is used as a detection electrode as described above when the relay RA1 is turned on. After that, when the relay RA1 is turned off, a normal bias voltage is applied as a developing electrode from the output circuit OC.

(効果) 以上のように本発明によれば、複数の現像ローラによ
り静電潜像を現像する現像装置におけるバイアス印加方
法において、前記複数の現像ローラのうちの検出電極と
して用いられる現像ローラを通過する像により該検出電
極用現像ローラに誘起した電圧を検出し、この検出電圧
に応じて前記複数の現像ローラにバイアス電圧を印加
し、且つ、前記検出に用いた像領域が前記複数の現像ロ
ーラのうちの前記検出電極用現像ローラ以降の他の現像
ローラを通過する間は前記他の現像ローラに印加するバ
イアス電圧を補正するので、静電潜像の先端部の現像で
もバイアスが不足せずに十分にかかって画像先端部の地
肌汚れがなくなる。
(Effects) As described above, according to the present invention, in the bias applying method in the developing device for developing the electrostatic latent image by the plurality of developing rollers, the developing roller that is used as the detection electrode among the plurality of developing rollers is passed. The voltage induced on the detection electrode developing roller is detected by the image, the bias voltage is applied to the plurality of developing rollers according to the detected voltage, and the image area used for the detection has the plurality of developing rollers. Since the bias voltage applied to the other developing roller is corrected while passing through the other developing roller after the detecting electrode developing roller, the bias does not become insufficient even at the development of the tip portion of the electrostatic latent image. It is applied sufficiently to eliminate background stains on the leading edge of the image.

【図面の簡単な説明】[Brief description of drawings]

第1図は本発明の実施回路例を示す回路図、第2図は同
実施回路例のタイミングチャート、第3図は複写機の一
例における現像装置を示す断面図である。 Z3……ツェナーダイオード、RA2……リレー。
FIG. 1 is a circuit diagram showing an embodiment circuit example of the present invention, FIG. 2 is a timing chart of the embodiment circuit example, and FIG. 3 is a sectional view showing a developing device in an example of a copying machine. Z3: Zener diode, RA2: Relay.

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】複数の現像ローラにより静電潜像を現像す
る現像装置におけるバイアス印加方法において、前記複
数の現像ローラのうちの検出電極として用いられる現像
ローラを通過する像により該検出電極用現像ローラに誘
起した電圧を検出し、この検出電圧に応じて前記複数の
現像ローラにバイアス電圧を印加し、且つ、前記検出に
用いた像領域が前記複数の現像ローラのうちの前記検出
電極用現像ローラ以降の他の現像ローラを通過する間は
前記他の現像ローラに印加するバイアス電圧を補正する
ことを特徴とするバイアス印加方法。
1. A bias applying method in a developing device for developing an electrostatic latent image by a plurality of developing rollers, wherein the detection electrode developing is performed by an image passing through a developing roller used as a detecting electrode among the plurality of developing rollers. The voltage induced in the roller is detected, a bias voltage is applied to the plurality of developing rollers according to the detected voltage, and the image area used for the detection is the detection electrode developing of the plurality of developing rollers. A bias applying method characterized in that the bias voltage applied to the other developing roller is corrected while passing through the other developing roller after the roller.
JP61264481A 1986-11-06 1986-11-06 Bias application method Expired - Lifetime JP2502296B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61264481A JP2502296B2 (en) 1986-11-06 1986-11-06 Bias application method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61264481A JP2502296B2 (en) 1986-11-06 1986-11-06 Bias application method

Publications (2)

Publication Number Publication Date
JPS63118169A JPS63118169A (en) 1988-05-23
JP2502296B2 true JP2502296B2 (en) 1996-05-29

Family

ID=17403831

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61264481A Expired - Lifetime JP2502296B2 (en) 1986-11-06 1986-11-06 Bias application method

Country Status (1)

Country Link
JP (1) JP2502296B2 (en)

Also Published As

Publication number Publication date
JPS63118169A (en) 1988-05-23

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