JP2501497Y2 - Channel data storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a channel data storage device using a rewritable nonvolatile memory as a channel storage means of a television receiver.

[Prior Art and its Problems] In a conventional television receiver, as a memory for storing a preset channel for auto tuning or a memory for storing a last channel when the power is turned off,
RAM is generally used. This conventionally used R
AM requires a backup power supply, and when the TV power is turned off, the stored data is retained by backing up some power supply.

However, in a portable liquid crystal television that uses a battery as a power source, it is necessary to reduce the load on the power source as much as possible, and there is a problem that RAM that requires a backup power source is difficult to use. In order to solve such a problem, a writable non-volatile memory such as an EEPROM (Electrically Era)
Storable and Programmable Read Only Memory) may be used to store preset channels or last channels. However, this EEPROM is
Although it has the advantage that it can be electrically programmed / erased and that it does not require a backup power supply, its life is about 10 ⁴ to 10 ^{5 in the} number of writable times, and it is used in places where rewriting is frequent. Is not enough for Therefore, in the past, the EEPROM could not be used as the channel data memory of the television receiver.

[Object of the Invention] The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a channel data storage device in which a rewritable nonvolatile memory is used as a memory for channel data and a practically sufficient life can be obtained. And

[Summary of the Invention] The present invention uses a rewritable non-volatile memory composed of a plurality of storage areas and a monitor storage area corresponding to each of the plurality of storage areas as a memory for storing channel data. When data is written by specifying the monitor storage area, the correctness of the data stored in the corresponding monitor storage area is judged every time the channel data in the specified storage area is rewritten, and when an error is detected, The designation of the storage area is switched to another storage area.

[Embodiment of the Invention] Hereinafter, a case where the present invention is applied to an LCD television will be described in detail with reference to the drawings. First, the external structure of the liquid crystal television device will be described with reference to FIG. In FIG. 1, reference numeral 1 is a case, and an image display section 2 and a channel display section 3 are provided on the front surface thereof. The image display section 2 and the channel display section 3 are one LC panel (liquid crystal display panel).
The display windows formed on the front surface of the case 1 separate the images from each other. Then, the channel display section 3 has a numerical value indicating a channel, a VHF band and a U on its side.
The letters V and U, which indicate the reception classification of the HF band, are displayed by printing. The channel display unit 3 has first to third
The display bars 3a to 3c are used to display channels. The first display bar 3a selects a channel, the second display bar 3b selects a tuning channel, and the third display bar 3c displays a reception band (VHF / UHF). Is displayed. In this case, for example, the display bar 3b that displays the channel being tuned is displayed in half the gradation of the other display bars 3a and 3c so that the display content can be determined. Also,
On the front of Case 1 above is the up key 5a for tuning.
Further, a down key 5b is provided, and a mode switch 6 for selecting and designating a normal mode and an auto tuning data set mode, a CH key 7 for designating a preset channel, and a channel setting SET key 8 are provided. Further, the rod antenna 9 is provided on the upper part of the case 1.
Is provided.

Next, the overall structure of the electronic circuit provided in the case 1 will be described with reference to FIG. The radio wave received by the antenna 9 is supplied to the tuner 11. This tuner
11 is a band switching signal BU / BV, BS from the band switching circuit 24.
Also, a designated channel is selected according to the tuning voltage BT from the tuning voltage generating circuit 23 and converted into an intermediate frequency signal. The band switching signal BU / BV output from the band switching circuit 24 is a signal for switching between the UHF band and the VHF band, and BS is a signal for switching between the low band and the high band in the VHF band. The intermediate frequency signal output from the tuner 11 is sent to the TV linear circuit 12. This TV linear circuit 12 is an intermediate frequency amplifier circuit,
It is composed of a video detection circuit, a video amplification circuit, an AFT detection circuit, etc., and amplifies the intermediate frequency signal from the tuner 11 and also performs video detection by the video detection circuit. Then, an audio signal is extracted from the output signal of this video detection circuit,
It is sent to the voice circuit 13. The audio circuit 13 is composed of an audio detection circuit and an audio amplification circuit, and audio-detects the signal from the TV linear circuit 12 to convert it into a low-frequency signal, and then amplifies the audio to drive the speaker 14.

The output signal of the video detection circuit in the TV linear circuit 12 is amplified by the video amplification circuit and then sent to the chroma circuit 15 and the sync separation circuit 16. This sync separation circuit
Reference numeral 16 is a tuning control circuit for separating the horizontal and vertical sync signals included in the video signal and the composite sync signal C-SYNC.
Then, the horizontal synchronizing signal H-SYNC and the vertical synchronizing signal V-SYNC are output to the timing control circuit 18. Further, the TV linear circuit 12 performs AFT detection of the output signal of the intermediate frequency amplification circuit by the AFT detection circuit to take out an S-shaped AFT signal and outputs it to the AFT control circuit 19 and the tuning control circuit 17. The tuning control circuit 17 is provided with key inputs such as tuning setting data and tuning up / down instructions from the key input unit 21. Tuning control circuit 17
Is the tuning up key 5a,
A tuning signal TU is created based on the operation of the down key 5b and the AFT signal from the TV linear circuit 12, and is output to the tuning voltage creating circuit 23 via the low pass filter 22, but during this tuning control, a mute signal ▲
The ▼ is output to the audio circuit 13 to the audio circuit 13 and the AFT control circuit 19. The audio circuit 13 stops the output operation while the mute signal ▽ ▼ is given. Further, the AFT control circuit 19 always superimposes the AFT signal from the TV linear circuit 12 on the tuning voltage created by the tuning voltage creating circuit 23, but when the tuning control circuit 17 gives the mute signal ▲ ▼, During that time, the output of the AFT signal is stopped. Further, the tuning control circuit 17 outputs the UHF band designation signal UHF and the low band designation signal ▲ ▼ to the band switching circuit 24 along with the search operation. The band switching circuit 24 performs band switching of the tuner 11 in response to a band designation signal from the tuning control circuit 17, and is a UHF band when the UHF band designation signal UHF is "1" and a VHF band when it is "0". Is selected, UHF high band when the low band designation signal ▲ ▼ is "1", VHF when it is "0"
High band, switch to VHF low band when "0". Further, the tuning control circuit 17 outputs the channel display instruction signals CH1 and CH2 to the timing control circuit 18 in response to the channel switching.

The timing control circuit 18 creates an ampling signal φs based on the horizontal and vertical sync signals sent from the sync separation circuit 16 and outputs it to the A / D conversion circuit 25. This A
The / D conversion circuit 25 samples the chroma signal output from the chroma circuit 15 in synchronization with the sampling signal φs, converts it into digital data of 3 to 4 bits, and outputs it to the segment driver 26. Further, the timing control circuit 18 produces a timing signal for display control based on the synchronization signal given from the synchronization separation circuit 16, and controls the operation of the segment driver 26 and the common driver 27.
The common driver 27 generates a scanning signal in accordance with the timing signal from the timing control circuit 18, and the LC panel 4
The common electrodes of are sequentially driven. Segment driver 26
Reads the video data of 3 to 4 bits supplied from the A / D conversion circuit 25 sequentially by the timing signal from the timing control circuit 18, reads the video data of one line, and then reads the floor according to the video data. A tonal signal is created and the segment electrodes of the image display unit 2 in the LC panel 4 are driven to display. Further, the timing control circuit 18 outputs a channel display control signal to the channel bar display driver 28 according to the synchronization signal from the synchronization separation circuit 16 and the channel display instruction signals CH1 and CH2 from the tuning control circuit 17. The driver 28 drives the channel display section 3 of the LC panel 4, and selects a selected channel and a reception band (UHF /
VHF) etc. are displayed.

Next, the details of the tuning control circuit 17 will be described.
It will be described with reference to the drawings. In the figure, 31 is an input control circuit,
For example, a read command R, a tuning up command KU, a tuning down command KW, a read / write command R / W1, R / W2, a load command LOAD1, LOAD2, a timing pulse CK according to a key operation signal input from the key input unit 21. Then, various timing signals such as an up / down signal / D and a power-on clear signal ▲ ▼ are output. The read instruction R, the tuning up instruction KU, and the tuning down instruction KW output from the input control circuit 31 are the tuning flow control circuit 32.
Sent to the timing pulse CK, up / down signal /
The D and load instruction LOAD2 are sent to the channel counter 33. The channel counter 33 is a counter that counts "0" to "11", and the count value corresponds to the tuning channel. The channel counter 33 is
Up / down is controlled by the up / down signal / D from the input control circuit 31, and in the set mode CH key 7
Each time is operated, the timing pulse CK is input to count up. In the normal mode, the up / down keys 5a and 5b are operated to count up / down. Then, the count outputs Q1 to Q4 of the channel counter 33
Is the address terminal A1 of the tuning voltage memory 34.
~ Input to A4 and last channel memory circuit 35
Data input terminals DI1 to DI4, and further to the channel display signal creating circuit 36. The tuning voltage storage memory 34 is composed of a rewritable non-volatile memory such as an EEPROM and can preset up to 12 stations in both the UHF and VHF bands. One area of the memory 34 is 16 bits (DO1 to DO16), and tuning voltage data is UHF15 bits (DO1 to DO15) and VHF14 bits (DO1 to DO14). MSB of data MSB (DO
16) is a bit that selects and specifies the UHF band and the VHF band, and the output of this bit becomes the band selection signal U /. This bit is "1" for UHF and "0" for VHF, and the 15th bit (DO15) when specifying the VHF band is a bit that distinguishes between the L (low) channel and the H (high) channel. . The last channel storage circuit 35 is composed of a rewritable non-volatile memory such as an EEPROM, and reads / writes data by a read / write command R / W2 from the input control circuit 31. The last channel storage circuit 35 stores the selected channel each time the channel is switched, and the stored channel data is loaded to the channel counter 33 by the load command Load2 when the power is turned on.

Then, the tuning voltage storage memory 34 performs data read / write by the read / write command R / W1 from the input control circuit 31, and stores the stored data DO1 to DO15,
The DO 16 is output to the tuning voltage counter 37. The tuning voltage counter 37 counts up / down by a signal from the tuning flow control circuit 32 at the time of auto tuning, and at the time of normal, data from the tuning voltage storage memory 34 is loaded by the load instruction Load1. The output data DO1 to DO15, DO16 of the tuning voltage counter 37 are sent to the comparison circuit 38, the tuning voltage storage memory 34, and the channel display signal creation circuit 36. Further, the count value of the comparison counter 39 is given to the comparison circuit 38. The comparison counter 39 counts, for example, a basic clock pulse φ2 of 3 MHz provided from the oscillation circuit 41,
The count value is output to the comparison circuit 38, and the clock pulses φ _M and φ _K are generated each time the predetermined count value is reached and output to the tuning flow control circuit 32. The clock pulses φ _M and φ _K are pulses that determine the tuning speed, and the cycle of φ _M is set to be fast and the cycle of φ _K is set to be slow. The comparison circuit 38 compares the count values of the tuning voltage counter 37 and the comparison counter 39 and outputs the comparison result to PW.
The M signal (TU) is output to the low pass filter 22 shown in FIG. Also, the output bit DO1 of the tuning voltage counter 37
5, DO16 is sent to the band control circuit 42. The band control circuit 42 uses the bit DO15 to switch between the H band and the L band in the VHF band.
▼ is output to the band switching circuit 24 and the bit DO
Band switching circuit for signal UHF that specifies UHF band by 16
Output to 24. Furthermore, the above channel display signal creation circuit
36 designates a designated channel and a selected band (U / U) from the count data of the channel counter 33 and the tuning voltage counter 37.
V) to display the channel display instruction signal CH1 and the channel display instruction signal CH2 for displaying the channel being tuned.
Output to 8.

On the other hand, the AFT sent from the TV linear circuit 12 in FIG.
The signal is input to the-terminal of the comparator 43 and the + terminal of the comparator 44. Further, the voltage between the reference power supply Vcc and the ground level GND is divided by the resistors 45, 46 and 47 and applied to the + terminal of the comparator 43 and the-terminal of the comparator 44 as a reference voltage. Comparator 43,4 above
From 4, the AFT-H signal and the AFT-L signal are output by comparing the AFT signal with the reference voltage, and the AND circuits 48,
It is input to the tuning flow control circuit 32 via 49. The AND circuits 48 and 49 are gate-controlled by the synchronization detection signal of the synchronization detection circuit 51. This synchronization detection circuit 51
Performs a sync signal detection process on the output signal C-SYNC of the sync separation circuit 16, opens the gates of the AND circuits 48 and 49 when the sync signal is detected, and controls the tuning flow of the outputs of the comparators 43 and 44. Feed to circuit 32. When the up / down command KU / KW from the input control circuit 31 is given, the tuning flow control circuit 32 first counts clock pulses φ _M with a fast cycle to start high-speed tuning, and then the tuning frequency When approaching the adjacent channel, the AFT-H, AFT- from the comparators 43 and 44
Based on the L signal, the count clock is switched from φ _M to φ _K , the tuning speed is lowered to perform fine tuning, and the tuning frequency is adjusted to the optimum value. In this case, the tuning flow control circuit 32 first tunes the VHF band if, for example, the up key 5a is operated continuously, but when the VHF band is terminated, the U
Perform tuning for the HF band. In this state, the operation of the up key 5a is further continued, and when the tuning of the UHF band is completed, it returns to the VHF band again. That is,
When the up key 5a or the down key 5b is operated continuously, the VHF band and the UHF band are circulated and tuned. Further, the tuning flow control circuit 32 sets the mute signal ▲ ▼ to “0” while performing the tuning control, and the audio circuit 13 and the AFT circuit.
The operation of the control circuit 19 is prohibited.

Next, details of the last channel memory circuit 35 will be described with reference to FIG. In the figure, 61 is a data storage for storing the data DI1 to DI4 from the channel counter 33.
EEPROM has a memory capacity of 4 words,
In each word, 2-bit monitor bits M1 and M2 are added to 4-bit data bits D1 to D4. The data storage EEPROM 61 reads / writes data according to the output enable signal ▲ ▼ and the write enable signal ▲ ▼.
Writing is controlled. Monitor bit for storing the above data
"0" and "1" are written in the addresses M1 and M2 in advance, and the monitor bits M1 and M2 are read out to the decision circuit 62 when the output enable signal ▲ ▼ is applied. The determination circuit 62 determines the error state of the data storage EEPROM 61 from the monitor bits M1 and M2 as will be described later in detail, and generates a timing pulse CK and a write enable signal ▲ ▼ when an error occurs. The timing pulse CK output from the judgment circuit 62 is an address counter.
It is sent to 63 as a count-up signal, and the write enable signal ▲ ▼ is a 2-bit address storage EEPROM 64.
Given to. The address counter 63 sends 2-bit count outputs A1 and A2 as address data to the EEPROM 61 for storing data, and the EEPRO for storing address via the inverters 65 and 66 and the clocked inverters 67 and 68.
Input to M64. The clocked inverters 67 and 68 are
Power-on clear signal given when the power is turned on ▲ ▼
Is gated by. Further, the power-on clear signal {circle over ()} is given to the address counter 63 as a load instruction L and to the address storage EEPROM 64 as an output enable signal OE2. In this EEPROM 64, "00" is written in advance as address data.

Thus, the judgment circuit 62 is constructed as shown in FIG. In the figure, 70a and 70b are flip-flops, which are monitor bits read from the EEPROM 61 for data storage.
Read M1 and M2 with a predetermined timing signal, latch circuit 71,
Input to the input terminal I of 72. The timing signal a sent from the input control circuit 31 is input to the clock terminals CK of the latch circuits 71 and 72 via the ON circuit 75, and the write enable signal ▲ sent from the input control circuit 31. Is input via the inverter 74 and the OR circuit 73. The latch circuits 71 and 72 are clock terminals CK.
The input data is latched by the timing signal given to the input signal and the latched output is returned to its own input terminal I through the clocked inverters 75 and 76 and the flip-flops 70a and 70b. The clocked inverters 75 and 76 have output enable signals ▲ from the input control circuit 31.
Gate controlled by ▼. Furthermore, the outputs of the clocked inverters 75 and 76 are exclusive OR circuits (hereinafter referred to as E
X-OR circuit) 77 through flip-flop 78
Entered in. The flip-flop 78 is reset by the output enable signal OE1 and then latches the input signal at the rising edge of the timing signal a. The latch output d of the flip-flop 78 is input to the OR circuit 79 and the AND circuit 81 via the inverter 80.
The timing signal b is input to the AND circuit 81, and the timing signal c (▲ ▼) is input to the OR circuit 79. Then, the output of the AND circuit 81 is taken out as the timing pulse CK, and the output of the OR circuit 79 is taken out as the write enable signal ▲ ▼.

FIG. 6 shows a timing signal generating circuit provided in the input control circuit 31, which is a timing signal for the judging circuit 62.
Generates a, b, and c. In this timing signal generating circuit, a flip-flop 82a to 82f constitutes a shift register 83, and an output enable signal ▲ ▼ is read by clock pulses φ1 and φ2 and sequentially shifted. In this case, the flip-flops 82a, 82c, 82e cause the clock pulse φ
1 and the flip-flops 82b, 82d, 82f operate by the clock pulse φ2. Then, the AND circuit outputs the output enable signal ▲ ▼ and the clock pulse φ1.
The output signal of the flip-flop 82b is input to the AND circuit 84 via the inverter 85 while being input to 84, and the output is taken out as the timing signal a. The output signal of the flip-flop 82a and the clock pulse φ2 are input to the AND circuit 86, and the flip-flop 82c
Input the output of AND into the AND circuit 86 via the inverter 87,
The output is taken out as a timing signal b. Further, the output signal of the inverter 87, the output signal of the flip-flop 87 and the power-on clear signal PC are input to the OR circuit 88, and the output thereof is output as the timing signal c (▲ ▼).

The timing signal generation circuit configured as described above is
As shown in the timing chart of FIG. 7, the output enable signal ▲ ▼ is read into the shift register 83 by the clock pulses φ1 and φ2 to generate the timing signals a, b and c. That is, when the output enable signal {circle over ()} goes low for a certain period and then rises to high level, the timing signal a is output in synchronization with the next clock pulse φ1. At this time, the output enable signal {circle over ()} is read into the flip-flop 82a by the clock pulse φ1 and its output becomes high level. Therefore, the timing signal b is output from the AND circuit 86 in synchronization with the next clock pulse φ2. Further, since the output of the flip-flop 82a is shifted to the next-stage flip-flop 82b by the crop pulse φ2, the output of the inverter 85 is "0".
Then, the gate of the AND circuit 84 is closed, and the output of the timing signal a is prohibited. Then, the next clock pulse φ
When the data "1" held in the flip-flop 82b is shifted to the flip-flop 82c by 1, the output of the inverter 87 becomes "0", the gate of the AND circuit 86 is closed, and the output of the timing signal b is prohibited. Also, the above inverter
The output signal “0” of 87 is output from the OR circuit 88 as the timing signal c.
It is output as (▲ ▼). The timing signal c output from the OR circuit 88 is the above flip-flop.
When the held data "1" of 82c is shifted to the flip-flop 82f, it returns to the normal high level. As described above, the timing signal generating circuit of FIG.
a, b, c are created.

Next, the reading / writing of channel data and the checking operation of the stored data with respect to the last channel storage circuit 35 in FIGS. 3 and 4 will be described. When the power is turned on, the power-on clear signal ▲
▼ (“0”) is given to the last channel storage circuit 35. The record data AE1 and AE2 are read from the address storage EEPROM 64 by the power-on clear signal () and loaded into the address counter 63. Since "00" is initially written in the address storage EEPROM 64, "00" is loaded in the address counter 63. Therefore, the address counter 3 specifies the address "00" for data storage. Power-on clear signal above ▲
▼ returns to “1” signal level after a certain period of time has passed since the power was turned on.

Then, the up / down key in the key input unit 21
When the up / down of the channel is instructed by the operation of 5a, 5b, the tuning up command KU or the tuning command KW is sent from the input control circuit 31 to the tuning flow control circuit 32. This causes the tuning flow control circuit 32 to start the tuning control operation, and the TV linear circuit
The AFT signal (AFT-H, AFT-L) given from 12 is detected and the adjacent channel is selected.

When the up / down keys 5a and 5b are operated, the input control circuit 31 gives the up / down instruction / D and one timing pulse CK to the channel counter 33, whereby the contents of the channel counter 33 are changed. "+
1 "or" -1 ". This channel counter
Every time 33 is up-counted or down-counted, the updated channel data is sent to the last channel storage circuit 35 as last channel data,
Written to EEPROM 61 for data storage.

When writing channel data to the data storage EEPROM 61, as shown in the timing chart of FIG.
First, output enable signal ▲ to the data storage EEPROM 61
▼ (“0”) is given to judge monitor bits M1 and M2 6
The data is read out to 2, and is temporarily set in the flip-flops 70a and 79b in synchronization with a predetermined timing signal, and then latched in the latch circuits 71 and 72 by the timing signal a. The data latched by the latch circuits 71, 72 is input to the OR circuit 78 via the clocked inverters 75, 76 and the EX OR circuit 77. Therefore, if the data latched in the latch circuits 71 and 72 is in the normal state “01”, the output of the EX OR circuit 77 becomes “1” and the flip-flop 78 latches “1” in synchronization with the timing signal a. To be done. Therefore, even if the timing signals b and c are given in this state, the output signal CK of the AND circuit 81 is held at "0" and the output signal ▲ ▼ of the OR circuit 79 is held at "1" as shown in FIG. The contents of the address counter 63 and the address storage EEPROM 64 of FIG. 4 are also held in the state of "00". In addition, the timing signal c (▲
When ▼) falls, the output of the inverter 74 rises to "1" and is given as a latch pulse to the latch circuits 71 and 72 via the OR circuit 73. At this time, the latch circuits 71 and 72 have
Owned data "01" is clocked inverter 75,76
Since it is inverted by and is input through the flip-flops 70a and 70b, the latch data of the latch circuits 71 and 72 is "1.
It is inverted to "0".

Further, the timing signal c is given to the data storage EEPROM 61 of FIG. 4 as a write enable signal ▲ ▼, and the channel data from the channel counter 33 is supplied.
DI1 to DI4 are written to EEPROM61.

Each time the channel is switched as described above, the data of the selected channel is written to the EEPROM 61, but the memory retention becomes unstable due to the multiple writing, and the monitor bit M1, read to the latch circuit 71, M2 is "0
When it becomes "0" or "11", the output of the EX OR circuit 77 becomes "0" and is latched by the flip-flop 78 at the rising of the timing signal a. As a result, as shown in FIG. 7, the AND circuit 81 outputs the clock pulse CK (“1”) and the OR circuit 79 outputs the write enable signal ▲ ▼ (“0”).
The address counter 63 is incremented to "01" by CK. The count output "01" of the address counter 63 is sent to the address storage EEPROM 64 via the inverters 65, 66 and the clocked inverters 67, 68, and written in the EEPROM 64 by the enable signal WE2. Further, the address value of the data storage EEPROM 61 is designated by the count value "01" of the address counter 63, and thereafter, the next channel data DI1 to DI4 are written in this new area.

When the data retention of the data storage EEPROM 61 becomes unstable as described above, the address is updated and the channel data is stored in the next area. As a result, the channel data is always accurately stored in the data storage EEPROM 61.

Then, when the power is turned off, the count data of the channel counter 33 is lost, but the data storage EEPROM 61 stores and holds the data of the channel selected when the power is turned off as the last channel data as it is. After that, when the power is turned on, the read command R / W2 and the load command Load2 are output from the input control circuit 31, the last channel data stored in the data storage EEPROM 61 of the last channel storage circuit 35 is read, and the channel counter 33 Loaded in. The data loaded in the channel counter 33 designates the address of the tuning voltage storage memory 34, and the tuning voltage stored in the designated address is loaded in the tuning voltage counter 37. And this tuning voltage counter 37
Tuning control is performed on the basis of the tuning voltage loaded in, and the last channel when the power was turned off last time is selected and designated. On the other hand, the channel display signal creation circuit 36 creates channel display data according to the channel data loaded in the channel counter 33, and displays the selected channel on the channel display unit 3.

After selecting the last channel as above,
Normal tuning operation is performed by operating the amplifier / down keys 5a and 5b.

In the above embodiment, the address storage EEPROM 64 is used and the address of the data storage EEPROM 61 is switched by this EEPROM 64.
OM64 is not absolutely necessary. Further, in the above-mentioned embodiment, the four address areas are sequentially switched and designated by the 2-bit address data A1 and A2 in the data storage EEPROM 61 so that the apparent life of four times can be obtained. A longer life can be obtained by increasing the number of bits and the memory capacity.

[Advantages of the Invention] As described in detail above, according to the present invention, a rewritable non-volatile memory including a plurality of storage areas and monitor storage areas corresponding to the plurality of storage areas is used as a channel data storage memory. Then, data is written by designating one storage area and the corresponding monitor storage area, and every time the data in the designated storage area is rewritten, the correctness of the data stored in the corresponding monitor storage area is determined. Since the designation of the storage area is switched to another storage area when an error is detected, a rewritable nonvolatile memory can be used as the channel data memory to obtain a practically sufficient life. For this reason, the backup power supply for the channel data memory becomes unnecessary, and the power consumption can be reduced.

[Brief description of drawings]

FIG. 1 shows an embodiment of the present invention. FIG. 1 is a front view showing an external configuration, FIG. 2 is a block diagram showing the entire circuit configuration of an electronic circuit, and FIG. 3 is a tuning control in FIG. FIG. 4 is a block diagram showing details of a circuit, FIG. 4 is a block diagram showing details of a last channel memory in FIG. 3, and FIG. 5 is a diagram showing details of a judgment circuit in FIG.
FIG. 6 is a block diagram showing the configuration of a timing signal generation circuit for generating the timing signal of the judgment circuit, and FIG. 7 is a timing chart for explaining the control operation for the last channel storage memory. 1 ... Case, 2 ... Image display part, 3 ... Channel display part, 4 ... LC panel, 5a, 5b ... Amp / down key, 6 ... Mode switch, 11 ... Tuner, 12 ... TV
Linear circuit, 16 …… Synchronous separation circuit, 17 …… Tuning control circuit, 18 …… Timing control circuit, 19 …… AFT control circuit, 21 …… Key input section, 23 …… Tuning voltage generation circuit, 24 …… Band Switching circuit, 25 ...... A / D conversion circuit, 28
...... Channel display driver, 31 …… Input control circuit,
32 ... Tuning flow control circuit, 33 ... Channel counter, 34 ... Memory for tuning voltage storage, 35 ...
… Last channel memory circuit, 36 …… Channel display signal creation circuit, 37 …… Tuning voltage counter, 38 …… Comparison circuit, 39 …… Comparison counter, 42 …… Hand control circuit, 43
…… Comparator, 44 …… Comparator, 51 …… Synchronous detection circuit, 61 …… Data storage EEPROM, 62 …… Judgment circuit,
63 …… Address counter, 64 …… EEPRO for address storage
M, 71, 72 ... Latch circuit.

Claims (1)

(57) [Scope of utility model registration request] 1. A rewritable nonvolatile memory for storing channel data, comprising a plurality of storage areas and a monitor storage area corresponding to each of the plurality of storage areas, and data stored in the storage area having the memory. When the data stored in the corresponding monitor storage area is judged to be correct when read out, and when the data stored in the monitor storage area is judged to be erroneous by the judging means And a switching means for switching the data to be stored in the certain storage area so as to be stored in another storage area.