JP2500404Y2 - Ship speed measuring device - Google Patents

Description

[Detailed description of the device]

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention emits an ultrasonic beam in each of the diagonally forward and diagonally backward directions of a ship, receives reflected waves from a water mass located at a position distant from the bottom of a ship, and receives Doppler waves. The present invention relates to a water-type ship speed measuring device that detects shifts and measures ship speeds.

[0002]

2. Description of the Related Art Generally, a ship speed measuring apparatus utilizing the Doppler effect has a structure in which an ultrasonic beam is simultaneously emitted in directions diagonally forward and diagonally backward of a ship in order to avoid the influence of pitching of the hull. ing. FIG. 9 shows an example of a conventional ship speed measuring device of this type.

The conventional ship speed measuring device shown in FIG. 1 includes an original oscillator section 10, front and rear transmitting sections 12 _F and 12 _A , and front and rear transmitting / receiving switching sections 14 _F and 14 _A. Front and rear transducers 16 _F and 16 _A , front and rear receivers 18 _F and 18 _A , front and rear frequency detectors 20 _F and 20 _A , front and rear Commonly provided calculation unit 22
And a ship speed display unit 24.

In this conventional ship speed measuring device, the excitation current shaped into a pulse signal in the original oscillator 10 is amplified in the corresponding transmitters 12 _F and 12 _A for the front and rear parts, respectively, and the transmission / reception switching part is provided. 14 _F, 14 via the _a, transducer 16 _F, 16 _a
As a narrow ultrasonic beam, it is launched into the sea diagonally forward and backward of the ship at a certain depression angle. Then, the scattered reflection signal from the water mass located at a position several meters away from the bottom of the ship is received by the transducers 16 _F , 16 _A and converted into an electric signal, and passed through the transmission / reception switching units 14 _F , 14 _A , Input to receivers 18 _F and 18 _A. The receivers 18 _F and 18 _A amplify the received signal to the required level, the frequency detectors 20 _F and 20 _A detect the Doppler shift in each direction, and the calculator 22 converts this signal into a ship speed signal. At the same time, the averaging process is performed and this is displayed on the ship speed display unit 24.

[0005]

However, since the conventional ship speed measuring device is configured to emit ultrasonic waves to the front and the rear of the ship at the same time, the received signal is transmitted forward when the reflected wave is received. It is necessary to perform processing independently for each of the front and rear sides, and it is necessary to provide the circuits up to the front stage of the arithmetic unit 22 in double for the front side and the rear side. In particular, it is necessary to double-provide the frequency detection part which is the central part of the ship speed measuring device.

Therefore, the circuit structure becomes complicated, and at the same time,
There is a drawback that the number of constituent parts also increases and a large printed circuit board or the like on which these parts are mounted is required.

On the other hand, the instantaneous value of the received signal is not a stable value and has a great variation. Therefore, even in the conventional ship speed device, the received signals are displayed by integrating for a certain period of time and averaging.

By the way, when the ship is stopped or at a very low speed, the instantaneous value of the received signal is often a forward signal or a reverse signal. However, in the conventional ship speed measuring device, when the forward signal and the reverse signal are input alternately or close to each other and disturbed, they are summed as they are, so that there is a drawback that the speed instruction is displayed larger than it actually is. is there.

The present invention has been made to solve the above-mentioned drawbacks, and transmission and reception can be alternately performed in the front and the rear, and the processing unit of the front and rear received signals is made common to simplify the circuit configuration. It is an object of the present invention to provide a ship speed measuring device that can perform accurate speed display even when the ship is stopped or at a very low speed.

[0010]

SUMMARY OF THE INVENTION The present invention emits an ultrasonic beam in each of the diagonally forward and diagonally rearward directions of a ship and receives reflected waves from a water mass located away from the bottom of the ship. In a ship speed measurement device that detects Doppler shift and measures ship speed, as means for solving the above problems, (a) switching before and after transmission that sets the firing timing so that ultrasonic waves are alternately emitted forward and backward (B) The reception signal processing means for detecting the Doppler shift from the received signals of the reflected waves received from the front and the rear, respectively, and measuring the ship speed are provided for both front and rear, and (c) from the front and the rear. A pre / post-reception switching means for connecting each received signal to the received signal processing means in synchronization with the emission timing is provided, and (d) the detected Doppler shift data is kept constant in the received signal processing means. Provided with a averaging means for averaging by integrating between every, by performing forward and reverse discrimination, when the Doppler shift data is a polar traveling in the opposite direction,
It is characterized in that the averaging processing means is provided with a forward / backward movement determining means for outputting a subtraction command.

[0011]

In the meantime, in the case of a water-speed type ship speed measuring device, if the target object is a water mass located at a position several meters away from the bottom of the ship, the echo of the ultrasonic waves emitted will return after a few milliseconds. Therefore, it is sufficient to repeat the transmission every 20 ms (50 Hz). This time of about 20 ms is very short compared to the pitching cycle of the hull, so even if ultrasonic waves are not emitted forward and backward at the same time, and even if they are alternately transmitted and received, they will be emitted simultaneously for pitching. It has the same effect. The present invention is based on such knowledge.

That is, the before and after transmission switching means alternately emits ultrasonic waves forward and backward, and the reception signals received from the front and rear are received by the before and after reception switching means in synchronization with the emission timing. Connect to signal processing means. The reception signal processing means for detecting the Doppler shift from the reception signals of the reflected waves respectively received from the front and the rear and measuring the ship speed is provided in common in the front and rear, and is shared by both.

As a result, the number of circuits conventionally provided in duplicate is sufficient, and the circuit configuration can be simplified.

Further, according to the present invention, the Doppler shift data is integrated and averaged to absorb the variation in the instantaneous value, thereby enabling a stable speed display. In addition, at that time, when the forward / backward movement of the vessel is determined and the forward / reverse traveling signals are disturbed and input, such as when the vessel is stopped or at a slow speed, the signal in the opposite direction to the signal to be integrated is subtracted. As a result, accurate speed display can be performed.

[0015]

Embodiments of the present invention will be described with reference to the drawings.

<Structure of Embodiment> FIG. 1 shows the structure of a first embodiment of a ship speed measuring device according to the present invention.

The ship speed measuring device of the embodiment shown in FIG. 1 includes an original oscillator 26, front and rear transmitters 12 _F and 12 _A ,
Front and rear transmission / reception switching units 14 _F and 14 _A , front and rear transmission / reception units 16 _F and 16 _A , and front / rear switching unit 28
And the reception unit 18, the frequency detection unit 56, which are provided in common in the front and rear,
It is configured to include a calculation unit 58 and a ship speed display unit 60.

In this embodiment, the original oscillator 26 and the front / rear switching unit 28
And constitute the switching means before and after transmission and the switching means before and after reception,
Further, the receiving unit 18, the frequency detecting unit 56, the calculating unit 58, and the ship speed display unit 60 are characterized in that they are commonly provided in the front and rear directions as a reception signal processing means. Further, it is characterized in that the arithmetic unit 58 is provided with an averaging processing means and a forward / backward movement judging means. On the other hand, the configuration of the other parts is basically the same as that of the conventional ship speed measuring device shown in FIG.
Therefore, in the following, the characteristic part of the present embodiment will be mainly described.

The original oscillating section 26 is constructed, for example, as shown in FIG. 2A. That is, the original oscillating unit 26 is a transmission frequency oscillator 30, a pulse repetition frequency oscillator 32, a transmission pulse width setting circuit 34, a depth position determining circuit 36, a reception gate setting circuit 38, a frequency divider 40, AND. Gate circuits 42, 44 and
46 and.

The transmission frequency oscillator 30 sets the frequency for exciting the ultrasonic transducer for wave transmission. On the other hand, the pulse repetition frequency oscillator 32 generates a pulse that sets a repetition frequency for transmitting ultrasonic waves.

The transmission pulse width setting circuit 34 is composed of, for example, a monostable multivibrator, and outputs a pulse corresponding to the transmission pulse width by using the pulse from the pulse repetition frequency oscillator 32 as a trigger. The depth position determination circuit 36
For example, it is composed of a monostable multivibrator, and sets the depth position and the position of the water mass from the bottom of the ship where the reflection should be received by using the transmission pulse as a trigger, and outputs a pulse that determines the start timing of the reception gate. Further, the reception gate setting circuit 38 is also composed of a monostable multivibrator, and uses the reception gate start timing determination pulse as a trigger to form a pulse for setting a sampling gate that receives a reception wave, and this is used as a frequency detection unit 56. Send to.

On the other hand, the frequency divider 40 is composed of, for example, a T flip-flop circuit, and has the pulse repetition frequency oscillator 32.
The pulse from is used as a trigger to alternately output a high level transmission gate signal to Q and * Q. (Here, * represents a signal of negative logic and is shown with an overline in the drawing.) The AND gate circuit 42 is the transmission frequency oscillator.
30 and the transmission pulse width setting circuit 34 are connected to the input, the pulse output by the latter becomes a gate signal, the transmission excitation current from the former to the AND gate circuits 44 and 46 for a time corresponding to the pulse width. Sent. The AND gate circuits 44 and 46 receive the transmission gate signals from the frequency divider 40 alternately, and alternately output the transmission excitation currents to the corresponding transmitters 12F 1 and 12A 2.

The front / rear switching unit 28 includes a switch drive circuit 48,
It consists of a switch 50. The switch drive circuit 48 receives the Q and * Q outputs from the frequency divider 40 and outputs a switching control signal for the switch 50. The switch 50 is composed of, for example, a semiconductor switch circuit as shown in FIG. 2B. That is, the switch 50 includes a front system circuit 52 including a PIN diode D ₁ , capacitors C ₁ and C ₄ and an inductance L ₁ , and a rear system circuit 54 including a PIN diode D ₂ , capacitors C ₂ and C ₅ and an inductance L _2. And a capacitor C ₃ and an inductance L ₃ common to both.

Here, a reflected wave signal is input to the input terminal F _IN from the front of the ship. On the other hand, the reflected wave signal is input to the input terminal A _IN from the rear of the ship. Also, the control terminal C
A control signal corresponding to the Q output from the frequency divider 40 is input to the _tF from the switch drive circuit 48.

On the other hand, a signal corresponding to the * Q output from the frequency divider 40 is input from the switch drive circuit 48 to the control terminal C _tA . The switch 50 is a PIN diode which is supplied with a control signal from the control terminal of the two PIN diodes.
The diode is a changeover switch utilizing the conduction of high frequency signals, and each PIN diode D
_A reception signal is sent from the cathode of ₁ or D ₂ to the common reception unit 18 from the output terminal O _t via the capacitor C ₃ .

The frequency detector 56, as shown in FIG.
A gate signal forming unit 62 including D flip-flop circuits 66 and 68, counters 70 and 72, and a clock generator 64, a speed pulse forming unit 74 including an exclusive OR gate circuit 76 and a NAND gate circuit 78, and exclusive OR gate circuits 82 and 84. And a backward pulse forming unit 80 including a NAND gate circuit 86. This frequency detection unit 56 is the original oscillation unit.
From the reception gate G _R from 26, the reference clock C _S from the clock generator 64, and the reception signal input via the forward / backward switching unit 28, a speed pulse * P _V and a reverse pulse * P _A To form.

As shown in FIG. 4, the calculation unit 58 and the ship speed display unit 60 include a pre-up / down counter 88 and an up / down counter 90 which form an averaging means, a forward / backward movement discriminating circuit 92, and a numerical display. It is configured to include a device 94 and a reverse display 96 as basic elements. Further, in this embodiment, as an additional circuit, a speed data transmission circuit 98, a speed comparison circuit 102, a speed alarm device 100 including a speed setting switch 104 and a buzzer 106, and a frequency divider 108 are used to output 200 P / M. A range counter 11 is provided via a relay 110 and a frequency divider 112.
4 and are connected.

The pre-up / down counter 88 counts the speed pulse * P _V according to the count-up signal U or the count-down signal D from the forward / backward movement discriminating circuit which will be described later,
The speed signal * P _S is output according to the preset division ratio. The frequency division ratio can be changed by a digital switch (not shown) or the like.

The up / down counter 90 functions as a decoder for dividing the speed signal * P _S and converting it from a binary number to a decimal number.

The numeral display 94 displays the speed converted into a decimal number by the up / down counter 90 by a numeral.
The numerical display 94 is additionally provided with a reverse display 96 which is turned on by a reverse display signal from the forward / backward determination circuit 92.

As shown in FIG. 5, the forward / backward movement determination circuit 92 includes an inverter 116, a P _A edge detection circuit 118, a D flip-flop circuit 120, and an exclusive OR gate circuit 122.
And a latch circuit 124 and a timing circuit 126, and an up / down counter group 89 including the pre-up / down counter 88 and the up / down counter 90.
In contrast, the switching signal for up-counting and down-counting
The U / D and the reverse display signal are output to the reverse display 96.

The P _A edge detection circuit 118 is composed of, for example, a monostable multivibrator, and the backward pulse * P _A
The negative pulse is output from the * Q terminal and sent to the set terminal * S of the D flip-flop circuit 120.

The latch circuit 124 is composed of, for example, a D flip-flop circuit, and latches the output of the Q terminal of the D flip-flop circuit 120.

The timing circuit 126 includes the latch circuit 12
The latch timing of 4, that is, the sampling strobe signal is supplied at a constant cycle, and the reset signal is sent to the reset terminal * R of the D flip-flop circuit 120 at a constant cycle.

<Operation of the Embodiment> The operation of the present embodiment will be described with reference to the above drawings and FIGS. 6 and 7.

In the original oscillating section 26, the transmission frequency oscillator 30 generates a transmission frequency signal for exciting the ultrasonic transducer. In this embodiment, this signal has a frequency of 2 MHz. Further, as shown in FIG. 6, the pulse repetition frequency oscillator 32 oscillates at a frequency twice as high as the transmission repetition period and sends the output R _P to the transmission pulse width setting circuit 34 and the frequency divider 40.

The transmission pulse width setting circuit 34 uses this output R _P as a trigger to set a transmission pulse width of a preset time width of 2 ms. The transmission pulse width signal W _P is sent to the AND gate circuit 42 and the depth position determining circuit 36.

In the AND gate circuit 42, the transmission frequency signal is put in the above transmission pulse width to form a transmission pulse T _P , which is sent to the AND gate circuits 44 and 46.

The depth position determining circuit 36 is a circuit for setting the water depth to be detected as a reflected wave, and in the present embodiment, it is assumed that the reflected wave at a water depth of about 3 m is detected.
A pulse width of 4 ms is set in consideration of the speed of sound. By the depth position determination pulse D _P , the reception reference setting gate signal G _R is formed in the reception gate setting circuit 38 and is sent to the frequency detection unit 56.

On the other hand, the frequency divider 40 divides the repetition cycle by half.
Frequency division is performed to form front-rear direction switching signals G _FA and * G _FA, which are sent to AND gate circuits 44 and 46 and switch drive circuit 48. The front-back direction switching signal G _FA is set to about 10 ms in this embodiment.

In the AND gate circuits 44 and 46, the gates are alternately opened by the front / rear direction switching signals G _FA and * G _FA to separate the above transmission pulse T _P in the front / rear direction, and 2 MHz, 2 m
s burst pulses (T _F , T _A ) are sent to the corresponding transmitters 12 F, 12 _A every 20 ms.

The transmitters 12 _F and 12 _A power-amplify this, and output it as, for example, an output pulse of about 20 W via the corresponding transmission / reception switching units 14 F and 14 A, and the front and rear transducers 16 _F. , 16 _A.

Front and rear transducers 16 _F , 16 _A
Converts this power pulse into ultrasonic waves and radiates it into the water.

The ultrasonic beam radiated into the water is scattered when it hits innumerable minute plankton, sand grains, bubbles, etc. floating in the seawater, and among them, the acoustic waves returning to the direction of the receiver are received. Become a signal. Here, if there is a relative velocity between these suspended solids in water and the ship, the frequency of the received wave will be Doppler-shifted due to the Doppler effect.

The received wave is converted into an electric signal in each of the front and rear transducers 16 _F and 16 _A , and is sent to the front / rear switching section 28 via the transmission / reception switching sections 14 F and 14 _A , respectively.

In the front / rear switching section 28, as shown in FIG. 2B, the received signal of the reflected wave from the front is input to the input terminal F _IN.
Input the received signal of the reflected wave from the rear to _IN . here,
To the control terminals C _tF and C _tA , the forward / backward direction switching signals G _FA and * G _FA from the frequency divider 40 are respectively amplified by the switch drive circuit 48, and the Q output G _FA is fed to the control terminal C _tF . * Q output * G _FA
Is input corresponding to the control terminal C _tA .

When Q is at high level, the coil L
₁ , a current flows through the path of the PIN diode D ₁ and the coil L ₃ , and as a result, the high frequency impedance of the PIN diode D ₁ is lowered, and the signal from the input terminal F _IN passes through the capacitor C ₃ to the receiving unit 18. Is output.

On the other hand, when * Q is high level, the coil L
₂ , a current flows through the path of the PIN diode D ₂ and the coil L ₃ , and as a result, the high frequency impedance of the PIN diode D ₂ decreases, and the signal from the input terminal A _IN passes through the capacitor C ₃ to the receiving unit 18. Is output.

The receiving unit 18 adopts the super-heterodyne system and converts the frequency of 2 MHz ± fd of the received signal including the Doppler shift fd into an intermediate frequency (200 KHz ± fd in this embodiment) by the local oscillation signal of 1.8 MHz. Then, it is sufficiently amplified and a TTL level rectangular wave is output.

Next, the frequency detector 56 detects the Doppler shift in each direction.

This detection method is a counting method,
An output 200 KHz ± fd of the receiving portion 18 is received signal, the reference clock C _S and a predetermined number (200 pieces) were counted, the required time difference by utilizing proportional to the Doppler shift, Searching for the time difference Detects Doppler shift.

The rectangular-wave-shaped received signal is input to the D flip-flop circuits 66 and 68 of the frequency detector 56 shown in FIG. 3 and the clock terminal C _K of the counter 70.

When the reception gate signal G _R and the reception signal are input to the D flip-flop circuits 66 and 68, the flip-flop circuits 66 and 68 respectively measure the measurement gate time signal G _S and the reference gate time signal G _r. Is output. These serve as enable signals for the corresponding counters 70 and 72, the counter 70 counts the received signal, and the counter 72 counts the reference clock C _S. When the counters 70 and 72 count up to preset values (in this embodiment, the former is 200 and the latter is 9000), they output count end signals.

This end signal resets the corresponding D flip-flop circuits 66 and 68, respectively. Each gate time signal
If the received signal and the reference clock do not match, G _S and G _r cause a difference in their gate times. In this embodiment,
The reference gate time G _r is set to 1 ms.

The gate time signals G _S and G _r are input to the exclusive OR gate circuit 76. Exclusive OR gate circuit 76, G _S
When ≠ G _r , the output becomes the difference gate G _F , and in that case, in the NAND gate circuit 78, in accordance with the difference between G _{S and} G _r , the reference clock C _S from the clock generator 64 (for example, 9M
(Hz) with its polarity reversed and passed. This output is the speed pulse * P _V.

On the other hand, the measurement gate time signal G _S and the front-rear direction switching signal G _FA are supplied to the exclusive OR gate circuit 82, and the reference time gate signal G _r inverted signal * G _r and the front-rear direction switching signal G
_FA and _FA are input to the exclusive OR gate circuit 84. And
The outputs of the exclusive OR gate circuit 82 and the exclusive OR gate circuit 84 are input to the NAND gate circuit 86. Here, when the measured gate time signal G _S of the received signal from the front is longer than the reference gate time signal G _r , or when the measured gate time signal G _S of the received signal from the rear is shorter than the reference gate time signal G _r , The exclusive OR gate circuit 82 corresponding to their time difference
And the output of the exclusive OR gate circuit 84 becomes high level both from the NAND gate circuit 86, the reverse pulse * P _A indicating that the ship is moving in reverse is output.

The number of pulses of the speed pulse * P _V is proportional to the Doppler shift, and the sum of the front Doppler shift and the rear Doppler shift is proportional to the speed of the ship. In the present embodiment, the average speed is obtained by integrating this for a certain time (sample time T _S ) and averaging the instantaneous speed. In this embodiment, this sample time
The T _S is set to 10 seconds, and outputs a single sample strobe signal from the timing circuit 126 to 10 seconds.

By the way, the instantaneous value of the received signal is not a stable value and has a great deal of variation. Therefore, if the integrated count is made as it is, when the ship is stopped or at a very low speed,
The signal in the reverse direction (reverse signal) is also integrated, and the speed instruction is greatly different from the actual one. In order to eliminate this, in the case of signals in the reverse direction, it is necessary to perform subtraction and integration. Therefore, this integration is performed by the pre-up / down counter 88 and the up / down counter 90 of the calculation unit 58. The pre-up / down counter 88 is set to a division ratio such that the display speed matches the actual speed.
This division ratio is provided so that it can be easily variably set by a digital switch or the like in order to eliminate an error due to the trim of the hull.

The up / down counter 90 further divides the output * P _S of the pre-up / down counter 88 and converts it into a 4-digit decimal number. The data of the up / down counter 90 is latched after the sample time T _S and sent to the numeral display 94 and the speed data sending circuit 98 as display data.

On the other hand, the forward / backward movement discrimination circuit 92 determines that the backward movement pulse P _A
Is used to determine whether the ship is moving forward or backward.

The latch circuit 124 of the forward / backward movement determination circuit 92 samples and latches the output of the Q terminal of the flip-flop circuit 120 according to the sample strobe signal from the timing circuit 126. The flip-flop circuit 120 is
Immediately after this sample strobe signal, the timing circuit 12
It is reset by the reset signal output from 6.
The cycle of the sample strobe signal and the reset signal is set as the sampling time T _{S, and} is set to 10 seconds in this embodiment.

After the flip-flop circuit 120 is reset, the reverse pulse * P _A is not output while the vessel is moving forward, so the flip-flop circuit 120 remains reset, and the up-down counter group 89 is
Count up. In this case, even if the next reset signal is input, the flip-flop circuit 120 does not change its state and the up-count state continues. This time,
The latch circuit 124 latches the output of the Q terminal of the flip-flop circuit 120 by the sample strobe signal, but since the Q terminal is at the low level, the backward display is not performed.

On the other hand, when the ship is moving in reverse, the reverse pulse is always applied *
Since P _A is output, the flip-flop circuit 120, P _A
The output pulse of the edge detection circuit 118 puts it in the set state, and the output of the * Q terminal becomes low level. In this state, in the exclusive OR gate circuit 122, the backward pulse P _A whose polarity has been inverted by the inverter 116 is input, so that the counter group 89 continues to count up.

Here, when the sample strobe signal is input, since the flip-flop circuit 120 is set, the high level state of the Q terminal thereof is latched by the latch circuit 124. Then, it is output as a backward display signal from the latch circuit 124 to turn on the backward display device 96.

By the way, in the vicinity of 0 knot where forward and reverse are mixed, when the sample strobe signal is finally input, if the flip-flop circuit 120 is set, it will be reverse, and if it is not set, it will be forward. Therefore, consider the case where forward and backward signals come randomly.

When the backward pulse * P _A is input, the flip-flop circuit 120 is set by the output of the P _A edge detection circuit 118. Therefore, until the reset signal is input or the clock signal is input, The state does not change. Therefore, once, after the reverse pulse * P _A has been input, forward signal is input (backward signal is not input)
Since the * Q terminal of the flip-flop circuit 120 is low level, the exclusive OR gate circuit 122 has its inputs in phase and its output becomes a low level countdown signal.

In this state, when the forward signal is input more than the backward signal, the counter group 89 continues the subtraction, the count value becomes "0", and the signal indicating that is output. On the other hand, when the forward signal is less than the reverse signal, the difference obtained by subtracting the forward signal from the reverse signal is the reverse speed.

The "0" output signal is input to the clock terminal C _K of the flip-flop circuit 120. This allows
The flip-flop circuit 120 is set or reset depending on the input signal at the D terminal at that time.

Here, assuming that the forward signal is input, the flip-flop circuit 120 changes to the reset state. After that, the same operation as described above is performed. On the other hand, assuming that a reverse signal is input, the flip-flop circuit 120 continues to be set and the latch circuit 124
Latches the high level state of the Q terminal and outputs a backward display signal.

By the way, the present embodiment is provided with a speed warning device, a lane counter and the like. Next, these actions will be described.

First, the alarm device receives speed data as serial data from the speed data transmission circuit 98 once every sampling time T _S , and latches the speed data in the speed comparison circuit 102. The speed comparison circuit 102 compares this data with the data input from the speed alarm setting switch 104,
When the speed is higher or lower than the preset data, an alarm signal is output and the buzzer 106 sounds.

The 200P / M relay 110 outputs 200 pulses per mile by the pulse obtained by dividing the output of the pre-up / down counter 88 by the frequency divider 108.

Further, the lane counter 114 is the frequency divider.
The output of 108 is further frequency-divided, converted into a unit distance signal, counted, and the navigation distance of the ship is displayed.

<Modification of Embodiment> In the above embodiment, the front / rear switching unit is arranged in the front stage of the receiving unit, but it may be arranged in the rear stage of the receiving units 18F and 18A as shown in FIG.

Further, in the above embodiment, the switch of the front / rear switching unit 28 is constituted by the PIN diode circuit, but the present invention is not limited to this, and it may be constituted by the FET, the bipolar transistor or the like. Further, as described above, when the front / rear switching unit 28 is arranged in the subsequent stage of the receiving units 18F and 18A, since the receiving unit output is at the logic level, the front / rear switching unit 28 has a simple gate, analog It can be configured with a switch or the like.

Further, in the above embodiment, the counter of the arithmetic unit is composed of the pre-up / down counter and the up / down counter, but they may be connected in series to form an integrated up / down counter.

[0077]

As described above, according to the present invention, transmission / reception can be alternately performed in the front and the rear, the front and rear reception signal processing units can be shared, and the circuit configuration can be simplified. The effect is that accurate speed display can be performed even when the ship is stopped or at a very low speed.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of a ship speed measuring device of the present invention.

FIG. 2 is a block diagram showing a configuration of an original oscillation unit and a front / rear switching unit which constitute the above embodiment, and FIG. 2 is a circuit diagram showing an example of the front / rear switching unit.

FIG. 3 is a block diagram showing a configuration of a frequency detection unit that constitutes the above embodiment.

FIG. 4 is a block diagram showing a configuration of an arithmetic unit that constitutes the above embodiment.

FIG. 5 is a block diagram showing a configuration of a forward / rearward traveling determination circuit which constitutes the arithmetic unit.

FIG. 6 is a time chart showing the operation of the original oscillator shown in FIG. 2A.

7 is a time chart showing the operation of the frequency detection unit shown in FIG.

FIG. 8 is a block diagram showing a configuration of a ship speed measuring device which is a modified example of the present embodiment.

FIG. 9 is a block diagram showing a configuration of a conventional ship speed measuring device.

[Explanation of symbols]

12F, 12A ... Transmission unit, 14F, 14A ... Transmission / reception switching unit, 16F,
16A ... Transceiver, 18,18F, 18A ... Reception section, 26 ... Original oscillation section, 28 ... Front-back switching section, 30 ... Transmission frequency oscillator, 32 ... Pulse repetition frequency oscillator, 34 ... Transmission pulse width setting circuit,
36 ... Depth position determination circuit, 38 ... Reception gate setting circuit, 40 ...
Frequency divider, 48 ... Switch drive circuit, 50 ... Switch, 56 ... Frequency detection section, 58 ... Calculation section, 60 ... Ship speed display section, 62 ... Gate signal forming section, 64 ... Clock generator, 66,68 ... D Flip-flop circuit, 70, 72 ... Counter, 74 ... Velocity pulse forming section, 80 ... Reverse pulse forming section, 88 ... Pre-up / down counter, 90 ... Up-down counter, 92 ... Forward / backward discrimination circuit, 94 ... Numeric display, 96 ... reverse display, 98 ... speed data transmission circuit, 100 ... speed alarm device.

Claims (1)

(57) [Scope of utility model registration request] 1. An oscillating circuit for oscillating a signal, and switching before and after transmission, which is connected to the oscillating circuit and alternately outputs the signal in two directions at a predetermined cycle shorter than the pitching cycle of a ship. Circuit and the front of the vessel, connected to one of the output terminals of the transmission / reception switching circuit, before converting the output signal into ultrasonic waves and emitting the ultrasonic waves before receiving and outputting the reflected waves. The directional transducer and the rear of the vessel are connected to the other output terminal of the transmission / reception switching circuit, and the output signal is converted into ultrasonic waves and emitted, and the reflected waves are received. A rear transducer to output, connected to the front transducer and the rear transducer,
A pre-reception and post-reception switching circuit that alternately switches and outputs any one of the outputs of the front-rear transducer and the rear-rear transducer at a predetermined cycle that is shorter than the ship's pitching cycle. A frequency detection circuit, which is connected to the switching circuit, detects a difference between the frequency of the output signal and the frequency of the reference clock, and outputs a pulse signal proportional to the detected frequency difference, and is connected to the frequency detection circuit and outputs the same. A pulse signal, an arithmetic circuit that integrates and outputs a predetermined fixed time, and is connected to the pre-reception switching circuit and the oscillation circuit,
The output of the switching circuit before and after the reception and the output of the oscillation circuit are compared, the reverse of the vessel is determined based on the comparison result, and a forward / backward determination circuit that outputs a reverse drive signal, the arithmetic circuit and the forward / backward movement. An integrating circuit which is connected to a discriminating circuit and which sums and accumulates the output of the arithmetic circuit when the backward signal is not input from the forward / backward discriminating circuit, and which subtracts and accumulates when the backward signal is input; A vessel speed measuring device, comprising: a display for displaying the output of the integrating circuit.