JP2025087846A5 - - Google Patents

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Publication number
JP2025087846A5
JP2025087846A5 JP2025035794A JP2025035794A JP2025087846A5 JP 2025087846 A5 JP2025087846 A5 JP 2025087846A5 JP 2025035794 A JP2025035794 A JP 2025035794A JP 2025035794 A JP2025035794 A JP 2025035794A JP 2025087846 A5 JP2025087846 A5 JP 2025087846A5
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JP
Japan
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intra
modes
list
mode
block
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JP2025035794A
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English (en)
Japanese (ja)
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JP2025087846A (ja
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Priority claimed from US17/573,856 external-priority patent/US12120335B2/en
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JP2025035794A 2021-08-24 2025-03-06 イントラモード符号化のためのハードウェアフレンドリーな設計 Pending JP2025087846A (ja)

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
US202163236542P 2021-08-24 2021-08-24
US63/236,542 2021-08-24
US17/573,856 2022-01-12
US17/573,856 US12120335B2 (en) 2021-08-24 2022-01-12 Hardware friendly design for intra mode coding
JP2023530738A JP7648761B2 (ja) 2021-08-24 2022-01-27 イントラモード符号化のためのハードウェアフレンドリーな設計
PCT/US2022/014145 WO2023027763A1 (en) 2021-08-24 2022-01-27 Hardware friendly design for intra mode coding

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JP2025087846A JP2025087846A (ja) 2025-06-10
JP2025087846A5 true JP2025087846A5 (https=) 2026-02-24

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JP2025035794A Pending JP2025087846A (ja) 2021-08-24 2025-03-06 イントラモード符号化のためのハードウェアフレンドリーな設計

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US (2) US12120335B2 (https=)
EP (1) EP4393153A4 (https=)
JP (2) JP7648761B2 (https=)
KR (1) KR20230117613A (https=)
CN (1) CN120602658A (https=)
WO (1) WO2023027763A1 (https=)

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