JP2024091861A - SiC semiconductor device - Google Patents

Abstract

An SiC semiconductor device is provided that can reduce the effect of a modified layer on a SiC semiconductor chip.
SOLUTION
The SiC semiconductor device 1 includes a SiC semiconductor layer 2 (SiC semiconductor chip) having a first main surface 3, a second main surface 4, and side surfaces 5A-5D, and modified lines 22A-22D (modified layers) formed in a portion of the SiC semiconductor substrate 6 at intervals from the SiC epitaxial layer 7 on the side surfaces 5A-5D and modified to have properties different from those of the SiC semiconductor substrate 6. Each of the modified lines 22A-22D has a plurality of modified portions 28, 29 extending in the normal direction Z of the first main surface 3. The modified portions 28, 29 have a tapered shape narrowing toward the second main surface 4.
[Selected figure] Figure 5

Description

This disclosure relates to a SiC semiconductor device.

In recent years, a processing method for SiC semiconductor wafers known as the stealth dicing method has been attracting attention. In the stealth dicing method, a SiC semiconductor wafer is selectively irradiated with laser light, and then the SiC semiconductor wafer is cut along the portion irradiated with the laser light. This method allows cutting of SiC semiconductor wafers with a relatively high hardness without using a cutting member such as a dicing blade, thereby shortening the manufacturing time.

Patent Document 1 discloses a method for manufacturing a SiC semiconductor device using a stealth dicing method. In the manufacturing method of Patent Document 1, multiple rows of modified regions (modified layers) are formed over the entire area of each side surface of a SiC semiconductor chip (SiC semiconductor layer) cut out from a SiC semiconductor wafer. The multiple rows of modified regions extend along the tangential direction of the main surface of the SiC semiconductor chip, and are formed at intervals in the normal direction of the main surface of the SiC semiconductor chip.

JP 2012-146878 A

The modified layer is formed by modifying the SiC single crystal to have other properties. Therefore, considering the influence of the modified layer on the SiC semiconductor chip (SiC semiconductor layer), it is not desirable to form multiple modified layers over the entire side surface of the SiC semiconductor chip. Examples of the influence of the modified layer on the SiC semiconductor chip include fluctuations in the electrical characteristics of the SiC semiconductor chip due to the modified layer and the occurrence of cracks in the SiC semiconductor chip originating from the modified layer.

One embodiment provides a SiC semiconductor device that can reduce the effects of a modified layer on a SiC semiconductor chip.

One embodiment provides a SiC semiconductor device having a stacked structure including a SiC semiconductor substrate and a SiC epitaxial layer, a device formation surface formed by the SiC epitaxial layer, and a side surface formed by the SiC semiconductor substrate and the SiC epitaxial layer, and a single modified layer formed in a portion of the SiC semiconductor substrate at a distance from the SiC epitaxial layer on the side surface and modified to have properties different from those of the SiC semiconductor substrate. This structure can reduce the effect of the modified layer on the SiC semiconductor chip, particularly on the SiC epitaxial layer that forms the device formation surface.

One embodiment provides a SiC semiconductor device including: a SiC semiconductor chip having a first main surface as an element formation surface, a second main surface opposite to the first main surface, and a side surface; a first impurity region of a first conductivity type formed in a surface layer portion of the first main surface so as to be exposed from the first main surface and the side surface; a second impurity region of a first conductivity type having a first conductivity type impurity concentration exceeding the first conductivity type impurity concentration of the first impurity region, exposed from the second main surface and the side surface, and formed in a region on the second main surface side with respect to the first impurity region so as to be electrically connected to the first impurity region; and a single modified layer formed in a portion of the side surface where the second impurity region is exposed at a distance from the first impurity region and modified to have properties different from those of the SiC semiconductor chip. With this structure, it is possible to reduce the influence of the modified layer on the SiC semiconductor chip, particularly on the element formation surface where the first impurity region is exposed.

One embodiment provides a SiC semiconductor device including a SiC chip having a first main surface on one side, a second main surface on the other side, and a side surface; a semiconductor substrate of a first conductivity type exposed from the side surface of the SiC chip; a semiconductor region of a first conductivity type formed on a surface layer of the first main surface so as to be stacked on the substrate main surface of the semiconductor substrate and exposed from the first main surface and the side surface; a pn junction region formed on the surface layer of the first main surface at the periphery of the first main surface; an impurity region of a second conductivity type formed on the surface layer of the semiconductor region at the periphery of the first main surface and forming the semiconductor region and the pn junction region; and a single reforming line formed on the side surface at a distance from the depth position of the pn junction region to the second main surface side and reformed to have a property different from SiC. The reforming line may be formed on the side surface at a distance from the depth position of the substrate main surface of the semiconductor substrate to the second main surface side. The reforming line may have a plurality of reforming portions each extending in a normal direction to the first main surface. The modified portion may have a tapered shape that narrows toward the second main surface.

One embodiment provides a SiC semiconductor device including a SiC chip having a first main surface on one side, a second main surface on the other side, and a side surface; a first surface portion located in an inner portion of the first main surface, a second surface portion formed on the periphery of the first main surface so as to be recessed from the first surface portion toward the second main surface, and a plateau defined on the first main surface by a connecting sidewall connecting the first surface portion and the second surface portion; a semiconductor substrate of a first conductivity type exposed from the side surface in the SiC chip; a semiconductor region of a first conductivity type formed on a surface layer portion of the first main surface so as to be exposed from the first main surface and the side surface; a pn junction region formed on the surface layer portion of the second surface portion; an impurity region of a second conductivity type formed in the surface layer portion of the semiconductor region and forming the semiconductor region and the pn junction region; and a single modification line formed on the side surface at a distance from a depth position of the pn junction region toward the second main surface, and modified to have properties different from SiC. The modification lines may be formed on the side surface at intervals from a depth position of the substrate main surface of the semiconductor substrate toward the second main surface. The modification lines may have a plurality of modification portions each extending in a normal direction of the first main surface. The modification portions may have a tapered shape narrowing toward the second main surface.

FIG. 1 is a diagram showing a unit cell of a 4H—SiC single crystal applied to an embodiment of the present disclosure. FIG. 2 is a plan view showing the silicon surface of the unit cell of the 4H—SiC single crystal shown in FIG. FIG. 3 is a perspective view of the SiC semiconductor device according to the first embodiment of the present disclosure as viewed from one angle, showing a first example of a modification line. FIG. 4 is a perspective view of the SiC semiconductor device shown in FIG. 3 as viewed from a different angle. FIG. 5 is an enlarged view of region V shown in FIG. FIG. 6 is an enlarged view of region VI shown in FIG. FIG. 7 is a plan view of the SiC semiconductor device shown in FIG. FIG. 8 is a cross-sectional view taken along line VIII-VIII shown in FIG. FIG. 9 is a perspective view showing a SiC semiconductor wafer used for manufacturing the SiC semiconductor device shown in FIG. 10A is a cross-sectional view showing an example of a method for manufacturing the SiC semiconductor device shown in FIG. 3. FIG. 10B is a diagram showing a step subsequent to that of FIG. 10A. FIG. 10C is a diagram showing a step subsequent to FIG. 10B. FIG. 10D is a diagram showing a step subsequent to FIG. 10C. FIG. 10E is a diagram showing a step subsequent to FIG. 10D. FIG. 10F is a diagram showing a step subsequent to FIG. 10E. FIG. 10G is a diagram showing a step subsequent to FIG. 10F. FIG. 10H is a diagram showing a step subsequent to FIG. 10G. FIG. 10I is a diagram showing a process subsequent to FIG. 10H. FIG. 10J is a diagram showing a step subsequent to FIG. 10I. FIG. 10K is a diagram showing a step subsequent to FIG. 10J. FIG. 10L is a diagram showing a step subsequent to FIG. 10K. FIG. 10M is a diagram showing a process subsequent to FIG. 10L. FIG. 11 is a perspective view showing a semiconductor package in which the SiC semiconductor device shown in FIG. 3 is assembled, with a sealing resin seen through. FIG. 12A is a perspective view showing the SiC semiconductor device shown in FIG. 3, and is a perspective view showing a second embodiment of the reforming line. 12B is a perspective view showing the SiC semiconductor device shown in FIG. 3, and is a perspective view showing a third embodiment of the reforming line. FIG. FIG. 12C is a perspective view showing the SiC semiconductor device shown in FIG. 3, and is a perspective view showing a fourth embodiment of the reforming line. FIG. 12D is a perspective view showing the SiC semiconductor device shown in FIG. 3 and showing a fifth embodiment of the reforming line. FIG. 12E is a perspective view showing the SiC semiconductor device shown in FIG. 3, and is a perspective view showing a sixth embodiment of the reforming line. FIG. 13 is a perspective view showing a SiC semiconductor device according to a second embodiment of the present disclosure, and is a perspective view showing a structure to which the modification line according to the first embodiment is applied. FIG. 14 is a perspective view of the SiC semiconductor device according to the third embodiment of the present disclosure as viewed from one angle, showing a structure to which the modification line according to the first embodiment example is applied. FIG. 15 is a perspective view of the SiC semiconductor device shown in FIG. 14 as viewed from a different angle. FIG. 16 is a plan view showing the SiC semiconductor device shown in FIG. FIG. 17 is a plan view showing a state where the resin layer is removed from FIG. FIG. 18 is an enlarged view of region XVIII shown in FIG. 17 and is a diagram for explaining the structure of the first main surface of the SiC semiconductor layer. FIG. 19 is a cross-sectional view taken along line XIX-XIX shown in FIG. FIG. 20 is a cross-sectional view taken along the line XX-XX shown in FIG. FIG. 21 is an enlarged view of region XXI shown in FIG. 22 is a cross-sectional view taken along line XXII-XXII shown in FIG. 17. FIG. FIG. 23 is an enlarged view of region XXIII shown in FIG. FIG. 24 is a graph for explaining the sheet resistance. FIG. 25 is an enlarged view of a region corresponding to FIG. 18 and shows a SiC semiconductor device according to a fourth embodiment of the present disclosure. 26 is a cross-sectional view taken along line XXVI-XXVI shown in FIG. 25. FIG. FIG. 27 is an enlarged view of a region corresponding to FIG. 21 and shows a SiC semiconductor device according to a fifth embodiment of the present disclosure. FIG. 28 is an enlarged view of a region corresponding to FIG. 18 and shows a SiC semiconductor device according to a sixth embodiment of the present disclosure.

Embodiments of the present disclosure are described in detail below with reference to the accompanying drawings.

In the embodiment of the present disclosure, a SiC (silicon carbide) single crystal made of a hexagonal crystal is applied. The SiC single crystal made of a hexagonal crystal has a number of polytypes, including 2H (Hexagonal)-SiC single crystal, 4H-SiC single crystal, and 6H-SiC single crystal, depending on the period of the atomic arrangement. In the embodiment of the present disclosure, an example in which a 4H-SiC single crystal is applied is described, but other polytypes are not excluded from the present disclosure.

The crystal structure of 4H-SiC single crystal will be described below. Figure 1 is a diagram showing a unit cell of 4H-SiC single crystal (hereinafter simply referred to as a "unit cell") that is applied to an embodiment of the present disclosure. Figure 2 is a plan view showing the silicon surface of the unit cell shown in Figure 1.

Referring to Figures 1 and 2, the unit cell includes a tetrahedral structure in which one Si atom and four C atoms are bonded in a tetrahedral arrangement (regular tetrahedral arrangement). The unit cell has an atomic arrangement in which four periods of tetrahedral structures are stacked. The unit cell has a hexagonal prism structure with regular hexagonal silicon faces, regular hexagonal carbon faces, and six side faces connecting the silicon faces and carbon faces.

A silicon surface is a surface terminated by Si atoms. In a silicon surface, one Si atom is located at each of the six vertices of a regular hexagon, and one Si atom is located at the center of the regular hexagon.

A carbon surface is a surface terminated by C atoms. In a carbon surface, one C atom is located at each of the six vertices of a regular hexagon, and one C atom is located at the center of the regular hexagon.

The crystal planes of the unit cell are defined by four coordinate axes (a1, a2, a3, c) including the a1 axis, a2 axis, a3 axis, and c axis. The value of a3 among the four coordinate axes is -(a1 + a2). Below, the crystal planes of a 4H-SiC single crystal are explained based on the silicon surface as an example of a hexagonal crystal termination surface.

The a1, a2 and a3 axes are set along the arrangement direction of the nearest Si atoms (hereinafter simply referred to as the "nearest atom direction") based on the central Si atom in a planar view of the silicon surface seen from the c-axis. The a1, a2 and a3 axes are set at angles of 120° each, following the arrangement of the Si atoms.

The c-axis is set in the normal direction of the silicon surface, based on the Si atom located at the center. The silicon surface is the (0001) surface. The carbon surface is the (000-1) surface.

The side of the hexagonal prism includes six crystal planes along the nearest atom direction in a planar view of the silicon surface from the c-axis. More specifically, the side of the hexagonal prism includes six crystal planes each including the two nearest Si atoms in a planar view of the silicon surface from the c-axis.

When viewed from the c-axis, the side of the hexagonal prism includes, clockwise from the tip of the a1 axis, the (1-100), (0-110), (-1010), (-1100), (01-10), and (10-10) planes.

The diagonal plane along the diagonal line of the hexagonal prism includes six crystal planes along an intersecting direction that intersects with the nearest-neighbor atom direction when viewed from the c-axis in a plan view of the silicon surface. More specifically, the diagonal plane of the hexagonal prism includes six crystal planes each including two non-nearest Si atoms when viewed from the c-axis in a plan view of the silicon surface. When viewed from the perspective of the Si atom located in the center, the intersecting direction of the nearest-neighbor atom direction is an orthogonal direction that is perpendicular to the nearest-neighbor atom direction.

The diagonal faces of the hexagonal prism include the (11-20), (1-210), (-2110), (-1-120), (-12-10), and (2-1-10) faces when viewed from the c-axis of the silicon surface.

The crystal orientation of the unit cell is defined by the normal direction of the crystal plane. The normal direction of the (1-100) plane is the [1-100] direction. The normal direction of the (0-110) plane is the [0-110] direction. The normal direction of the (-1010) plane is the [-1010] direction. The normal direction of the (-1100) plane is the [-1100] direction. The normal direction of the (01-10) plane is the [01-10] direction. The normal direction of the (10-10) plane is the [10-10] direction.

The normal direction of the (11-20) plane is the [11-20] direction. The normal direction of the (1-210) plane is the [1-210] direction. The normal direction of the (-2110) plane is the [-2110] direction. The normal direction of the (-1-120) plane is the [-1-120] direction. The normal direction of the (-12-10) plane is the [-12-10] direction. The normal direction of the (2-1-10) plane is the [2-1-10] direction.

Hexagonal crystals have six-fold symmetry, and there are equivalent crystal planes and equivalent crystal directions every 60°. For example, the (1-100) plane, (0-110) plane, (-1010) plane, (-1100) plane, (01-10) plane, and (10-10) plane form equivalent crystal planes.

The [1-100], [0-110], [-1010], [-1100], [01-10] and [10-10] directions form equivalent crystal directions. The [11-20], [1-210], [-2110], [-1-120], [-12-10] and [2-1-10] directions form equivalent crystal directions.

The c-axis is in the [0001] direction ([000-1] direction). The a1-axis is in the [2-1-10] direction ([-2110] direction). The a2-axis is in the [-12-10] direction ([1-210] direction). The a3-axis is in the [-1-120] direction ([11-20] direction).

The (0001) and (000-1) planes are collectively referred to as c-planes. The [0001] and [000-1] directions are collectively referred to as the c-axis direction. The (11-20) and (-1-120) planes are collectively referred to as a-planes. The [11-20] and [-1-120] directions are collectively referred to as the a-axis direction. The (1-100) and (-1100) planes are collectively referred to as m-planes. The [1-100] and [-1100] directions are collectively referred to as the m-axis direction.

Figure 3 is a perspective view of the SiC semiconductor device 1 according to the first embodiment of the present disclosure, seen from one angle, and is a perspective view showing a first example of the reforming lines 22A to 22D. Figure 4 is a perspective view of the SiC semiconductor device 1 shown in Figure 3, seen from another angle.

Figure 5 is an enlarged view of region V shown in Figure 3. Figure 6 is an enlarged view of region VI shown in Figure 3. Figure 7 is a plan view of the SiC semiconductor device 1 shown in Figure 3. Figure 8 is a cross-sectional view taken along line VIII-VIII shown in Figure 7.

Referring to Figures 3 to 8, the SiC semiconductor device 1 includes a SiC semiconductor layer 2. The SiC semiconductor layer 2 includes a 4H-SiC single crystal, which is an example of a SiC single crystal made of a hexagonal crystal. The SiC semiconductor layer 2 (SiC semiconductor chip) is formed in the shape of a rectangular parallelepiped chip.

The SiC semiconductor layer 2 has a first main surface 3 on one side, a second main surface 4 on the other side, and side surfaces 5A, 5B, 5C, and 5D connecting the first main surface 3 and the second main surface 4. The first main surface 3 and the second main surface 4 are formed in a quadrangular shape (square shape in this embodiment) in a plan view (hereinafter simply referred to as "plan view") seen from their normal direction Z.

The first main surface 3 is an element formation surface on which a semiconductor element is formed. The second main surface 4 of the SiC semiconductor layer 2 is a ground surface having grinding marks. The side surfaces 5A to 5D are each a smooth cleavage surface facing the crystal plane of the SiC single crystal. The side surfaces 5A to 5D do not have grinding marks.

The thickness TL of the SiC semiconductor layer 2 may be 40 μm or more and 200 μm or less. The thickness TL may be 40 μm or more and 60 μm or less, 60 μm or more and 80 μm or less, 80 μm or more and 100 μm or less, 100 μm or more and 120 μm or less, 120 μm or more and 140 μm or less, 140 μm or more and 160 μm or less, 160 μm or more and 180 μm or less, or 180 μm or more and 200 μm or less. The thickness TL is preferably 60 μm or more and 150 μm or less.

In this embodiment, the first main surface 3 and the second main surface 4 face the c-plane of the SiC single crystal. The first main surface 3 faces the (0001) plane (silicon plane). The second main surface 4 faces the (000-1) plane (carbon plane) of the SiC single crystal.

The first and second main surfaces 3 and 4 have an off angle θ that is inclined at an angle of 10° or less in the [11-20] direction with respect to the c-plane of the SiC single crystal. The normal direction Z is inclined by the off angle θ with respect to the c-axis ([0001] direction) of the SiC single crystal.

The off angle θ may be 0° or more and 5.0° or less. The off angle θ may be set in the range of 0° or more and 1.0° or less, 1.0° or more and 1.5° or less, 1.5° or more and 2.0° or less, 2.0° or more and 2.5° or less, 2.5° or more and 3.0° or less, 3.0° or more and 3.5° or less, 3.5° or more and 4.0° or less, 4.0° or more and 4.5° or less, or 4.5° or more and 5.0° or less. It is preferable that the off angle θ is greater than 0°. The off angle θ may be less than 4.0°.

The off angle θ may be set in the range of 3.0° to 4.5°. In this case, it is preferable that the off angle θ is set in the range of 3.0° to 3.5° or 3.5° to 4.0°.

The off angle θ may be set in the range of 1.5° to 3.0°. In this case, it is preferable that the off angle θ is set in the range of 1.5° to 2.0° or 2.0° to 2.5°.

The length of each of the sides 5A to 5D may be 0.5 mm or more and 10 mm or less. In this embodiment, the surface areas of the sides 5A to 5D are equal to each other. When the first main surface 3 and the second main surface 4 are formed in a rectangular shape in a plan view, the surface areas of the sides 5A and 5C may be less than the surface areas of the sides 5B and 5D, or may be greater than the surface areas of the sides 5B and 5D.

In this embodiment, side 5A and side 5C extend along a first direction X and face each other in a second direction Y that intersects with the first direction X. In this embodiment, side 5B and side 5D extend along the second direction Y and face each other in the first direction X. More specifically, the second direction Y is a direction perpendicular to the first direction X.

In this embodiment, the first direction X is set to the m-axis direction ([1-100] direction) of the SiC single crystal. The second direction Y is set to the a-axis direction ([11-20] direction) of the SiC single crystal.

Side 5A and side 5C are formed by the a-plane of the SiC single crystal and face each other in the a-axis direction. Side 5A is formed by the (-1-120) plane of the SiC single crystal. Side 5C is formed by the (11-20) plane of the SiC single crystal.

Side 5B and side 5D are formed by the m-plane of the SiC single crystal and face each other in the m-axis direction. Side 5B is formed by the (-1100) plane of the SiC single crystal. Side 5D is formed by the (1-100) plane of the SiC single crystal.

When the normal to the first main surface 3 of the SiC semiconductor layer 2 is used as a reference, the side surface 5A and the side surface 5C may form an inclined surface that is inclined toward the c-axis direction ([0001] direction) of the SiC single crystal with respect to the normal.

In this case, when the normal to the first main surface 3 of the SiC semiconductor layer 2 is set to 0°, the side surface 5A and the side surface 5C may be inclined at an angle corresponding to the off angle θ with respect to the normal to the first main surface 3 of the SiC semiconductor layer 2. The angle corresponding to the off angle θ may be equal to the off angle θ or may be an angle greater than 0° and less than the off angle θ.

On the other hand, side surface 5B and side surface 5D extend planarly along the normal to first main surface 3 of SiC semiconductor layer 2. More specifically, side surface 5B and side surface 5D are formed approximately perpendicular to first main surface 3 and second main surface 4.

In this embodiment, the SiC semiconductor layer 2 has a laminated structure including an n ⁺ type SiC semiconductor substrate 6 (second impurity region) and an n-type SiC epitaxial layer 7 (first impurity region). The second main surface 4 of the SiC semiconductor layer 2 is formed by the SiC semiconductor substrate 6.

The first main surface 3 of the SiC semiconductor layer 2 is formed by the SiC epitaxial layer 7. The side surfaces 5A to 5D of the SiC semiconductor layer 2 are formed by the SiC semiconductor substrate 6 and the SiC epitaxial layer 7.

The n-type impurity concentration of the SiC epitaxial layer 7 is equal to or lower than the n-type impurity concentration of the SiC semiconductor substrate 6. More specifically, the n-type impurity concentration of the SiC epitaxial layer 7 is lower than the n-type impurity concentration of the SiC semiconductor substrate 6. The n-type impurity concentration of the SiC semiconductor substrate 6 may be equal to or higher than 1.0×10 ¹⁸ cm ^-3 and equal to or lower than 1.0×10 ²¹ cm ^-3 . The n-type impurity concentration of the SiC epitaxial layer 7 may be equal to or higher than 1.0×10 ¹⁵ cm ^-3 and equal to or lower than 1.0×10 ¹⁸ cm ^-3 .

The thickness TS of the SiC semiconductor substrate 6 may be 40 μm or more and 150 μm or less. The thickness TS may be 40 μm or more and 50 μm or less, 50 μm or more and 60 μm or less, 60 μm or more and 70 μm or less, 70 μm or more and 80 μm or less, 80 μm or more and 90 μm or less, 90 μm or more and 100 μm or less, 100 μm or more and 110 μm or less, 110 μm or more and 120 μm or less, 120 μm or more and 130 μm or less, 130 μm or more and 140 μm or less, or 140 μm or more and 150 μm or less. The thickness TS is preferably 40 μm or more and 130 μm or less. By thinning the SiC semiconductor substrate 6, the resistance value can be reduced by shortening the current path.

The thickness TE of the SiC epitaxial layer 7 may be 1 μm or more and 50 μm or less. The thickness TE may be 1 μm or more and 5 μm or less, 5 μm or more and 10 μm or less, 10 μm or more and 15 μm or less, 15 μm or more and 20 μm or less, 20 μm or more and 25 μm or less, 25 μm or more and 30 μm or less, 30 μm or more and 35 μm or less, 35 μm or more and 40 μm or less, 40 μm or more and 45 μm or less, or 45 μm or more and 50 μm or less. The thickness TE is preferably 5 μm or more and 15 μm or less.

The SiC semiconductor layer 2 has an active region 8 and an outer region 9. The active region 8 is a region in which a Schottky barrier diode D, which is an example of a semiconductor element, is formed. The outer region 9 is a region outside the active region 8.

The active region 8 is set in the center of the SiC semiconductor layer 2, spaced apart from the side surfaces 5A to 5D of the SiC semiconductor layer 2 in a plan view. The active region 8 is set in a quadrangle shape having four sides parallel to the side surfaces 5A to 5D of the SiC semiconductor layer 2 in a plan view.

The outer region 9 is set in the region between the side surfaces 5A-5D of the SiC semiconductor layer 2 and the periphery of the active region 8. The outer region 9 is set in an endless shape (a square ring in this embodiment) surrounding the active region 8 in a plan view.

A main surface insulating layer 10 is formed on the first main surface 3 of the SiC semiconductor layer 2. The main surface insulating layer 10 selectively covers the active region 8 and the outer region 9. The main surface insulating layer 10 may have a single-layer structure made of a silicon oxide (SiO ₂ ) layer or a silicon nitride (SiN) layer.

The main surface insulating layer 10 may have a laminated structure including a silicon oxide layer and a silicon nitride layer. The silicon oxide layer may be formed on the silicon nitride layer. The silicon nitride layer may be formed on the silicon oxide layer. In this embodiment, the main surface insulating layer 10 has a single layer structure consisting of a silicon oxide layer.

The main surface insulating layer 10 has insulating side surfaces 11A, 11B, 11C, and 11D exposed from the side surfaces 5A to 5D of the SiC semiconductor layer 2. The insulating side surfaces 11A to 11D are continuous with the side surfaces 5A to 5D of the SiC semiconductor layer 2. The insulating side surfaces 11A to 11D are formed flush with the side surfaces 5A to 5D. The insulating side surfaces 11A to 11D are made of cleavage planes.

The thickness of the main surface insulating layer 10 may be 1 μm or more and 50 μm or less. The thickness of the main surface insulating layer 10 may be 1 μm or more and 10 μm or less, 10 μm or more and 20 μm or less, 20 μm or more and 30 μm or less, 30 μm or more and 40 μm or less, or 40 μm or more and 50 μm or less.

A first principal surface electrode layer 12 is formed on the principal surface insulating layer 10. The first principal surface electrode layer 12 is formed in the center of the SiC semiconductor layer 2, spaced apart from the side surfaces 5A to 5D of the SiC semiconductor layer 2 in a plan view.

A passivation layer 13 (insulating layer) is formed on the main surface insulating layer 10. The passivation layer 13 may have a single-layer structure made of a silicon oxide layer or a silicon nitride layer.

The passivation layer 13 may have a laminated structure including a silicon oxide layer and a silicon nitride layer. The silicon oxide layer may be formed on the silicon nitride layer. The silicon nitride layer may be formed on the silicon oxide layer. In this embodiment, the passivation layer 13 has a single-layer structure consisting of a silicon nitride layer.

The side surfaces 14A, 14B, 14C, and 14D of the passivation layer 13 are formed at intervals inward from the side surfaces 5A to 5D of the SiC semiconductor layer 2 in a plan view. The passivation layer 13 exposes the peripheral portion of the first main surface 3 of the SiC semiconductor layer 2 in a plan view. The passivation layer 13 exposes the main surface insulating layer 10.

A subpad opening 15 is formed in the passivation layer 13, exposing a portion of the first principal surface electrode layer 12 as a pad region. The subpad opening 15 is formed in a quadrangle shape having four sides parallel to the side surfaces 5A to 5D of the SiC semiconductor layer 2 in a plan view.

The thickness of the passivation layer 13 may be 1 μm or more and 50 μm or less. The thickness of the passivation layer 13 may be 1 μm or more and 10 μm or less, 10 μm or more and 20 μm or less, 20 μm or more and 30 μm or less, 30 μm or more and 40 μm or less, or 40 μm or more and 50 μm or less.

A resin layer 16 (insulating layer) is formed on the passivation layer 13. The passivation layer 13 and the resin layer 16 form a single insulating laminated structure (insulating layer). In FIG. 7, the resin layer 16 is shown by hatching.

The resin layer 16 may contain a negative type or a positive type photosensitive resin. In this embodiment, the resin layer 16 contains polybenzoxazole as an example of a positive type photosensitive resin. The resin layer 16 may contain polyimide as an example of a negative type photosensitive resin.

The resin side surfaces 17A, 17B, 17C, and 17D of the resin layer 16 are formed at intervals inward from the side surfaces 5A to 5D of the SiC semiconductor layer 2 in a plan view. The resin layer 16 exposes the peripheral portion of the first main surface 3 of the SiC semiconductor layer 2 in a plan view. The resin layer 16 exposes the main surface insulating layer 10 together with the passivation layer 13. In this embodiment, the resin side surfaces 17A to 17D of the resin layer 16 are formed flush with the side surfaces 14A to 14D of the passivation layer 13.

The resin side surfaces 17A-17D of the resin layer 16 are the parts that define the dicing streets when the SiC semiconductor device 1 is cut out from a single SiC semiconductor wafer. In this embodiment, the side surfaces 14A-14D of the passivation layer 13 are also the parts that define the dicing streets.

By exposing the peripheral portion of the first main surface 3 of the SiC semiconductor layer 2 from the resin layer 16 and the passivation layer 13, it is no longer necessary to physically cut the resin layer 16 and the passivation layer 13. This makes it possible to smoothly cut out the SiC semiconductor device 1 from one SiC semiconductor wafer. In addition, the insulation distance from the side surfaces 5A to 5D of the SiC semiconductor layer 2 can be increased.

The distance between the side surfaces 5A-5D and the resin side surfaces 17A-17D (side surfaces 14A-14D) may be 1 μm or more and 25 μm or less. The distance between the side surfaces 5A-5D and the resin side surfaces 17A-17D (side surfaces 14A-14D) may be 1 μm or more and 5 μm or less, 5 μm or more and 10 μm or less, 10 μm or more and 15 μm or less, 15 μm or more and 20 μm or less, or 20 μm or more and 25 μm or less. Of course, the side surfaces 14A-14D of the passivation layer 13 may be formed flush with the side surfaces 5A-5D of the SiC semiconductor layer 2.

A pad opening 18 is formed in the resin layer 16, exposing a portion of the first principal surface electrode layer 12 as a pad region. The pad opening 18 is formed in a quadrangle shape having four sides parallel to the side surfaces 5A to 5D of the SiC semiconductor layer 2 in a plan view.

The pad opening 18 is connected to the subpad opening 15. The inner wall of the pad opening 18 is formed flush with the inner wall of the subpad opening 15. The inner wall of the pad opening 18 may be located on the side of the side surfaces 5A to 5D of the SiC semiconductor layer 2 relative to the inner wall of the subpad opening 15. The inner wall of the pad opening 18 may be located in an inner region of the SiC semiconductor layer 2 relative to the inner wall of the subpad opening 15. The resin layer 16 may cover the inner wall of the subpad opening 15.

The thickness of the resin layer 16 may be 1 μm or more and 50 μm or less. The thickness of the resin layer 16 may be 1 μm or more and 10 μm or less, 10 μm or more and 20 μm or less, 20 μm or more and 30 μm or less, 30 μm or more and 40 μm or less, or 40 μm or more and 50 μm or less.

A second principal surface electrode layer 19 is formed on the second principal surface 4 of the SiC semiconductor layer 2. The second principal surface electrode layer 19 forms an ohmic contact with the second principal surface 4 of the SiC semiconductor layer 2 (SiC semiconductor substrate 6).

A plurality of modification lines 22A-22D (modification layers) are formed on the side surfaces 5A-5D of the SiC semiconductor layer 2. More specifically, the modification lines 22A-22D are formed one layer at a time in a one-to-one correspondence with the side surfaces 5A-5D.

The reforming lines 22A to 22D include one layer of reforming lines 22A formed on side 5A, one layer of reforming lines 22B formed on side 5B, one layer of reforming lines 22C formed on side 5C, and one layer of reforming lines 22D formed on side 5D. In this embodiment, the reforming lines 22A to 22D consist of a single layer.

A single layer of reforming line 22A may include a configuration in which multiple reforming lines 22A are formed by overlapping each other, such that one layer of reforming line 22A can be considered to be formed by multiple layers of reforming lines 22A.

A single layer of reforming line 22B may include a configuration in which multiple reforming lines 22B are formed by overlapping each other, such that one layer of reforming line 22B can be considered to be formed by multiple layers of reforming lines 22B.

A single layer of reforming line 22C may include a configuration in which multiple reforming lines 22C are formed by overlapping each other, such that one layer of reforming line 22C can be considered to be formed by multiple layers of reforming lines 22C.

A single layer of reforming line 22D may include a configuration in which multiple reforming lines 22D are formed by overlapping each other, such that one layer of reforming line 22D can be considered to be formed by multiple layers of reforming lines 22D.

However, in these cases, the reforming lines 22A-22D must be formed in multiple layers on the corresponding sides 5A-5D, which is not desirable from the standpoint of increasing the number of steps and delaying the manufacturing time. Therefore, this embodiment shows an example in which the reforming lines 22A-22D consisting of a single layer are formed on each of the sides 5A-5D.

The modification lines 22A-22D include layered regions in which a portion of the SiC single crystal forming the side surfaces 5A-5D has been modified to have properties different from those of the SiC single crystal. The modification lines 22A-22D include regions in which the density, refractive index, mechanical strength (crystal strength), or other physical properties have been modified to have properties different from those of the SiC single crystal.

The modification lines 22A to 22D may include at least one of a melt-rehardened layer, a defect layer, a dielectric breakdown layer, and a refractive index change layer. The melt-rehardened layer is a layer in which a part of the SiC semiconductor layer 2 melts and then hardens again. The defect layer is a layer that contains voids, cracks, etc. formed in the SiC semiconductor layer 2. The dielectric breakdown layer is a layer in which a part of the SiC semiconductor layer 2 has undergone dielectric breakdown. The refractive index change layer is a layer in which a part of the SiC semiconductor layer 2 has changed to a refractive index different from that of the SiC single crystal.

The modification lines 22A to 22D extend in a band shape along the tangential direction of the first main surface 3 of the SiC semiconductor layer 2. The tangential direction of the first main surface 3 is a direction perpendicular to the normal direction Z. The tangential direction includes a first direction X (the m-axis direction of the SiC single crystal) and a second direction Y (the a-axis direction of the SiC single crystal).

More specifically, the reforming line 22A is formed in a band shape that extends linearly along the m-axis direction on the side 5A. The reforming line 22B is formed in a band shape that extends linearly along the a-axis direction on the side 5B. The reforming line 22C is formed in a band shape that extends linearly along the m-axis direction on the side 5C. The reforming line 22D is formed in a band shape that extends linearly along the a-axis direction on the side 5D.

The modification lines 22A-22D are formed at intervals from the first main surface 3 to the second main surface 4 of the SiC semiconductor layer 2. The modification lines 22A-22D expose the surface portion of the first main surface 3 of the SiC semiconductor layer 2 from the side surfaces 5A-5D. In other words, the modification lines 22A-22D are not formed in the main surface insulating layer 10, the passivation layer 13, and the resin layer 16.

The modification lines 22A to 22D are formed at intervals from the second main surface 4 to the first main surface 3 of the SiC semiconductor layer 2. The modification lines 22A to 22D expose the surface portion of the second main surface 4 of the SiC semiconductor layer 2 from the side surfaces 5A to 5D.

As a result, the modification lines 22A-22D divide each side surface 5A-5D of the SiC semiconductor layer 2 into two regions, one on the first main surface 3 side and the other on the second main surface 4 side, when viewed from the side normal to each side surface 5A-5D of the SiC semiconductor layer 2.

The modification lines 22A to 22D are formed on the SiC semiconductor substrate 6. The modification lines 22A to 22D are formed at intervals from the boundary between the SiC semiconductor substrate 6 and the SiC epitaxial layer 7 to the second main surface 4.

As a result, the modification lines 22A-22D expose the SiC epitaxial layer 7 in the surface portion of the first main surface 3 of the SiC semiconductor layer 2. In other words, the SiC epitaxial layer 7 is included in the region on the first main surface 3 side of the region divided into two by the modification lines 22A-22D on each side surface 5A-5D of the SiC semiconductor layer 2.

On each side surface 5A to 5D, a stripe pattern extending in the tangent direction of the first main surface 3 is formed by the modification lines 22A to 22D, the surface layer portion of the first main surface 3 of the SiC semiconductor layer 2, and the surface layer portion of the second main surface 4 of the SiC semiconductor layer 2.

The reforming line 22A and the reforming line 22B are connected to each other at a corner that connects the side 5A and the side 5B of the SiC semiconductor layer 2. The reforming line 22B and the reforming line 22C are connected to each other at a corner that connects the side 5B and the side 5C of the SiC semiconductor layer 2.

The reforming line 22C and the reforming line 22D are connected to each other at a corner that connects the side 5C and the side 5D of the SiC semiconductor layer 2. The reforming line 22D and the reforming line 22A are connected to each other at a corner that connects the side 5D and the side 5A of the SiC semiconductor layer 2.

As a result, the reforming lines 22A to 22D are integrally formed to surround the SiC semiconductor layer 2. In other words, the reforming lines 22A to 22D form a single endless (annular) reforming line that surrounds the SiC semiconductor layer 2 on the side surfaces 5A to 5D of the SiC semiconductor layer 2.

The thickness TR of the modification lines 22A to 22D in the normal direction Z is preferably equal to or less than the thickness TL of the SiC semiconductor layer 2 (TR≦TL). It is further preferable that the thickness TR of the modification lines 22A to 22D is less than the thickness TS of the SiC semiconductor substrate 6 (TR<TS).

The thickness TR of the reforming lines 22A to 22D may be equal to or greater than the thickness TE of the SiC epitaxial layer 7 (TR≧TE). The thickness TR of the reforming line 22A, the thickness TR of the reforming line 22B, the thickness TR of the reforming line 22C, and the thickness TR of the reforming line 22D may be equal to or different from each other.

The ratio TR/TL of the thickness TR of the reforming lines 22A-22D to the thickness TL of the SiC semiconductor layer 2 is preferably 0.1 or more and less than 1.0. The ratio TR/TL may be 0.1 or more and 0.2 or less, 0.2 or more and 0.4 or less, 0.4 or more and 0.6 or less, 0.6 or more and 0.8 or less, or 0.8 or more and less than 1.0.

The ratio TR/TL may be 0.1 or more and 0.2 or less, 0.2 or more and 0.3 or less, 0.3 or more and 0.4 or less, 0.4 or more and 0.5 or less, 0.5 or more and 0.6 or less, 0.6 or more and 0.7 or less, 0.7 or more and 0.8 or less, 0.8 or more and 0.9 or less, or 0.9 or more and less than 1.0. The ratio TR/TL is preferably 0.2 or more and 0.5 or less.

It is more preferable that the ratio TR/TS of the thickness TR of the reforming lines 22A-22D to the thickness TS of the SiC semiconductor substrate 6 is 0.1 or more and less than 1.0. The ratio TR/TS may be 0.1 or more and 0.2 or less, 0.2 or more and 0.4 or less, 0.4 or more and 0.6 or less, 0.6 or more and 0.8 or less, or 0.8 or more and less than 1.0.

The ratio TR/TS may be 0.1 or more and 0.2 or less, 0.2 or more and 0.3 or less, 0.3 or more and 0.4 or less, 0.4 or more and 0.5 or less, 0.5 or more and 0.6 or less, 0.6 or more and 0.7 or less, 0.7 or more and 0.8 or less, 0.8 or more and 0.9 or less, or 0.9 or more and less than 1.0. The ratio TR/TS is preferably 0.2 or more and 0.5 or less.

Referring to FIG. 5, the modification line 22A includes a plurality of a-plane modified portions 28 (modified portions). In other words, the modification line 22A is formed by an assembly of a plurality of a-plane modified portions 28. The plurality of a-plane modified portions 28 are portions in which the SiC single crystal exposed from the side surface 5A has been modified to have properties different from those of the SiC single crystal. The area surrounding each a-plane modified portion 28 on the side surface 5A may be modified to have properties different from those of the SiC single crystal.

Each of the multiple a-plane modified portions 28 includes one end 28a located on the first main surface 3 side, the other end 28b located on the second main surface 4 side, and a connection portion 28c connecting the one end 28a and the other end 28b.

The multiple a-plane modified regions 28 are each formed in a line extending in the normal direction Z. As a result, the multiple a-plane modified regions 28 are formed in a striped pattern as a whole. The multiple a-plane modified regions 28 may include multiple a-plane modified regions 28 formed in a tapered shape in which the m-axis direction width narrows from one end 28a side to the other end 28b side.

The multiple a-plane modified portions 28 are formed at intervals in the m-axis direction so as to face each other in the m-axis direction. The multiple a-plane modified portions 28 may overlap each other in the m-axis direction. A band-shaped region extending in the m-axis direction is formed by a line connecting one end 28a of the multiple a-plane modified portions 28 and a line connecting the other end 28b of the multiple a-plane modified portions 28. The modified line 22A is formed by this band-shaped region.

The multiple a-plane modified regions 28 may each form a notch by cutting out the side surface 5A. The multiple a-plane modified regions 28 may each form a recess recessed from the side surface 5A toward the a-axis direction. The multiple a-plane modified regions 28 may each be formed in a dot shape according to their length in the normal direction Z and their width in the m-axis direction.

In the m-axis direction, the pitch PR between the central portions of adjacent a-plane modified portions 28 may be greater than 0 μm and less than 20 μm. The pitch PR may be greater than 0 μm and less than 5 μm, greater than 5 μm and less than 10 μm, greater than 10 μm and less than 15 μm, or greater than 15 μm and less than 20 μm.

In the m-axis direction, the width WR of each a-plane modified portion 28 may be greater than 0 μm and less than or equal to 20 μm. The width WR may be greater than 0 μm and less than or equal to 5 μm, greater than or equal to 5 μm and less than or equal to 10 μm, greater than or equal to 10 μm and less than or equal to 15 μm, or greater than or equal to 15 μm and less than or equal to 20 μm.

Reforming line 22C has the same structure as reforming line 22A, except that it is formed on side 5C. The description of reforming line 22A applies mutatis mutandis to the description of reforming line 22C, with "side 5A" read as "side 5C."

Referring to FIG. 6, the modification line 22D includes a plurality of m-plane modified portions 29 (modified portions). In other words, the modification line 22D is formed by an assembly of a plurality of m-plane modified portions 29. The plurality of m-plane modified portions 29 are portions in which the SiC single crystal exposed from the side surface 5D has been modified to have properties different from those of the SiC single crystal. The area around each m-plane modified portion 29 on the side surface 5D may be modified to have properties different from those of the SiC single crystal.

Each of the multiple m-plane modified portions 29 includes one end 29a located on the first main surface 3 side, the other end 29b located on the second main surface 4 side, and a connection portion 29c connecting the one end 29a and the other end 29b.

The multiple m-plane modified regions 29 are each formed in a line extending in the normal direction Z. As a result, the multiple m-plane modified regions 29 are formed in a striped pattern as a whole. The multiple m-plane modified regions 29 may include multiple m-plane modified regions 29 formed in a tapered shape in which the width in the a-axis direction narrows from one end 29a side to the other end 29b side.

The multiple m-plane modified regions 29 are formed at intervals in the a-axis direction so as to face each other in the a-axis direction. The multiple m-plane modified regions 29 may overlap each other in the a-axis direction. A band-shaped region extending in the a-axis direction is formed by a line connecting one end 29a of the multiple m-plane modified regions 29 and a line connecting the other end 29b of the multiple m-plane modified regions 29. The modification line 22D is formed by this band-shaped region.

The multiple m-plane modified regions 29 may each form a notch by cutting out the side surface 5D. The multiple m-plane modified regions 29 may each form a recess recessed from the side surface 5D toward the m-axis direction. The multiple m-plane modified regions 29 may each be formed in a dot shape according to the length in the normal direction Z and the width in the a-axis direction.

In the a-axis direction, the pitch PR between the central portions of adjacent m-plane modified portions 29 may be 0 μm or more and 20 μm or less. The pitch PR may be 0 μm or more and 5 μm or less, 5 μm or more and 10 μm or less, 10 μm or more and 15 μm or less, or 15 μm or more and 20 μm or less.

In the a-axis direction, the width WR of each m-plane modified portion 29 may be greater than 0 μm and less than or equal to 20 μm. The width WR may be greater than 0 μm and less than or equal to 5 μm, greater than or equal to 5 μm and less than or equal to 10 μm, greater than or equal to 10 μm and less than or equal to 15 μm, or greater than or equal to 15 μm and less than or equal to 20 μm.

Reforming line 22B has a structure similar to that of reforming line 22D, except that it is formed on side 5B. The description of reforming line 22D applies mutatis mutandis to the description of reforming line 22B, with "side 5D" read as "side 5B."

Referring to FIG. 8, an n-type diode region 35 is formed in the surface layer of the first main surface 3 of the SiC semiconductor layer 2 in the active region 8. In this embodiment, the diode region 35 is formed in the center of the first main surface 3 of the SiC semiconductor layer 2. In this embodiment, the diode region 35 is set to have a quadrangle shape having four sides parallel to the side surfaces 5A to 5D of the SiC semiconductor layer 2 in a plan view.

The n-type impurity concentration of the diode region 35 may be equal to or greater than the n-type impurity concentration of the SiC epitaxial layer 7. In this embodiment, the diode region 35 is formed by utilizing a portion of the SiC epitaxial layer 7. The n-type impurity concentration of the diode region 35 is equal to the n-type impurity concentration of the SiC epitaxial layer 7. The diode region 35 may be formed by introducing an n-type impurity into the surface portion of the SiC epitaxial layer 7.

In the outer region 9, a p ⁺ type guard region 36 is formed in a surface layer portion of the first main surface 3 of the SiC semiconductor layer 2. The guard region 36 is formed in a strip shape extending along the diode region 35 in a plan view.

More specifically, the guard region 36 is formed in an endless shape (for example, a square ring, a square ring with chamfered corners, or a circular ring) surrounding the diode region 35 in a plan view. In this way, the guard region 36 is formed as a guard ring region. In this embodiment, the diode region 35 is defined by the guard region 36. In addition, the active region 8 is defined by the guard region 36.

The p-type impurity in the guard region 36 may not be activated. In this case, the guard region 36 is formed as a non-semiconductor region. The p-type impurity in the guard region 36 may be activated. In this case, the guard region 36 is formed as a p-type semiconductor region.

The aforementioned main surface insulating layer 10 is formed on the first main surface 3 of the SiC semiconductor layer 2. A diode opening 37 that exposes the diode region 35 is formed in the main surface insulating layer 10. The diode opening 37 exposes not only the diode region 35 but also the inner edge of the guard region 36. The diode opening 37 is formed in a quadrangle shape having four sides parallel to the side surfaces 5A to 5D of the SiC semiconductor layer 2 in a plan view.

The first principal surface electrode layer 12 described above is formed on the principal surface insulating layer 10. The first principal surface electrode layer 12 extends from above the insulating layer into the diode opening 37. The first principal surface electrode layer 12 is electrically connected to the diode region 35 within the diode opening 37.

More specifically, the first principal surface electrode layer 12 forms a Schottky junction with the diode region 35. This forms a Schottky barrier diode D with the first principal surface electrode layer 12 as the anode and the diode region 35 as the cathode. The aforementioned passivation layer 13 and resin layer 16 are formed on the principal surface insulating layer 10.

Figure 9 is a perspective view showing a SiC semiconductor wafer 41 used in the manufacture of the SiC semiconductor device 1 shown in Figure 3.

The SiC semiconductor wafer 41 is a base member for the SiC semiconductor substrate 6. The SiC semiconductor wafer 41 includes a 4H-SiC single crystal, which is an example of a SiC single crystal made of a hexagonal crystal. In this form, the SiC semiconductor wafer 41 has an n-type impurity concentration that corresponds to the n-type impurity concentration of the SiC semiconductor substrate 6.

The SiC semiconductor wafer 41 is formed in a plate or disk shape. The SiC semiconductor wafer 41 may be formed in a disk shape. The SiC semiconductor wafer 41 has a first wafer main surface 42 on one side, a second wafer main surface 43 on the other side, and a wafer side surface 44 connecting the first wafer main surface 42 and the second wafer main surface 43.

The thickness TW of the SiC semiconductor wafer 41 exceeds the thickness TS of the SiC semiconductor substrate 6 (TS<TW). The thickness TW of the SiC semiconductor wafer 41 is adjusted to the thickness TS of the SiC semiconductor substrate 6 by grinding.

The thickness TW may be more than 150 μm and not more than 750 μm. The thickness TW may be more than 150 μm and not more than 300 μm, 300 μm or more and not more than 450 μm, 450 μm or more and not more than 600 μm, or 600 μm or more and not more than 750 μm. In consideration of the grinding time of the SiC semiconductor wafer 41, it is preferable that the thickness TW is more than 150 μm and not more than 500 μm. The thickness TW is typically more than 300 μm and not more than 450 μm.

In this embodiment, the first wafer main surface 42 and the second wafer main surface 43 face the c-plane of the SiC single crystal. The first wafer main surface 42 faces the (0001) plane (silicon plane). The second wafer main surface 43 faces the (000-1) plane (carbon plane) of the SiC single crystal.

The first wafer main surface 42 and the second wafer main surface 43 have an off-angle θ that is inclined at an angle of 10° or less in the [11-20] direction with respect to the c-plane of the SiC single crystal. The normal direction Z of the first wafer main surface 42 is inclined by the off-angle θ with respect to the c-axis ([0001] direction) of the SiC single crystal.

The off angle θ may be 0° or more and 5.0° or less. The off angle θ may be set in the range of 0° or more and 1.0° or less, 1.0° or more and 1.5° or less, 1.5° or more and 2.0° or less, 2.0° or more and 2.5° or less, 2.5° or more and 3.0° or less, 3.0° or more and 3.5° or less, 3.5° or more and 4.0° or less, 4.0° or more and 4.5° or less, or 4.5° or more and 5.0° or less. It is preferable that the off angle θ is greater than 0°. The off angle θ may be less than 4.0°.

The off angle θ may be set in the range of 3.0° to 4.5°. In this case, it is preferable that the off angle θ is set in the range of 3.0° to 3.5° or 3.5° to 4.0°.

The off angle θ may be set in the range of 1.5° to 3.0°. In this case, it is preferable that the off angle θ is set in the range of 1.5° to 2.0° or 2.0° to 2.5°.

The SiC semiconductor wafer 41 includes a first wafer corner 45 that connects the first wafer main surface 42 and the wafer side surface 44, and a second wafer corner 46 that connects the second wafer main surface 43 and the wafer side surface 44. The first wafer corner 45 has a first chamfered portion 47 that slopes downward from the first wafer main surface 42 toward the wafer side surface 44. The second wafer corner 46 has a second chamfered portion 48 that slopes downward from the second wafer main surface 43 toward the wafer side surface 44.

The first chamfered portion 47 may be formed in a convex curved shape. The second chamfered portion 48 may be formed in a convex curved shape. The first chamfered portion 47 and the second chamfered portion 48 suppress cracks in the SiC semiconductor wafer 41.

An orientation flat 49 is formed on the wafer side surface 44 of the SiC semiconductor wafer 41 as an example of a mark indicating the crystal orientation of the SiC single crystal. The orientation flat 49 is a notch formed on the wafer side surface 44 of the SiC semiconductor wafer 41. In this embodiment, the orientation flat 49 extends linearly along the a-axis direction ([11-20] direction) of the SiC single crystal.

The wafer side surface 44 of the SiC semiconductor wafer 41 may have a plurality of (e.g., two) orientation flats 49 formed thereon that indicate a crystal orientation. The plurality of (e.g., two) orientation flats 49 may include a first orientation flat and a second orientation flat.

The first orientation flat may be a notch that extends linearly along the a-axis direction ([11-20] direction) of the SiC single crystal. The second orientation flat may be a notch that extends linearly along the m-axis direction ([1-100] direction) of the SiC single crystal.

A plurality of device formation regions 51 each corresponding to a SiC semiconductor device 1 are set on the first wafer main surface 42 of the SiC semiconductor wafer 41. The device formation regions 51 are set in a matrix array spaced apart in the m-axis direction ([1-100] direction) and the a-axis direction ([11-20] direction).

Each device formation region 51 has four sides 52A, 52B, 52C, and 52D aligned along the crystal orientation of the SiC single crystal. The four sides 52A to 52D correspond to the four side surfaces 5A to 5D of the SiC semiconductor layer 2, respectively. The four sides 52A to 52D include two sides 52A and 52C aligned along the m-axis direction ([1-100] direction) and two sides 52B and 52D aligned along the a-axis direction ([11-20] direction).

The multiple device formation regions 51 are each partitioned by a lattice-shaped planned cutting lines 53 extending along the m-axis direction ([1-100] direction) and the a-axis direction ([11-20] direction). The planned cutting lines 53 include multiple first planned cutting lines 54 and multiple second planned cutting lines 55.

The multiple first cutting lines 54 each extend along the m-axis direction (the [1-100] direction). The multiple second cutting lines 55 each extend along the a-axis direction (the [11-20] direction). After the predetermined structures are fabricated in the multiple device formation regions 51, the SiC semiconductor wafer 41 is cut along the cutting lines 53 to cut out multiple SiC semiconductor devices 1.

Figures 10A to 10M are cross-sectional views showing an example of a method for manufacturing the SiC semiconductor device 1 shown in Figure 3. For ease of explanation, Figures 10A to 10M show only the regions in which three SiC semiconductor devices 1 are formed, and omit illustration of other regions.

Referring to FIG. 10A, in manufacturing the SiC semiconductor device 1, first, a SiC semiconductor wafer 41 is prepared (also see FIG. 9). Next, an n-type SiC epitaxial layer 7 is formed on the first wafer main surface 42 of the SiC semiconductor wafer 41.

In the process of forming the SiC epitaxial layer 7, SiC is epitaxially grown from the first wafer main surface 42 of the SiC semiconductor wafer 41. The thickness TE of the SiC epitaxial layer 7 may be 1 μm or more and 50 μm or less.

This results in the formation of a SiC semiconductor wafer structure 61 including a SiC semiconductor wafer 41 and a SiC epitaxial layer 7. The SiC semiconductor wafer structure 61 includes a first main surface 62 and a second main surface 63.

The first main surface 62 and the second main surface 63 of the SiC semiconductor wafer structure 61 correspond to the first main surface 3 and the second main surface 4 of the SiC semiconductor layer 2, respectively. The thickness TWS of the SiC semiconductor wafer structure 61 may be greater than 150 μm and less than or equal to 800 μm. The thickness TWS is preferably greater than 150 μm and less than or equal to 550 μm.

10B , p ⁺ type guard region 36 is formed on first main surface 62 of SiC semiconductor wafer structure 61. The step of forming guard region 36 includes a step of selectively introducing p-type impurities into a surface layer portion of first main surface 62 of SiC semiconductor wafer structure 61 via an ion implantation mask (not shown). More specifically, guard region 36 is formed in a surface layer portion of SiC epitaxial layer 7.

The guard region 36 defines an active region 8 and an outer region 9 in the SiC semiconductor wafer structure 61. An n-type diode region 35 is defined in the region surrounded by the guard region 36 (active region 8).

The diode region 35 may be formed by selectively introducing n-type impurities into a surface layer of the first main surface 62 of the SiC semiconductor wafer structure 61 through an ion implantation mask (not shown).

10C , a main surface insulating layer 10 is formed on a first main surface 62 of the SiC semiconductor wafer structure 61. The main surface insulating layer 10 includes silicon oxide (SiO ₂ ). The main surface insulating layer 10 may be formed by a chemical vapor deposition (CVD) method or an oxidation treatment method (for example, a thermal oxidation treatment method).

Next, referring to FIG. 10D, a mask 64 having a predetermined pattern is formed on the main surface insulating layer 10. The mask 64 has a plurality of openings 65. The plurality of openings 65 each exposes an area in the main surface insulating layer 10 where the diode opening 37 is to be formed.

Next, unnecessary portions of the main surface insulating layer 10 are removed by etching through the mask 64. This forms a diode opening 37 in the main surface insulating layer 10. After the diode opening 37 is formed, the mask 64 is removed.

Next, referring to FIG. 10E, a base electrode layer 66 that serves as the base of the first principal surface electrode layer 12 is formed on the first principal surface 62 of the SiC semiconductor wafer structure 61. The base electrode layer 66 is formed over the entire first principal surface 62 of the SiC semiconductor wafer structure 61, and covers the principal surface insulating layer 10. The first principal surface electrode layer 12 may be formed by a vapor deposition method, a sputtering method, or a plating method.

Next, referring to FIG. 10F, a mask 67 having a predetermined pattern is formed on the base electrode layer 66. The mask 67 has openings 68 that expose areas of the base electrode layer 66 other than the areas where the first principal surface electrode layer 12 is to be formed.

Next, unnecessary portions of the base electrode layer 66 are removed by etching through the mask 67. This divides the base electrode layer 66 into a plurality of first principal surface electrode layers 12. After the first principal surface electrode layers 12 are formed, the mask 67 is removed.

Next, referring to FIG. 10G, a passivation layer 13 is formed on the first main surface 62 of the SiC semiconductor wafer structure 61. The passivation layer 13 includes silicon nitride (SiN). The passivation layer 13 may be formed by a CVD method.

Next, referring to FIG. 10H, a resin layer 16 is applied onto the passivation layer 13. The resin layer 16 collectively covers the active region 8 and the outer region 9. The resin layer 16 may contain polybenzoxazole, which is an example of a positive-type photosensitive resin.

Next, referring to FIG. 10I, the resin layer 16 is selectively exposed to light and then developed. As a result, pad openings 18 are formed in the resin layer 16. Also, dicing streets 69 are defined in the resin layer 16 along the intended cutting lines 53 (sides 52A to 52D of each device formation area 51).

Next, unnecessary portions of the passivation layer 13 are removed. The unnecessary portions of the passivation layer 13 may be removed by an etching method via the resin layer 16. This forms a subpad opening 15 in the passivation layer 13. Also, a dicing street 69 is defined in the passivation layer 13 along the intended cutting line 53.

In this embodiment, the process of removing unnecessary portions of the passivation layer 13 using the resin layer 16 has been described. However, the resin layer 16 and the pad opening 18 may be formed after the subpad opening 15 is formed in the passivation layer 13.

In this case, prior to the process of forming the resin layer 16, unnecessary portions of the passivation layer 13 are removed by etching through a mask to form the subpad opening 15. This process allows the passivation layer 13 to be formed into any shape.

Next, referring to FIG. 10J, the second main surface 63 of the SiC semiconductor wafer structure 61 (the second wafer main surface 43 of the SiC semiconductor wafer 41) is ground. This causes the SiC semiconductor wafer structure 61 (SiC semiconductor wafer 41) to be thinned. In addition, grinding marks are formed on the second main surface 63 of the SiC semiconductor wafer structure 61.

The SiC semiconductor wafer structure 61 is ground to a thickness TWS corresponding to the thickness TL of the SiC semiconductor layer 2. The SiC semiconductor wafer structure 61 may be ground to a thickness TWS of 40 μm or more and 200 μm or less.

That is, the SiC semiconductor wafer 41 is ground to a thickness TW corresponding to the thickness TS of the SiC semiconductor substrate 6. The SiC semiconductor wafer 41 may be ground to a thickness TW of 40 μm or more and 150 μm or less.

Next, referring to FIG. 10K, a plurality of modification lines 70 (modification layers) are formed, which serve as the base for the modification lines 22A to 22D. In the process of forming the modification lines 70, a pulsed laser beam is irradiated from a laser beam irradiation device 71 toward the SiC semiconductor wafer structure 61.

In this embodiment, the laser light is irradiated onto the SiC semiconductor wafer structure 61 from the first main surface 62 side of the SiC semiconductor wafer structure 61 through the main surface insulating layer 10. The laser light may be irradiated directly onto the SiC semiconductor wafer structure 61 from the second main surface 63 side of the SiC semiconductor wafer structure 61.

The focal point of the laser light is set midway through the thickness of the SiC semiconductor wafer structure 61. The irradiation position of the laser light on the SiC semiconductor wafer structure 61 is moved along the intended cutting lines 53 (the four sides 52A to 52D of each device formation area 51).

More specifically, the irradiation position of the laser light on the SiC semiconductor wafer structure 61 is moved along the first planned cutting line 54. Furthermore, the irradiation position of the laser light on the SiC semiconductor wafer structure 61 is moved along the second planned cutting line 55.

As a result, multiple modification lines 70 are formed in the middle of the thickness direction of the SiC semiconductor wafer structure 61, extending along the intended cutting lines 53 (the four sides 52A-52D of each device formation region 51) and modifying the crystalline state of the SiC single crystal to have properties different from those in other regions.

The two modification lines 70 along sides 52A and 52C of the device formation region 51 each include an a-plane modification portion 28. The two modification lines 70 along sides 52B and 52D of the device formation region 51 each include an m-plane modification portion 29.

The multiple modification lines 70 are formed layer by layer in a one-to-one correspondence with the four sides 52A-52D of each device formation region 51. The multiple modification lines 70 are also laser processing marks formed in the middle of the thickness direction of the SiC semiconductor wafer structure 61. More specifically, the a-plane modified portion 28 and the m-plane modified portion 29 included in the modification line 70 are laser processing marks.

The focal point of the laser light, the laser energy, the pulse duty ratio, the irradiation speed, etc. are determined to arbitrary values depending on the position, size, shape, thickness, etc. of the modification line 70 (modification lines 22A to 22D) to be formed.

Next, referring to FIG. 10L, a second principal surface electrode layer 19 is formed on the second principal surface 63 of the SiC semiconductor wafer structure 61. The second principal surface electrode layer 19 may be formed by a vapor deposition method, a sputtering method, or a plating method.

Prior to the process of forming the second principal surface electrode layer 19, an annealing process may be performed on the second principal surface 63 (ground surface) of the SiC semiconductor wafer structure 61. The annealing process may be performed by a laser annealing process method using laser light.

The laser annealing method modifies the SiC single crystal in the surface layer of the second main surface 63 of the SiC semiconductor wafer structure 61 to form a Si amorphous layer. In this case, a SiC semiconductor device 1 having a Si amorphous layer in the surface layer of the second main surface 4 of the SiC semiconductor layer 2 is manufactured. Grinding marks and a Si amorphous layer coexist on the second main surface 4 of the SiC semiconductor layer 2. The laser annealing method can improve the ohmic properties of the second main surface electrode layer 19 with respect to the second main surface 4 of the SiC semiconductor layer 2.

Next, referring to FIG. 10M, a plurality of SiC semiconductor devices 1 are cut out from the SiC semiconductor wafer structure 61. In this process, a tape-shaped support member 73 is attached to the second main surface 63 side of the SiC semiconductor wafer structure 61.

Next, an external force is applied to the intended cutting line 53 from the second main surface 63 side of the SiC semiconductor wafer structure 61 via the support member 73. The external force to the intended cutting line 53 may be applied by a pressing member such as a blade.

In another embodiment, a support member 73 may be attached to the first main surface 62 side of the SiC semiconductor wafer structure 61. In this case, an external force may be applied to the intended cutting line 53 from the first main surface 62 side of the SiC semiconductor wafer structure 61 via the support member 73. The external force may be applied by a pressing member such as a blade.

In yet another embodiment, an elastic support member 73 may be attached to the first main surface 62 side or the second main surface 63 side of the SiC semiconductor wafer structure 61. In this case, the SiC semiconductor wafer structure 61 may be cleaved by stretching the elastic support member 73 in the m-axis direction and the a-axis direction.

When using the support member 73 to cleave the SiC semiconductor wafer structure 61, it is preferable that the support member 73 be attached to the second main surface 63 side of the SiC semiconductor wafer structure 61, which has fewer obstacles.

In this way, the SiC semiconductor wafer structure 61 is cleaved along the intended cutting lines 53 starting from the modification lines 70 (modification lines 22A to 22D), and multiple SiC semiconductor devices 1 are cut out from one SiC semiconductor wafer structure 61 (SiC semiconductor wafer 41).

The portion of the modification line 70 that runs along side 52A of each device formation area 51 becomes modification line 22A. The portion of the modification line 70 that runs along side 52B of each device formation area 51 becomes modification line 22B. The portion of the modification line 70 that runs along side 52C of each device formation area 51 becomes modification line 22C. The portion of the modification line 70 that runs along side 52D of each device formation area 51 becomes modification line 22D. The SiC semiconductor device 1 is manufactured through the processes including those described above.

In this embodiment, the grinding process (FIG. 10J) of the SiC semiconductor wafer structure 61 is performed prior to the forming process (FIG. 10K) of the modification line 70 (modification lines 22A-22D). However, the grinding process (FIG. 10J) of the SiC semiconductor wafer structure 61 can be performed at any time after the preparing process (FIG. 10A) of the SiC semiconductor wafer 41 and before the forming process (FIG. 10L) of the second principal surface electrode layer 19.

For example, the grinding process of the SiC semiconductor wafer structure 61 (FIG. 10J) may be performed prior to the formation process of the SiC epitaxial layer 7 (FIG. 10A). Also, the grinding process of the SiC semiconductor wafer structure 61 (FIG. 10J) may be performed after the formation process of the modification line 70 (modification lines 22A-22D) (FIG. 10K).

The grinding process (FIG. 10J) of the SiC semiconductor wafer structure 61 may be performed in multiple steps at any timing after the preparation process (FIG. 10A) of the SiC semiconductor wafer 41 and before the formation process (FIG. 10K) of the modification line 70 (modification lines 22A-22D). The grinding process (FIG. 10J) of the SiC semiconductor wafer structure 61 may be performed in multiple steps at any timing after the preparation process (FIG. 10A) of the SiC semiconductor wafer 41 and before the formation process (FIG. 10L) of the second main surface electrode layer 19.

Figure 11 is a perspective view showing a semiconductor package 74 incorporating the SiC semiconductor device 1 shown in Figure 3, with the sealing resin 79 seen through.

Referring to FIG. 11, the semiconductor package 74 in this embodiment is a so-called TO-220 type. The semiconductor package 74 includes a SiC semiconductor device 1, a pad portion 75, a heat sink 76, a plurality of terminals 77 (two in this embodiment), a plurality of conductive wires 78 (two in this embodiment), and a sealing resin 79. The pad portion 75, the heat sink 76, and the plurality of terminals 77 form a lead frame as an example of an object to be connected.

The pad portion 75 includes a metal plate. The pad portion 75 may include iron, gold, silver, copper, aluminum, etc. The pad portion 75 is formed in a quadrangular shape in a plan view. The pad portion 75 has a planar area equal to or greater than the planar area of the SiC semiconductor device 1. The SiC semiconductor device 1 is disposed on the pad portion 75.

The second principal surface electrode layer 19 of the SiC semiconductor device 1 is electrically connected to the pad portion 75 via a conductive bonding material 80. The conductive bonding material 80 is interposed in the region between the second principal surface electrode layer 19 and the pad portion 75.

The conductive bonding material 80 may be a metallic paste or solder. The metallic paste may be a conductive paste containing Au (gold), Ag (silver) or Cu (copper). The conductive bonding material 80 is preferably made of solder. The solder may be a lead-free solder. The solder may contain at least one of SnAgCu, SnZnBi, SnCu, SnCuNi or SnSbNi.

The heat sink 76 is connected to one side of the pad portion 75. In this embodiment, the pad portion 75 and the heat sink 76 are formed from a single metal plate. A through hole 76a is formed in the heat sink 76. The through hole 76a is formed in a circular shape.

The multiple terminals 77 are arranged along the side of the pad portion 75 opposite the heat sink 76. Each of the multiple terminals 77 includes a metal plate. The terminals 77 may include iron, gold, silver, copper, aluminum, etc.

The multiple terminals 77 include a first terminal 77A and a second terminal 77B. The first terminal 77A and the second terminal 77B are arranged at intervals along the side of the pad portion 75 opposite the heat sink 76. The first terminal 77A and the second terminal 77B extend in a strip shape in a direction perpendicular to the direction of their arrangement.

The multiple conductors 78 may be bonding wires or the like. The multiple conductors 78 include conductors 78A and conductors 78B. The conductor 78A is electrically connected to the first terminal 77A and the first principal surface electrode layer 12 of the SiC semiconductor device 1. As a result, the first terminal 77A is electrically connected to the first principal surface electrode layer 12 of the SiC semiconductor device 1 via the conductor 78A.

The conductor 78B is electrically connected to the second terminal 77B and the pad portion 75. As a result, the second terminal 77B is electrically connected to the second main surface electrode layer 19 of the SiC semiconductor device 1 via the conductor 78B. The second terminal 77B may be formed integrally with the pad portion 75.

The sealing resin 79 seals the SiC semiconductor device 1, the pad portion 75, and the multiple conductive wires 78 so as to expose the heat sink 76 and a portion of the multiple terminals 77. The sealing resin 79 is formed in a rectangular parallelepiped shape.

The form of the semiconductor package 74 is not limited to TO-220. The semiconductor package 74 may be SOP (Small Outline Package), QFN (Quad For Non Lead Package), DFP (Dual Flat Package), DIP (Dual Inline Package), QFP (Quad Flat Package), SIP (Single Inline Package), SOJ (Small Outline J-leaded Package), or various other similar forms.

As described above, the SiC semiconductor device 1 includes a plurality of reforming lines 22A-22D formed one layer on each of the side surfaces 5A-5D of the SiC semiconductor layer 2. According to the SiC semiconductor device 1, only one reforming line 22A-22D is formed on each of the side surfaces 5A-5D of the SiC semiconductor layer 2. This reduces the effect of the reforming lines 22A-22D on the SiC semiconductor layer 2.

Examples of the effects of the reforming line on the SiC semiconductor layer 2 include fluctuations in the electrical characteristics of the SiC semiconductor layer 2 caused by the reforming line and the occurrence of cracks in the SiC semiconductor layer 2 originating from the reforming line.

Fluctuations in leakage current characteristics are exemplified as fluctuations in the electrical characteristics of the SiC semiconductor layer 2 caused by the reforming line. The SiC semiconductor device may be encapsulated by an encapsulation resin 79, as shown in FIG. 11.

In this case, it is conceivable that mobile ions in the sealing resin 79 may enter the SiC semiconductor layer 2 through the modification lines. In a structure in which multiple modification lines are formed at intervals along the normal direction Z over the entire area of each of the side surfaces 5A to 5D, the risk of a current path being formed due to such an external structure increases.

In addition, in a structure in which multiple reforming lines are formed along the normal direction Z over the entire area of each side surface 5A-5D of the SiC semiconductor layer 2, the risk of cracks occurring in the SiC semiconductor layer 2 also increases. Therefore, by limiting the area in which the reforming lines 22A-22D are formed, as in the SiC semiconductor device 1, it is possible to suppress fluctuations in the electrical characteristics of the SiC semiconductor layer 2 and the occurrence of cracks.

In addition, according to the SiC semiconductor device 1, since a thinning process is performed on the SiC semiconductor wafer structure 61 (SiC semiconductor wafer 41), the SiC semiconductor wafer structure 61 can be appropriately cleaved by one layer of modification line 70 (modification lines 22A to 22D).

In other words, the thinned SiC semiconductor wafer structure 61 (SiC semiconductor wafer 41) can be properly cleaved without forming multiple modification lines 70 (modification lines 22A to 22D) at intervals in the normal direction Z.

In this case, the second main surface 4 of the SiC semiconductor layer 2 is a ground surface. The SiC semiconductor device 1 preferably includes a SiC semiconductor layer 2 having a thickness TL of 40 μm or more and 200 μm or less. The SiC semiconductor layer 2 having such a thickness TL can be appropriately cut out from the SiC semiconductor wafer structure 61 (SiC semiconductor wafer 41).

In the SiC semiconductor layer 2, the thickness TS of the SiC semiconductor substrate 6 may be 40 μm or more and 150 μm or less. In the SiC semiconductor layer 2, the thickness TE of the SiC epitaxial layer 7 may be 1 μm or more and 50 μm or less. Thinning the SiC semiconductor layer 2 is also effective in reducing the resistance value.

In addition, according to the SiC semiconductor device 1, the reforming lines 22A-22D are formed at intervals from the first main surface 3 to the second main surface 4 of the SiC semiconductor layer 2. Stress tends to concentrate at the corners connecting the first main surface 3 and the side surfaces 5A-5D of the SiC semiconductor layer 2.

Therefore, by forming the modification lines 22A-22D at intervals from the corners connecting the first main surface 3 and the side surfaces 5A-5D of the SiC semiconductor layer 2, it is possible to appropriately suppress the occurrence of cracks at the corners of the SiC semiconductor layer 2.

In particular, according to the SiC semiconductor device 1, the reforming lines 22A-22D are formed on the SiC semiconductor substrate 6, avoiding the SiC epitaxial layer 7. In other words, the reforming lines 22A-22D expose the SiC epitaxial layer 7 in which the main portion of the semiconductor element (in this embodiment, the Schottky barrier diode D) is formed. This also appropriately reduces the impact of the reforming lines 22A-22D on the semiconductor element.

In addition, according to the SiC semiconductor device 1, the reforming lines 22A-22D are formed at intervals from the second main surface 4 to the first main surface 3 of the SiC semiconductor layer 2. Stress tends to concentrate at the corners connecting the second main surface 4 and the side surfaces 5A-5D of the SiC semiconductor layer 2.

Therefore, by forming the reforming lines 22A-22D at intervals from the corners connecting the second main surface 4 and the side surfaces 5A-5D of the SiC semiconductor layer 2, it is possible to appropriately suppress the occurrence of cracks at the corners of the SiC semiconductor layer 2.

The SiC semiconductor device 1 also includes a main surface insulating layer 10 and a first main surface electrode layer 12 formed on the first main surface 3 of the SiC semiconductor layer 2. The main surface insulating layer 10 has insulating side surfaces 11A-11D that are continuous with the side surfaces 5A-5D of the SiC semiconductor layer 2.

The main surface insulating layer 10 enhances the insulation between the side surfaces 5A-5D of the SiC semiconductor layer 2 and the first main surface electrode layer 12 in a structure in which the reforming lines 22A-22D are formed. This enhances the stability of the electrical characteristics of the SiC semiconductor layer 2 in a structure in which the reforming lines 22A-22D are formed on the side surfaces 5A-5D of the SiC semiconductor layer 2.

Figure 12A is a perspective view showing the SiC semiconductor device 1 shown in Figure 3, and is a perspective view showing a second embodiment of the reforming lines 22A to 22D. In the following, structures corresponding to those described for the SiC semiconductor device 1 are given the same reference numerals and will not be described.

The reforming lines 22A-22D in the first embodiment are connected to each other at the corners that connect the side surfaces 5A-5D of the SiC semiconductor layer 2. In contrast, the reforming lines 22A-22D in the second embodiment are formed with a gap between each other at the corners that connect the side surfaces 5A-5D of the SiC semiconductor layer 2.

More specifically, the reforming line 22A and the reforming line 22B are formed at intervals from each other in the normal direction Z at the corner connecting the side 5A and the side 5B of the SiC semiconductor layer 2. The reforming line 22B and the reforming line 22C are formed at intervals from each other in the normal direction Z at the corner connecting the side 5B and the side 5C of the SiC semiconductor layer 2.

The reforming line 22C and the reforming line 22D are formed at intervals from each other in the normal direction Z at the corner connecting the side 5C and the side 5D of the SiC semiconductor layer 2. The reforming line 22D and the reforming line 22A are formed at intervals from each other in the normal direction Z at the corner connecting the side 5D and the side 5A of the SiC semiconductor layer 2.

Of course, at least one of the reforming lines 22A-22D may be formed at a distance from the other reforming lines 22A-22D at a corner that connects any of the side surfaces 5A-5D of the SiC semiconductor layer 2. Two or three of the reforming lines 22A-22D may be connected to each other at a corner that connects any of the side surfaces 5A-5D of the SiC semiconductor layer 2.

The reforming lines 22A to 22D according to the second embodiment are formed by adjusting the focusing area (focus) of the laser light during the process of forming the reforming lines 70 (the reforming lines 22A to 22D) (see also FIG. 10K). Even when the reforming lines 22A to 22D according to the second embodiment are formed, the same effect as when the reforming lines 22A to 22D according to the first embodiment are formed can be achieved.

Figure 12B is a perspective view showing the SiC semiconductor device 1 shown in Figure 3, and is a perspective view showing a third embodiment of the reforming lines 22A to 22D. In the following, structures corresponding to those described for the SiC semiconductor device 1 are given the same reference numerals and will not be described.

The reforming lines 22A to 22D according to the first embodiment are formed in a band shape extending linearly along the tangential direction of the first main surface 3 of the SiC semiconductor layer 2. In contrast, the reforming lines 22A to 22D according to the third embodiment are formed in a band shape extending in a downward inclination from the first main surface 3 to the second main surface 4 of the SiC semiconductor layer 2. More specifically, the reforming lines 22A to 22D according to the third embodiment each include a first end region 81, a second end region 82, and an inclined region 83.

The first end region 81 is located on the first main surface 3 side of the SiC semiconductor layer 2 near the corner of the SiC semiconductor layer 2. The second end region 82 is located on the second main surface 4 side of the SiC semiconductor layer 2 relative to the first end region 81 near the corner of the SiC semiconductor layer 2. The inclined region 83 slopes downward from the first main surface 3 toward the second main surface 4 in the region between the first end region 81 and the second end region 82.

A first end region 81 of the reforming line 22A and a first end region 81 of the reforming line 22B may be located at the corner connecting the side 5A and the side 5B of the SiC semiconductor layer 2. A second end region 82 of the reforming line 22A and a second end region 82 of the reforming line 22B may be located at the corner connecting the side 5A and the side 5B of the SiC semiconductor layer 2.

The first end region 81 of the reforming line 22A and the second end region 82 of the reforming line 22B may be located at the corner connecting the side 5A and the side 5B of the SiC semiconductor layer 2. The second end region 82 of the reforming line 22A and the first end region 81 of the reforming line 22B may be located at the corner connecting the side 5A and the side 5B of the SiC semiconductor layer 2.

The reforming line 22A and the reforming line 22B may be connected to each other at the corner that connects the side 5A and the side 5B of the SiC semiconductor layer 2, or may be formed with a gap between them.

A first end region 81 of the reforming line 22B and a first end region 81 of the reforming line 22C may be located at the corner connecting the side 5B and the side 5C of the SiC semiconductor layer 2. A second end region 82 of the reforming line 22B and a second end region 82 of the reforming line 22C may be located at the corner connecting the side 5B and the side 5C of the SiC semiconductor layer 2.

The first end region 81 of the reforming line 22B and the second end region 82 of the reforming line 22C may be located at the corner connecting the side 5B and the side 5C of the SiC semiconductor layer 2. The second end region 82 of the reforming line 22B and the first end region 81 of the reforming line 22C may be located at the corner connecting the side 5B and the side 5C of the SiC semiconductor layer 2.

The reforming line 22B and the reforming line 22C may be connected to each other at the corner that connects the side 5B and the side 5C of the SiC semiconductor layer 2, or may be formed with a gap between them.

A first end region 81 of the reforming line 22C and a first end region 81 of the reforming line 22D may be located at the corner connecting the side 5C and the side 5D of the SiC semiconductor layer 2. A second end region 82 of the reforming line 22C and a second end region 82 of the reforming line 22D may be located at the corner connecting the side 5C and the side 5D of the SiC semiconductor layer 2.

The first end region 81 of the reforming line 22C and the second end region 82 of the reforming line 22D may be located at the corner connecting the side 5C and the side 5D of the SiC semiconductor layer 2. The second end region 82 of the reforming line 22C and the first end region 81 of the reforming line 22D may be located at the corner connecting the side 5C and the side 5D of the SiC semiconductor layer 2.

The reforming line 22C and the reforming line 22D may be connected to each other at the corner that connects the side 5C and the side 5D of the SiC semiconductor layer 2, or may be formed with a gap between them.

A first end region 81 of the reforming line 22D and a first end region 81 of the reforming line 22A may be located at the corner connecting the side 5D and the side 5A of the SiC semiconductor layer 2. A second end region 82 of the reforming line 22D and a second end region 82 of the reforming line 22A may be located at the corner connecting the side 5D and the side 5A of the SiC semiconductor layer 2.

The first end region 81 of the reforming line 22D and the second end region 82 of the reforming line 22A may be located at the corner connecting the side 5D and the side 5A of the SiC semiconductor layer 2. The second end region 82 of the reforming line 22D and the first end region 81 of the reforming line 22A may be located at the corner connecting the side 5D and the side 5A of the SiC semiconductor layer 2.

The reforming line 22D and the reforming line 22A may be connected to each other at the corner connecting the side 5D and the side 5A of the SiC semiconductor layer 2, or may be formed with a gap between them.

The reforming lines 22A to 22D according to the third embodiment are formed by adjusting the focusing area (focus) of the laser light during the process of forming the reforming lines 70 (the reforming lines 22A to 22D) (see also FIG. 10K). Even when the reforming lines 22A to 22D according to the third embodiment are formed, the same effect as when the reforming lines 22A to 22D according to the first embodiment are formed can be achieved.

In particular, the modification lines 22A-22D according to the third embodiment can form cleavage origins in different regions in the thickness direction of the SiC semiconductor wafer structure 61 (SiC semiconductor wafer 41). This allows the SiC semiconductor wafer structure 61 to be properly cleaved even when the modification lines 22A-22D are formed from a single layer.

Figure 12C is a perspective view showing the SiC semiconductor device 1 shown in Figure 3, and is a perspective view showing a fourth embodiment of the reforming lines 22A to 22D. In the following, structures corresponding to those described for the SiC semiconductor device 1 are given the same reference numerals and will not be described.

The reforming lines 22A to 22D according to the first embodiment are formed in a band shape extending linearly along the tangential direction of the first main surface 3 of the SiC semiconductor layer 2. In contrast, the reforming lines 22A to 22D according to the fourth embodiment are formed in a band shape extending in a curved (curved) manner, sloping downward from the first main surface 3 to the second main surface 4 of the SiC semiconductor layer 2. More specifically, the reforming lines 22A to 22D according to the fourth embodiment each include a first end region 84, a second end region 85, and a curved region 86.

The first end region 84 is located on the first main surface 3 side of the SiC semiconductor layer 2 near the corner of the SiC semiconductor layer 2. The second end region 85 is located on the second main surface 4 side of the SiC semiconductor layer 2 relative to the first end region 84 near the corner of the SiC semiconductor layer 2.

The curved region 86 slopes downward in a concave curve from the first main surface 3 toward the second main surface 4, connecting the first end region 84 and the second end region 85. The curved region 86 may also slope downward in a convex curve from the second main surface 4 toward the first main surface 3.

A first end region 84 of the reforming line 22A and a first end region 84 of the reforming line 22B may be located at the corner connecting the side 5A and the side 5B of the SiC semiconductor layer 2. A second end region 85 of the reforming line 22A and a second end region 85 of the reforming line 22B may be located at the corner connecting the side 5A and the side 5B of the SiC semiconductor layer 2.

The first end region 84 of the reforming line 22A and the second end region 85 of the reforming line 22B may be located at the corner connecting the side 5A and the side 5B of the SiC semiconductor layer 2. The second end region 85 of the reforming line 22A and the first end region 84 of the reforming line 22B may be located at the corner connecting the side 5A and the side 5B of the SiC semiconductor layer 2.

The reforming line 22A and the reforming line 22B may be connected to each other at the corner that connects the side 5A and the side 5B of the SiC semiconductor layer 2, or may be formed with a gap between them.

The first end region 84 of the reforming line 22B and the first end region 84 of the reforming line 22C may be located at the corner connecting the side 5B and the side 5C of the SiC semiconductor layer 2. The second end region 85 of the reforming line 22B and the second end region 85 of the reforming line 22C may be located at the corner connecting the side 5B and the side 5C of the SiC semiconductor layer 2.

The first end region 84 of the reforming line 22B and the second end region 85 of the reforming line 22C may be located at the corner connecting the side 5B and the side 5C of the SiC semiconductor layer 2. The second end region 85 of the reforming line 22B and the first end region 84 of the reforming line 22C may be located at the corner connecting the side 5B and the side 5C of the SiC semiconductor layer 2.

The reforming line 22B and the reforming line 22C may be connected to each other at the corner that connects the side 5B and the side 5C of the SiC semiconductor layer 2, or may be formed with a gap between them.

The first end region 84 of the reforming line 22C and the first end region 84 of the reforming line 22D may be located at the corner connecting the side 5C and the side 5D of the SiC semiconductor layer 2. The second end region 85 of the reforming line 22C and the second end region 85 of the reforming line 22D may be located at the corner connecting the side 5C and the side 5D of the SiC semiconductor layer 2.

The first end region 84 of the reforming line 22C and the second end region 85 of the reforming line 22D may be located at the corner connecting the side 5C and the side 5D of the SiC semiconductor layer 2. The second end region 85 of the reforming line 22C and the first end region 84 of the reforming line 22D may be located at the corner connecting the side 5C and the side 5D of the SiC semiconductor layer 2.

The reforming line 22C and the reforming line 22D may be connected to each other at the corner that connects the side 5C and the side 5D of the SiC semiconductor layer 2, or may be formed with a gap between them.

A first end region 84 of the reforming line 22D and a first end region 84 of the reforming line 22A may be located at the corner connecting the side 5D and the side 5A of the SiC semiconductor layer 2. A second end region 85 of the reforming line 22D and a second end region 85 of the reforming line 22A may be located at the corner connecting the side 5D and the side 5A of the SiC semiconductor layer 2.

The first end region 84 of the reforming line 22D and the second end region 85 of the reforming line 22A may be located at the corner connecting the side 5D and the side 5A of the SiC semiconductor layer 2. The second end region 85 of the reforming line 22D and the first end region 84 of the reforming line 22A may be located at the corner connecting the side 5D and the side 5A of the SiC semiconductor layer 2.

The reforming line 22D and the reforming line 22A may be connected to each other at the corner connecting the side 5D and the side 5A of the SiC semiconductor layer 2, or may be formed with a gap between them.

The reforming lines 22A to 22D according to the fourth embodiment are formed by adjusting the focusing area (focus) of the laser light during the process of forming the reforming lines 70 (the reforming lines 22A to 22D) (see also FIG. 10K). Even when the reforming lines 22A to 22D according to the fourth embodiment are formed, the same effect as when the reforming lines 22A to 22D according to the first embodiment are formed can be achieved.

In particular, the reforming lines 22A-22D according to the fourth embodiment can form cleavage origins in different regions in the thickness direction of the SiC semiconductor wafer structure 61 (SiC semiconductor wafer 41). This allows the SiC semiconductor wafer structure 61 to be properly cleaved even when forming reforming lines 22A-22D consisting of a single layer.

Figure 12D is a perspective view showing the SiC semiconductor device 1 shown in Figure 3, and is a perspective view showing a fifth embodiment of the reforming lines 22A to 22D. In the following, structures corresponding to those described for the SiC semiconductor device 1 are given the same reference numerals and will not be described.

The reforming lines 22A-22D according to the first embodiment are formed in a band shape extending linearly along the tangential direction of the first main surface 3 of the SiC semiconductor layer 2. In contrast, the reforming lines 22A-22D according to the fifth embodiment are formed in a band shape extending in a meandering curve (curved shape) toward the first main surface 3 and the second main surface 4 of the SiC semiconductor layer 2. More specifically, the reforming lines 22A-22D according to the fifth embodiment each include a plurality of first regions 87, a plurality of second regions 88, and a plurality of connection regions 89.

The multiple first regions 87 are located in a region on the first main surface 3 side of the SiC semiconductor layer 2. The multiple second regions 88 are located in a region on the second main surface 4 side of the SiC semiconductor layer 2 relative to the multiple first regions 87. The multiple curved regions 86 each connect the corresponding first regions 87 and second regions 88.

The reforming line 22A and the reforming line 22B may be connected to each other at the corner that connects the side 5A and the side 5B of the SiC semiconductor layer 2, or may be formed with a gap between them.

The reforming line 22B and the reforming line 22C may be connected to each other at the corner that connects the side 5B and the side 5C of the SiC semiconductor layer 2, or may be formed with a gap between them.

The reforming line 22C and the reforming line 22D may be connected to each other at the corner that connects the side 5C and the side 5D of the SiC semiconductor layer 2, or may be formed with a gap between them.

The reforming line 22D and the reforming line 22A may be connected to each other at the corner connecting the side 5D and the side 5A of the SiC semiconductor layer 2, or may be formed with a gap between them.

The meandering period of the reforming lines 22A-22D is arbitrary. The reforming lines 22A-22D may each be formed as a strip extending in a concave curve from the first main surface 3 toward the second main surface 4. In this case, the reforming lines 22A-22D may each include two first regions 87, one second region 88, and two connection regions 89.

The reforming lines 22A-22D may each be formed as a strip extending in a convex curve from the second main surface 4 toward the first main surface 3. In this case, the reforming lines 22A-22D may each include one first region 87, two second regions 88, and two connection regions 89.

The reforming lines 22A to 22D according to the fifth embodiment are formed by adjusting the focusing area (focus) of the laser light during the process of forming the reforming lines 70 (the reforming lines 22A to 22D) (see also FIG. 10K). Even when the reforming lines 22A to 22D according to the fifth embodiment are formed, the same effect as when the reforming lines 22A to 22D according to the first embodiment are formed can be achieved.

In particular, according to the modification lines 22A to 22D of the fifth embodiment, cleavage origins can be formed in different regions in the thickness direction of the SiC semiconductor wafer structure 61 (SiC semiconductor wafer 41). This allows the SiC semiconductor wafer structure 61 to be properly cleaved even when the modification lines 22A to 22D are formed from a single layer.

Figure 12E is a perspective view showing the SiC semiconductor device 1 shown in Figure 3, and is a perspective view showing a sixth embodiment of the reforming lines 22A to 22D. In the following, structures corresponding to those described for the SiC semiconductor device 1 are given the same reference numerals and will not be described.

The reforming lines 22A-22D in the first embodiment are formed in the same shape as the side surfaces 5A-5D of the SiC semiconductor layer 2. In contrast, the reforming lines 22A-22D in the sixth embodiment are formed with different exclusive ratios RA, RB, RC, RD on the side surfaces 5A-5D of the SiC semiconductor layer 2. The exclusive ratios RA-RD are the ratios that the reforming lines 22A-22D occupy of the side surfaces 5A-5D.

More specifically, the exclusive ratios RA to RD differ depending on the crystal plane of the SiC single crystal. The exclusive ratios RB and RD of the reforming lines 22B and 22D formed on the m-plane of the SiC single crystal are equal to or less than the exclusive ratios RA and RC of the reforming lines 22A and 22C formed on the a-plane of the SiC single crystal (RB, RD≦RA, RC). More specifically, the exclusive ratios RB and RD are less than the exclusive ratios RA and RC (RB, RD<RA, RC).

The exclusive ratios RA and RC of the reforming lines 22A and 22C may be equal to each other or different from each other. The exclusive ratios RB and RD of the reforming lines 22B and 22D may be equal to each other or different from each other.

In this embodiment, the surface area of the reforming lines 22B and 22D relative to the sides 5B and 5D is less than the surface area of the reforming lines 22A and 22C relative to the sides 5A and 5C, respectively. In this embodiment, the thickness TR of the reforming lines 22B and 22D is less than the thickness TR of the reforming lines 22A and 22C, respectively.

The reforming lines 22A to 22D according to the sixth embodiment are formed by adjusting the focusing area (focus) of the laser light during the process of forming the reforming line 70 (see also FIG. 10K). Even when the reforming lines 22A to 22D according to the sixth embodiment are formed, the same effect as when the reforming lines 22A to 22D according to the first embodiment are formed can be achieved.

In particular, the reforming lines 22A-22D according to the sixth embodiment are formed with different exclusive ratios RA-RD on the side surfaces 5A-5D of the SiC semiconductor layer 2, respectively. More specifically, the reforming lines 22A-22D have different exclusive ratios RA-RD depending on the crystal planes of the SiC single crystal.

The exclusive ratios RB, RD of the reforming lines 22B, 22D formed on the m-plane of the SiC single crystal are equal to or less than the exclusive ratios RA, RC of the reforming lines 22A, 22C formed on the a-plane of the SiC single crystal (RB, RD ≦ RA, RC).

SiC single crystals have the physical property that, in a planar view of the c-plane (silicon plane) seen from the c-axis, they tend to crack along the nearest atomic direction (see also Figures 1 and 2), but are difficult to crack along directions that intersect with the nearest atomic direction. The nearest atomic direction is the a-axis direction and its equivalent direction. The intersecting directions with the nearest atomic direction are the m-axis direction and its equivalent direction.

Therefore, in the process of forming the reforming line 70, the crystal plane along the nearest neighbor atomic direction of the SiC single crystal has a relatively fragile nature, so the SiC single crystal can be appropriately cut (cleaved) without forming a reforming line 70 with a relatively large exclusive ratio (see also FIG. 10L). The crystal plane along the nearest neighbor atomic direction is the m-plane and its equivalent plane.

In other words, in the process of forming the reformed lines 70, the proportion of the reformed lines 70 along the second planned cutting lines 55 extending in the a-axis direction can be made smaller than the proportion of the reformed lines 70 along the first planned cutting lines 54 extending in the m-axis direction.

On the other hand, a modification line 70 having a relatively large proportion of monopoly is formed on the crystal plane along the intersecting direction of the nearest neighbor atomic direction of the SiC single crystal. This makes it possible to suppress inappropriate cutting (cleavage) of the SiC semiconductor wafer structure 61, and therefore to appropriately suppress the occurrence of cracks due to the physical properties of the SiC single crystal. The crystal plane along the intersecting direction of the nearest neighbor atomic direction is the a-plane and its equivalent plane.

In this way, according to the reforming lines 22A-22D of the sixth embodiment, the physical properties of the SiC single crystal can be utilized to adjust and reduce the exclusive ratios RA-RD of the reforming lines 22A-22D to the side surfaces 5A-5D. This can further reduce the impact of the reforming lines 22A-22D on the SiC semiconductor layer 2. In addition, the time required for the process of forming the reforming line 70 can be shortened.

The exclusive ratios RA to RD may be adjusted by the surface area of the reforming lines 22A to 22D relative to the sides 5A to 5D. The exclusive ratios RA to RD may be adjusted by the thickness TR of the reforming lines 22A to 22D. The exclusive ratios RA to RD may be adjusted by the number of reforming lines 22A to 22D.

A SiC semiconductor device 1 may be formed that simultaneously includes at least two of the reforming lines 22A to 22D according to the first, second, third, fourth, fifth and sixth embodiments (hereinafter simply referred to as the "first to sixth embodiments").

Furthermore, the features of the reforming lines 22A to 22D according to the first to sixth embodiment examples can be combined in any manner and in any form. In other words, reforming lines 22A to 22D having a form in which at least two of the features of the reforming lines 22A to 22D according to the first to sixth embodiment examples are combined may be adopted.

For example, the features of the reforming lines 22A-22D according to the third embodiment may be combined with the features of the reforming lines 22A-22D according to the fifth embodiment. In this case, the reforming lines 22A-22D are formed in a strip shape that slopes downward from the first main surface 3 to the second main surface 4 of the SiC semiconductor layer 2 and extends in a meandering curved (curved) shape toward the first main surface 3 and the second main surface 4 of the SiC semiconductor layer 2.

Figure 13 is a perspective view showing a SiC semiconductor device 91 according to the second embodiment of the present disclosure, and shows a structure to which the reforming lines 22A to 22D according to the first embodiment are applied. In the following, structures corresponding to those described for the SiC semiconductor device 1 are given the same reference numerals and will not be described.

In this embodiment, the reforming lines 22A to 22D according to the first embodiment are applied. However, instead of or in addition to the reforming lines 22A to 22D according to the first embodiment, the reforming lines 22A to 22D according to the second, third, fourth, fifth or sixth embodiment may be adopted. Furthermore, the reforming lines 22A to 22D may have a configuration that combines at least two of the features of the reforming lines 22A to 22D according to the first to sixth embodiments.

Referring to FIG. 13, in this embodiment, the insulating side surfaces 11A-11D of the main surface insulating layer 10 are formed at intervals inward from the side surfaces 5A-5D of the SiC semiconductor layer 2 in a plan view. The main surface insulating layer 10 exposes the peripheral portion of the first main surface 3 of the SiC semiconductor layer 2 in a plan view.

The main surface insulating layer 10, together with the resin layer 16 and the passivation layer 13, exposes the peripheral portion of the first main surface 3 of the SiC semiconductor layer 2. In this embodiment, the insulating side surfaces 11A-11D of the main surface insulating layer 10 are formed flush with the resin side surfaces 17A-17D of the resin layer 16 and the side surfaces 14A-14D of the passivation layer 13. In this embodiment, the insulating side surfaces 11A-11D of the main surface insulating layer 10 also form part of the dicing street.

This main surface insulating layer 10 is formed by performing a process of removing the main surface insulating layer 10 by an etching method after the process of removing the passivation layer 13 in the process shown in FIG. 10I described above.

In this case, in the process of FIG. 10K described above, laser light may be directly irradiated from the first main surface 62 side of the SiC semiconductor wafer structure 61 into the interior of the SiC semiconductor wafer structure 61 without passing through the main surface insulating layer 10.

As described above, the SiC semiconductor device 91 can achieve the same effects as those described for the SiC semiconductor device 1. However, in terms of improving the insulation between the side surfaces 5A-5D of the SiC semiconductor layer 2 and the first principal surface electrode layer 12, the structure of the SiC semiconductor device 1 according to the first embodiment is preferable.

Figure 14 is a perspective view of the SiC semiconductor device 101 according to the third embodiment of the present disclosure, seen from one angle, showing a structure to which the reforming lines 22A to 22D according to the first embodiment are applied. Figure 15 is a perspective view of the SiC semiconductor device 101 shown in Figure 14, seen from another angle. Figure 16 is a plan view showing the SiC semiconductor device 101 shown in Figure 14. Figure 17 is a plan view of Figure 16 with the resin layer 129 removed.

In this embodiment, the reforming lines 22A to 22D according to the first embodiment are applied. In other words, in the manufacturing process of the SiC semiconductor device 101, the same steps as those shown in Figures 10A to 10M described above are applied.

In the SiC semiconductor device 101, the reforming lines 22A-22D according to the second, third, fourth, fifth or sixth embodiment may be employed instead of or in addition to the reforming lines 22A-22D according to the first embodiment. In addition, the reforming lines 22A-22D may be employed that have a configuration that combines at least two of the features of the reforming lines 22A-22D according to the first to sixth embodiments.

Referring to Figures 14 to 17, the SiC semiconductor device 101 includes a SiC semiconductor layer 102. The SiC semiconductor layer 102 includes a 4H-SiC single crystal, which is an example of a SiC single crystal made of hexagonal crystals. The SiC semiconductor layer 102 (SiC semiconductor chip) is formed in the shape of a rectangular parallelepiped chip.

The SiC semiconductor layer 102 has a first main surface 103 on one side, a second main surface 104 on the other side, and side surfaces 105A, 105B, 105C, and 105D connecting the first main surface 103 and the second main surface 104. The first main surface 103 and the second main surface 104 are formed in a quadrangular shape (rectangular in this embodiment) in a plan view (hereinafter simply referred to as "plan view") seen from their normal direction Z.

The first main surface 103 is an element formation surface on which a semiconductor element is formed. The second main surface 104 of the SiC semiconductor layer 102 is a ground surface having grinding marks. The side surfaces 105A to 105D are each a smooth cleavage surface facing a crystal surface of the SiC single crystal. The side surfaces 105A to 105D do not have grinding marks.

The thickness TL of the SiC semiconductor layer 102 may be 40 μm or more and 200 μm or less. The thickness TL may be 40 μm or more and 60 μm or less, 60 μm or more and 80 μm or less, 80 μm or more and 100 μm or less, 100 μm or more and 120 μm or less, 120 μm or more and 140 μm or less, 140 μm or more and 160 μm or less, 160 μm or more and 180 μm or less, or 180 μm or more and 200 μm or less. The thickness TL is preferably 60 μm or more and 150 μm or less.

In this embodiment, the first main surface 103 and the second main surface 104 face the c-plane of the SiC single crystal. The first main surface 103 faces the (0001) plane (silicon plane). The second main surface 104 faces the (000-1) plane (carbon plane) of the SiC single crystal.

The first main surface 103 and the second main surface 104 have an off angle θ that is inclined at an angle of 10° or less in the [11-20] direction with respect to the c-plane of the SiC single crystal. The normal direction Z is inclined by the off angle θ with respect to the c-axis ([0001] direction) of the SiC single crystal.

The off angle θ may be 0° or more and 5.0° or less. The off angle θ may be set in the range of 0° or more and 1.0° or less, 1.0° or more and 1.5° or less, 1.5° or more and 2.0° or less, 2.0° or more and 2.5° or less, 2.5° or more and 3.0° or less, 3.0° or more and 3.5° or less, 3.5° or more and 4.0° or less, 4.0° or more and 4.5° or less, or 4.5° or more and 5.0° or less. It is preferable that the off angle θ is greater than 0°. The off angle θ may be less than 4.0°.

The off angle θ may be set in the range of 3.0° to 4.5°. In this case, it is preferable that the off angle θ is set in the range of 3.0° to 3.5° or 3.5° to 4.0°.

The off angle θ may be set in the range of 1.5° to 3.0°. In this case, it is preferable that the off angle θ is set in the range of 1.5° to 2.0° or 2.0° to 2.5°.

The length of each of the sides 105A to 105D may be 1 mm or more and 10 mm or less (e.g., 2 mm or more and 5 mm or less). In this embodiment, the surface area of the sides 105B and 105D exceeds the surface area of the sides 105A and 105C. The first main surface 103 and the second main surface 104 may be formed in a square shape in a plan view. In this case, the surface area of the sides 105B and 105D is equal to that of the sides 105B and 105C.

In this embodiment, side 105A and side 105C extend along a first direction X and face each other in a second direction Y that intersects with the first direction X. In this embodiment, side 105B and side 105D extend along the second direction Y and face each other in the first direction X. More specifically, the second direction Y is a direction perpendicular to the first direction X.

In this embodiment, the first direction X is set to the m-axis direction ([1-100] direction) of the SiC single crystal. The second direction Y is set to the a-axis direction ([11-20] direction) of the SiC single crystal.

Side 105A and side 105C form the short sides of SiC semiconductor layer 102 in a plan view. Side 105A and side 105C are formed by the a-plane of the SiC single crystal and face each other in the a-axis direction. Side 105A is formed by the (-1-120) plane of the SiC single crystal. Side 105C is formed by the (11-20) plane of the SiC single crystal.

Side 105B and side 105D form the long sides of SiC semiconductor layer 102 in a plan view. Side 105B and side 105D are formed by the m-plane of the SiC single crystal and face each other in the m-axis direction. Side 105B is formed by the (-1100) plane of the SiC single crystal. Side 105D is formed by the (1-100) plane of the SiC single crystal.

When the normal to the first main surface 103 of the SiC semiconductor layer 102 is used as a reference, the side surface 105A and the side surface 105C may form an inclined surface that is inclined toward the c-axis direction ([0001] direction) of the SiC single crystal with respect to the normal.

In this case, when the normal to the first main surface 103 of the SiC semiconductor layer 102 is set to 0°, the side surface 105A and the side surface 105C may be inclined at an angle corresponding to the off angle θ with respect to the normal to the first main surface 103 of the SiC semiconductor layer 102. The angle corresponding to the off angle θ may be equal to the off angle θ or may be an angle greater than 0° and less than the off angle θ.

In this embodiment, the SiC semiconductor layer 102 has a laminated structure including an n ⁺ type SiC semiconductor substrate 106 (second impurity region) and an n-type SiC epitaxial layer 107 (first impurity region). The SiC semiconductor substrate 106 and the SiC epitaxial layer 107 correspond to the SiC semiconductor substrate 6 and the SiC epitaxial layer 7, respectively, according to the first embodiment. The second main surface 104 of the SiC semiconductor layer 102 is formed by the SiC semiconductor substrate 106.

The first main surface 103 of the SiC semiconductor layer 102 is formed by the SiC epitaxial layer 107. The side surfaces 105A to 105D of the SiC semiconductor layer 102 are formed by the SiC semiconductor substrate 106 and the SiC epitaxial layer 107.

The thickness TS of the SiC semiconductor substrate 106 may be 40 μm or more and 150 μm or less. The thickness TS may be 40 μm or more and 50 μm or less, 50 μm or more and 60 μm or less, 60 μm or more and 70 μm or less, 70 μm or more and 80 μm or less, 80 μm or more and 90 μm or less, 90 μm or more and 100 μm or less, 100 μm or more and 110 μm or less, 110 μm or more and 120 μm or less, 120 μm or more and 130 μm or less, 130 μm or more and 140 μm or less, or 140 μm or more and 150 μm or less. The thickness TS is preferably 40 μm or more and 130 μm or less. By thinning the SiC semiconductor substrate 106, the resistance value can be reduced by shortening the current path.

The thickness TE of the SiC epitaxial layer 107 may be 1 μm or more and 50 μm or less. The thickness TE may be 1 μm or more and 5 μm or less, 5 μm or more and 10 μm or less, 10 μm or more and 15 μm or less, 15 μm or more and 20 μm or less, 20 μm or more and 25 μm or less, 25 μm or more and 30 μm or less, 30 μm or more and 35 μm or less, 35 μm or more and 40 μm or less, 40 μm or more and 45 μm or less, or 45 μm or more and 50 μm or less. The thickness TE is preferably 5 μm or more and 15 μm or less.

The n-type impurity concentration of the SiC epitaxial layer 107 is equal to or lower than the n-type impurity concentration of the SiC semiconductor substrate 106. More specifically, the n-type impurity concentration of the SiC epitaxial layer 107 is lower than the n-type impurity concentration of the SiC semiconductor substrate 106. The n-type impurity concentration of the SiC semiconductor substrate 106 may be equal to or higher than 1.0×10 ¹⁸ cm ^-3 and equal to or lower than 1.0×10 ²¹ cm ^-3 . The n-type impurity concentration of the SiC epitaxial layer 107 may be equal to or higher than 1.0×10 ¹⁵ cm ^-3 and equal to or lower than 1.0×10 ¹⁸ cm ^-3 .

In this embodiment, the SiC epitaxial layer 107 has a plurality of regions having different n-type impurity concentrations along the normal direction Z. More specifically, the SiC epitaxial layer 107 includes a high-concentration region 108 having a relatively high n-type impurity concentration, and a low-concentration region 109 having a low n-type impurity concentration relative to the high-concentration region 108.

The high concentration region 108 is formed in a region on the first main surface 103 side of the SiC semiconductor layer 102. The low concentration region 109 is formed in a region on the second main surface 104 side of the SiC semiconductor layer 102 relative to the high concentration region 108.

The n-type impurity concentration of the high concentration region 108 may be 1×10 ¹⁶ cm ⁻³ or more and 1×10 ¹⁸ cm ⁻³ or less, and the n-type impurity concentration of the low concentration region 109 may be 1×10 ¹⁵ cm ⁻³ or more and 1×10 ¹⁶ cm ⁻³ or less.

The thickness of the high concentration region 108 is equal to or less than the thickness of the low concentration region 109. More specifically, the thickness of the high concentration region 108 is less than the thickness of the low concentration region 109. The thickness of the high concentration region 108 is less than half the total thickness of the SiC epitaxial layer 107.

The SiC semiconductor layer 102 has an active region 111 and an outer region 112. The active region 111 is a region in which a vertical MISFET (Metal Insulator Field Effect Transistor) as an example of a semiconductor element is formed. The outer region 112 is a region outside the active region 111.

The active region 111 is set in the center of the SiC semiconductor layer 102 with a gap inward from the side surfaces 105A-105D of the SiC semiconductor layer 102 in a plan view. The active region 111 is set in a quadrangular shape (rectangular in this embodiment) with four sides parallel to the side surfaces 105A-105D of the SiC semiconductor layer 102 in a plan view.

The outer region 112 is set in the region between the side surfaces 105A-105D of the SiC semiconductor layer 102 and the periphery of the active region 111. The outer region 112 is set in an endless shape (a square ring in this embodiment) surrounding the active region 111 in a plan view.

A main surface insulating layer 113 is formed on the first main surface 103 of the SiC semiconductor layer 102. The main surface insulating layer 113 selectively covers the active region 111 and the outer region 112. The main surface insulating layer 113 may contain silicon oxide (SiO ₂ ).

The main surface insulating layer 113 has insulating side surfaces 114A, 114B, 114C, and 114D exposed from the side surfaces 105A to 105D of the SiC semiconductor layer 102. The insulating side surfaces 114A to 114D are continuous with the side surfaces 105A to 105D. The insulating side surfaces 114A to 114D are formed flush with the side surfaces 105A to 105D, respectively. The insulating side surfaces 114A to 114D are made of cleavage planes.

The thickness of the main surface insulating layer 113 may be 1 μm or more and 50 μm or less. The thickness of the main surface insulating layer 113 may be 1 μm or more and 10 μm or less, 10 μm or more and 20 μm or less, 20 μm or more and 30 μm or less, 30 μm or more and 40 μm or less, or 40 μm or more and 50 μm or less.

A main surface gate electrode layer 115 is formed on the main surface insulating layer 113 as one of the first main surface electrode layers. The main surface gate electrode layer 115 penetrates the main surface insulating layer 113 and is electrically connected to any region of the SiC semiconductor layer 102.

The main surface gate electrode layer 115 includes a gate pad 116 and gate fingers 117 and 118. The gate pad 116 and the gate fingers 117 and 118 are disposed in the active region 111.

The gate pad 116 is formed along the side surface 105A of the SiC semiconductor layer 102 in a planar view. The gate pad 116 is formed along the central region of the side surface 105A of the SiC semiconductor layer 102 in a planar view.

The gate pad 116 may be formed along a corner that connects any two of the side surfaces 105A to 105D of the SiC semiconductor layer 102 in a plan view. The gate pad 116 may be formed in a quadrangular shape in a plan view.

The gate fingers 117, 118 include an outer gate finger 117 and an inner gate finger 118. The outer gate finger 117 is drawn out from the gate pad 116 and extends in a strip along the periphery of the active region 111.

In this embodiment, the outer gate fingers 117 are formed along the three side surfaces 105A, 105B, and 105D of the SiC semiconductor layer 102 so as to partition the inner region of the active region 111 from three directions.

The outer gate finger 117 has a pair of open ends 119, 120. The pair of open ends 119, 120 are formed in a region facing the gate pad 116 across the inner region of the active region 111. In this embodiment, the pair of open ends 119, 120 are formed along the side surface 105C of the SiC semiconductor layer 102.

The inner gate finger 118 is extended from the gate pad 116 to the inner region of the active region 111. The inner gate finger 118 extends in a strip shape in the inner region of the active region 111. The inner gate finger 118 extends from the gate pad 116 toward the side surface 105C.

A main surface source electrode layer 121 is further formed on the main surface insulating layer 113 as one of the first main surface electrode layers. The main surface source electrode layer 121 penetrates the main surface insulating layer 113 and is electrically connected to any region of the SiC semiconductor layer 102. In this embodiment, the main surface source electrode layer 121 includes a source pad 122, a source routing wiring 123, and a source connection portion 124.

The source pad 122 is formed in the active region 111 at a distance from the gate pad 116 and the gate fingers 117 and 118. The source pad 122 is formed in a C-shape (inverted C-shape in FIGS. 16 and 17) in plan view so as to cover the C-shaped (inverted C-shape in FIGS. 16 and 17) region defined by the gate pad 116 and the gate fingers 117 and 118.

The source wiring 123 is formed in the outer region 112. The source wiring 123 extends in a strip shape along the active region 111. In this embodiment, the source wiring 123 is formed in an endless shape (a square ring shape in this embodiment) surrounding the active region 111 in a plan view. The source wiring 123 is electrically connected to the SiC semiconductor layer 102 in the outer region 112.

The source connection part 124 connects the source pad 122 and the source wiring 123. The source connection part 124 is provided in the region between the pair of open ends 119, 120 of the outer gate finger 117. The source connection part 124 crosses the boundary region between the active region 111 and the outer region 112 from the source pad 122 and is connected to the source wiring 123.

The MISFET formed in the active region 111 includes an npn-type parasitic bipolar transistor due to its structure. When an avalanche current generated in the outer region 112 flows into the active region 111, the parasitic bipolar transistor turns on. In this case, control of the MISFET may become unstable due to latch-up, for example.

Therefore, in the SiC semiconductor device 101, the structure of the main surface source electrode layer 121 is used to form an avalanche current absorption structure that absorbs the avalanche current generated in the outer region 112.

More specifically, the avalanche current generated in the outer region 112 is absorbed by the source routing wiring 123 and reaches the source pad 122 via the source connection part 124. If an external connection conductor (e.g., a bonding wire) is connected to the source pad 122, the avalanche current is extracted by this conductor.

This prevents the parasitic bipolar transistor from turning on due to undesired current generated in the outer region 112. This prevents latch-up, thereby improving the stability of MISFET control.

A gate voltage is applied to the main surface gate electrode layer 115. The gate voltage may be 10 V or more and 50 V or less (for example, about 30 V). A source voltage is applied to the main surface source electrode layer 121. The source voltage may be a reference voltage (for example, a GND voltage).

A passivation layer 125 (insulating layer) is formed on the main surface insulating layer 113. The passivation layer 125 may have a single-layer structure made of a silicon oxide layer or a silicon nitride layer.

The passivation layer 125 may have a laminated structure including a silicon oxide layer and a silicon nitride layer. The silicon oxide layer may be formed on the silicon nitride layer. The silicon nitride layer may be formed on the silicon oxide layer. In this embodiment, the passivation layer 125 has a single-layer structure consisting of a silicon nitride layer.

The side surfaces 126A, 126B, 126C, and 126D of the passivation layer 125 are formed at intervals inward from the side surfaces 105A to 105D of the SiC semiconductor layer 102 in a planar view. The passivation layer 125 exposes the peripheral portion of the SiC semiconductor layer 102 in a planar view. The passivation layer 125 exposes the main surface insulating layer 113.

The passivation layer 125 selectively covers the main surface gate electrode layer 115 and the main surface source electrode layer 121. A gate subpad opening 127 and a source subpad opening 128 are formed in the passivation layer 125. The gate subpad opening 127 exposes the gate pad 116. The source subpad opening 128 exposes the source pad 122.

The thickness of the passivation layer 125 may be 1 μm or more and 50 μm or less. The thickness of the passivation layer 125 may be 1 μm or more and 10 μm or less, 10 μm or more and 20 μm or less, 20 μm or more and 30 μm or less, 30 μm or more and 40 μm or less, or 40 μm or more and 50 μm or less.

A resin layer 129 (insulating layer) is formed on the passivation layer 125. The passivation layer 125 and the resin layer 129 form a single insulating laminated structure (insulating layer). In FIG. 16, the resin layer 129 is shown by hatching.

The resin layer 129 may contain a negative type or a positive type photosensitive resin. In this embodiment, the resin layer 129 contains polybenzoxazole as an example of a positive type photosensitive resin. The resin layer 129 may contain polyimide as an example of a negative type photosensitive resin.

The resin layer 129 selectively covers the main surface gate electrode layer 115 and the main surface source electrode layer 121. The resin side surfaces 130A, 130B, 130C, and 130D of the resin layer 129 are formed at intervals inward from the side surfaces 105A to 105D of the SiC semiconductor layer 102. The resin layer 129 exposes the main surface insulating layer 113 together with the passivation layer 125. In this embodiment, the resin side surfaces 130A to 130D of the resin layer 129 are formed flush with the side surfaces 126A to 126D of the passivation layer 125.

The resin side surfaces 130A-130D of the resin layer 129 are the parts that define the dicing streets when the SiC semiconductor device 101 is cut out from a single SiC semiconductor wafer. In this embodiment, the sides 126A-126D of the passivation layer 125 are also the parts that define the dicing streets.

By exposing the peripheral portion of the SiC semiconductor layer 102 from the resin layer 129 and the passivation layer 125, it is not necessary to physically cut the resin layer 129 and the passivation layer 125. This makes it possible to smoothly cut out the SiC semiconductor device 101 from one SiC semiconductor wafer. In addition, the insulation distance from the side surfaces 105A to 105D of the SiC semiconductor layer 102 can be increased.

The distance between the side surfaces 105A-105D and the resin side surfaces 130A-130D (side surfaces 126A-126D) may be 1 μm or more and 25 μm or less. The distance between the side surfaces 105A-105D and the resin side surfaces 130A-130D (side surfaces 126A-126D) may be 1 μm or more and 5 μm or less, 5 μm or more and 10 μm or less, 10 μm or more and 15 μm or less, 15 μm or more and 20 μm or less, or 20 μm or more and 25 μm or less. Of course, the side surfaces 126A-126D of the passivation layer 125 may be formed flush with the side surfaces 105A-105D of the SiC semiconductor layer 102.

A gate pad opening 131 and a source pad opening 132 are formed in the resin layer 129. The gate pad opening 131 exposes the gate pad 116. The source pad opening 132 exposes the source pad 122.

The gate pad opening 131 of the resin layer 129 is connected to the gate subpad opening 127 of the passivation layer 125. The inner wall of the gate pad opening 131 may be located outside the inner wall of the gate subpad opening 127. The inner wall of the gate pad opening 131 may be located inside the inner wall of the gate subpad opening 127. The resin layer 129 may cover the inner wall of the gate subpad opening 127.

The source pad opening 132 of the resin layer 129 is connected to the source subpad opening 128 of the passivation layer 125. The inner wall of the gate pad opening 131 may be located outside the inner wall of the source subpad opening 128. The inner wall of the source pad opening 132 may be located inside the inner wall of the source subpad opening 128. The resin layer 129 may cover the inner wall of the source subpad opening 128.

The thickness of the resin layer 129 may be 1 μm or more and 50 μm or less. The thickness of the resin layer 129 may be 1 μm or more and 10 μm or less, 10 μm or more and 20 μm or less, 20 μm or more and 30 μm or less, 30 μm or more and 40 μm or less, or 40 μm or more and 50 μm or less.

A drain electrode layer 133 serving as a second principal surface electrode layer is connected to the second principal surface 104 of the SiC semiconductor layer 102. The maximum voltage that can be applied between the principal surface source electrode layer 121 and the drain electrode layer 133 in the off state may be 1000 V or more and 10000 V or less.

The drain electrode layer 133 may include at least one of a Ti layer, a Ni layer, an Au layer, an Ag layer, or an Al layer. The drain electrode layer 133 may have a single layer structure including a Ti layer, a Ni layer, an Au layer, an Ag layer, or an Al layer.

The drain electrode layer 133 may have a laminated structure in which at least two of a Ti layer, a Ni layer, an Au layer, an Ag layer, and an Al layer are laminated in any manner. The drain electrode layer 133 may have a four-layer structure including a Ti layer, a Ni layer, an Au layer, and an Ag layer laminated in this order from the second main surface 104 of the SiC semiconductor layer 102.

The SiC semiconductor substrate 106 is formed as a drain region 134 (second impurity region) of the MISFET. The SiC epitaxial layer 107 is formed as a drift region 135 (first impurity region) of the MISFET.

A plurality of reforming lines 22A-22D according to the first embodiment are formed on the side surfaces 105A-105D of the SiC semiconductor layer 102. The structure of the reforming lines 22A-22D according to the third embodiment is similar to the structure of the reforming lines 22A-22D according to the first embodiment, except that they are formed on the SiC semiconductor layer 102 instead of the SiC semiconductor layer 2.

The description of the reforming lines 22A to 22D according to the first embodiment applies mutatis mutandis to the description of the reforming lines 22A to 22D according to the third embodiment, and a specific description of the reforming lines 22A to 22D according to the third embodiment will be omitted.

Figure 18 is an enlarged view of region XVIII shown in Figure 17, and is a diagram for explaining the structure of the first main surface 103 of the SiC semiconductor layer 102. Figure 19 is a cross-sectional view taken along line XIX-XIX shown in Figure 18. Figure 20 is a cross-sectional view taken along line XX-XX shown in Figure 18. Figure 21 is an enlarged view of region XXI shown in Figure 19. Figure 22 is a cross-sectional view taken along line XXII-XXII shown in Figure 17. Figure 23 is an enlarged view of region XXIII shown in Figure 22.

Referring to Figures 18 to 22, a p-type body region 141 is formed in the surface layer of the first main surface 103 of the SiC semiconductor layer 102 in the active region 111. The body region 141 defines the active region 111.

In this embodiment, the body region 141 is formed in the entire region forming the active region 111 on the first main surface 103 of the SiC semiconductor layer 102. The p-type impurity concentration of the body region 141 may be not less than 1.0×10 ¹⁷ cm ⁻³ and not more than 1.0×10 ¹⁹ cm ⁻³ .

In the active region 111, a plurality of gate trenches 142 are formed in the surface layer of the first main surface 103 of the SiC semiconductor layer 102. The plurality of gate trenches 142 are each formed in a strip shape extending along the first direction X (the m-axis direction of the SiC single crystal) in a plan view, and are formed at intervals along the second direction Y (the a-axis direction of the SiC single crystal).

In this embodiment, each gate trench 142 extends from the periphery on one side (side surface 105B) of the active region 111 to the periphery on the other side (side surface 105D). The multiple gate trenches 142 are formed in a striped pattern as a whole in a plan view.

Each gate trench 142 crosses the middle portion between the periphery on one side and the periphery on the other side of the active region 111. One end of each gate trench 142 is located on the periphery on one side of the active region 111. The other end of each gate trench 142 is located on the periphery on the other side of the active region 111.

The length of each gate trench 142 may be 0.5 mm or more. The length of each gate trench 142 is the length from the end of the connection portion of each gate trench 142 and the outer gate finger 117 to the opposite end in the cross section shown in FIG. 20.

In this embodiment, the length of each gate trench 142 is 1 mm or more and 10 mm or less (e.g., 2 mm or more and 5 mm or less). The total extension of one or more gate trenches 142 per unit area may be 0.5 μm/μm2 or more and 0.75 μm/μm2 or less.

Each gate trench 142 integrally includes an active trench portion 143 and a contact trench portion 144. The active trench portion 143 is a portion of the active region 111 that is aligned with the channel of the MISFET.

The contact trench portion 144 is a portion of the gate trench 142 that is intended primarily for contact with the outer gate finger 117. The contact trench portion 144 is extended from the active trench portion 143 to the periphery of the active region 111. The contact trench portion 144 is formed in the region directly below the outer gate finger 117. The amount of extension of the contact trench portion 144 is arbitrary.

Each gate trench 142 penetrates the body region 141 and reaches the SiC epitaxial layer 107. Each gate trench 142 includes a sidewall and a bottom wall. The sidewalls forming the long sides of each gate trench 142 are formed by the a-plane of the SiC single crystal. The sidewalls forming the short sides of each gate trench 142 are formed by the m-plane of the SiC single crystal.

The sidewalls of each gate trench 142 may extend along the normal direction Z. The sidewalls of each gate trench 142 may be formed substantially perpendicular to the first main surface 103 of the SiC semiconductor layer 102.

The angle that the sidewall of each gate trench 142 makes with the first main surface 103 of the SiC semiconductor layer 102 may be 90° or more and 95° or less (e.g., 91° or more and 93° or less). Each gate trench 142 may be formed in a tapered shape in which the opening area on the bottom wall side is smaller than the opening area on the opening side in a cross-sectional view.

The bottom wall of each gate trench 142 is located in the SiC epitaxial layer 107. More specifically, the bottom wall of each gate trench 142 is located in a high concentration region 108 of the SiC epitaxial layer 107.

The bottom wall of each gate trench 142 faces the c-plane of the SiC single crystal. The bottom wall of each gate trench 142 has an off angle θ inclined in the [11-20] direction with respect to the c-plane of the SiC single crystal.

The bottom wall of each gate trench 142 may be formed parallel to the first major surface 103 of the SiC semiconductor layer 102. Of course, the bottom wall of each gate trench 142 may be formed in a convex curve toward the second major surface 104 of the SiC semiconductor layer 102.

With respect to the normal direction Z, the depth of each gate trench 142 may be 0.5 μm or more and 3.0 μm or less. The depth of each gate trench 142 may be 0.5 μm or more and 1.0 μm or less, 1.0 μm or more and 1.5 μm or less, 1.5 μm or more and 2.0 μm or less, 2.0 μm or more and 2.5 μm or less, or 2.5 μm or more and 3.0 μm or less.

The width of each gate trench 142 along the second direction Y may be 0.1 μm or more and 2 μm or less. The width of each gate trench 142 may be 0.1 μm or more and 0.5 μm or less, 0.5 μm or more and 1.0 μm or less, 1.0 μm or more and 1.5 μm or less, or 1.5 μm or more and 2 μm or less.

21, the opening edge portion 146 of each gate trench 142 includes an inclined portion 147 that slopes downward from the first main surface 103 of the SiC semiconductor layer 102 toward the inside of each gate trench 142. The opening edge portion 146 of each gate trench 142 is a corner portion that connects the first main surface 103 of the SiC semiconductor layer 102 and the sidewall of each gate trench 142.

In this embodiment, the inclined portion 147 is formed in a concave curve toward the inside of the SiC semiconductor layer 102. The inclined portion 147 may be formed in a convex curve toward the inside of each gate trench 142. The inclined portion 147 reduces electric field concentration at the opening edge portion 146 of each gate trench 142.

A gate insulating layer 148 and a gate electrode layer 149 are formed in each gate trench 142. In FIG. 18, the gate insulating layer 148 and the gate electrode layer 149 are indicated by hatching.

The gate insulating layer 148 includes at least one of silicon oxide (SiO ₂ ), silicon nitride (SiN), aluminum oxide (Al ₂ O ₃ ), zirconium oxide (ZrO ₂ ), or tantalum oxide (Ta ₂ O ₃ ).

The gate insulating layer 148 may have a laminated structure including a SiN layer and a SiO ₂ layer laminated in this order from the first main surface 103 side of the SiC semiconductor layer 102. The gate insulating layer 148 may have a laminated structure including a SiO ₂ layer and a SiN layer laminated in this order from the first main surface 103 side of the SiC semiconductor layer 102. The gate insulating layer 148 may have a single layer structure made of a SiO ₂ layer or a SiN layer. In this embodiment, the gate insulating layer 148 has a single layer structure made of a SiO ₂ layer.

The gate insulating layer 148 is formed in the form of a film along the inner wall surface of the gate trench 142 so as to define a concave space within the gate trench 142. The gate insulating layer 148 includes a first region 148a, a second region 148b, and a third region 148c.

The first region 148a is formed along the sidewall of the gate trench 142. The second region 148b is formed along the bottom wall of the gate trench 142. The third region 148c is formed along the first main surface 103 of the SiC semiconductor layer 102. The third region 148c of the gate insulating layer 148 forms part of the main surface insulating layer 113.

The thickness Ta of the first region 148a is smaller than the thickness Tb of the second region 148b and the thickness Tc of the third region 148c. The ratio Tb/Ta of the thickness Tb of the second region 148b to the thickness Ta of the first region 148a may be 2 or more and 5 or less. The ratio T3/Ta of the thickness Tc of the third region 148c to the thickness Ta of the first region 148a may be 2 or more and 5 or less.

The thickness Ta of the first region 148a may be 0.01 μm or more and 0.2 μm or less. The thickness Tb of the second region 148b may be 0.05 μm or more and 0.5 μm or less. The thickness Tc of the third region 148c may be 0.05 μm or more and 0.5 μm or less.

By thinning the first region 148a of the gate insulating layer 148, the increase in carriers induced in the body region 141 near the sidewalls of each gate trench 142 can be suppressed. This makes it possible to suppress an increase in channel resistance. By thickening the second region 148b of the gate insulating layer 148, the electric field concentration on the bottom wall of each gate trench 142 can be alleviated.

By thickening the third region 148c of the gate insulating layer 148, the breakdown voltage of the gate insulating layer 148 near the opening edge portion 146 of each gate trench 142 can be improved. In addition, by thickening the third region 148c, it is possible to prevent the third region 148c from disappearing due to the etching method.

This prevents the first region 148a from being removed by the etching method due to the disappearance of the third region 148c. As a result, the gate electrode layer 149 can be appropriately opposed to the SiC semiconductor layer 102 (body region 141) with the gate insulating layer 148 interposed therebetween.

The gate insulating layer 148 further includes a bulge portion 148d that bulges into each gate trench 142 at the opening edge portion 146 of each gate trench 142. The bulge portion 148d is formed at a corner portion that connects the first region 148a and the third region 148c of the gate insulating layer 148.

The bulging portion 148d protrudes inwardly of each gate trench 142 in a convex curved shape. The bulging portion 148d narrows the opening of each gate trench 142 at the opening edge portion 146 of each gate trench 142.

The bulge 148d improves the dielectric strength of the gate insulating layer 148 at the opening edge 146. Of course, the gate insulating layer 148 may be formed without the bulge 148d. Also, the gate insulating layer 148 may be formed to have a uniform thickness.

The gate electrode layer 149 is embedded in each gate trench 142 with the gate insulating layer 148 sandwiched therebetween. More specifically, the gate electrode layer 149 is embedded in a concave space defined by the gate insulating layer 148 in each gate trench 142. The gate electrode layer 149 is controlled by a gate voltage.

The gate electrode layer 149 has an upper end located on the opening side of each gate trench 142. The upper end of the gate electrode layer 149 is formed in a concave curved shape recessed toward the bottom wall of each gate trench 142. The upper end of the gate electrode layer 149 has a narrowed portion that is narrowed along the bulging portion 148d of the gate insulating layer 148.

The cross-sectional area of the gate electrode layer 149 (the cross-sectional area perpendicular to the direction in which each gate trench 142 extends) may be 0.05 μm2 or more and 0.5 μm2 or less. The cross-sectional area of the gate electrode layer 149 is defined as the product of the depth of the gate electrode layer 149 and the width of the gate electrode layer 149.

The depth of the gate electrode layer 149 is the distance from the upper end to the lower end of the gate electrode layer 149. The width of the gate electrode layer 149 is the width of the gate trench 142 at the midpoint between the upper and lower ends of the gate electrode layer 149. If the upper end is curved (concavely curved in this embodiment), the position of the upper end of the gate electrode layer 149 is the midpoint in the depth direction on the upper surface of the gate electrode layer 149.

The gate electrode layer 149 includes p-type polysilicon doped with p-type impurities. The p-type impurities in the gate electrode layer 149 may include at least one of boron (B), aluminum (Al), indium (In), or gallium (Ga).

The p-type impurity concentration of the gate electrode layer 149 is equal to or greater than the p-type impurity concentration of the body region 141. More specifically, the p-type impurity concentration of the gate electrode layer 149 is greater than the p-type impurity concentration of the body region 141.

The p-type impurity concentration of the gate electrode layer 149 may be 1×10 ¹⁸ cm ⁻³ or more and 1×10 ²² cm ⁻³ or less. The sheet resistance of the gate electrode layer 149 may be 10 Ω/□ or more and 500 Ω/□ or less (about 200 Ω/□ in this embodiment).

Referring to FIG. 18 and FIG. 20, a gate wiring layer 150 is formed in the active region 111. The gate wiring layer 150 is electrically connected to the gate pad 116 and the gate fingers 117 and 118. In FIG. 20, the gate wiring layer 150 is indicated by hatching.

The gate wiring layer 150 is formed on the first main surface 103 of the SiC semiconductor layer 102. More specifically, the gate wiring layer 150 is formed on the third region 148c of the gate insulating layer 148.

In this embodiment, the gate wiring layer 150 is formed along the outer gate finger 117. More specifically, the gate wiring layer 150 is formed along the three side surfaces 105A, 105B, and 105D of the SiC semiconductor layer 102 so as to partition the inner region of the active region 111 from three directions.

The gate wiring layer 150 is connected to the gate electrode layer 149 exposed from the contact trench portion 144 of each gate trench 142. In this embodiment, the gate wiring layer 150 is formed by an extension portion of the gate electrode layer 149 that is extended from each gate trench 142 onto the first main surface 103 of the SiC semiconductor layer 102. The upper end of the gate wiring layer 150 is connected to the upper end of the gate electrode layer 149.

Referring to Figures 18, 19, and 21, a plurality of source trenches 155 are formed in the first main surface 103 of the SiC semiconductor layer 102 in the active region 111. Each source trench 155 is formed in a region between two adjacent gate trenches 142.

The multiple source trenches 155 are each formed in a band shape extending along the first direction X (the m-axis direction of the SiC single crystal). The multiple source trenches 155 are formed in a stripe shape as a whole in a plan view. In the second direction Y, the pitch between the centers of adjacent source trenches 155 may be 1.5 μm or more and 3 μm or less.

Each source trench 155 penetrates the body region 141 and reaches the SiC epitaxial layer 107. Each source trench 155 includes a sidewall and a bottom wall. The sidewalls forming the long sides of each source trench 155 are formed by the a-plane of the SiC single crystal. The sidewalls forming the short sides of each source trench 155 are formed by the m-plane of the SiC single crystal.

The sidewalls of each source trench 155 may extend along the normal direction Z. The sidewalls of each source trench 155 may be formed substantially perpendicular to the first main surface 103 of the SiC semiconductor layer 102.

The angle that the sidewall of each source trench 155 in the SiC semiconductor layer 102 makes with the first main surface 103 of the SiC semiconductor layer 102 may be 90° or more and 95° or less (e.g., 91° or more and 93° or less). Each source trench 155 may be formed in a tapered shape in which the opening area on the bottom wall side is smaller than the opening area on the opening side in a cross-sectional view.

The bottom wall of each source trench 155 is located in the SiC epitaxial layer 107. More specifically, the bottom wall of each source trench 155 is located in the high concentration region 108 of the SiC epitaxial layer 107. More specifically, the bottom wall of each source trench 155 is located in the region between the bottom wall of each gate trench 142 and the low concentration region 109.

The bottom wall of each source trench 155 faces the c-plane of the SiC single crystal. The bottom wall of each source trench 155 has an off-angle θ inclined in the [11-20] direction with respect to the c-plane of the SiC single crystal.

The bottom wall of each source trench 155 may be formed parallel to the first major surface 103 of the SiC semiconductor layer 102. Of course, the bottom wall of each source trench 155 may be formed in a convex curve toward the second major surface 104 of the SiC semiconductor layer 102.

In this embodiment, the depth of each source trench 155 is equal to or greater than the depth of each gate trench 142. More specifically, the depth of each source trench 155 is greater than the depth of each gate trench 142.

The bottom wall of each source trench 155 is located on the second main surface 104 side of the SiC semiconductor layer 102 relative to the bottom wall of each gate trench 142. Of course, the depth of each source trench 155 may be equal to the depth of each gate trench 142.

With respect to the normal direction Z, the depth of each source trench 155 may be 0.5 μm or more and 10 μm or less (for example, about 2 μm). The ratio of the depth of each source trench 155 to the depth of each gate trench 142 may be 1.5 or more. It is preferable that the ratio of the depth of each source trench 155 to the depth of each gate trench 142 is 2 or more.

The first direction width of each source trench 155 may be approximately equal to the first direction width of each gate trench 142. The first direction width of each source trench 155 may be equal to or greater than the first direction width of each gate trench 142. The first direction width of each source trench 155 may be equal to or greater than 0.1 μm and equal to or less than 2 μm (for example, about 0.5 μm).

A source insulating layer 156 and a source electrode layer 157 are formed in each source trench 155. In FIG. 18, the source insulating layer 156 and the source electrode layer 157 are indicated by hatching.

The source insulating layer 156 includes at least one of silicon oxide (SiO ₂ ), silicon nitride (SiN), aluminum oxide (Al ₂ O ₃ ), zirconium oxide (ZrO ₂ ), and tantalum oxide (Ta ₂ O ₃ ).

The source insulating layer 156 may have a laminated structure including a SiN layer and a SiO ₂ layer laminated in this order from the first main surface 103 side of the SiC semiconductor layer 102. The source insulating layer 156 may have a laminated structure including a SiO ₂ layer and a SiN layer laminated in this order from the first main surface 103 side of the SiC semiconductor layer 102. The source insulating layer 156 may have a single layer structure made of a SiO ₂ layer or a SiN layer. In this embodiment, the source insulating layer 156 has a single layer structure made of a SiO ₂ layer.

The source insulating layer 156 is formed in the form of a film along the inner wall surface of each source trench 155 so that a concave space is defined within each source trench 155. The source insulating layer 156 includes a first region 156a and a second region 156b.

The first region 156a is formed along the sidewall of each source trench 155. The second region 156b is formed along the bottom wall of each source trench 155. The thickness Tsa of the first region 156a is smaller than the thickness Tsb of the second region 156b.

The ratio Tsb/Tsa of the thickness Tsb of the second region 156b to the thickness Tsa of the first region 156a may be 2 or more and 5 or less. The thickness Tsa of the first region 156a may be 0.01 μm or more and 0.2 μm or less. The thickness Tsb of the second region 156b may be 0.05 μm or more and 0.5 μm or less.

The thickness Tsa of the first region 156a may be approximately equal to the thickness Ta of the first region 156a of the gate insulating layer 148. The thickness Tsb of the second region 156b may be approximately equal to the thickness Tb of the second region 156b of the gate insulating layer 148. Of course, the source insulating layer 156 may be formed to have a uniform thickness.

The source electrode layer 157 is embedded in each source trench 155 with the source insulating layer 156 sandwiched therebetween. More specifically, the source electrode layer 157 is embedded in a concave space defined by the source insulating layer 156 in each source trench 155. The source electrode layer 157 is controlled by a source voltage.

The source electrode layer 157 has an upper end located on the opening side of each source trench 155. The upper end of the source electrode layer 157 is formed below the first main surface 103 of the SiC semiconductor layer 102. The upper end of the source electrode layer 157 may be located above the first main surface 103 of the SiC semiconductor layer 102.

The upper end of the source electrode layer 157 is formed in a concave curved shape recessed toward the bottom wall of each source trench 155. The upper end of the source electrode layer 157 may be formed parallel to the first main surface 103 of the SiC semiconductor layer 102.

The upper end of the source electrode layer 157 may protrude above the upper end of the source insulating layer 156. The upper end of the source electrode layer 157 may be located below the upper end of the source insulating layer 156. The thickness of the source electrode layer 157 may be 0.5 μm or more and 10 μm or less (for example, about 1 μm).

The source electrode layer 157 preferably contains polysilicon having properties similar to those of SiC. This reduces the stress generated in the SiC semiconductor layer 102. In this embodiment, the source electrode layer 157 contains p-type polysilicon doped with p-type impurities. In this case, the source electrode layer 157 can be formed simultaneously with the gate electrode layer 149.

The p-type impurity concentration of the source electrode layer 157 is equal to or greater than the p-type impurity concentration of the body region 141. More specifically, the p-type impurity concentration of the source electrode layer 157 is greater than the p-type impurity concentration of the body region 141. The p-type impurity of the source electrode layer 157 may include at least one of boron (B), aluminum (Al), indium (In), or gallium (Ga).

The p-type impurity concentration of the source electrode layer 157 may be 1×10 ¹⁸ cm ⁻³ or more and 1×10 ²² cm ⁻³ or less. The sheet resistance of the source electrode layer 157 may be 10 Ω/□ or more and 500 Ω/□ or less (about 200 Ω/□ in this embodiment).

The p-type impurity concentration of the source electrode layer 157 may be approximately equal to the p-type impurity concentration of the gate electrode layer 149. The sheet resistance of the source electrode layer 157 may be approximately equal to the sheet resistance of the gate electrode layer 149.

The source electrode layer 157 may contain n-type polysilicon instead of or in addition to p-type polysilicon. The source electrode layer 157 may contain at least one of tungsten, aluminum, copper, an aluminum alloy, or a copper alloy instead of or in addition to p-type polysilicon.

As such, the SiC semiconductor device 101 has multiple trench gate structures 161 and multiple trench source structures 162. Each trench gate structure 161 includes a gate trench 142, a gate insulating layer 148, and a gate electrode layer 149. Each trench source structure 162 includes a source trench 155, a source insulating layer 156, and a source electrode layer 157.

An n ⁺ type source region 163 is formed in a surface layer portion of the body region 141 in a region along the side wall of each gate trench 142. The n-type impurity concentration of the source region 163 may be 1.0×10 ¹⁸ cm ⁻³ or more and 1.0×10 ²¹ cm ⁻³ or less. The n-type impurity of the source region 163 may be phosphorus (P).

Multiple source regions 163 are formed along one sidewall and the other sidewall of each gate trench 142. Each of the multiple source regions 163 is formed in a strip shape extending along the first direction X.

The multiple source regions 163 are formed in a striped pattern as a whole in a plan view. Each source region 163 is exposed from the sidewall of each gate trench 142 and the sidewall of each source trench 155.

In this manner, in the surface portion of the first main surface 103 of the SiC semiconductor layer 102, in the region along the sidewall of the gate trench 142, the source region 163, the body region 141, and the drift region 135 are formed in this order from the first main surface 103 toward the second main surface 104 of the SiC semiconductor layer 102.

The channel of the MISFET is formed in the body region 141 in a region along the sidewall of the gate trench 142. The channel is formed in the region along the sidewall of the gate trench 142 that faces the a-plane of the SiC single crystal. The ON/OFF of the channel is controlled by the gate electrode layer 149.

In the active region 111, a plurality of p ⁺ type contact regions 164 are formed in a surface layer portion of the first main surface 103 of the SiC semiconductor layer 102. Each contact region 164 is formed in a region between two gate trenches 142 adjacent to each other in a plan view. Each contact region 164 is formed in a region on the opposite side of each source region 163 from the gate trenches 142.

Each contact region 164 is formed along the inner wall of each source trench 155. In this embodiment, multiple contact regions 164 are formed at intervals along the inner wall of each source trench 155. Each contact region 164 is formed at an interval from each gate trench 142.

The p-type impurity concentration of each contact region 164 is higher than the p-type impurity concentration of the body region 141. The p-type impurity concentration of each contact region 164 may be not less than 1.0×10 ¹⁸ cm ⁻³ and not more than 1.0×10 ²¹ cm ⁻³ . The p-type impurity of each contact region 164 may be aluminum (Al).

Each contact region 164 covers the sidewall and bottom wall of each source trench 155. The bottom of each contact region 164 may be formed parallel to the bottom wall of each source trench 155. More specifically, each contact region 164 integrally includes a first surface region 164a, a second surface region 164b, and an inner wall region 164c.

The first surface region 164a covers one sidewall of the source trench 155 in the surface portion of the body region 141. The first surface region 164a is electrically connected to the body region 141 and the source region 163.

The first surface region 164a is located in a region on the first major surface 103 side of the SiC semiconductor layer 102 relative to the bottom of the source region 163. In this embodiment, the first surface region 164a has a bottom that extends parallel to the first major surface 103 of the SiC semiconductor layer 102.

In this embodiment, the bottom of the first surface region 164a is located in the region between the bottom of the body region 141 and the bottom of the source region 163. The bottom of the first surface region 164a may also be located in the region between the first main surface 103 of the SiC semiconductor layer 102 and the bottom of the body region 141.

In this embodiment, the first surface region 164a extends from the source trench 155 toward the adjacent gate trench 142. The first surface region 164a may extend to an intermediate region between the gate trench 142 and the source trench 155. The first surface region 164a is formed at a distance from the gate trench 142 toward the source trench 155.

The second surface region 164b covers the other sidewall of the source trench 155 in the surface portion of the body region 141. The second surface region 164b is electrically connected to the body region 141 and the source region 163.

The second surface region 164b is located in a region on the first main surface 103 side of the SiC semiconductor layer 102 relative to the bottom of the source region 163. In this embodiment, the second surface region 164b has a bottom that extends parallel to the first main surface 103 of the SiC semiconductor layer 102.

In this embodiment, the bottom of the second surface region 164b is located in the region between the bottom of the body region 141 and the bottom of the source region 163. The bottom of the second surface region 164b may be located in the region between the first main surface 103 of the SiC semiconductor layer 102 and the bottom of the body region 141.

In this embodiment, the second surface region 164b extends from the other sidewall of the source trench 155 toward the adjacent gate trench 142. The second surface region 164b may extend to an intermediate region between the source trench 155 and the gate trench 142. The second surface region 164b is formed at a distance from the gate trench 142 toward the source trench 155.

The inner wall region 164c is located in a region on the second main surface 104 side of the SiC semiconductor layer 102 relative to the first surface region 164a and the second surface region 164b (the bottom of the source region 163). The inner wall region 164c is formed in a region of the SiC semiconductor layer 102 along the inner wall of the source trench 155. The inner wall region 164c covers the side wall of the source trench 155.

The inner wall region 164c covers the corners that connect the side walls and bottom walls of the source trench 155. The inner wall region 164c covers the bottom wall of the source trench 155 from the side walls of the source trench 155 through the corners. The bottom of the contact region 164 is formed by the inner wall region 164c.

A plurality of deep well regions 165 are formed in the surface layer of the first main surface 103 of the SiC semiconductor layer 102. Each deep well region 165 is also referred to as a breakdown voltage adjustment region (breakdown voltage holding region) that adjusts the breakdown voltage of the SiC semiconductor layer 102 in the active region 111.

Each deep well region 165 is formed in the SiC epitaxial layer 107. More specifically, each deep well region 165 is formed in a high concentration region 108 of the SiC epitaxial layer 107.

Each deep well region 165 is formed along the inner wall of each source trench 155 so as to cover each contact region 164. Each deep well region 165 is electrically connected to each contact region 164.

Each deep well region 165 is formed in a strip shape extending along each source trench 155 in a plan view. Each deep well region 165 covers the sidewall of each source trench 155.

Each deep well region 165 covers the corners connecting the sidewalls and bottom wall of each source trench 155. Each deep well region 165 covers the sidewalls of each source trench 155 through the corners to the bottom wall of each source trench 155. Each deep well region 165 is connected to the body region 141 at the sidewall of each source trench 155.

Each deep well region 165 has a bottom located on the second main surface 104 side of the SiC semiconductor layer 102 relative to the bottom wall of each gate trench 142. The bottom of each deep well region 165 may be formed parallel to the bottom wall of each source trench 155.

The p-type impurity concentration of each deep well region 165 may be approximately equal to the p-type impurity concentration of the body region 141. The p-type impurity concentration of each deep well region 165 may be greater than the p-type impurity concentration of the body region 141. The p-type impurity concentration of each deep well region 165 may be less than the p-type impurity concentration of the body region 141.

The p-type impurity concentration of each deep well region 165 may be equal to or lower than the p-type impurity concentration of the contact region 164. The p-type impurity concentration of each deep well region 165 may be lower than the p-type impurity concentration of the contact region 164. The p-type impurity concentration of each deep well region 165 may be equal to or higher than 1.0×10 ¹⁷ cm ⁻³ and equal to or lower than 1.0×10 ¹⁹ cm ⁻³ .

Each deep well region 165 forms a pn junction with the SiC semiconductor layer 102 (high concentration region 108 of the SiC epitaxial layer 107). A depletion layer extends from this pn junction toward the region between adjacent gate trenches 142. This depletion layer extends toward the region on the second main surface 104 side of the SiC semiconductor layer 102 relative to the bottom wall of each gate trench 142.

The depletion layer extending from each deep well region 165 may overlap the bottom wall of each gate trench 142. The depletion layer extending from the bottom of each deep well region 165 may overlap the bottom wall of each gate trench 142.

Referring to FIG. 18 and FIG. 20, a p-type peripheral deep well region 166 is formed on the periphery of the active region 111. The peripheral deep well region 166 is formed in the SiC epitaxial layer 107. More specifically, the peripheral deep well region 166 is formed in the high concentration region 108 of the SiC epitaxial layer 107.

The peripheral deep well region 166 is electrically connected to each deep well region 165. The peripheral deep well region 166 has the same potential as each deep well region 165. In this embodiment, the peripheral deep well region 166 is formed integrally with each deep well region 165.

More specifically, the peripheral deep well region 166 is formed in a region along the inner wall of the contact trench portion 144 of each gate trench 142 at the periphery of the active region 111.

The peripheral deep well region 166 covers the sidewalls of the contact trench portion 144 of each gate trench 142. The peripheral deep well region 166 covers the corners connecting the sidewalls and bottom wall of each contact trench portion 144.

The peripheral deep well region 166 covers the sidewalls and corners of each contact trench portion 144 and the bottom wall of each contact trench portion 144. Each deep well region 165 is connected to the body region 141 at the sidewall of each contact trench portion 144. The bottom of the peripheral deep well region 166 is located on the second main surface 104 side of the SiC semiconductor layer 102 relative to the bottom wall of each contact trench portion 144.

The peripheral deep well region 166 overlaps the gate wiring layer 150 in a plan view. The peripheral deep well region 166 faces the gate wiring layer 150 with the gate insulating layer 148 (third region 148c) in between.

The peripheral deep well region 166 includes an extension portion 166a that is extended from each contact trench portion 144 to each active trench portion 143. The extension portion 166a is formed in the high concentration region 108 of the SiC epitaxial layer 107. The extension portion 166a extends along the sidewall of each active trench portion 143, passing through the corners to cover the bottom wall of the active trench portion 143.

The pull-out portion 166a covers the sidewalls of the active trench portion 143 of each gate trench 142. The pull-out portion 166a covers the corners that connect the sidewalls and bottom wall of each active trench portion 143.

The extension portion 166a covers the sidewalls and the bottom wall of each active trench portion 143 through the corners of each active trench portion 143. The extension portion 166a is connected to the body region 141 at the sidewall of each active trench portion 143. The bottom of the extension portion 166a is located on the second main surface 104 side of the SiC semiconductor layer 102 relative to the bottom wall of each active trench portion 143.

The p-type impurity concentration of the peripheral deep well region 166 may be approximately equal to the p-type impurity concentration of the body region 141. The p-type impurity concentration of the peripheral deep well region 166 may be greater than the p-type impurity concentration of the body region 141. The p-type impurity concentration of the peripheral deep well region 166 may be less than the p-type impurity concentration of the body region 141.

The p-type impurity concentration of the peripheral deep well region 166 may be approximately equal to the p-type impurity concentration of each deep well region 165. The p-type impurity concentration of the peripheral deep well region 166 may be greater than the p-type impurity concentration of each deep well region 165. The p-type impurity concentration of the peripheral deep well region 166 may be less than the p-type impurity concentration of each deep well region 165.

The p-type impurity concentration of the peripheral deep well region 166 may be equal to or lower than the p-type impurity concentration of the contact region 164. The p-type impurity concentration of the peripheral deep well region 166 may be lower than the p-type impurity concentration of the contact region 164. The p-type impurity concentration of the peripheral deep well region 166 may be equal to or higher than 1.0×10 ¹⁷ cm ⁻³ and equal to or lower than 1.0×10 ¹⁹ cm ⁻³ .

In a SiC semiconductor device that has only a pn junction diode, the problem of electric field concentration in the SiC semiconductor layer 102 is minimal because the device does not have a trench. Each deep well region 165 (peripheral deep well region 166) brings the trench gate type MISFET closer to the structure of a pn junction diode.

This allows the electric field in the SiC semiconductor layer 102 to be alleviated in a trench-gate MISFET. Therefore, narrowing the pitch between adjacent deep well regions 165 is effective in alleviating electric field concentration.

In addition, each deep well region 165 has a bottom on the second main surface 104 side of the SiC semiconductor layer 102 relative to the bottom wall of each gate trench 142, and the depletion layer can appropriately reduce electric field concentration in each gate trench 142.

It is preferable that the distance between the bottom of each deep well region 165 and the second main surface 104 of the SiC semiconductor layer 102 is approximately constant. This makes it possible to suppress variation in the distance between the bottom of each deep well region 165 and the second main surface 104 of the SiC semiconductor layer 102.

This makes it possible to prevent the breakdown voltage (e.g., breakdown resistance) of the SiC semiconductor layer 102 from being limited by the shape of each deep well region 165, thereby enabling the breakdown voltage to be appropriately improved.

In this embodiment, a high concentration region 108 of the SiC epitaxial layer 107 is interposed between adjacent deep well regions 165. This reduces the JFET (junction field effect transistor) resistance in the region between adjacent deep well regions 165.

Furthermore, in this embodiment, the bottom of each deep well region 165 is located within the high concentration region 108 of the SiC epitaxial layer 107. This allows the current path to extend from the bottom of each deep well region 165 in a lateral direction parallel to the first main surface 103 of the SiC semiconductor layer 102. This reduces the current spreading resistance. In this structure, the low concentration region 109 of the SiC epitaxial layer 107 increases the breakdown voltage of the SiC semiconductor layer 102.

By forming the source trenches 155, p-type impurities can be introduced into the inner walls of the source trenches 155. This allows each deep well region 165 to be formed conformally to the source trenches 155, so that variations in the depth of each deep well region 165 can be appropriately suppressed. In addition, by using each source trench 155, each deep well region 165 can be appropriately formed in a relatively deep region of the SiC semiconductor layer 102.

Referring to FIG. 21, a low-resistance electrode layer 167 is formed on the gate electrode layer 149. The low-resistance electrode layer 167 covers the upper end of the gate electrode layer 149 in each gate trench 142.

The low resistance electrode layer 167 includes a conductive material having a sheet resistance less than the sheet resistance of the gate electrode layer 149. The sheet resistance of the low resistance electrode layer 167 may be 0.01 Ω/□ or more and 10 Ω/□ or less.

The low resistance electrode layer 167 is formed in a film shape. The low resistance electrode layer 167 has a connection portion 167a that contacts the upper end of the gate electrode layer 149 and a non-connection portion 167b on the opposite side. The connection portion 167a and the non-connection portion 167b of the low resistance electrode layer 167 may be formed in a concave curved shape following the upper end of the gate electrode layer 149. The connection portion 167a and the non-connection portion 167b of the low resistance electrode layer 167 may take various forms.

The entire connection portion 167a of the low resistance electrode layer 167 may be located above the first main surface 103 of the SiC semiconductor layer 102. The entire connection portion 167a of the low resistance electrode layer 167 may be located below the first main surface 103 of the SiC semiconductor layer 102.

The connection portion 167a of the low resistance electrode layer 167 may include a portion located above the first main surface 103 of the SiC semiconductor layer 102. The connection portion 167a of the low resistance electrode layer 167 may include a portion located below the first main surface 103 of the SiC semiconductor layer 102.

For example, the center of the connection portion 167a of the low resistance electrode layer 167 may be located below the first main surface 103 of the SiC semiconductor layer 102, and the peripheral portion of the connection portion 167a of the low resistance electrode layer 167 may be located above the first main surface 103 of the SiC semiconductor layer 102.

The entire non-connected portion 167b of the low resistance electrode layer 167 may be located above the first main surface 103 of the SiC semiconductor layer 102. The entire non-connected portion 167b of the low resistance electrode layer 167 may be located below the first main surface 103 of the SiC semiconductor layer 102.

The non-connected portion 167b of the low resistance electrode layer 167 may include a portion located above the first main surface 103 of the SiC semiconductor layer 102. The non-connected portion 167b of the low resistance electrode layer 167 may include a portion located below the first main surface 103 of the SiC semiconductor layer 102.

For example, the center of the non-connected portion 167b of the low-resistance electrode layer 167 may be located below the first main surface 103 of the SiC semiconductor layer 102, and the peripheral portion of the non-connected portion 167b of the low-resistance electrode layer 167 may be located above the first main surface 103 of the SiC semiconductor layer 102.

The low resistance electrode layer 167 has an edge 167c that contacts the gate insulating layer 148. The edge 167c of the low resistance electrode layer 167 contacts a corner of the gate insulating layer 148 that connects the first region 148a and the second region 148b.

The edge 167c of the low resistance electrode layer 167 is in contact with the third region 148c of the gate insulating layer 148. More specifically, the edge 167c of the low resistance electrode layer 167 is in contact with the bulge 148d of the gate insulating layer 148.

The edge portion 167c of the low resistance electrode layer 167 is formed in a region on the first main surface 103 side of the SiC semiconductor layer 102 relative to the bottom of the source region 163. The edge portion 167c of the low resistance electrode layer 167 is formed in a region on the first main surface 103 side of the SiC semiconductor layer 102 relative to the boundary region between the body region 141 and the source region 163.

Therefore, the edge 167c of the low resistance electrode layer 167 faces the source region 163 across the gate insulating layer 148. The edge 167c of the low resistance electrode layer 167 does not face the body region 141 across the gate insulating layer 148.

This makes it possible to suppress the formation of a current path in the region between the low resistance electrode layer 167 and the body region 141 in the gate insulating layer 148. The current path may be formed by undesired diffusion of the electrode material of the low resistance electrode layer 167 into the gate insulating layer 148.

In particular, a design that connects the edge 167c of the low resistance electrode layer 167 to the third region 148c (corner of the gate insulation layer 148) of the relatively thick gate insulation layer 148 is effective in reducing the risk of a current path being formed.

In the normal direction Z, the thickness Tr of the low resistance electrode layer 167 is equal to or less than the thickness TG of the gate electrode layer 149 (Tr≦TG). The thickness Tr of the low resistance electrode layer 167 is preferably less than the thickness TG of the gate electrode layer 149 (Tr<TG). More specifically, the thickness Tr of the low resistance electrode layer 167 is preferably equal to or less than half the thickness TG of the gate electrode layer 149 (Tr≦TG/2).

The ratio Tr/TG of the thickness Tr of the low resistance electrode layer 167 to the thickness TG of the gate electrode layer 149 is 0.01 or more and 1 or less. The thickness TG of the gate electrode layer 149 may be 0.5 μm or more and 3 μm or less. The thickness Tr of the low resistance electrode layer 167 may be 0.01 μm or more and 3 μm or less.

The current supplied to each gate trench 142 flows through the low resistance electrode layer 167, which has a relatively low sheet resistance, and is transmitted to the entire gate electrode layer 149. This allows the entire gate electrode layer 149 (the entire active region 111) to be quickly transitioned from the OFF state to the ON state, thereby suppressing delays in the switching response.

In particular, in the case of gate trenches 142 having a length on the order of millimeters (length of 1 mm or more), it takes time for the current to be transmitted, but the low-resistance electrode layer 167 can appropriately suppress delays in the switching response. In other words, the low-resistance electrode layer 167 is formed as a current diffusion electrode layer that diffuses the current within each gate trench 142.

In addition, as the cell structure becomes finer, the width, depth, cross-sectional area, etc. of the gate electrode layer 149 become smaller, which raises concerns about delayed switching response due to increased electrical resistance within each gate trench 142.

However, the low-resistance electrode layer 167 allows the entire gate electrode layer 149 to be quickly switched from the OFF state to the ON state, so that delays in switching response caused by miniaturization can be appropriately suppressed.

Referring to FIG. 20, in this embodiment, the low resistance electrode layer 167 also covers the upper end of the gate wiring layer 150. The portion of the low resistance electrode layer 167 that covers the upper end of the gate wiring layer 150 is integrally formed with the portion of the low resistance electrode layer 167 that covers the upper end of the gate electrode layer 149. As a result, the low resistance electrode layer 167 covers the entire area of the gate electrode layer 149 and the entire area of the gate wiring layer 150.

Therefore, the current supplied to the gate wiring layer 150 from the gate pad 116 and the gate fingers 117 and 118 is transmitted to the entire gate electrode layer 149 and the gate wiring layer 150 via the low resistance electrode layer 167, which has a relatively low sheet resistance.

This allows the entire gate electrode layer 149 (the entire active region 111) to be quickly switched from an OFF state to an ON state via the gate wiring layer 150, thereby suppressing delays in switching response.

In particular, in the case of a gate trench 142 having a length on the order of millimeters, the delay in switching response can be appropriately suppressed by the low-resistance electrode layer 167 covering the upper end of the gate wiring layer 150.

The low resistance electrode layer 167 includes a polycide layer. The polycide layer is formed by silicidating the portion forming the surface layer of the gate electrode layer 149 with a metal material. More specifically, the polycide layer is made of a p-type polycide layer containing p-type impurities added to the gate electrode layer 149 (p-type polysilicon). The polycide layer preferably has a resistivity of 10 μΩ·cm or more and 110 μΩ·cm or less.

The sheet resistance in the gate trench 142 in which the gate electrode layer 149 and the low resistance electrode layer 167 are embedded is equal to or less than the sheet resistance of the gate electrode layer 149 alone. It is preferable that the sheet resistance in the gate trench 142 is equal to or less than the sheet resistance of n-type polysilicon doped with n-type impurities.

The sheet resistance in the gate trench 142 is approximated to the sheet resistance of the low resistance electrode layer 167. That is, the sheet resistance in the gate trench 142 may be 0.01 Ω/□ or more and 10 Ω/□ or less. It is preferable that the sheet resistance in the gate trench 142 is less than 10 Ω/□.

The low resistance electrode layer 167 may contain at least one of TiSi, TiSi ₂ , NiSi, CoSi, CoSi ₂ , MoSi ₂ , and WSi _2. Among these species, NiSi, CoSi ₂ and TiSi ₂ are particularly suitable as a polycide layer forming the low resistance electrode layer 167 because they have relatively small resistivity values and temperature dependences.

In the first main surface 103 of the SiC semiconductor layer 102, a source sub-trench 168 that communicates with each source trench 155 is formed in a region along the upper end of the source electrode layer 157. The source sub-trench 168 forms part of the sidewall of each source trench 155.

In this embodiment, the source sub-trench 168 is formed in an endless shape (in this embodiment, a square ring shape) that surrounds the upper end of the source electrode layer 157 in a plan view. The source sub-trench 168 borders the upper end of the source electrode layer 157.

The source sub-trench 168 is formed by digging down a portion of the source insulating layer 156. More specifically, the source sub-trench 168 is formed by digging down the upper end of the source insulating layer 156 and the upper end of the source electrode layer 157 from the first main surface 103 of the SiC semiconductor layer 102.

The upper end of the source electrode layer 157 has a shape that is narrowed inward relative to the lower end of the source electrode layer 157. The lower end of the source electrode layer 157 is a portion of the source electrode layer 157 that is located on the bottom wall side of each source trench 155. The width in the first direction of the upper end of the source electrode layer 157 may be less than the width in the first direction of the lower end of the source electrode layer 157.

The source sub-trench 168 is formed in a tapered shape in which the bottom area is smaller than the opening area in a cross-sectional view. The bottom wall of the source sub-trench 168 may be formed in a convex curved shape toward the second main surface 104 of the SiC semiconductor layer 102.

The source region 163, the contact region 164, the source insulating layer 156, and the source electrode layer 157 are exposed from the inner wall of the source sub-trench 168. The first surface region 164a and the second surface region 164b of the contact region 164 are exposed from the inner wall of the source sub-trench 168.

At least the first region 156a of the source insulating layer 156 is exposed from the bottom wall of the source sub-trench 168. The upper end of the first region 156a of the source insulating layer 156 is located below the first main surface 103 of the SiC semiconductor layer 102.

The opening edge portion 169 of each source trench 155 includes a slope portion 170 that slopes downward from the first main surface 103 of the SiC semiconductor layer 102 toward the inside of each source trench 155. The opening edge portion 169 of each source trench 155 is a corner portion that connects the first main surface 103 of the SiC semiconductor layer 102 and the sidewall of each source trench 155. The slope portion 170 of each source trench 155 is formed by a source sub-trench 168.

In this embodiment, the inclined portion 170 is formed in a concave curved shape toward the inside of the SiC semiconductor layer 102. The inclined portion 170 may be formed in a convex curved shape toward the inside of the source sub-trench 168. The inclined portion 170 reduces electric field concentration at the opening edge portion 169 of each source trench 155.

22 and 23, the active region 111 has an active main surface 171 that forms part of the first main surface 103 of the SiC semiconductor layer 102. The outer region 112 has an outer main surface 172 that forms part of the first main surface 103 of the SiC semiconductor layer 102. In this embodiment, the outer main surface 172 is connected to the side surfaces 105A to 105D of the SiC semiconductor layer 102.

The active principal surface 171 and the outer principal surface 172 each face the c-plane of the SiC single crystal. In addition, the active principal surface 171 and the outer principal surface 172 each have an off angle θ inclined in the [11-20] direction with respect to the c-plane of the SiC single crystal.

The outer principal surface 172 is located on the second principal surface 104 side of the SiC semiconductor layer 102 relative to the active principal surface 171. In this embodiment, the outer region 112 is formed by digging the first principal surface 103 of the SiC semiconductor layer 102 toward the second principal surface 104 side. Therefore, the outer principal surface 172 is formed in a region recessed toward the second principal surface 104 side of the SiC semiconductor layer 102 relative to the active principal surface 171.

The outer major surface 172 may be located on the second major surface 104 side of the SiC semiconductor layer 102 relative to the bottom wall of each gate trench 142. The outer major surface 172 may be formed at a depth position approximately equal to the bottom wall of each source trench 155. The outer major surface 172 may be located on approximately the same plane as the bottom wall of each source trench 155.

The distance between the outer major surface 172 and the second major surface 104 of the SiC semiconductor layer 102 may be approximately equal to the distance between the bottom wall of each source trench 155 and the second major surface 104 of the SiC semiconductor layer 102.

The outer major surface 172 may be located on the second major surface 104 side of the SiC semiconductor layer 102 relative to the bottom wall of each source trench 155. The outer major surface 172 may be located on the second major surface 104 side of the SiC semiconductor layer 102 within a range of 0 μm to 1 μm relative to the bottom wall of each source trench 155.

The SiC epitaxial layer 107 is exposed from the outer major surface 172. More specifically, the high concentration region 108 of the SiC epitaxial layer 107 is exposed from the outer major surface 172 of the outer region 112. The outer major surface 172 faces the low concentration region 109 of the SiC epitaxial layer 107 across the high concentration region 108 of the SiC epitaxial layer 107.

In this embodiment, the active region 111 is partitioned into a plateau shape by the outer region 112. The active region 111 is formed as an active plateau 173 that protrudes upward from the outer region 112.

The active plateau 173 includes an active sidewall 174 that connects the active main surface 171 and the outer main surface 172. The active sidewall 174 defines a boundary region between the active region 111 and the outer region 112. The first main surface 103 of the SiC semiconductor layer 102 is formed by the active main surface 171, the outer main surface 172, and the active sidewall 174.

In this embodiment, the active sidewall 174 extends along the normal direction Z of the active main surface 171 (outer main surface 172). The active sidewall 174 is formed by the m-plane and a-plane of the SiC single crystal.

The active sidewall 174 may have an inclined surface that slopes downward from the active main surface 171 toward the outer main surface 172. The inclination angle of the active sidewall 174 is the angle that the active sidewall 174 forms with the active main surface 171 within the SiC semiconductor layer 102.

In this case, the inclination angle of the active sidewall 174 may be greater than 90° and less than or equal to 135°. The inclination angle of the active sidewall 174 may be greater than 90° and less than or equal to 95°, greater than or equal to 95° and less than or equal to 100°, greater than or equal to 100° and less than or equal to 110°, greater than or equal to 110° and less than or equal to 120°, or greater than or equal to 120° and less than or equal to 135°. It is preferable that the inclination angle of the active sidewall 174 is greater than 90° and less than or equal to 95°.

The SiC epitaxial layer 107 is exposed from the active sidewall 174. More specifically, the high concentration region 108 of the SiC epitaxial layer 107 is exposed from the active sidewall 174.

At least the body region 141 is exposed from the region of the active sidewall 174 on the active main surface 171 side. Figures 22 and 23 show an example in which the body region 141 and the source region 163 are exposed from the active sidewall 174.

In the outer region 112, a p ⁺ type diode region 181 (impurity region), a p-type outer deep well region 182, and a p-type field limit structure 183 are formed in the surface layer portion of the first main surface 103 (outer main surface 172) of the SiC semiconductor layer 102.

The diode region 181 is formed in the outer region 112 in the region between the active sidewall 174 and the side surfaces 105A-105D of the SiC semiconductor layer 102. The diode region 181 is formed at a distance from the active sidewall 174 and the side surfaces 105A-105D.

The diode region 181 extends in a band shape along the active region 111 in a plan view. In this embodiment, the diode region 181 is formed in an endless shape (a square ring shape in this embodiment) surrounding the active region 111 in a plan view.

The diode region 181 overlaps with the source lead-out wiring 123 in a plan view. The diode region 181 is electrically connected to the source lead-out wiring 123. The diode region 181 forms part of the avalanche current absorption structure.

The diode region 181 forms a pn junction with the SiC semiconductor layer 102. More specifically, the diode region 181 is located within the SiC epitaxial layer 107. Thus, the diode region 181 forms a pn junction with the SiC epitaxial layer 107.

More specifically, the diode region 181 is located within the high concentration region 108 of the SiC epitaxial layer 107. Therefore, the diode region 181 forms a pn junction with the high concentration region 108. This forms a pn junction diode Dpn with the diode region 181 as the anode and the SiC semiconductor layer 102 as the cathode.

The entire diode region 181 is located on the second major surface 104 side of the SiC semiconductor layer 102 relative to the bottom wall of each gate trench 142. The bottom of the diode region 181 is located on the second major surface 104 side of the SiC semiconductor layer 102 relative to the bottom wall of each source trench 155.

The bottom of the diode region 181 may be formed at a depth substantially equal to the bottom of the contact region 164. The bottom of the diode region 181 may be located on substantially the same plane as the bottom of the contact region 164.

The p-type impurity concentration of the diode region 181 is approximately equal to the p-type impurity concentration of the contact region 164. The p-type impurity concentration of the diode region 181 is greater than the p-type impurity concentration of the body region 141. The p-type impurity concentration of the diode region 181 may be not less than 1.0×10 ¹⁸ cm ⁻³ and not more than 1.0×10 ²¹ cm ⁻³ .

The outer deep well region 182 is formed in a region between the active sidewall 174 and the diode region 181 in a plan view. In this embodiment, the outer deep well region 182 is formed at a distance from the active sidewall 174 toward the diode region 181. The outer deep well region 182 is also referred to as a breakdown voltage adjustment region (breakdown voltage holding region) that adjusts the breakdown voltage of the SiC semiconductor layer 102 in the outer region 112.

The outer deep well region 182 extends in a band shape along the active region 111 in a plan view. In this embodiment, the outer deep well region 182 is formed in an endless shape (a square ring shape in this embodiment) surrounding the active region 111 in a plan view.

The outer deep well region 182 is electrically connected to the source lead-out wiring 123 via the diode region 181. The outer deep well region 182 may form part of a pn junction diode Dpn. The outer deep well region 182 may form part of an avalanche current absorption structure.

The entire outer deep well region 182 is located on the second major surface 104 side of the SiC semiconductor layer 102 relative to the bottom wall of each gate trench 142. The bottom of the outer deep well region 182 is located on the second major surface 104 side of the SiC semiconductor layer 102 relative to the bottom wall of each source trench 155.

The bottom of the outer deep well region 182 is located on the second main surface 104 side of the SiC semiconductor layer 102 relative to the bottom of the diode region 181. The bottom of the outer deep well region 182 may be formed at a depth position approximately equal to the bottom of each deep well region 165. The bottom of the outer deep well region 182 may be located on approximately the same plane as the bottom of each deep well region 165.

The distance between the bottom of the outer deep well region 182 and the outer major surface 172 may be approximately equal to the distance between the bottom of each deep well region 165 and the bottom wall of each source trench 155.

The distance between the bottom of the outer deep well region 182 and the second major surface 104 of the SiC semiconductor layer 102 may be approximately equal to the distance between the bottom of each deep well region 165 and the second major surface 104 of the SiC semiconductor layer 102.

This makes it possible to suppress variation between the distance between the bottom of the outer deep well region 182 and the second main surface 104 of the SiC semiconductor layer 102 and the distance between the bottom of each deep well region 165 and the second main surface 104 of the SiC semiconductor layer 102.

This makes it possible to prevent the breakdown voltage (e.g., breakdown resistance) of the SiC semiconductor layer 102 from being limited by the shape of the outer deep well region 182 and the shape of each deep well region 165, thereby enabling the breakdown voltage to be appropriately improved.

The bottom of the outer deep well region 182 may be located on the second main surface 104 side of the SiC semiconductor layer 102 relative to the bottom of each deep well region 165. The bottom of the outer deep well region 182 may be located on the second main surface 104 side of the SiC semiconductor layer 102 within a range of 0 μm to 1 μm relative to the bottom of each deep well region 165.

The inner edge of the outer deep well region 182 may extend to near the boundary region between the active region 111 and the outer region 112. The outer deep well region 182 may cross the boundary region between the active region 111 and the outer region 112.

The inner edge of the outer deep well region 182 may cover the corner connecting the active sidewall 174 and the outer major surface 172. The inner edge of the outer deep well region 182 may further extend along the active sidewall 174 and connect to the body region 141.

In this embodiment, the outer peripheral edge of the outer deep well region 182 covers the diode region 181 from the second main surface 104 side of the SiC semiconductor layer 102. The outer deep well region 182 may overlap the source lead-out wiring 123 in a plan view. The outer peripheral edge of the outer deep well region 182 may be formed at a distance from the diode region 181 toward the active sidewall 174.

The p-type impurity concentration of the outer deep well region 182 may be equal to or less than the p-type impurity concentration of the diode region 181. The p-type impurity concentration of the outer deep well region 182 may be less than the p-type impurity concentration of the diode region 181.

The p-type impurity concentration of the outer deep well region 182 may be approximately equal to the p-type impurity concentration of each deep well region 165. The p-type impurity concentration of the outer deep well region 182 may be approximately equal to the p-type impurity concentration of the body region 141.

The p-type impurity concentration of the outer deep well region 182 may be greater than the p-type impurity concentration of the body region 141. The p-type impurity concentration of the outer deep well region 182 may be less than the p-type impurity concentration of the body region 141.

The p-type impurity concentration of the outer deep well region 182 may be equal to or lower than the p-type impurity concentration of the contact region 164. The p-type impurity concentration of the outer deep well region 182 may be lower than the p-type impurity concentration of the contact region 164. The p-type impurity concentration of the outer deep well region 182 may be equal to or higher than 1.0×10 ¹⁷ cm ⁻³ and equal to or lower than 1.0×10 ¹⁹ cm ⁻³ .

The field limit structure 183 is formed in a region between the diode region 181 and the side surfaces 105A-105D of the SiC semiconductor layer 102 in a plan view. In this embodiment, the field limit structure 183 is formed at a distance from the side surfaces 105A-105D toward the diode region 181.

The field limit structure 183 includes one or more (e.g., 2 to 20) field limit regions 184. In this embodiment, the field limit structure 183 includes a field limit region group having multiple (5) field limit regions 184A, 184B, 184C, 184D, and 184E.

The field limit regions 184A to 184E are formed in this order at intervals in a direction away from the diode region 181. The field limit regions 184A to 184E each extend in a band shape along the periphery of the active region 111 in a plan view.

More specifically, the field limit regions 184A to 184E are each formed in an endless shape (in this embodiment, a square ring shape) surrounding the active region 111 in a plan view. The field limit regions 184A to 184E are also referred to as FLR (Field Limiting Ring) regions.

In this embodiment, the bottoms of the field limit regions 184A-184E are located on the second main surface 104 side of the SiC semiconductor layer 102 relative to the bottom of the diode region 181.

In this embodiment, the innermost field limit region 184A of the field limit regions 184A to 184E covers the diode region 181 from the second main surface 104 side of the SiC semiconductor layer 102. The field limit region 184A may overlap the aforementioned source lead-out wiring 123 in a plan view.

The field limit region 184A is electrically connected to the source lead-out wiring 123 via the diode region 181. The field limit region 184A may form part of the pn junction diode Dpn. The field limit region 184A may form part of the avalanche current absorption structure.

The entire field limit regions 184A-184E are located on the second main surface 104 side of the SiC semiconductor layer 102 relative to the bottom wall of each gate trench 142. The bottoms of the field limit regions 184A-184E are located on the second main surface 104 side of the SiC semiconductor layer 102 relative to the bottom wall of each source trench 155.

The field limit regions 184A-184E may be formed at a depth substantially equal to that of each deep well region 165 (outer deep well region 182). The bottoms of the field limit regions 184A-184E may be located on substantially the same plane as the bottoms of each deep well region 165 (outer deep well region 182).

The bottoms of the field limit regions 184A-184E may be located on the outer main surface 172 side relative to the bottoms of the respective deep well regions 165 (outer deep well regions 182). The bottoms of the field limit regions 184A-184E may be located on the second main surface 104 side of the SiC semiconductor layer 102 relative to the bottoms of the respective deep well regions 165 (outer deep well regions 182).

The width between adjacent field limit regions 184A-184E may be different from each other. The width between adjacent field limit regions 184A-184E may be larger in the direction away from the active region 111. The width between adjacent field limit regions 184A-184E may be smaller in the direction away from the active region 111.

The depths of the field limit regions 184A-184E may be different from each other. The depths of the field limit regions 184A-184E may decrease in a direction away from the active region 111. The depths of the field limit regions 184A-184E may increase in a direction away from the active region 111.

The p-type impurity concentration of the field limit regions 184A to 184E may be equal to or lower than the p-type impurity concentration of the diode region 181. The p-type impurity concentration of the field limit regions 184A to 184E may be lower than the p-type impurity concentration of the diode region 181.

The p-type impurity concentration of the field limit regions 184A-184E may be equal to or less than the p-type impurity concentration of the outer deep well region 182. The p-type impurity concentration of the field limit regions 184A-184E may be less than the p-type impurity concentration of the outer deep well region 182.

The p-type impurity concentration of the field limit regions 184A-184E may be equal to or greater than the p-type impurity concentration of the outer deep well region 182. The p-type impurity concentration of the field limit regions 184A-184E may be greater than the p-type impurity concentration of the outer deep well region 182.

The p-type impurity concentration of the field limit regions 184A to 184E may be 1.0×10 ¹⁵ cm ⁻³ or more and 1.0×10 ¹⁸ cm ⁻³ or less. It is preferable that the p-type impurity concentration of the diode region 181>the p-type impurity concentration of the outer deep well region 182>the p-type impurity concentration of the field limit regions 184A to 184E.

The field limit structure 183 relieves electric field concentration in the outer region 112. The number, width, depth, p-type impurity concentration, etc. of the field limit regions 184 can take various values depending on the electric field to be relieved.

In this embodiment, an example has been described in which the field limit structure 183 includes one or more field limit regions 184 formed in the region between the diode region 181 and the side surfaces 105A to 105D of the SiC semiconductor layer 102 in a planar view.

However, the field limit structure 183 may include one or more field limit regions 184 formed in the region between the active sidewall 174 and the diode region 181 in a plan view, instead of the region between the diode region 181 and the side surfaces 105A-105D of the SiC semiconductor layer 102.

The field limit structure 183 may also include one or more field limit regions 184 formed in a region between the diode region 181 and the side surfaces 105A-105D of the SiC semiconductor layer 102 in a planar view, and one or more field limit regions 184 formed in a region between the active sidewall 174 and the diode region 181 in a planar view.

In the outer region 112, an outer insulating layer 191 is formed on the first main surface 103 of the SiC semiconductor layer 102. The outer insulating layer 191 forms part of the main surface insulating layer 113. The outer insulating layer 191 forms part of the insulating side surfaces 114A to 114D of the main surface insulating layer 113.

The outer insulating layer 191 selectively covers the diode region 181, the outer deep well region 182, and the field limit structure 183 in the outer region 112. The outer insulating layer 191 is formed in a film shape along the active sidewall 174 and the outer main surface 172. The outer insulating layer 191 is continuous with the gate insulating layer 148 on the active main surface 171. More specifically, the outer insulating layer 191 is continuous with the third region 148c of the gate insulating layer 148.

The outer insulating layer 191 may include silicon oxide. The outer insulating layer 191 may include other insulating films such as silicon nitride. In this embodiment, the outer insulating layer 191 is formed of the same insulating material type as the gate insulating layer 148.

The outer insulating layer 191 includes a first region 191a and a second region 191b. The first region 191a of the outer insulating layer 191 covers the active sidewall 174. The second region 191b of the outer insulating layer 191 covers the outer main surface 172.

The thickness of the second region 191b of the outer insulating layer 191 may be less than or equal to the thickness of the first region 191a of the outer insulating layer 191. The thickness of the second region 191b of the outer insulating layer 191 may be less than the thickness of the first region 191a of the outer insulating layer 191.

The thickness of the first region 191a of the outer insulating layer 191 may be approximately equal to the thickness of the first region 191a of the gate insulating layer 148. The thickness of the second region 191b of the outer insulating layer 191 may be approximately equal to the thickness of the third region 148c of the gate insulating layer 148. Of course, the outer insulating layer 191 may be formed to have a uniform thickness.

22 and 23, the SiC semiconductor device 101 further includes a sidewall 192 that covers the active sidewall 174. The sidewall 192 protects and reinforces the active plateau 173 from the outer region 112 side.

The sidewalls 192 also form a step reduction structure that reduces the step formed between the active main surface 171 and the outer main surface 172. When an upper layer structure (covering layer) is formed that covers the boundary region between the active region 111 and the outer region 112, the upper layer structure covers the sidewalls 192. The sidewalls 192 increase the flatness of the upper layer structure.

The sidewall 192 may have an inclined portion 193 that slopes downward from the active main surface 171 toward the outer main surface 172. The inclined portion 193 can appropriately reduce the step.

The inclined portion 193 of the sidewall 192 may be formed in a concave curve toward the SiC semiconductor layer 102. The inclined portion 193 of the sidewall 192 may be formed in a convex curve toward the opposite side to the SiC semiconductor layer 102.

The inclined portion 193 of the sidewall 192 may extend in a plane from the active principal surface 171 side toward the outer principal surface 172 side. The inclined portion 193 of the sidewall 192 may extend in a straight line from the active principal surface 171 side toward the outer principal surface 172 side.

The inclined portion 193 of the sidewall 192 may be formed in a step-like shape descending from the active principal surface 171 toward the outer principal surface 172. The inclined portion 193 of the sidewall 192 may have one or more steps recessed toward the outer principal surface 172. The multiple steps increase the surface area of the inclined portion 193 of the sidewall 192, enhancing adhesion to the upper layer structure.

The inclined portion 193 of the sidewall 192 may include multiple ridges that rise toward the outside of the sidewall 192. The multiple ridges increase the surface area of the inclined portion 193 of the sidewall 192, enhancing adhesion to the upper layer structure.

The inclined portion 193 of the sidewall 192 may include multiple recesses recessed toward the inside of the sidewall 192. The multiple recesses increase the surface area of the inclined portion 193 of the sidewall 192 and increase adhesion to the upper layer structure.

The sidewall 192 is formed in a self-aligned manner with respect to the active main surface 171. More specifically, the sidewall 192 is formed along the active sidewall 174. In this embodiment, the sidewall 192 is formed in an endless shape (a square ring in this embodiment) surrounding the active region 111 in a plan view.

The sidewall 192 preferably includes p-type polysilicon doped with p-type impurities. In this case, the sidewall 192 can be formed simultaneously with the gate electrode layer 149 and the source electrode layer 157.

The p-type impurity concentration of the sidewall 192 is equal to or greater than the p-type impurity concentration of the body region 141. More specifically, the p-type impurity concentration of the sidewall 192 is greater than the p-type impurity concentration of the body region 141. The p-type impurity of the sidewall 192 may include at least one of boron (B), aluminum (Al), indium (In), or gallium (Ga).

The p-type impurity concentration of the sidewall 192 may be 1×10 ¹⁸ cm ⁻³ or more and 1×10 ²² cm ⁻³ or less. The sheet resistance of the sidewall 192 may be 10 Ω/□ or more and 500 Ω/□ or less (about 200 Ω/□ in this embodiment).

The p-type impurity concentration of the sidewall 192 may be approximately equal to the p-type impurity concentration of the gate electrode layer 149. The sheet resistance of the sidewall 192 may be approximately equal to the sheet resistance of the gate electrode layer 149.

The sidewall 192 may contain n-type polysilicon instead of or in addition to p-type polysilicon. The sidewall 192 may contain at least one of tungsten, aluminum, copper, an aluminum alloy, or a copper alloy instead of or in addition to p-type polysilicon.

The sidewalls 192 may contain an insulating material. In this case, the sidewalls 192 can increase the insulation of the active region 111 from the outer region 112.

With reference to Figures 19 to 23, an interlayer insulating layer 201 is formed on the first main surface 103 of the SiC semiconductor layer 102. The interlayer insulating layer 201 forms part of the main surface insulating layer 113. The interlayer insulating layer 201 forms part of the insulating side surfaces 114A to 114D of the main surface insulating layer 113. The main surface insulating layer 113 has a layered structure including the gate insulating layer 148 (outer insulating layer 191) and the interlayer insulating layer 201.

The interlayer insulating layer 201 selectively covers the active region 111 and the outer region 112. More specifically, the interlayer insulating layer 201 selectively covers the third region 148c of the gate insulating layer 148 and the outer insulating layer 191.

The interlayer insulating layer 201 is formed in a film shape along the active principal surface 171 and the outer principal surface 172. The interlayer insulating layer 201 selectively covers the trench gate structure 161, the gate wiring layer 150, and the trench source structure 162 in the active region 111. The interlayer insulating layer 201 selectively covers the diode region 181, the outer deep well region 182, and the field limit structure 183 in the outer region 112.

The interlayer insulating layer 201 is formed along the outer surface (inclined portion 193) of the sidewall 192 in the boundary region between the active region 111 and the outer region 112. The interlayer insulating layer 201 forms part of an upper layer structure that covers the sidewall 192.

The interlayer insulating layer 201 may contain silicon oxide or silicon nitride. The interlayer insulating layer 201 may contain PSG (Phosphor Silicate Glass) and/or BPSG (Boron Phosphor Silicate Glass) as examples of silicon oxide.

The interlayer insulating layer 201 may have a laminated structure including a PSG layer and a BPSG layer laminated in this order from the first main surface 103 side of the SiC semiconductor layer 102. The interlayer insulating layer 201 may have a laminated structure including a BPSG layer and a PSG layer laminated in this order from the first main surface 103 side of the SiC semiconductor layer 102.

The interlayer insulating layer 201 has a gate contact hole 202, a source contact hole 203, and a diode contact hole 204 formed therein. The interlayer insulating layer 201 also has an anchor hole 205 formed therein.

The gate contact hole 202 exposes the gate wiring layer 150 in the active region 111. The gate contact hole 202 may be formed in a strip shape along the gate wiring layer 150. The opening edge portion of the gate contact hole 202 is formed in a convex curved shape toward the inside of the gate contact hole 202.

The source contact hole 203 exposes the source region 163, the contact region 164, and the trench source structure 162 in the active region 111. The source contact hole 203 may be formed in a strip shape along the trench source structure 162, etc. The opening edge portion of the source contact hole 203 is formed in a convex curved shape toward the inside of the source contact hole 203.

The diode contact hole 204 exposes the diode region 181 in the outer region 112. The diode contact hole 204 may be formed in a strip shape (more specifically, endless) extending along the diode region 181.

The diode contact hole 204 may expose the outer deep well region 182 and/or the field limit structure 183. The opening edge of the diode contact hole 204 is formed with a convex curve toward the inside of the diode contact hole 204.

The anchor hole 205 is formed by digging down the interlayer insulating layer 201 in the outer region 112. The anchor hole 205 is formed in the region between the diode region 181 and the side surfaces 105A to 105D of the SiC semiconductor layer 102 in a planar view. More specifically, the anchor hole 205 is formed in the region between the field limit structure 183 and the side surfaces 105A to 105D of the SiC semiconductor layer 102 in a planar view.

The anchor hole 205 exposes the first main surface 103 (outer main surface 172) of the SiC semiconductor layer 102. The opening edge of the anchor hole 205 is formed in a convex curve toward the inside of the anchor hole 205.

Referring to FIG. 17, the anchor hole 205 extends in a band shape along the active region 111 in a plan view. In this embodiment, the anchor hole 205 is formed in an endless shape (a square ring shape in this embodiment) surrounding the active region 111 in a plan view.

In this embodiment, one anchor hole 205 is formed in the portion of the interlayer insulating layer 201 that covers the outer region 112. However, multiple anchor holes 205 may be formed in the portion of the interlayer insulating layer 201 that covers the outer region 112.

A principal surface gate electrode layer 115 and a principal surface source electrode layer 121 are formed on the interlayer insulating layer 201. The principal surface gate electrode layer 115 and the principal surface source electrode layer 121 each have a laminated structure including a barrier electrode layer 206 and a principal electrode layer 207 laminated in this order from the first principal surface 103 side of the SiC semiconductor layer 102.

The barrier electrode layer 206 may have a single layer structure including a titanium layer or a titanium nitride layer. The barrier electrode layer 206 may have a laminated structure including a titanium layer and a titanium nitride layer laminated in this order from the first main surface 103 side of the SiC semiconductor layer 102.

The thickness of the main electrode layer 207 is greater than the thickness of the barrier electrode layer 206. The main electrode layer 207 includes a conductive material having a resistance value less than the resistance value of the barrier electrode layer 206. The main electrode layer 207 may include at least one of aluminum, copper, an aluminum alloy, or a copper alloy.

The main electrode layer 207 may include at least one of an aluminum-silicon alloy, an aluminum-silicon-copper alloy, or an aluminum-copper alloy. In this embodiment, the main electrode layer 207 includes an aluminum-silicon-copper alloy.

The outer gate finger 117 of the main surface gate electrode layer 115 penetrates into the gate contact hole 202 from above the interlayer insulating layer 201. The outer gate finger 117 is electrically connected to the gate wiring layer 150 within the gate contact hole 202. As a result, an electrical signal from the gate pad 116 is transmitted to the gate electrode layer 149 via the outer gate finger 117.

The source pad 122 of the main surface source electrode layer 121 extends from above the interlayer insulating layer 201 into the source contact hole 203 and the source sub-trench 168. The source pad 122 is electrically connected to the source region 163, the contact region 164, and the source electrode layer 157 within the source contact hole 203 and the source sub-trench 168.

The source electrode layer 157 may be formed by utilizing a partial region of the source pad 122. The source electrode layer 157 may be formed by a portion of the source pad 122 that extends into each source trench 155.

The source wiring 123 of the main surface source electrode layer 121 enters the diode contact hole 204 from above the interlayer insulating layer 201. The source wiring 123 is electrically connected to the diode region 181 within the diode contact hole 204.

The source connection portion 124 of the main surface source electrode layer 121 is drawn from the active region 111 across the sidewall 192 to the outer region 112. The source connection portion 124 forms part of the upper layer structure that covers the sidewall 192.

The aforementioned passivation layer 125 is formed on the interlayer insulating layer 201. The passivation layer 125 is formed in a film shape along the interlayer insulating layer 201. The passivation layer 125 selectively covers the active region 111 and the outer region 112 via the interlayer insulating layer 201.

The passivation layer 125 extends from the active region 111 across the sidewall 192 to the outer region 112. The passivation layer 125 forms part of an upper layer structure that covers the sidewall 192.

Referring to FIG. 22, in the outer region 112, the passivation layer 125 extends from above the interlayer insulating layer 201 into the anchor hole 205. The passivation layer 125 is connected to the first main surface 103 (outer main surface 172) of the SiC semiconductor layer 102 within the anchor hole 205. In the region located above the anchor hole 205 on the outer surface of the passivation layer 125, a recess 211 is formed that is recessed to match the anchor hole 205.

The aforementioned resin layer 129 is formed on the passivation layer 125. The resin layer 129 is formed in a film shape along the passivation layer 125. The resin layer 129 selectively covers the active region 111 and the outer region 112, sandwiching the passivation layer 125 and the interlayer insulating layer 201.

The resin layer 129 extends from the active region 111 across the sidewall 192 to the outer region 112. The resin layer 129 forms part of an upper layer structure that covers the sidewall 192.

Referring to FIG. 22, the resin layer 129 has an anchor portion that penetrates into the recess 211 of the passivation layer 125 in the outer region 112. In this way, an anchor structure is formed in the outer region 112 to increase the connection strength of the resin layer 129.

The anchor structure includes an uneven structure formed on the first main surface 103 of the SiC semiconductor layer 102 in the outer region 112. More specifically, the uneven structure (anchor structure) includes unevenness formed by utilizing the interlayer insulating layer 201 that covers the outer main surface 172. More specifically, the uneven structure (anchor structure) includes anchor holes 205 formed in the interlayer insulating layer 201.

The resin layer 129 is engaged with the anchor hole 205. In this embodiment, the resin layer 129 is engaged with the anchor hole 205 via the passivation layer 125. This increases the connection strength of the resin layer 129 to the first main surface 103 of the SiC semiconductor layer 102, thereby suppressing peeling of the resin layer 129.

As described above, the SiC semiconductor device 101 can achieve the same effects as those described for the SiC semiconductor device 1. Furthermore, the SiC semiconductor device 101 can expand the depletion layer from the boundary region (pn junction) between the SiC semiconductor layer 102 and the deep well region 165 toward the region on the second main surface 104 side of the SiC semiconductor layer 102 relative to the bottom wall of the gate trench 142.

This narrows the current path of the short-circuit current flowing between the main surface source electrode layer 121 and the drain electrode layer 133. In addition, the depletion layer extending from the boundary region between the SiC semiconductor layer 102 and the deep well region 165 reduces the feedback capacitance Crss inversely proportionally. This makes it possible to provide a SiC semiconductor device 101 that can improve short-circuit resistance and reduce the feedback capacitance Crss.

The depletion layer extending from the boundary region (pn junction) between the SiC semiconductor layer 102 and the deep well region 165 may overlap the bottom wall of the gate trench 142. In this case, the depletion layer extending from the bottom of the deep well region 165 may overlap the bottom wall of the gate trench 142.

In addition, according to the SiC semiconductor device 101, the area occupied by the depletion layer in the SiC semiconductor layer 102 can be increased, so that the feedback capacitance Crss can be reduced inversely proportionally. The feedback capacitance Crss is the electrostatic capacitance between the gate electrode layer 149 and the drain electrode layer 133.

In addition, according to the SiC semiconductor device 101, the distance between the bottom of each deep well region 165 and the second main surface 104 of the SiC semiconductor layer 102 is approximately constant. This makes it possible to suppress variation in the distance between the bottom of each deep well region 165 and the second main surface 104 of the SiC semiconductor layer 102.

This makes it possible to prevent the breakdown voltage (e.g., breakdown resistance) of the SiC semiconductor layer 102 from being limited by the shape of the deep well region 165, thereby enabling the breakdown voltage to be appropriately improved.

In addition, according to the SiC semiconductor device 101, a diode region 181 is formed in the outer region 112. This diode region 181 is electrically connected to the main surface source electrode layer 121. This allows the avalanche current generated in the outer region 112 to flow into the main surface source electrode layer 121 via the diode region 181.

In other words, the avalanche current generated in the outer region 112 can be absorbed by the diode region 181 and the main surface source electrode layer 121. As a result, the stability of the MISFET operation can be improved.

In addition, according to the SiC semiconductor device 101, an outer deep well region 182 is formed in the outer region 112. This allows the breakdown voltage of the SiC semiconductor layer 102 to be adjusted in the outer region 112.

In particular, in the SiC semiconductor device 101, the outer deep well region 182 is formed at a depth position substantially equal to that of the deep well region 165. More specifically, the bottom of the outer deep well region 182 is located on substantially the same plane as the bottom of the deep well region 165.

The distance between the bottom of the outer deep well region 182 and the second major surface 104 of the SiC semiconductor layer 102 is approximately equal to the distance between the bottom of the deep well region 165 and the second major surface 104 of the SiC semiconductor layer 102.

This makes it possible to suppress variation between the distance between the bottom of the outer deep well region 182 and the second main surface 104 of the SiC semiconductor layer 102 and the distance between the bottom of the deep well region 165 and the second main surface 104 of the SiC semiconductor layer 102.

This makes it possible to prevent the breakdown voltage (e.g., breakdown resistance) of the SiC semiconductor layer 102 from being limited by the shape of the outer deep well region 182 and the shape of the deep well region 165. As a result, the breakdown voltage can be appropriately improved.

In particular, in the SiC semiconductor device 101, the outer region 112 is formed in the region on the second main surface 104 side of the SiC semiconductor layer 102 relative to the active region 111. This allows the position of the bottom of the outer deep well region 182 to be appropriately brought close to the position of the bottom of the deep well region 165.

In other words, when forming the outer deep well region 182, it is no longer necessary to introduce p-type impurities into a relatively deep position in the surface layer of the first main surface 103 of the SiC semiconductor layer 102. Therefore, it is possible to appropriately prevent the position of the bottom of the outer deep well region 182 from shifting significantly from the position of the bottom of the deep well region 165.

Moreover, in the SiC semiconductor device 101, the outer major surface 172 of the outer region 112 is located on approximately the same plane as the bottom wall of the source trench 155. This allows the deep well region 165 and the outer deep well region 182 to be formed at approximately the same depth when p-type impurities are introduced into the bottom wall of the source trench 155 and the outer major surface 172 of the outer region 112 with equal energy.

As a result, it is possible to more appropriately prevent the position of the bottom of the outer deep well region 182 from shifting significantly from the position of the bottom of the deep well region 165.

In addition, according to the SiC semiconductor device 101, a field limit structure 183 is formed in the outer region 112. This makes it possible to obtain an electric field relaxation effect due to the field limit structure 183 in the outer region 112. Therefore, the breakdown resistance of the SiC semiconductor layer 102 can be appropriately improved.

In addition, according to the SiC semiconductor device 101, the active region 111 is formed as a plateau-shaped active plateau 173. The active plateau 173 includes an active sidewall 174 that connects the active main surface 171 of the active region 111 and the outer main surface 172 of the outer region 112.

In the region between the active main surface 171 and the outer main surface 172, a step reduction structure is formed that reduces the step between the active main surface 171 and the outer main surface 172. The step reduction structure includes a sidewall 192.

This allows the step between the active main surface 171 and the outer main surface 172 to be appropriately reduced. This allows the flatness of the upper layer structure formed on the sidewall 192 to be appropriately improved. In the SiC semiconductor device 101, an interlayer insulating layer 201, a main surface source electrode layer 121, a passivation layer 125, and a resin layer 129 are formed as an example of the upper layer structure.

In addition, according to the SiC semiconductor device 101, an anchor structure is formed in the outer region 112 to increase the connection strength of the resin layer 129. The anchor structure includes an uneven structure formed on the first main surface 103 of the SiC semiconductor layer 102 in the outer region 112.

More specifically, the uneven structure (anchor structure) includes unevenness formed in the outer region 112 by utilizing the interlayer insulating layer 201 formed on the first main surface 103 of the SiC semiconductor layer 102. Even more specifically, the uneven structure (anchor structure) includes anchor holes 205 formed in the interlayer insulating layer 201.

The resin layer 129 is engaged with the anchor hole 205. In this embodiment, the resin layer 129 is engaged with the anchor hole 205 via the passivation layer 125. This increases the connection strength of the resin layer 129 to the first main surface 103 of the SiC semiconductor layer 102, thereby appropriately suppressing peeling of the resin layer 129.

In addition, according to the SiC semiconductor device 101, a trench gate structure 161 is formed in which a gate electrode layer 149 is embedded in the gate trench 142 with a gate insulating layer 148 sandwiched therebetween. In this trench gate structure 161, the gate electrode layer 149 is covered with a low resistance electrode layer 167 in the limited space of the gate trench 142. With such a structure, it is possible to achieve the effects described with reference to FIG. 24.

Figure 24 is a graph to explain the sheet resistance in the gate trench 142. In Figure 24, the vertical axis represents the sheet resistance [Ω/ ], and the horizontal axis represents the items. Figure 24 shows a first bar graph BL1, a second bar graph BL2, and a third bar graph BL3.

The first bar graph BL1 represents the sheet resistance in the gate trench 142 filled with n-type polysilicon. The second bar graph BL2 represents the sheet resistance in the gate trench 142 filled with p-type polysilicon.

The third bar graph BL3 represents the sheet resistance in the gate trench 142 in which the gate electrode layer 149 (p-type polysilicon) and the low-resistance electrode layer 167 are embedded. Here, a case will be described in which the low-resistance electrode layer 167 is formed of TiSi ₂ (p-type titanium silicide) as an example of polycide (silicide).

Referring to the first bar graph BL1, the sheet resistance in the gate trench 142 filled with n-type polysilicon was 10 Ω/ .Referring to the second bar graph BL2, the sheet resistance in the gate trench 142 filled with p-type polysilicon was 200 Ω/ .Referring to the third bar graph BL3, the sheet resistance in the gate trench 142 filled with the gate electrode layer 149 (p-type polysilicon) and the low resistance electrode layer 167 was 2 Ω/ .

P-type polysilicon has a different work function from n-type polysilicon. With a structure in which p-type polysilicon is embedded in the gate trench 142, the gate threshold voltage Vth can be increased by about 1 V.

However, p-type polysilicon has a sheet resistance several tens of times (here, 20 times) higher than that of n-type polysilicon. Therefore, when p-type polysilicon is used as the material for the gate electrode layer 149, the energy loss increases significantly as the parasitic resistance in the gate trench 142 (hereinafter simply referred to as "gate resistance") increases.

In contrast, a structure having a low resistance electrode layer 167 on the gate electrode layer 149 (p-type polysilicon) can reduce the sheet resistance to 1/100 or less compared to a structure in which the low resistance electrode layer 167 is not formed. In other words, a structure having a low resistance electrode layer 167 can reduce the sheet resistance to 1/5 or less compared to a gate electrode layer 149 including n-type polysilicon.

In this way, the structure having the low resistance electrode layer 167 can reduce the sheet resistance in the gate trench 142 while increasing the gate threshold voltage Vth (for example, by about 1 V). This reduces the gate resistance, and allows the current to be efficiently diffused along the trench gate structure 161. As a result, the switching delay can be reduced.

In addition, the structure having the low resistance electrode layer 167 eliminates the need to increase the p-type impurity concentration in the body region 141 and the p-type impurity concentration in the contact region 164. This makes it possible to appropriately increase the gate threshold voltage Vth while suppressing an increase in channel resistance.

The low resistance electrode layer 167 may include at least one of TiSi, TiSi ₂ , NiSi, CoSi, CoSi ₂ , MoSi ₂ , and WSi _2. Among these materials, NiSi, CoSi ₂ and TiSi ₂ are particularly suitable as a polycide layer for forming the low resistance electrode layer 167, since they have relatively small resistivity and temperature dependency.

As a result of further verification by the inventors of the present application, when _TiSi2 was used as the material for the low resistance electrode layer 167, an increase in the leakage current between the gate and the source was observed when a low electric field was applied. In contrast, when _CoSi2 was used, no increase in the leakage current between the gate and the source was observed when a low electric field was applied. Considering this point, it is considered that _CoSi2 is most preferable as the polycide layer forming the low resistance electrode layer 167.

Furthermore, in the SiC semiconductor device 101, the gate wiring layer 150 is covered with a low resistance electrode layer 167. This also reduces the gate resistance in the gate wiring layer 150.

In particular, in a structure in which the gate electrode layer 149 and the gate wiring layer 150 are covered with the low-resistance electrode layer 167, the current can be efficiently diffused along the trench gate structure 161. Therefore, the switching delay can be appropriately reduced.

Figure 25 is an enlarged view of the area corresponding to Figure 18, showing a SiC semiconductor device 221 according to the fourth embodiment of the present disclosure. Figure 26 is a cross-sectional view taken along line XXVI-XXVI shown in Figure 25. In the following, structures corresponding to those described for the SiC semiconductor device 101 are given the same reference numerals and will not be described.

25 and 26, the SiC semiconductor device 221 includes an outer gate trench 222 formed in the first main surface 103 of the SiC semiconductor layer 102 in the active region 111. The outer gate trench 222 extends in a strip shape along the periphery of the active region 111.

The outer gate trench 222 is formed in the region directly below the outer gate finger 117 on the first main surface 103 of the SiC semiconductor layer 102. The outer gate trench 222 extends along the outer gate finger 117.

More specifically, the outer gate trench 222 is formed along the three side surfaces 105A, 105B, and 105D of the SiC semiconductor layer 102 so as to partition the inner region of the active region 111 from three directions. The outer gate trench 222 may be formed in an endless shape (e.g., a rectangular ring shape) surrounding the inner region of the active region 111.

The outer gate trench 222 is connected to the contact trench portion 144 of each gate trench 142. As a result, the outer gate trench 222 and the gate trench 142 are formed by a single trench.

A gate wiring layer 150 is embedded in the outer gate trench 222. The gate wiring layer 150 is connected to the gate electrode layer 149 at the communicating portion between the gate trench 142 and the outer gate trench 222.

A low-resistance electrode layer 167 that covers the gate wiring layer 150 is formed in the outer gate trench 222. In this case, the low-resistance electrode layer 167 that covers the gate electrode layer 149 and the low-resistance electrode layer 167 that covers the gate wiring layer 150 are located within one trench.

As described above, the SiC semiconductor device 221 can achieve the same effects as those described for the SiC semiconductor device 101. Furthermore, with the SiC semiconductor device 221, it is not necessary to extend the gate wiring layer 150 onto the first main surface 103 of the SiC semiconductor layer 102.

This prevents the gate wiring layer 150 from facing the SiC semiconductor layer 102 across the gate insulating layer 148 at the opening edge 146 of the gate trench 142 (outer gate trench 222). As a result, electric field concentration at the opening edge 146 of the gate trench 142 (outer gate trench 222) can be suppressed.

Figure 27 is an enlarged view of the area corresponding to Figure 21, showing a SiC semiconductor device 231 according to the fifth embodiment of the present disclosure. In the following, structures corresponding to those described for the SiC semiconductor device 101 are given the same reference numerals and will not be described.

Referring to FIG. 27, in this embodiment, the SiC epitaxial layer 107 includes a high concentration region 108, a low concentration region 109, and a concentration gradient region 232 interposed between the high concentration region 108 and the low concentration region 109.

In the SiC epitaxial layer 107, the concentration gradient region 232 is formed in the outer region 112 as well as in the active region 111. The concentration gradient region 232 is formed throughout the entire SiC epitaxial layer 107.

The concentration gradient region 232 has a concentration gradient in which the n-type impurity concentration gradually decreases from the high concentration region 108 toward the low concentration region 109. In other words, the concentration gradient region 232 has a concentration gradient in which the n-type impurity concentration gradually increases from the low concentration region 109 toward the high concentration region 108. The concentration gradient region 232 suppresses abrupt fluctuations in the n-type impurity concentration in the region between the high concentration region 108 and the low concentration region 109.

When the SiC epitaxial layer 107 includes a concentration gradient region 232, the n-type impurity concentration of the high concentration region 108 is preferably 1.5 to 5 times the n-type impurity concentration of the low concentration region 109. The n-type impurity concentration of the high concentration region 108 may be 3 to 5 times the n-type impurity concentration of the low concentration region 109.

The thickness of the concentration gradient region 232 may be 0.5 μm or more and 2.0 μm or less. The thickness of the concentration gradient region 232 may be 0.5 μm or more and 1.0 μm or less, 1.0 μm or more and 1.5 μm or less, or 1.5 μm or more and 2.0 μm or less.

Although a detailed description will be omitted, the aforementioned gate trench 142, source trench 155, deep well region 165, outer deep well region 182, etc. are formed in the high concentration region 108.

In other words, the aforementioned gate trench 142, source trench 155, deep well region 165, outer deep well region 182, etc. are formed in the region of the SiC semiconductor layer 102 on the first main surface 103 side relative to the boundary region between the high concentration region 108 and the concentration gradient region 232.

As described above, the SiC semiconductor device 231 can achieve the same effects as those described for the SiC semiconductor device 101.

Figure 28 is an enlarged view of the area corresponding to Figure 18, showing a SiC semiconductor device 241 according to the sixth embodiment of the present disclosure. In the following, structures corresponding to those described for the SiC semiconductor device 101 are given the same reference numerals and will not be described.

Referring to FIG. 28, in this embodiment, the gate trench 142 is formed in a lattice shape in a plan view. More specifically, the gate trench 142 includes a plurality of first gate trenches 242 and a plurality of second gate trenches 243. The plurality of first gate trenches 242 and the plurality of second gate trenches 243 form an active trench portion 143.

The first gate trenches 242 are spaced apart in the second direction Y and are each formed in a strip shape extending along the first direction X. The first gate trenches 242 are formed in a stripe shape overall in a plan view.

The sidewalls forming the long sides of each first gate trench 242 are formed by the a-plane of the SiC single crystal. The sidewalls forming the short sides of each first gate trench 242 are formed by the m-plane of the SiC single crystal.

The second gate trenches 243 are spaced apart in the first direction X and are each formed in a strip shape extending along the second direction Y. The second gate trenches 243 are formed in a stripe shape overall in a plan view.

The sidewalls forming the long sides of each second gate trench 243 are formed by the m-plane of the SiC single crystal. The sidewalls forming the short sides of each second gate trench 243 are formed by the a-plane of the SiC single crystal.

The first gate trenches 242 and the second gate trenches 243 intersect with each other. This forms a single gate trench 142 that has a lattice shape in plan view. A number of cell regions 244 are defined in the area surrounded by the gate trench 142.

The multiple cell regions 244 are arranged in a matrix at intervals in the first direction X and the second direction Y in a plan view. The multiple cell regions 244 are formed in a rectangular shape in a plan view. In each cell region 244, the body region 141 is exposed from the sidewall of the gate trench 142. The body region 141 is exposed from the sidewall of the gate trench 142 formed by the m-plane and a-plane of the SiC single crystal.

Of course, the gate trench 142 may be formed in a honeycomb shape as a form of a lattice shape in a plan view. In this case, the multiple cell regions 244 may be arranged in a staggered pattern with intervals in the first direction X and the second direction Y. Also, in this case, the multiple cell regions 244 may be formed in a hexagonal shape in a plan view.

Each source trench 155 is formed in the center of each cell region 244 in a plan view. Each source trench 155 is formed in a pattern that appears on a cut surface that appears when each cell region 244 is cut along the first direction X. Also, each source trench 155 is formed in a pattern that appears on a cut surface that appears when each cell region 244 is cut along the second direction Y.

More specifically, each source trench 155 is formed in a rectangular shape in a plan view. The four side walls of each source trench 155 are formed by the m-plane and a-plane of the SiC single crystal.

The planar shape of each source trench 155 is arbitrary. Each source trench 155 may be formed in a polygonal shape such as a triangular shape, a pentagonal shape, or a hexagonal shape, or in a circular or elliptical shape in a planar view.

The cross-sectional view taken along line XIX-XIX in FIG. 28 corresponds to the cross-sectional view shown in FIG. 19. The cross-sectional view taken along line XX-XX in FIG. 28 corresponds to the cross-sectional view shown in FIG. 20.

As described above, the SiC semiconductor device 241 can achieve the same effects as those described for the SiC semiconductor device 101.

Although an embodiment of the present disclosure has been described, the embodiment of the present disclosure can also be implemented in other forms.

In each of the above-described embodiments, the side surfaces 5A, 105A and 5C, 105C of the SiC semiconductor layers 2, 102 face the a-plane of the SiC single crystal, and the side surfaces 5B, 105B and 5D, 105D face the m-plane of the SiC single crystal. However, a configuration in which the side surfaces 5A, 105A and 5C, 105C face the m-plane of the SiC single crystal, and the side surfaces 5B, 105B and 5D, 105D face the a-plane of the SiC single crystal may also be adopted.

In each of the above-described embodiments, examples have been described in which the reforming lines 22A-22D are formed in a continuous band shape. However, in each of the above-described embodiments, the reforming lines 22A-22D may be formed in a dashed band shape (broken line shape). In other words, the reforming lines 22A-22D may be formed in a band shape that extends intermittently. In this case, one, two, or three of the reforming lines 22A-22D may be formed in a dashed band shape, and the rest may be formed in a band shape.

In the above-described third to sixth embodiments, an example was described in which multiple gate trenches 142 (first gate trenches 242) were formed extending along the m-axis direction ([1-100] direction) of the SiC single crystal.

However, multiple gate trenches 142 (first gate trenches 242) extending along the a-axis direction ([11-20] direction) of the SiC single crystal may be formed. In this case, multiple source trenches 155 extending along the a-axis direction ([11-20] direction) of the SiC single crystal are formed.

In the third to sixth embodiments described above, an example was described in which the source electrode layer 157 is embedded in the source trench 155 with the source insulating layer 156 sandwiched therebetween. However, the source electrode layer 157 may be embedded directly in the source trench 155 without the source insulating layer 156 being interposed therebetween.

In the third to sixth embodiments described above, examples were described in which the source insulating layer 156 was formed along the sidewalls and bottom wall of the source trench 155.

However, the source insulating layer 156 may be formed along the sidewalls of the source trench 155 so as to expose the bottom wall of the source trench 155. The source insulating layer 156 may be formed along the sidewalls and bottom wall of the source trench 155 so as to expose a portion of the bottom wall of the source trench 155.

The source insulating layer 156 may also be formed along the bottom wall of the source trench 155 so as to expose the sidewall of the source trench 155. The source insulating layer 156 may also be formed along the sidewall and bottom wall of the source trench 155 so as to expose a portion of the sidewall of the source trench 155.

In the third to sixth embodiments described above, examples have been described in which the gate electrode layer 149 and the gate wiring layer 150 are formed to include p-type polysilicon doped with p-type impurities. However, if the increase in the gate threshold voltage Vth is not important, the gate electrode layer 149 and the gate wiring layer 150 may include n-type polysilicon doped with n-type impurities instead of or in addition to p-type polysilicon.

In this case, the low resistance electrode layer 167 may be formed by silicidating the portion of the gate electrode layer 149 (n-type polysilicon) that forms the surface layer with a metal material. In other words, the low resistance electrode layer 167 may include n-type polycide. With such a structure, it is possible to reduce the gate resistance.

In the third to sixth embodiments described above, ap ^{+ type SiC semiconductor substrate (106) may be adopted instead of the n + type} SiC semiconductor substrate 106. With this structure, an IGBT (Insulated Gate Bipolar Transistor) can be provided instead of a MISFET. In this case, in each of the above-described embodiments, the "source" of the MISFET is replaced with the "emitter" of the IGBT, and the "drain" of the MISFET is replaced with the "collector" of the IGBT.

In each of the above-described embodiments, a structure in which the conductivity type of each semiconductor portion is inverted may be adopted. That is, the p-type portion may be made n-type, and the n-type portion may be made p-type.

The above-described embodiments can also be applied to a semiconductor device using a semiconductor material other than SiC. The semiconductor material other than SiC may be a compound semiconductor material. The compound semiconductor material may be either or both of gallium nitride (GaN) and gallium oxide (Ga ₂ O ₃ ).

For example, the third to sixth embodiments described above may be a compound semiconductor device including a vertical compound semiconductor MISFET in which a compound semiconductor material is used instead of SiC. In the compound semiconductor, magnesium may be used as a p-type impurity (acceptor). Also, germanium (Ge), oxygen (O), or silicon (Si) may be used as an n-type impurity (donor).

Below are some examples of features extracted from this specification and drawings.

[A1] A SiC semiconductor device including: a SiC semiconductor layer including a SiC single crystal and having a first main surface as an element formation surface, a second main surface opposite to the first main surface, and a side surface connecting the first main surface and the second main surface; an insulating layer including an insulating material, covering the first main surface of the SiC semiconductor layer, and having an insulating side surface formed flush with the side surface of the SiC semiconductor layer; an electrode formed on the insulating layer; and a modified layer formed on the side surface of the SiC semiconductor layer and modified to have properties different from those of the SiC single crystal.

According to this SiC semiconductor device, in a structure in which a modified layer is formed on the side surface of the SiC semiconductor layer, the insulating layer can improve the insulation between the side surface of the SiC semiconductor layer and the electrode. This can improve the stability of the electrical characteristics of the SiC semiconductor layer.

[A2] The SiC semiconductor device according to A1, in which the modified layer is formed at a distance from the insulating layer and at a midpoint in the thickness direction of the SiC semiconductor layer.

[A3] The SiC semiconductor device according to A1 or A2, in which the SiC semiconductor layer has a laminated structure including a SiC semiconductor substrate and a SiC epitaxial layer, the first main surface being formed by the SiC epitaxial layer, the insulating layer covers the SiC epitaxial layer, and the modified layer is formed in a region of the SiC semiconductor substrate.

[A4] The SiC semiconductor device described in A3, in which the modified layer is formed on the SiC semiconductor substrate while avoiding the SiC epitaxial layer.

[A5] The SiC semiconductor device according to A3 or A4, in which the SiC epitaxial layer has a thickness equal to or less than the thickness of the SiC semiconductor substrate.

[A6] The SiC semiconductor device according to any one of A3 to A5, wherein the SiC semiconductor substrate has a thickness of 40 μm or more and 150 μm or less, and the SiC epitaxial layer has a thickness of 1 μm or more and 50 μm or less.

[B1] A method for manufacturing a SiC semiconductor device, comprising the steps of: preparing a SiC semiconductor wafer including a SiC single crystal, the wafer having a first main surface on which a device formation region having a plurality of sides is set, and a second main surface opposite the first main surface; forming a plurality of modified lines modified to have properties different from those of the SiC single crystal, layer by layer, in a one-to-one correspondence with the plurality of sides of the device formation region by irradiating the inside of the SiC semiconductor wafer with laser light along the plurality of sides of the device formation region; and cutting the SiC semiconductor wafer along the plurality of modified lines.

According to this manufacturing method, it is possible to manufacture and provide a SiC semiconductor device including a SiC single crystal, a SiC semiconductor layer having a first main surface as an element formation surface, a second main surface opposite the first main surface, and a plurality of side surfaces connecting the first main surface and the second main surface, and a plurality of modification lines formed one by one on each of the side surfaces of the SiC semiconductor layer, each extending in a band shape along the tangential direction of the first main surface of the SiC semiconductor layer, and modified to have properties different from those of the SiC single crystal.

[B2] The method for manufacturing a SiC semiconductor device according to B1, further comprising a step of grinding the second main surface of the SiC semiconductor wafer prior to the step of cutting the SiC semiconductor wafer.

[B3] The method for manufacturing a SiC semiconductor device according to B2, in which the process for forming the modification line is carried out prior to the grinding process.

[B4] The method for manufacturing a SiC semiconductor device according to B2, in which the process for forming the modification line is carried out after the grinding process.

[B5] The method for manufacturing a SiC semiconductor device according to any one of B2 to B4, wherein the step of preparing the SiC semiconductor wafer includes a step of preparing the SiC semiconductor wafer having a thickness exceeding 150 μm, and the grinding step includes a step of grinding the SiC semiconductor wafer until the SiC semiconductor wafer has a thickness of 40 μm or more and 150 μm or less.

[B6] The method for manufacturing a SiC semiconductor device according to any one of B1 to B5, wherein the process for forming the modification line includes a process for irradiating the inside of the SiC semiconductor wafer with laser light from the first main surface side of the SiC semiconductor wafer.

[B7] The method for manufacturing a SiC semiconductor device according to any one of B1 to B5, wherein the process for forming the modification line includes a process for irradiating the inside of the SiC semiconductor wafer with laser light from the second main surface side of the SiC semiconductor wafer.

[B8] A method for manufacturing a SiC semiconductor device, comprising the steps of: preparing a SiC semiconductor wafer including a SiC single crystal and having a first main surface on which a device formation region having a plurality of sides is set and a second main surface opposite to the first main surface; forming an insulating layer on the first main surface of the SiC semiconductor wafer; forming an electrode on the insulating layer; forming a plurality of modified layers modified to have properties different from those of the SiC single crystal by irradiating the inside of the SiC semiconductor wafer with laser light along the plurality of sides of the device formation region; and cutting the SiC semiconductor wafer together with the insulating layer along the plurality of modified layers.

According to this manufacturing method, it is possible to manufacture and provide a SiC semiconductor device including: a SiC semiconductor layer including a SiC single crystal and having a first main surface as an element formation surface, a second main surface opposite to the first main surface, and a side surface connecting the first main surface and the second main surface; an insulating layer including an insulating material, covering the first main surface of the SiC semiconductor layer, and having an insulating side surface formed flush with the side surface of the SiC semiconductor layer; a main surface electrode layer formed on the insulating layer; and a modified layer formed on the side surface of the SiC semiconductor layer and modified to have properties different from those of the SiC single crystal.

[B9] A method for manufacturing a SiC semiconductor device, comprising the steps of: preparing a SiC semiconductor wafer including a SiC single crystal and having a first main surface on which a device formation region having a plurality of sides is set and a second main surface opposite to the first main surface; forming an insulating layer on the first main surface of the SiC semiconductor wafer; partially removing the insulating layer and forming openings in the insulating layer that expose the plurality of sides of the device formation region; irradiating the inside of the SiC semiconductor wafer with laser light along the plurality of sides of the device formation region to form a plurality of modified layers modified to have properties different from those of the SiC single crystal; and cutting the SiC semiconductor wafer along the plurality of modified layers.

[B10] The method for manufacturing a SiC semiconductor device according to B8 or B9, further comprising a step of grinding the second main surface of the SiC semiconductor wafer.

[B11] The method for manufacturing a SiC semiconductor device according to B10, in which the process for forming the modification line is carried out prior to the grinding process.

[B12] The method for manufacturing a SiC semiconductor device according to B10, in which the process for forming the modification line is carried out after the grinding process.

[B13] The method for manufacturing a SiC semiconductor device according to any one of B10 to B12, wherein the step of preparing the SiC semiconductor wafer includes a step of preparing the SiC semiconductor wafer having a thickness of more than 150 μm, and the grinding step includes a step of grinding the SiC semiconductor wafer until the SiC semiconductor wafer has a thickness of 40 μm or more and 150 μm or less.

[C1] A SiC semiconductor device including a SiC single crystal, a SiC semiconductor layer having a first main surface as an element formation surface, a second main surface opposite to the first main surface, and a side surface connecting the first main surface and the second main surface, and a plurality of modified layers formed at intervals from the first main surface to the second main surface of the SiC semiconductor layer so as to expose a surface portion of the first main surface of the SiC semiconductor layer from the side surface of the SiC semiconductor layer, and modified to have properties different from those of the SiC single crystal.

The modified layer is formed by modifying the SiC single crystal of the SiC semiconductor layer to give it a different property, and as such, it is prone to becoming the starting point of cracks. In particular, stress is likely to concentrate at the corners connecting the first main surface and the side surface of the SiC semiconductor layer, so in a structure in which a modified layer is formed at the corners of the SiC semiconductor layer, there is an increased risk of cracks occurring at the corners of the SiC semiconductor layer.

In this SiC semiconductor device, the modified layer is formed at a distance from the first main surface to the second main surface of the SiC semiconductor layer so that the surface portion of the first main surface of the SiC semiconductor layer is exposed from the side of the SiC semiconductor layer. Therefore, the risk of cracks occurring at the corners on the first main surface side of the SiC semiconductor layer can be reduced.

[C2] A SiC semiconductor device including a SiC single crystal, a SiC semiconductor layer having a first main surface as an element formation surface, a second main surface opposite to the first main surface, and a side surface connecting the first main surface and the second main surface, and a plurality of modified layers formed at intervals from the second main surface of the SiC semiconductor layer to the first main surface so as to expose a surface portion of the second main surface of the SiC semiconductor layer from the side surface of the SiC semiconductor layer, and modified to have properties different from those of the SiC single crystal.

The modified layer is formed by modifying the SiC single crystal of the SiC semiconductor layer to give it a different property, and so it is prone to becoming the starting point of cracks. In particular, stress tends to concentrate at the corners connecting the second main surface and the side surface of the SiC semiconductor layer, so in a structure in which a modified layer is formed at the corners of the SiC semiconductor layer, there is an increased risk of cracks occurring at the corners of the SiC semiconductor layer.

In this SiC semiconductor device, the modified layer is formed at a distance from the second main surface to the first main surface of the SiC semiconductor layer so that the surface portion of the second main surface of the SiC semiconductor layer is exposed from the side of the SiC semiconductor layer. This reduces the risk of cracks occurring at the corners on the second main surface side of the SiC semiconductor layer.

The reforming lines are formed by reforming the SiC single crystal of the SiC semiconductor layer to have different properties. Therefore, considering the influence of the reforming lines on the SiC semiconductor layer, it is not desirable to form multiple reforming lines over the entire side of the SiC semiconductor layer. Examples of the influence of the reforming lines on the SiC semiconductor layer include fluctuations in the electrical characteristics of the SiC semiconductor layer due to the reforming lines and the occurrence of cracks in the SiC semiconductor layer starting from the reforming lines.

The following [D1] to [D20] and [E1] to [E20] aim to provide a SiC semiconductor device that can reduce the impact of the reforming line on the SiC semiconductor layer.

[D1] A SiC semiconductor device including a SiC single crystal, a SiC semiconductor layer having a first main surface as an element forming surface, a second main surface opposite to the first main surface, and a plurality of side surfaces connecting the first main surface and the second main surface, and a plurality of reforming lines formed one by one on each of the side surfaces of the SiC semiconductor layer, each extending in a band shape along the tangential direction of the first main surface of the SiC semiconductor layer, and reformed to have properties different from those of the SiC single crystal. According to this SiC semiconductor device, only one reforming line is formed on each side surface of the SiC semiconductor layer. Therefore, the influence of the reforming lines on the SiC semiconductor layer can be reduced.

[D2] The SiC semiconductor device described in D1, in which the SiC semiconductor layer has a thickness of 40 μm or more and 200 μm or less.

[D3] The SiC semiconductor device according to D1 or D2, wherein the second main surface of the SiC semiconductor layer is a ground surface.

[D4] A SiC semiconductor device according to any one of D1 to D3, in which each of the reforming lines is formed at an interval from the first main surface to the second main surface of the SiC semiconductor layer.

[D5] A SiC semiconductor device according to any one of D1 to D4, in which each of the reforming lines is formed at a distance from the second main surface to the first main surface of the SiC semiconductor layer.

[D6] The SiC semiconductor device according to any one of D1 to D5, wherein the SiC semiconductor layer includes a corner portion connecting the two side surfaces, and the multiple reforming lines include two reforming lines that are connected at the corner portion of the SiC semiconductor layer.

[D7] A SiC semiconductor device according to any one of D1 to D6, in which the multiple reforming lines are integrally formed to surround the SiC semiconductor layer.

[D8] A SiC semiconductor device according to any one of D1 to D7, in which each of the reforming lines extends in a straight or curved manner.

[D9] A SiC semiconductor device according to any one of D1 to D8, in which each of the modification lines extends in the normal direction of the first main surface of the SiC semiconductor layer and includes a plurality of modification portions that face each other in the tangential direction of the first main surface of the SiC semiconductor layer.

[D10] The SiC semiconductor device according to any one of D1 to D9, wherein each of the side surfaces of the SiC semiconductor layer is a cleavage surface.

[D11] The SiC semiconductor device according to any one of D1 to D10, wherein the SiC single crystal is a hexagonal crystal.

[D12] The SiC semiconductor device according to D11, wherein the SiC single crystal is a 2H (Hexagonal)-SiC single crystal, a 4H-SiC single crystal, or a 6H-SiC single crystal.

[D13] The SiC semiconductor device according to D11 or D12, in which the first main surface of the SiC semiconductor layer faces the c-plane of the SiC single crystal.

[D14] The SiC semiconductor device according to any one of D11 to D13, in which the first main surface of the SiC semiconductor layer has an off-angle inclined at an angle of 0° or more and 10° or less with respect to the c-plane of the SiC single crystal.

[D15] The SiC semiconductor device according to D14, in which the off angle is 5° or less.

[D16] The SiC semiconductor device according to D14 or D15, in which the off angle is greater than 0° and less than 4°.

[D17] The SiC semiconductor device according to any one of D1 to D16, in which the SiC semiconductor layer has a laminated structure including a SiC semiconductor substrate and a SiC epitaxial layer, in which the first main surface is formed by the SiC epitaxial layer, and the modification line is formed in a region of the SiC semiconductor substrate.

[D18] The SiC semiconductor device described in D17, in which the reforming lines are formed in the SiC semiconductor substrate while avoiding the SiC epitaxial layer.

[D19] The SiC semiconductor device according to D17 or D18, in which the SiC epitaxial layer has a thickness equal to or less than the thickness of the SiC semiconductor substrate.

[D20] The SiC semiconductor device according to any one of D17 to D19, wherein the SiC semiconductor substrate has a thickness of 40 μm or more and 150 μm or less, and the SiC epitaxial layer has a thickness of 1 μm or more and 50 μm or less.

[E1] A SiC semiconductor device including a SiC single crystal, a first main surface as an element formation surface, a second main surface opposite to the first main surface, and a plurality of side surfaces connecting the first main surface and the second main surface, each of which is a cleavage surface, and a SiC semiconductor substrate forming a part of the second main surface and the side surfaces, and a SiC epitaxial layer forming the first main surface and a part of the side surfaces, and a plurality of modification lines formed one by one in the portion of the SiC semiconductor substrate on each of the side surfaces of the SiC semiconductor layer at intervals from the SiC epitaxial layer to the second main surface side, each extending in a band shape along the tangential direction of the first main surface of the SiC semiconductor layer, and modified to have properties different from those of the SiC single crystal.

[E2] The SiC semiconductor device according to E1, further comprising an insulating layer covering the SiC epitaxial layer on the first main surface and having insulating sidewalls continuous with each of the side surfaces.

[E3] The SiC semiconductor device described in E2, further including a first electrode formed on the insulating layer and spaced inward from each of the side surfaces.

[E4] The SiC semiconductor device described in E3, further including a resin layer formed on the insulating layer at a distance inward from each of the side surfaces and having an opening for exposing the first electrode.

[E5] The SiC semiconductor device according to any one of E1 to E4, further comprising a second electrode covering the entire second main surface.

[E6] The SiC semiconductor device according to any one of E1 to E5, wherein the SiC semiconductor layer has a thickness of 40 μm or more and 200 μm or less.

[E7] The SiC semiconductor device according to any one of E1 to E6, wherein the second main surface of the SiC semiconductor layer is a ground surface.

[E8] The SiC semiconductor device according to any one of E1 to E7, in which each of the reforming lines is formed at an interval from the second main surface of the SiC semiconductor layer toward the first main surface.

[E9] The SiC semiconductor device according to any one of E1 to E8, in which the SiC semiconductor layer includes a corner portion connecting the two side surfaces, and the multiple reforming lines include two reforming lines that are connected at the corner portion of the SiC semiconductor layer.

[E10] A SiC semiconductor device according to any one of E1 to E9, in which the multiple reforming lines are integrally formed to surround the SiC semiconductor layer.

[E11] A SiC semiconductor device according to any one of E1 to E10, in which each of the reforming lines extends in a straight line or curved line.

[E12] The SiC semiconductor device according to any one of E1 to E11, wherein each of the modification lines extends in a normal direction of the first main surface of the SiC semiconductor layer and includes a plurality of modification portions that face each other in a tangential direction of the first main surface of the SiC semiconductor layer.

[E13] The SiC semiconductor device according to any one of E1 to E12, wherein the SiC single crystal is a hexagonal crystal.

[E14] The SiC semiconductor device according to E13, wherein the SiC single crystal is a 2H (Hexagonal)-SiC single crystal, a 4H-SiC single crystal, or a 6H-SiC single crystal.

[E15] The SiC semiconductor device according to E13 or E14, wherein the first main surface of the SiC semiconductor layer faces the c-plane of the SiC single crystal.

[E16] The SiC semiconductor device according to any one of E13 to E15, wherein the first main surface of the SiC semiconductor layer has an off-angle inclined at an angle of 0° or more and 10° or less with respect to the c-plane of the SiC single crystal.

[E17] The SiC semiconductor device according to E16, in which the off angle is 5° or less.

[E18] The SiC semiconductor device according to E16 or E17, wherein the off angle is greater than 0° and less than 4°.

[E19] The SiC semiconductor device according to any one of E1 to E18, wherein the SiC epitaxial layer has a thickness equal to or less than the thickness of the SiC semiconductor substrate.

[E20] The SiC semiconductor device according to any one of E1 to E19, wherein the SiC semiconductor substrate has a thickness of 40 μm or more and 150 μm or less, and the SiC epitaxial layer has a thickness of 1 μm or more and 50 μm or less.

[F1] A SiC semiconductor device having a layered structure including a SiC semiconductor substrate and a SiC epitaxial layer, a device formation surface formed by the SiC epitaxial layer, and a side surface formed by the SiC semiconductor substrate and the SiC epitaxial layer, the device including a SiC semiconductor chip, and a single modified layer formed on the side surface in a portion of the SiC semiconductor substrate spaced apart from the SiC epitaxial layer and modified to have properties different from those of the SiC semiconductor substrate.

[F2] The SiC semiconductor device described in F1, in which the modified layer is formed in a strip shape extending along the element formation surface.

[F3] The SiC semiconductor device according to F1 or F2, in which the side surface is a cleavage surface.

[F4] The SiC semiconductor device according to any one of F1 to F3, wherein the SiC semiconductor chip has a back surface consisting of a ground surface formed by the SiC semiconductor substrate.

[F5] The SiC semiconductor device described in F4, in which the modified layer is formed at a distance from the back surface to the element forming surface side.

[F6] The SiC semiconductor device described in any one of F1 to F5, in which the modified layer is formed in a linear or curved strip shape.

[F7] A SiC semiconductor device according to any one of F1 to F6, in which the modified layer is formed by a collection of multiple modified parts that each extend in the normal direction of the element formation surface and face each other in the tangential direction of the element formation surface.

[F8] The SiC semiconductor device according to any one of F1 to F7, wherein the SiC semiconductor chip is made of a hexagonal crystal.

[F9] The SiC semiconductor device according to any one of F1 to F8, wherein the SiC semiconductor chip is made of 2H (Hexagonal)-SiC single crystal, 4H-SiC single crystal, or 6H-SiC single crystal.

[F10] The SiC semiconductor device according to any one of F1 to F9, in which the element formation surface faces the c-plane of the SiC single crystal.

[F11] The SiC semiconductor device according to any one of F1 to F10, in which the element formation surface has an off-angle.

[F12] The SiC semiconductor device according to F11, in which the off angle is greater than 0° and less than 4°.

[F13] A SiC semiconductor device according to any one of F1 to F12, in which the SiC semiconductor chip has a thickness of 40 μm or more and 200 μm or less.

[F14] The SiC semiconductor device according to any one of F1 to F13, wherein the SiC epitaxial layer has a thickness less than the thickness of the SiC semiconductor substrate.

[F15] The SiC semiconductor device according to any one of F1 to F14, wherein the SiC semiconductor substrate has a thickness of 40 μm or more and 150 μm or less, and the SiC epitaxial layer has a thickness of 1 μm or more and 50 μm or less.

[F16] The SiC semiconductor device according to any one of F1 to F15, further comprising an insulating layer formed on the element formation surface and an electrode formed on the insulating layer.

[F17] The SiC semiconductor device according to F16, in which the electrode is formed on the insulating layer at a distance from the side surface.

[F18] The SiC semiconductor device described in F16 or F17, in which the insulating layer has an insulating side surface that is continuous with the side surface.

[F19] The SiC semiconductor device according to any one of F16 to F18, further comprising a passivation layer that covers the electrode and a resin layer that covers the passivation layer.

[F20] A SiC semiconductor device including: a SiC semiconductor chip having a first main surface as an element formation surface, a second main surface opposite to the first main surface, and a side surface; a first impurity region of a first conductivity type formed in a surface layer portion of the first main surface so as to be exposed from the first main surface and the side surface; a second impurity region of a first conductivity type having a first conductivity type impurity concentration exceeding the first conductivity type impurity concentration of the first impurity region, exposed from the second main surface and the side surface, and formed in a region on the second main surface side with respect to the first impurity region so as to be electrically connected to the first impurity region; and a single modified layer formed in a portion of the side surface where the second impurity region is exposed with a gap from the first impurity region, and modified to have properties different from those of the SiC semiconductor chip.

[G1] A SiC chip having a first main surface on one side and a second main surface and a side surface on the other side; a semiconductor substrate of a first conductivity type exposed from the side surface of the SiC chip; a semiconductor region of a first conductivity type formed on a surface layer of the first main surface so as to be exposed from the first main surface and the side surface, stacked on the substrate main surface of the semiconductor substrate; a pn junction region formed on the surface layer of the first main surface at the periphery of the first main surface; and a semiconductor region and the pn A SiC semiconductor device including a second conductivity type impurity region forming a connection region, and a single reforming line formed on the side surface at a distance from the depth position of the pn connection region toward the second main surface, and reformed to have properties different from SiC, the reforming line being formed on the side surface at a distance from the depth position of the substrate main surface of the semiconductor substrate toward the second main surface, the reforming line having a plurality of reformed portions each extending in the normal direction of the first main surface, and the reformed portion having a tapered shape narrowing toward the second main surface.

[G2] The SiC semiconductor device described in G1, in which the pn junction region is formed at a distance from the side surface inwardly of the first main surface.

[G3] an active region provided in an inner portion of the first main surface;
an outer region provided at a peripheral portion of the first main surface,
The SiC semiconductor device according to G1 or G2, wherein the pn junction region is formed in the outer region.

[G4] The SiC semiconductor device according to G3, further comprising a diode structure formed on the first main surface of the active region.

[G5] The SiC semiconductor device described in G4, in which the diode structure includes a diode region formed in a surface layer of the first main surface of the active region, and an electrode electrically connected to the diode region on the first main surface.

[G6] The SiC semiconductor device according to any one of G3 to G5, further including a field effect transistor structure formed on the first main surface of the active region.

[G7] The SiC semiconductor device described in G6, in which the transistor structure includes a body region formed in a surface layer portion of the first main surface of the active region, a trench gate structure formed in the first main surface so as to penetrate the body region, and a source region formed in a region along the trench gate structure in the surface layer portion of the body region.

[G8] The SiC semiconductor device described in G7, in which the reforming lines are formed on the side surface at intervals from the depth position of the bottom wall of the trench gate structure toward the second main surface.

[G9] A SiC semiconductor device according to G7 or G8, in which the active region has an active main surface consisting of a part of the first main surface, the outer region has an outer main surface recessed from the active main surface toward the second main surface so as to divide the active region into a plateau shape, and the pn junction region is formed in a surface layer of the outer main surface.

[G10] The SiC semiconductor device according to G9, in which the outer main surface is continuous with the side surface.

[G11] The SiC semiconductor device according to any one of claims 1 to 10, further comprising an insulating film covering the pn junction region on the first main surface.

[G12] The SiC semiconductor device according to G11, further comprising a resin layer that covers the insulating film.

[G13] A SiC chip having a first main surface on one side and a second main surface and a side surface on the other side, a first surface portion located on the inner side of the first main surface, a second surface portion formed on the periphery of the first main surface so as to be recessed from the first surface portion toward the second main surface, and a plateau partitioned on the first main surface by a connecting sidewall connecting the first surface portion and the second surface portion, a semiconductor substrate of a first conductivity type exposed from the side surface in the SiC chip, a semiconductor region of a first conductivity type formed on a surface layer portion of the first main surface so as to be exposed from the first main surface and the side surface, and a semiconductor region of a first conductivity type formed on a surface layer portion of the second surface portion. A SiC semiconductor device including a pn junction region formed on the first main surface, a second conductivity type impurity region formed in the surface layer of the semiconductor region and forming the semiconductor region and the pn junction region, and a single reforming line formed on the side surface at a distance from the depth position of the pn junction region to the second main surface side, the reforming line being formed on the side surface at a distance from the depth position of the substrate main surface of the semiconductor substrate to the second main surface side, the reforming line having a plurality of reforming portions each extending in the normal direction of the first main surface, and the reforming portion having a tapered shape narrowing toward the second main surface.

[G14] The SiC semiconductor device described in G13, in which the second surface portion is continuous with the side surface, and the pn junction region is formed at a distance from the side surface toward the first surface portion.

[G15] The SiC semiconductor device according to G113 or G14, further comprising a body region formed in a surface layer of the first surface, a trench gate structure formed in the first surface so as to penetrate the body region, and a source region formed in a region along the trench gate structure in the surface layer of the body region.

[G16] The SiC semiconductor device described in G15, in which the second surface portion is located closer to the second main surface than the depth position of the bottom wall of the trench gate structure.

This specification does not limit any combination of the features shown in the first to sixth embodiments. The first to sixth embodiments may be combined in any manner and in any form. In other words, the features shown in the first to sixth embodiments may be combined in any manner and in any form.

In addition, various design changes may be made within the scope of the claims.

1 SiC semiconductor device 2 SiC semiconductor layer 3 First main surface of SiC semiconductor layer 4 Second main surface of SiC semiconductor layer 5A Side surface of SiC semiconductor layer 5B Side surface of SiC semiconductor layer 5C Side surface of SiC semiconductor layer 5D Side surface of SiC semiconductor layer 6 SiC semiconductor substrate 7 SiC epitaxial layer 22A Modification line 22B Modification line 22C Modification line 22D Modification line 28 a-plane modification section (modification section)
29 m surface modification section (modification section)
81 SiC semiconductor device 101 SiC semiconductor device 102 SiC semiconductor layer 103 First main surface 104 of SiC semiconductor layer Second main surface 105A of SiC semiconductor layer Side surface 105B of SiC semiconductor layer Side surface 105C of SiC semiconductor layer Side surface 105D of SiC semiconductor layer Side surface 106 of SiC semiconductor substrate 107 SiC epitaxial layer θ Off-angle Z Normal direction X First direction (m-axis direction)
Y: second direction (a-axis direction)

Claims (16)

A SiC chip having a first main surface on one side and a second main surface and a side surface on the other side;
a semiconductor substrate of a first conductivity type exposed from the side surface of the SiC chip;
a first conductivity type semiconductor region formed on a substrate main surface of the semiconductor substrate and exposed from the first main surface and the side surface;
a pn junction region formed in a surface layer portion of the first main surface at a peripheral portion of the first main surface;
an impurity region of a second conductivity type formed in a surface layer of the semiconductor region in a peripheral portion of the first main surface, the impurity region forming the pn junction region with the semiconductor region;
a single reforming line formed on the side surface at an interval from a depth position of the pn junction region toward the second main surface, the single reforming line being reformed to have a property different from SiC;
The modification line is formed on the side surface at an interval from a depth position of the substrate main surface of the semiconductor substrate to the second main surface side,
The modification line has a plurality of modification portions each extending in a normal direction of the first main surface,
The modified portion has a tapered shape narrowing toward the second main surface. The SiC semiconductor device according to claim 1, wherein the pn junction region is formed at a distance inward from the side surface toward the first main surface. an active region provided in an inner portion of the first main surface;
an outer region provided at a peripheral portion of the first main surface,
The SiC semiconductor device according to claim 1 , wherein the pn junction region is formed in the outer region. The SiC semiconductor device of claim 3, further comprising a diode structure formed on the first main surface of the active region. The diode structure comprises:
a diode region formed in a surface layer portion of the first main surface of the active region;
The SiC semiconductor device according to claim 4 , further comprising: an electrode electrically connected to said diode region on said first main surface. The SiC semiconductor device of claim 3, further comprising a field effect transistor structure formed on the first main surface of the active region. The transistor structure comprises:
a body region formed in a surface layer portion of the first main surface of the active region;
a trench gate structure formed in the first major surface so as to penetrate the body region;
7. The SiC semiconductor device according to claim 6, further comprising: a source region formed in a surface portion of the body region in a region along the trench gate structure. The SiC semiconductor device according to claim 7, wherein the reforming lines are formed on the side surfaces at intervals from the depth position of the bottom wall of the trench gate structure toward the second main surface. the active region has an active main surface that is a part of the first main surface,
the outer region has an outer main surface recessed toward the second main surface with respect to the active main surface so as to divide the active region into a plateau shape,
The SiC semiconductor device according to claim 7 , wherein the pn junction region is formed in a surface layer portion of the outer main surface. The SiC semiconductor device according to claim 9, wherein the outer main surface is continuous with the side surface. The SiC semiconductor device according to any one of claims 1 to 10, further comprising an insulating film covering the pn junction region on the first main surface. The SiC semiconductor device according to claim 11, further comprising a resin layer that covers the insulating film. A SiC chip having a first main surface on one side and a second main surface and a side surface on the other side;
a first surface portion located on an inner side of the first main surface, a second surface portion formed on a peripheral edge portion of the first main surface so as to be recessed from the first surface portion toward the second main surface, and a plateau defined on the first main surface by a connecting sidewall connecting the first surface portion and the second surface portion;
a semiconductor substrate of a first conductivity type exposed from the side surface of the SiC chip;
a first conductivity type semiconductor region formed on a substrate main surface of the semiconductor substrate and exposed from the first main surface and the side surface;
a pn junction region formed in a surface layer portion of the second surface portion;
an impurity region of a second conductivity type formed in a surface layer portion of the semiconductor region and forming the pn junction region with the semiconductor region;
a single reforming line formed on the side surface at an interval from a depth position of the pn junction region toward the second main surface, the single reforming line being reformed to have a property different from SiC;
The modification line is formed on the side surface at an interval from a depth position of the substrate main surface of the semiconductor substrate to the second main surface side,
The modification line has a plurality of modification portions each extending in a normal direction of the first main surface,
The modified portion has a tapered shape narrowing toward the second main surface. The second surface portion is continuous with the side surface,
The SiC semiconductor device according to claim 13 , wherein the pn junction region is formed at a distance from the side surface toward the first surface portion. a body region formed on a surface layer portion of the first surface portion;
a trench gate structure formed on the first surface portion so as to penetrate the body region;
The SiC semiconductor device according to claim 13 , further comprising: a source region formed in a surface portion of the body region in a region along the trench gate structure. The SiC semiconductor device according to claim 15, wherein the second surface portion is located closer to the second main surface than the depth position of the bottom wall of the trench gate structure.

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