JP2024089605A - Storage device - Google Patents

Abstract

A memory device having a switching element with excellent characteristics is provided.
[Solution] A memory device according to an embodiment includes a memory cell including a first conductive layer, a second conductive layer, a third conductive layer provided between the first conductive layer and the second conductive layer, a resistance change layer provided between the first conductive layer and the third conductive layer, and a switching layer provided between the third conductive layer and the second conductive layer. The switching layer includes an oxide of a first element, which is at least one element selected from the group consisting of zirconium, yttrium, tantalum, lanthanum, cerium, titanium, hafnium, and magnesium, a compound of a second element, which is at least one element selected from the group consisting of zinc, tin, gallium, indium, and bismuth, and a third element, which is at least one element selected from the group consisting of tellurium, sulfur, and selenium.
[Selected figure] Figure 2

Description

An embodiment of the present invention relates to a storage device.

Cross-point type two-terminal memory devices are examples of large-capacity non-volatile memory devices. Cross-point type two-terminal memory devices make it easy to miniaturize memory cells and achieve high integration.

The memory cells of a cross-point type two-terminal memory device have, for example, a resistance change element and a switching element. By having a switching element in the memory cell, the current flowing to memory cells other than the selected memory cell is suppressed.

Switching elements are required to have excellent characteristics, such as low leakage current, high on-state current, and high reliability.

U.S. Pat. No. 1,017,7308 US Patent Application Publication No. 2017/0352807

The problem that this invention aims to solve is to provide a memory device that has switching elements with excellent characteristics.

The memory device of the embodiment includes a memory cell including a first conductive layer, a second conductive layer, a third conductive layer provided between the first conductive layer and the second conductive layer, a resistance change layer provided between the first conductive layer and the third conductive layer, and a switching layer provided between the third conductive layer and the second conductive layer, and the switching layer includes an oxide of a first element which is at least one element selected from the group consisting of zirconium (Zr), yttrium (Y), tantalum (Ta), lanthanum (La), cerium (Ce), titanium (Ti), hafnium (Hf), and magnesium (Mg), a second element which is at least one element selected from the group consisting of zinc (Zn), tin (Sn), gallium (Ga), indium (In), and bismuth (Bi), and a compound of a third element which is at least one element selected from the group consisting of tellurium (Te), sulfur (S), and selenium (Se).

FIG. 1 is a block diagram of a storage device according to a first embodiment. 1 is a schematic cross-sectional view of a memory cell of a memory device according to a first embodiment; FIG. 4 is a diagram showing an analysis result of the storage device according to the first embodiment. FIG. 4 is a diagram showing an analysis result of the storage device according to the first embodiment. 4A and 4B are diagrams showing an example of a chemical composition of a switching layer of the memory device according to the first embodiment; FIG. 4 is an explanatory diagram of a problem of the storage device of the first embodiment. FIG. 4 is an explanatory diagram of current-voltage characteristics of the switching element according to the first embodiment. FIG. 4 is an explanatory diagram of the operation and effect of the storage device of the first embodiment. FIG. 4 is a schematic cross-sectional view of a memory cell of a memory device according to a first modified example of the first embodiment. FIG. 13 is a schematic cross-sectional view of a memory cell of a memory device according to a second modification of the first embodiment. FIG. 13 is a schematic cross-sectional view of a memory cell of a memory device according to a third modified example of the first embodiment. FIG. 13 is a schematic cross-sectional view of a memory cell of a memory device according to a second embodiment. FIG. 13 is a schematic cross-sectional view of a memory cell of a memory device according to a third embodiment. FIG. 13 is a graph showing current-voltage characteristics of the memory element according to the third embodiment. FIG. 13 is an explanatory diagram of a first operation example of a memory operation of the storage device according to the third embodiment. FIG. 13 is an explanatory diagram of a second operation example of the memory operation of the storage device according to the third embodiment. FIG. 13 is a graph showing current-voltage characteristics of a memory element according to a first modified example of the third embodiment. FIG. 13 is an explanatory diagram of a third operation example of the memory operation of the storage device according to the first modified example of the third embodiment. FIG. 13 is an explanatory diagram of a fourth operation example of the memory operation of the storage device according to the first modified example of the third embodiment. FIG. 13 is a graph showing current-voltage characteristics of a memory element according to a second modified example of the third embodiment. FIG. 13 is an explanatory diagram of a fifth operation example of the memory operation of the storage device according to the second modified example of the third embodiment. FIG. 13 is an explanatory diagram of a sixth operation example of the memory operation of the storage device according to the second modified example of the third embodiment. FIG. 13 is a graph showing current-voltage characteristics of a memory element according to a third modified example of the third embodiment. FIG. 13 is an explanatory diagram of a seventh operation example of the memory operation of the storage device according to the third modified example of the third embodiment. FIG. 13 is an explanatory diagram of an eighth operation example of the memory operation of the storage device according to the third modified example of the third embodiment. FIG. 13 is a schematic cross-sectional view of a memory cell of a memory device according to a fourth embodiment. FIG. 13 is a schematic cross-sectional view of a memory cell of a memory device according to a first modified example of the fourth embodiment. FIG. 13 is a schematic cross-sectional view of a memory cell of a memory device according to a second modified example of the fourth embodiment. FIG. 13 is a schematic cross-sectional view of a memory cell of a memory device according to a third modified example of the fourth embodiment. FIG. 13 is a schematic cross-sectional view of a memory cell of a memory device according to a fifth embodiment. FIG. 13 is a schematic cross-sectional view of a memory cell of a memory device according to a sixth embodiment. FIG. 13 is a schematic cross-sectional view of a memory cell of a memory device according to a seventh embodiment. FIG. 23 is a schematic cross-sectional view of a memory cell of a memory device according to an eighth embodiment. FIG. 13 is a schematic cross-sectional view of a memory cell of a memory device according to a ninth embodiment.

Below, an embodiment of the present invention will be described with reference to the drawings. In the following description, the same or similar components will be given the same reference numerals, and the description of components that have already been described will be omitted as appropriate.

Qualitative and quantitative analysis of the chemical composition constituting the memory device in this specification can be performed, for example, by Rutherford Backscattering Spectroscopy (RBS), Secondary Ion Mass Spectroscopy (SIMS), Energy Dispersive X-ray Spectroscopy (EDX), and Electron Energy Loss Spectroscopy (EELS). In addition, for example, a transmission electron microscope (TEM) can be used to measure the thickness of the components constituting the memory device, the distance between the components, etc. In addition, for example, X-ray photoelectron spectroscopy (XPS), X-ray absorption fine structure (XAFS), Raman spectroscopy (Raman), or EELS can be used to identify the constituent materials of the components constituting the memory device, and measure their abundance ratio, bonding state, local structure (atomic distance, coordination number), and chemical state.

First Embodiment
The memory device of the first embodiment includes a memory cell including a first conductive layer, a second conductive layer, a third conductive layer provided between the first conductive layer and the second conductive layer, a resistance change layer provided between the first conductive layer and the third conductive layer, and a switching layer provided between the third conductive layer and the second conductive layer. The switching layer includes an oxide of a first element, which is at least one element selected from the group consisting of zirconium (Zr), yttrium (Y), tantalum (Ta), lanthanum (La), cerium (Ce), titanium (Ti), hafnium (Hf), and magnesium (Mg), a second element, which is at least one element selected from the group consisting of zinc (Zn), tin (Sn), gallium (Ga), indium (In), and bismuth (Bi), and a compound of a third element, which is at least one element selected from the group consisting of tellurium (Te), sulfur (S), and selenium (Se).

The memory device of the first embodiment further includes a plurality of first wirings and a plurality of second wirings that intersect with the plurality of first wirings. The memory cell is provided in a region where one of the plurality of first wirings intersects with one of the plurality of second wirings.

Figure 1 is a block diagram of a storage device according to the first embodiment.

The memory cell array 100 of the memory device of the first embodiment includes, for example, a plurality of word lines 102 and a plurality of bit lines 103 intersecting the word lines 102 on a semiconductor substrate 101 via an insulating layer. The bit lines 103 are provided, for example, in an upper layer above the word lines 102. In addition, a first control circuit 104, a second control circuit 105, and a sense circuit 106 are provided around the memory cell array 100 as peripheral circuits.

The word line 102 is an example of a first wiring. The bit line 103 is an example of a second wiring.

Multiple memory cells MC are provided in the region where the word lines 102 and bit lines 103 intersect. The memory device of the first embodiment is a two-terminal magnetoresistive memory with a cross-point structure.

The word lines 102 are each connected to a first control circuit 104. The bit lines 103 are each connected to a second control circuit 105. The sense circuit 106 is connected to the first control circuit 104 and the second control circuit 105.

The first control circuit 104 and the second control circuit 105 have functions, for example, to select a desired memory cell MC and write data to the memory cell MC, read data from the memory cell MC, erase data from the memory cell MC, etc. When reading data, the data in the memory cell MC is read as the amount of current flowing between the word line 102 and the bit line 103, or as a change in potential of the bit line 103. The sense circuit 106 has a function to determine the amount of current and judge the polarity of the data. For example, it judges whether the data is "0" or "1".

The first control circuit 104, the second control circuit 105, and the sense circuit 106 are composed of electronic circuits using semiconductor devices formed on the semiconductor substrate 101, for example.

Figure 2 is a schematic cross-sectional view of a memory cell of the memory device of the first embodiment. Figure 2 shows a cross-section of one memory cell MC, for example, indicated by a dotted circle, in the memory cell array 100 of Figure 1.

As shown in FIG. 2, the memory cell MC includes a lower electrode 10, an upper electrode 20, an intermediate electrode 30, a switching layer 40, and a resistance change layer 50. The resistance change layer 50 includes a fixed layer 51, a tunnel layer 52, and a free layer 53.

The lower electrode 10 is an example of a first conductive layer. The upper electrode 20 is an example of a second conductive layer. The middle electrode 30 is an example of a third conductive layer.

The lower electrode 10, the switching layer 40, and the intermediate electrode 30 constitute the switching element of the memory cell MC. The intermediate electrode 30, the resistance change layer 50, and the upper electrode 20 constitute the resistance change element of the memory cell MC.

The bottom electrode 10 is connected to the word line 102. The bottom electrode 10 is, for example, a metal. The bottom electrode 10 includes, for example, at least one material selected from the group consisting of carbon, carbon nitride, tungsten, tungsten carbide, and tungsten nitride. The bottom electrode 10 may be part of the word line 102.

The upper electrode 20 is connected to the bit line 103. The upper electrode 20 is, for example, a metal. The upper electrode 20 includes, for example, at least one material selected from the group consisting of carbon, carbon nitride, tungsten, tungsten carbide, and tungsten nitride. The upper electrode 20 may be part of the bit line 103.

The intermediate electrode 30 is provided between the lower electrode 10 and the upper electrode 20. The intermediate electrode 30 is, for example, a metal. The intermediate electrode 30 includes, for example, at least one material selected from the group consisting of carbon, carbon nitride, tungsten, tungsten carbide, and tungsten nitride.

The switching layer 40 is provided between the lower electrode 10 and the intermediate electrode 30. The thickness of the switching layer 40 in the first direction from the lower electrode 10 to the upper electrode 20 is, for example, 5 nm or more and 50 nm or less. It is more preferable that the thickness of the switching layer 40 in the first direction from the lower electrode 10 to the upper electrode 20 is, for example, 5 nm or more and 20 nm or less.

The switching layer 40 has the function of suppressing an increase in the semi-selected leakage current flowing through the semi-selected cells. The switching layer 40 has a non-linear current-voltage characteristic in which the current rises sharply at a specific threshold voltage.

The switching layer 40 includes an oxide and a chalcogenide. A chalcogenide is a compound in which the chalcogen element tellurium (Te), sulfur (S), or selenium (Se) is combined with another element.

The switching layer 40 includes an oxide of a first element, which is at least one element selected from the group consisting of zirconium (Zr), yttrium (Y), tantalum (Ta), lanthanum (La), cerium (Ce), titanium (Ti), hafnium (Hf), and magnesium (Mg). The switching layer 40 includes at least one oxide selected from the group consisting of, for example, zirconium oxide, yttrium oxide, tantalum oxide, lanthanum oxide, cerium oxide, titanium oxide, hafnium oxide, and magnesium oxide. The switching layer 40 more preferably includes an oxide of a first element, which is at least one element selected from the group consisting of zirconium (Zr), yttrium (Y), lanthanum (La), and cerium (Ce). The switching layer 40 more preferably includes at least one oxide selected from the group consisting of zirconium oxide, yttrium oxide, lanthanum oxide, and cerium oxide.

Whether the switching layer 40 contains an oxide of the first element can be determined, for example, by using X-ray photoelectron spectroscopy (XPS) or electron energy loss spectroscopy (EELS).

In the switching layer 40, the ratio of the atomic concentration of oxygen (O) to the atomic concentration of the first element is, for example, 0.5 or more and 4.0 or less. In the switching layer 40, the ratio of the atomic concentration of oxygen (O) to the atomic concentration of the first element is more preferably 0.5 or more and 3.0 or less.

The switching layer 40 includes a chalcogenide, which is a compound of a second element, which is at least one element selected from the group consisting of zinc (Zn), tin (Sn), gallium (Ga), indium (In), and bismuth (Bi), and a third element, which is at least one element selected from the group consisting of tellurium (Te), sulfur (S), and selenium (Se). The switching layer 40 includes a chalcogenide of the second element. The switching layer 40 includes at least one chalcogenide selected from the group consisting of, for example, zinc telluride, tin telluride, gallium telluride, indium telluride, bismuth telluride, zinc sulfide, tin sulfide, gallium sulfide, indium sulfide, bismuth sulfide, zinc selenide, tin selenide, gallium selenide, indium selenide, and bismuth selenide. The third element is preferably tellurium (Te), and the switching layer 40 preferably contains at least one chalcogenide selected from the group consisting of zinc telluride, tin telluride, gallium telluride, indium telluride, and bismuth telluride. Tellurides have a smaller band gap than sulfides and selenides, and therefore have the advantage of being able to relatively reduce the write voltage and suppress characteristic fluctuations such as fluctuations in semi-selection leakage current and on-current when writing is repeated.

Whether the switching layer 40 contains a chalcogenide of the second element can be determined, for example, by using X-ray absorption fine structure analysis (XAFS), Raman spectroscopy (Raman), or electron energy loss spectroscopy (EELS).

Figures 3(a), 3(b), 4(a), and 4(b) are diagrams showing the analysis results of the memory device of the first embodiment. Figures 3(a), 3(b), 4(a), and 4(b) show the analysis results by XAFS of the switching layer 40 when the first element is zirconium (Zr), the second element is zinc (Zn), and the third element is tellurium (Te).

Figures 3(a) and 3(b) show the results of measuring the interatomic distance focusing on zinc (Zn). The horizontal axis of Figures 3(a) and 3(b) is the interatomic distance, and the vertical axis is the signal intensity. Figure 3(a) shows the waveform of the standard sample, and Figure 3(b) shows the measured waveform of the switching layer 40.

Comparing the waveforms in Figures 3(a) and 3(b), it can be seen that the measured waveform corresponds to zinc telluride (ZnTe). For example, in Figure 3(b), there is a peak at about 2.5 Å (angstroms), which corresponds to the zinc telluride (ZnTe) peak in Figure 3(a). Therefore, it can be confirmed that zinc telluride is contained in the switching layer 40.

Figures 4(a) and 4(b) show the results of measuring the absorption spectrum focusing on zinc (Zn). The horizontal axis of Figures 4(a) and 4(b) is energy, and the vertical axis is signal intensity. Figure 4(a) shows the waveform of the standard sample, and Figure 4(b) shows the measured waveform of the switching layer 40.

Comparing the waveforms in FIG. 4(a) and FIG. 4(b), it can be seen that the measured waveform corresponds to zinc telluride (ZnTe). For example, in FIG. 4(b), there is a peak at about 9663 eV, which corresponds to the peak of zinc telluride (ZnTe) in FIG. 4(a). Therefore, it can be confirmed that zinc telluride is contained in the switching layer 40. In addition, it can be confirmed that zinc telluride (ZnTe) is contained from the peaks that appear from about 1020 eV to about 1050 eV, for example. The peak at about 9663 eV corresponds to the K-end of zinc (Zn), and the peak from about 1020 eV to about 1050 eV corresponds to the L-end of zinc (Zn).

Note that Figures 3(a), 3(b), 4(a), and 4(b) show examples of XAFS measurements using X-rays as incident light, but measurements similar to XAFS are also possible using EELS, which uses an electron beam as incident light and is based on the same measurement principle as XAFS.

The oxide and the chalcogenide are, for example, the main components of the switching layer 40. The fact that the oxide and the chalcogenide are the main components of the switching layer 40 means that, among the substances contained in the switching layer 40, there is no substance that has a higher mole fraction than the oxide or the chalcogenide.

The sum of the atomic concentrations of the first element, the second element, the third element, and oxygen (O) in the switching layer 40 is, for example, 90% or more.

The switching layer 40 includes, for example, a mixture of the oxide and the chalcogenide. The oxide and the chalcogenide are present in the switching layer 40, for example, in a mixed state.

In the switching layer 40, the ratio of the sum of the atomic concentrations of the first element and oxygen (O) to the sum of the atomic concentrations of the first element, the second element, the third element, and oxygen (O) is, for example, 3% or more and 97% or less. For example, when the first element is zirconium (Zr), the second element is zinc (Zn), and the third element is tellurium (Te), the ratio of the sum of the atomic concentrations of zirconium (Zr) and oxygen (O) to the sum of the atomic concentrations of zirconium (Zr), zinc (Zn), tellurium (Te), and oxygen (O) in the switching layer 40 ((Zr+O)/(Zr+Zn+Te+O)) is, for example, 3% or more and 97% or less.

Figure 5 is a diagram showing an example of the chemical composition of the switching layer of the memory device of the first embodiment. Figure 5 shows an example of the chemical composition on a triangular diagram when the first element is zirconium (Zr), the second element is zinc (Zn), and the third element is tellurium (Te). The triangular diagram has the vertices of "the sum of zirconium (Zr) and oxygen (O)", "zinc (Zn)", and "tellurium (Te)" of the switching layer 40.

In the switching layer 40, the ratio of the sum of the atomic concentrations of the first element and oxygen (O) to the sum of the atomic concentrations of the first element, the second element, the third element, and oxygen (O) is, for example, 5% or more and less than 80%. In addition, the ratio of the absolute value of the difference between the atomic concentration of the third element and the atomic concentration of the second element to the sum of the atomic concentrations of the first element, the second element, the third element, and oxygen (O) is, for example, 20% or less. The above composition range when the first element is zirconium (Zr), the second element is zinc (Zn), and the third element is tellurium (Te) is the composition range of the hatched area on the triangular diagram in FIG. 5.

The ratio (Zr+O)/(Zr+Zn+Te+O) of the sum of the atomic concentrations of zirconium (Zr) and oxygen (O) to the sum of the atomic concentrations of zirconium (Zr), zinc (Zn), tellurium (Te), and oxygen (O) is, for example, 5% or more and less than 80%. And, for example, the ratio (|Te-Zn|)/(Zr+Zn+Te+O) of the absolute value of the difference between the atomic concentration of tellurium (Te) and the atomic concentration of zinc (Zn) to the sum of the atomic concentrations of zirconium (Zr), zinc (Zn), tellurium (Te), and oxygen (O) is, for example, 20% or less.

The atomic concentration of the third element in the switching layer 40 is, for example, higher than the atomic concentration of the second element. For example, if the second element is zinc (Zn) and the third element is tellurium (Te), the atomic concentration of tellurium (Te) in the switching layer 40 is, for example, higher than the atomic concentration of zinc (Zn).

In the switching layer 40, for example, there exists a chalcogenide formed by combining a second element with a third element, and an excess of the third element that does not form a chalcogenide. For example, when the second element is zinc (Zn) and the third element is tellurium (Te), zinc telluride and excess tellurium (Te) coexist in the switching layer 40.

For example, at least a portion of the oxide contained in the switching layer 40 is crystalline. Whether or not at least a portion of the oxide contained in the switching layer 40 is crystalline can be determined, for example, by using an electron beam diffraction method. Note that a portion of the chalcogenide contained in the switching layer 40 may be crystalline.

The switching layer 40 includes a fourth element, which is at least one element selected from the group consisting of carbon (C), boron (B), nitrogen (N), germanium (Ge), silicon (Si), and aluminum (Al). The atomic concentration of the fourth element included in the switching layer 40 is, for example, 5% or more and 20% or less.

The switching layer 40 can be formed, for example, by a sputtering method. The switching layer 40 including an oxide of a first element and a chalcogenide of a second element can be formed, for example, by a co-sputtering method using a target made of an oxide of the first element and a target made of a chalcogenide of the second element. The switching layer 40 can also be formed, for example, by a sputtering method using a target made of a mixture of an oxide of a first element and a chalcogenide of a second element.

The resistance change layer 50 is provided between the intermediate electrode 30 and the upper electrode 20. The resistance change layer 50 has a fixed layer 51, a tunnel layer 52, and a free layer 53. The resistance change layer 50 includes a magnetic tunnel junction composed of the fixed layer 51, the tunnel layer 52, and the free layer 53.

The resistance change layer 50 has the function of storing data by changing the resistance. For example, the resistance change layer 50 has a characteristic that the electrical resistance changes when a predetermined voltage is applied.

The fixed layer 51 is a ferromagnetic material. In the fixed layer 51, the magnetization direction does not change for a specific write voltage, and the magnetization direction is fixed in a specific direction.

The tunnel layer 52 is an insulator. Electrons pass through the tunnel layer 52 by the tunnel effect.

The free layer 53 is a ferromagnetic material. In the free layer 53, the magnetization direction changes in response to a predetermined write voltage. The magnetization direction of the free layer 53 can be either parallel to the magnetization direction of the fixed layer 51 or anti-parallel to the magnetization direction of the fixed layer 51. For example, the magnetization direction of the free layer 53 can be changed by applying a voltage and passing a current between the intermediate electrode 30 and the upper electrode 20.

The electrical resistance of the resistance change layer 50 changes when the magnetization direction of the free layer 53 is changed. When the magnetization direction of the free layer 53 is antiparallel to the magnetization direction of the fixed layer 51, a high resistance state is achieved in which current does not easily flow. On the other hand, when the magnetization direction of the free layer 53 is parallel to the magnetization direction of the fixed layer 51, a low resistance state is achieved in which current easily flows. The arrangement of the fixed layer 51 and the free layer 53 may be reversed. In other words, the intermediate electrode 30, free layer 53, tunnel layer 52, fixed layer 51, and upper electrode 20 may be stacked in this order.

Next, the operation and effects of the storage device of the first embodiment will be described.

As described above, in the memory device of the first embodiment, the resistance of the resistance change layer 50 changes by changing the magnetization direction of the free layer 53. When the magnetization direction of the free layer 53 is antiparallel to the magnetization direction of the fixed layer 51, a high resistance state is achieved in which current does not easily flow. On the other hand, when the magnetization direction of the free layer 53 is parallel to the magnetization direction of the fixed layer 51, a low resistance state is achieved in which current easily flows.

For example, the high resistance state of the resistance change layer 50 is defined as data "1", and the low resistance state is defined as data "0". The memory cell MC can maintain different resistance states, making it possible to store one bit of data, "0" and "1". Writing to one memory cell MC is performed by applying a voltage between the bit line 103 and word line 102 connected to that memory cell MC to pass a current.

Figure 6 is an explanatory diagram of the problem of the memory device of the first embodiment. Figure 6 shows the voltage applied to a memory cell MC when one memory cell MC in the memory cell array is selected for a write operation. Each memory cell MC is represented by an intersection of a word line and a bit line.

The selected memory cell MC is memory cell A (selected cell). A write voltage Vwrite is applied to the word line connected to memory cell A. In addition, 0 V is applied to the bit line connected to memory cell A.

The following describes an example in which half the write voltage (Vwrite/2) is applied to the word line and bit line that are not connected to memory cell A.

The voltage applied to memory cell C (unselected cell) connected to the word line and bit line that are not connected to memory cell A is 0V. In other words, no voltage is applied.

Meanwhile, a voltage that is half the write voltage Vwrite (Vwrite/2) is applied to memory cell B (half-selected cell) connected to the word line or bit line connected to memory cell A. Therefore, a half-selection leakage current flows through memory cell B (half-selected cell).

In addition, as an alternative to the above, a method of applying half the write voltage (Vwrite/2) to the word line connected to memory cell A, a negative voltage (-Vwrite/2) that is half the write voltage to the bit line, and 0 V to the word line and bit line not connected to memory cell A may be used.

Figure 7 is an explanatory diagram of the current-voltage characteristics of the switching element of the first embodiment. The horizontal axis is the voltage applied to the switching element, and the vertical axis is the current flowing through the switching element.

The switching element has a nonlinear current-voltage characteristic in which the current rises sharply at a threshold voltage Vth. The threshold voltage Vth is, for example, 0.5 V or more and 3 V or less.

The write voltage Vwrite is set so that the write voltage Vwrite is higher than the threshold voltage Vth and half the write voltage Vwrite (Vwrite/2) is lower than the threshold voltage. The current that flows through the switching element when the write voltage Vwrite is applied is the on-current (Ion in FIG. 7). The current that flows through the switching element when half the write voltage Vwrite (Vwrite/2) is applied is the half-select leakage current (Ihalf in FIG. 7).

The read voltage Vread of the memory cell MC is set to a voltage higher than the threshold voltage Vth and lower than the write voltage Vwrite, for example, as shown in FIG. 7. Therefore, when reading the memory cell MC, the half-selection leakage current flowing through the half-selected cell can also be suppressed.

If the half-select leakage current is large, for example, it will lead to increased power consumption of the chip. Also, for example, the voltage drop in the wiring will increase, and a sufficiently high voltage will not be applied to the selected cell, making the write operation to the memory cell MC unstable. Also, if the on-current is small, for example, the current flowing to the selected cell will be insufficient, resulting in insufficient writing to the memory cell MC. Therefore, the current-voltage characteristics of the switching element are required to achieve both a low half-select leakage current and a high on-current.

Furthermore, the current-voltage characteristics of the switching element must be highly reliable. In other words, it is necessary to suppress characteristic variations, such as variations in the semi-selection leakage current and the on-current, when data is repeatedly written to the memory cell MC, and to achieve high reliability.

For example, as a switching element of the first comparative example, consider a switching element in which the switching layer is formed only from a chalcogenide of the second element and does not contain an oxide of the first element. The switching element of the first comparative example has problems such as a high semi-selection leakage current and large fluctuations in characteristics when data is repeatedly written to the memory cell MC.

One of the causes of the above problems occurring in the switching element of the first comparative example is believed to be the crystallization of the amorphous chalcogenide. For example, it is believed that as the chalcogenide crystallizes, the density increases and the interatomic distance decreases, causing an increase in leakage current. It is also believed that, for example, the crystal grain boundaries of the chalcogenide increase the leakage current. It is also believed that, for example, the stress generated by the crystallization of the chalcogenide causes film peeling between the switching layer and the electrode.

For example, as a switching element of the second comparative example, consider a switching element in which the switching layer is formed only from an oxide of the first element and the second element, and does not contain a chalcogenide of the second element. The switching element of the second comparative example has a problem in that the characteristics fluctuate greatly when data is repeatedly written to the memory cell MC.

One of the causes of the above problem occurring in the switching element of the second comparative example is thought to be the aggregation of the second element in the switching layer when writing is repeated. For example, it is thought that this is caused by the aggregation of the second element forming a path for leakage current.

The switching layer 40 of the switching element of the first embodiment contains an oxide of a first element and a chalcogenide of a second element. Since the switching layer 40 contains an oxide of a first element and a chalcogenide of a second element, a low semi-selective leakage current and suppression of characteristic fluctuations can be achieved.

In the first embodiment, it is believed that the reason why low semi-selective leakage current and suppression of characteristic fluctuations of the switching element can be achieved is that the switching layer 40 contains an oxide of the first element and a chalcogenide of the second element, which suppresses crystallization of the chalcogenide of the second element. In other words, it is believed that this is because the amorphous state of the chalcogenide of the second element is stabilized. In particular, in the region of the switching layer 40 where the chalcogenide of the second element occupies a large proportion, it is believed that the suppression of crystallization of the chalcogenide of the second element becomes the dominant factor, and excellent characteristics of the switching element can be achieved.

In the first embodiment, the low semi-selective leakage current of the switching element and the suppression of characteristic fluctuations are realized because the switching layer 40 contains an oxide of the first element and a chalcogenide of the second element, which suppresses aggregation of the second element. In other words, the second element is contained in the switching layer 40 as a chalcogenide of the second element having a higher melting point than the second element alone, which suppresses diffusion of the second element and suppresses aggregation of the second element. In particular, in the region where the oxide of the first element occupies a large proportion of the switching layer 40, the suppression of aggregation of the second element is the dominant factor, and it is believed that excellent characteristics of the switching element can be realized.

In the switching layer 40, the ratio of the atomic concentration of oxygen (O) to the atomic concentration of the first element is preferably 0.5 to 4.0, more preferably 0.5 to 3.0. By satisfying the above range, the characteristics of the switching element are further improved.

In the switching layer 40, the ratio of the sum of the atomic concentrations of the first element and oxygen (O) to the sum of the atomic concentrations of the first element, the second element, the third element, and oxygen (O) is, for example, preferably 3% or more and 97% or less, more preferably 5% or more and less than 80%, even more preferably 10% or more and less than 60%, and most preferably 20% or more and less than 50%. By satisfying the above range, the characteristics of the switching element are further improved.

In addition, in the switching layer 40, the ratio of the sum of the atomic concentrations of the first element and oxygen (O) to the sum of the atomic concentrations of the first element, the second element, the third element, and oxygen (O) is preferably, for example, 5% or more and less than 80%. In addition, the ratio of the absolute value of the difference between the atomic concentration of the third element and the atomic concentration of the second element to the sum of the atomic concentrations of the first element, the second element, the third element, and oxygen (O) is preferably 20% or less, more preferably 10% or less, and even more preferably 5% or less. By satisfying the above range, the characteristics of the switching element are further improved.

Figure 8 is an explanatory diagram of the action and effect of the memory device of the first embodiment. Figure 8 is a diagram showing the relationship between the chemical composition of the switching layer 40 and the semi-selective leakage current. Figure 8 shows measurement data on a triangular diagram when the first element is zirconium (Zr), the second element is zinc (Zn), and the third element is tellurium (Te). The triangular diagram has the vertices at the "sum of zirconium (Zr) and oxygen (O)", "zinc (Zn)", and "tellurium (Te)" of the switching layer 40.

Measurement points A, B, C, and D are categorized by the amount of semi-selective leakage current measured. Measurement point A has the smallest semi-selective leakage current, and measurement point D has the largest semi-selective leakage current.

8, from the viewpoint of reducing the semi-selective leakage current, it is preferable that the switching layer 40 has a chemical composition in the hatched region on the triangular diagram. That is, it is preferable that the atomic concentration of tellurium (Te) in the switching layer 40 is higher than the atomic concentration of zinc (Zn), and the ratio of the sum of the atomic concentrations of zirconium (Zr) and oxygen (O) to the sum of the atomic concentrations of zirconium (Zr), zinc (Zn), tellurium (Te), and oxygen (O) is 5% or more and less than 80%, and the ratio of the difference between the atomic concentration of tellurium (Te) and the atomic concentration of zinc (Zn) to the sum of the atomic concentrations of zirconium (Zr), zinc (Zn), tellurium (Te), and oxygen (O) is 5% or more and 20% or less.

Generalizing the above findings, it is preferable that the atomic concentration of the third element in the switching layer 40 is higher than the atomic concentration of the second element, the ratio of the sum of the atomic concentrations of the first element and oxygen to the sum of the atomic concentrations of the first element, the second element, the third element, and oxygen (O) is 5% or more and less than 80%, and the ratio of the difference between the atomic concentration of the third element and the atomic concentration of the second element to the sum of the atomic concentrations of the first element, the second element, the third element, and oxygen (O) is 5% or more and 20% or less. Since the first element, the second element, and the third element are elements having properties similar to zirconium (Zr), zinc (Zn), and tellurium (Te), respectively, it is considered that the above findings regarding zirconium (Zr), zinc (Zn), and tellurium (Te) can be generalized.

It is preferable that the atomic concentration of the third element in the switching layer 40 is higher than the atomic concentration of the second element. When the atomic concentration of the third element is higher than the atomic concentration of the second element, the characteristics of the switching element are further improved.

From the viewpoint of further improving the characteristics of the switching element, it is preferable that the switching layer 40 contains a fourth element which is at least one element selected from the group consisting of carbon (C), boron (B), nitrogen (N), germanium (Ge), silicon (Si), and aluminum (Al). From the viewpoint of further improving the characteristics of the switching element, it is preferable that the atomic concentration of the fourth element contained in the switching layer 40 is 5% or more and 20% or less.

From the viewpoint of further improving the characteristics of the switching element, it is preferable that at least a portion of the oxide of the first element contained in the switching layer 40 is crystalline. It is believed that by making at least a portion of the oxide of the first element crystalline, the diffusion of the first element is suppressed, and an increase in leakage current caused by the separated first element can be suppressed.

(First Modification)
The memory device of the first variant of the first embodiment differs from the memory device of the first embodiment in that the first conductive layer includes a first portion and a second portion, and the first portion includes at least one element selected from hafnium (Hf), aluminum (Al), magnesium (Mg), zirconium (Zr), and titanium (Ti).

Figure 9 is a schematic cross-sectional view of a memory cell of a memory device according to a first modification of the first embodiment. Figure 9 corresponds to Figure 2 of the first embodiment.

The lower electrode 10 includes a first portion 11 and a second portion 12. The second portion 12 is provided between the first portion 11 and the switching layer 40.

The first portion 11 includes at least one element selected from hafnium (Hf), aluminum (Al), magnesium (Mg), zirconium (Zr), and titanium (Ti). The first portion 11 includes, for example, a boride of the above element. The first portion 11 includes, for example, at least one substance selected from the group consisting of hafnium, hafnium boride, aluminum magnesium boride, zirconium, zirconium boride, and titanium boride.

The second portion 12 includes, for example, at least one material selected from the group consisting of carbon, carbon nitride, tungsten, tungsten carbide, and tungsten nitride.

In the memory device of the first modification of the first embodiment, the first portion 11 of the lower electrode 10 contains at least one element selected from hafnium (Hf), aluminum (Al), magnesium (Mg), zirconium (Zr), and titanium (Ti), thereby suppressing deterioration of the characteristics of the resistance change element. In addition, the first portion 11 is not in contact with the switching layer 40, thereby suppressing detachment of oxygen (O) from the switching layer 40 and suppressing deterioration of the characteristics of the switching element.

As described above, according to the first modification of the first embodiment, a switching element having excellent characteristics such as low semi-selection leakage current and high reliability can be realized, similar to the first embodiment.

(Second Modification)
A memory device of the second modification of the first embodiment differs from the memory device of the first embodiment in that the first conductive layer includes a first portion and a second portion, the first portion including at least one element selected from among hafnium (Hf), aluminum (Al), magnesium (Mg), zirconium (Zr), and titanium (Ti), the second conductive layer includes one element selected from among hafnium (Hf), aluminum (Al), magnesium (Mg), zirconium (Zr), and titanium (Ti), and the third conductive layer includes a third portion and a fourth portion, the fourth portion including at least one element selected from among hafnium (Hf), aluminum (Al), magnesium (Mg), zirconium (Zr), and titanium (Ti).

Figure 10 is a schematic cross-sectional view of a memory cell of a memory device according to a second modification of the first embodiment. Figure 10 corresponds to Figure 2 of the first embodiment.

The lower electrode 10 includes a first portion 11 and a second portion 12. The second portion 12 is provided between the first portion 11 and the switching layer 40.

The first portion 11 includes at least one element selected from hafnium (Hf), aluminum (Al), magnesium (Mg), zirconium (Zr), and titanium (Ti). The first portion 11 includes, for example, a boride of the above element. The first portion 11 includes, for example, at least one substance selected from the group consisting of hafnium, hafnium boride, aluminum magnesium boride, zirconium, zirconium boride, and titanium boride.

The second portion 12 includes, for example, at least one material selected from the group consisting of carbon, carbon nitride, tungsten, tungsten carbide, and tungsten nitride.

The upper electrode 20 includes at least one element selected from hafnium (Hf), aluminum (Al), magnesium (Mg), zirconium (Zr), and titanium (Ti). The upper electrode 20 includes, for example, a boride of the above element. The upper electrode 20 includes, for example, at least one material selected from the group consisting of hafnium, hafnium boride, aluminum magnesium boride, zirconium, zirconium boride, and titanium boride.

The intermediate electrode 30 includes a third portion 31 and a fourth portion 32. The third portion 31 is provided between the fourth portion 32 and the switching layer 40.

The third portion 31 includes, for example, at least one material selected from the group consisting of carbon, carbon nitride, tungsten, tungsten carbide, and tungsten nitride.

The fourth portion 32 includes at least one element selected from hafnium (Hf), aluminum (Al), magnesium (Mg), zirconium (Zr), and titanium (Ti). The fourth portion 32 includes, for example, a boride of the above element. The fourth portion 32 includes, for example, at least one substance selected from the group consisting of hafnium, hafnium boride, aluminum magnesium boride, zirconium, zirconium boride, and titanium boride.

In the memory device of the second modification of the first embodiment, the first portion 11 of the lower electrode 10, the upper electrode 20, and the fourth portion 32 of the intermediate electrode 30 contain at least one element selected from hafnium (Hf), aluminum (Al), magnesium (Mg), zirconium (Zr), and titanium (Ti), thereby suppressing deterioration of the characteristics of the resistance change element. In addition, the first portion 11 of the lower electrode 10, the upper electrode 20, and the fourth portion 32 of the intermediate electrode 30 are not in contact with the switching layer 40, thereby suppressing detachment of oxygen (O) from the switching layer 40 and suppressing deterioration of the characteristics of the switching element.

As described above, according to the second modification of the first embodiment, a switching element having excellent characteristics such as low semi-selection leakage current and high reliability can be realized, similar to the first embodiment.

(Third Modification)
A memory device of the third modification of the first embodiment differs from the memory device of the first embodiment in that the first conductive layer includes a first portion, a second portion, and a fifth portion, the first portion including at least one element selected from among hafnium (Hf), aluminum (Al), magnesium (Mg), zirconium (Zr), and titanium (Ti), the second conductive layer includes at least one element selected from among hafnium (Hf), aluminum (Al), magnesium (Mg), zirconium (Zr), and titanium (Ti), and the third conductive layer includes a third portion and a fourth portion, and the fourth portion includes at least one element selected from among hafnium (Hf), aluminum (Al), magnesium (Mg), zirconium (Zr), and titanium (Ti).

Figure 11 is a schematic cross-sectional view of a memory cell of a memory device according to a third modified example of the first embodiment. Figure 11 corresponds to Figure 2 of the first embodiment.

The lower electrode 10 includes a first portion 11, a second portion 12, and a fifth portion 13. The second portion 12 is provided between the first portion 11 and the switching layer 40. The first portion 11 is provided between the fifth portion 13 and the second portion 12.

The first portion 11 includes at least one element selected from hafnium (Hf), aluminum (Al), magnesium (Mg), zirconium (Zr), and titanium (Ti). The first portion 11 includes, for example, a boride of the above element. The first portion 11 includes, for example, at least one substance selected from the group consisting of hafnium, hafnium boride, aluminum magnesium boride, zirconium, zirconium boride, and titanium boride.

The second portion 12 and the fifth portion 13 contain, for example, at least one material selected from the group consisting of carbon, carbon nitride, tungsten, tungsten carbide, and tungsten nitride.

The upper electrode 20 includes at least one element selected from hafnium (Hf), aluminum (Al), magnesium (Mg), zirconium (Zr), and titanium (Ti). The upper electrode 20 includes, for example, a boride of the above element. The upper electrode 20 includes, for example, at least one material selected from the group consisting of hafnium, hafnium boride, aluminum magnesium boride, zirconium, zirconium boride, and titanium boride.

The intermediate electrode 30 includes a third portion 31 and a fourth portion 32. The third portion 31 is provided between the fourth portion 32 and the switching layer 40.

The third portion 31 includes, for example, at least one material selected from the group consisting of carbon, carbon nitride, tungsten, tungsten carbide, and tungsten nitride.

The fourth portion 32 includes at least one element selected from hafnium (Hf), aluminum (Al), magnesium (Mg), zirconium (Zr), and titanium (Ti). The fourth portion 32 includes, for example, a boride of the above element. The fourth portion 32 includes, for example, at least one substance selected from the group consisting of hafnium, hafnium boride, aluminum magnesium boride, zirconium, zirconium boride, and titanium boride.

In the memory device of the third modification of the first embodiment, the first portion 11 of the lower electrode 10, the upper electrode 20, and the fourth portion 32 of the intermediate electrode 30 contain at least one element selected from hafnium (Hf), aluminum (Al), magnesium (Mg), zirconium (Zr), and titanium (Ti), thereby suppressing deterioration of the characteristics of the resistance change element. In addition, the first portion 11 of the lower electrode 10, the upper electrode 20, and the fourth portion 32 of the intermediate electrode 30 are not in contact with the switching layer 40, thereby suppressing detachment of oxygen (O) from the switching layer 40 and suppressing deterioration of the characteristics of the switching element.

As described above, according to the third modification of the first embodiment, a switching element having excellent characteristics such as low semi-selection leakage current and high reliability can be realized, similar to the first embodiment.

According to the first embodiment and the modification, a switching element having excellent characteristics such as low semi-selection leakage current and high reliability can be realized. Therefore, according to the first embodiment and the modification, a memory device having a switching element with excellent characteristics can be realized.

Second Embodiment
The storage device of the second embodiment differs from the storage device of the first embodiment in that the storage device of the second embodiment is a resistive random access memory (ReRAM).

Figure 12 is a schematic cross-sectional view of a memory cell of a memory device of the second embodiment. Figure 12 shows a cross-section of one memory cell MC, for example, indicated by a dotted circle, in the memory cell array 100 of Figure 1.

As shown in FIG. 12, the memory cell MC includes a lower electrode 10, an upper electrode 20, an intermediate electrode 30, a switching layer 40, and a resistance change layer 50. The resistance change layer 50 includes a high resistance layer 50x and a low resistance layer 50y.

The lower electrode 10 is an example of a first conductive layer. The upper electrode 20 is an example of a second conductive layer. The middle electrode 30 is an example of a third conductive layer.

The lower electrode 10, the switching layer 40, and the intermediate electrode 30 constitute the switching element of the memory cell MC. The intermediate electrode 30, the resistance change layer 50, and the upper electrode 20 constitute the resistance change element of the memory cell MC.

The configuration of the switching layer 40 is the same as that of the memory device of the first embodiment.

The resistance change layer 50 includes a high resistance layer 50x and a low resistance layer 50y.

The high resistance layer 50x is, for example, a metal oxide. The high resistance layer 50x is, for example, aluminum oxide, hafnium oxide, zirconium oxide, tantalum oxide, or niobium oxide.

The low resistance layer 50y is, for example, a metal oxide. The low resistance layer 50y is, for example, titanium oxide, niobium oxide, tantalum oxide, or tungsten oxide.

The resistance change layer 50 has the function of storing data by changing the resistance. For example, the resistance change layer 50 has a characteristic that the electrical resistance changes when a predetermined voltage is applied.

By applying a voltage to the resistance change layer 50, the resistance change layer 50 changes from a high resistance state to a low resistance state, or from a low resistance state to a high resistance state. By applying a voltage to the resistance change layer 50, oxygen ions move between the high resistance layer 50x and the low resistance layer 50y, and the amount of oxygen vacancies (oxygen vacancies) in the low resistance layer 50y changes. The conductivity of the resistance change layer 50 changes according to the amount of oxygen vacancies in the low resistance layer 50y. The low resistance layer 50y is a so-called vacancy modulated conductive oxide.

For example, a high resistance state is defined as data "1" and a low resistance state is defined as data "0." A memory cell MC can store one bit of data, "0" and "1."

As described above, according to the memory device of the second embodiment, a switching element having excellent characteristics such as low semi-selection leakage current and high reliability can be realized, as in the first embodiment. Therefore, according to the second embodiment, a memory device having a switching element with excellent characteristics can be realized.

Third Embodiment
The memory device of the third embodiment includes a memory cell including a first conductive layer, a second conductive layer, and a memory layer provided between the first conductive layer and the second conductive layer, and the memory layer includes an oxide of a first element, which is at least one element selected from the group consisting of zirconium (Zr), yttrium (Y), tantalum (Ta), lanthanum (La), cerium (Ce), titanium (Ti), hafnium (Hf), and magnesium (Mg), a compound of a second element, which is at least one element selected from the group consisting of zinc (Zn), tin (Sn), gallium (Ga), indium (In), and bismuth (Bi), and a third element, which is at least one element selected from the group consisting of tellurium (Te), sulfur (S), and selenium (Se).

The memory device of the third embodiment further includes a plurality of first wirings and a plurality of second wirings that intersect with the plurality of first wirings. The memory cell is provided in a region where one of the plurality of first wirings intersects with one of the plurality of second wirings.

The memory device of the third embodiment differs from the memory devices of the first and second embodiments in that the memory cell does not include a third conductive layer and a resistance change layer, but includes a configuration similar to the switching layer of the first and second embodiments as a memory layer. Below, some of the description that overlaps with the first and second embodiments will be omitted.

Figure 13 is a schematic cross-sectional view of a memory cell of a memory device of the third embodiment. Figure 13 shows a cross-section of one memory cell MC, for example, indicated by a dotted circle, in the memory cell array 100 of Figure 1.

As shown in FIG. 13, the memory cell MC includes a lower electrode 10, an upper electrode 20, and a memory layer 60.

The lower electrode 10 is an example of a first conductive layer. The upper electrode 20 is an example of a second conductive layer.

The lower electrode 10, the memory layer 60, and the upper electrode 20 constitute the memory element of the memory cell MC. The memory element of the memory cell MC has a switching function and a function of storing information.

The memory layer 60 has a configuration similar to that of the switching layer 40 of the first and second embodiments. That is, the memory layer 60 includes an oxide of a first element, which is at least one element selected from the group consisting of zirconium (Zr), yttrium (Y), tantalum (Ta), lanthanum (La), cerium (Ce), titanium (Ti), hafnium (Hf), and magnesium (Mg), a second element, which is at least one element selected from the group consisting of zinc (Zn), tin (Sn), gallium (Ga), indium (In), and bismuth (Bi), and a compound of a third element, which is at least one element selected from the group consisting of tellurium (Te), sulfur (S), and selenium (Se).

The memory layer 60 has a nonlinear current-voltage characteristic in which the current rises steeply at a specific threshold voltage. The memory layer 60 also has a characteristic in which the threshold voltage changes with application of a specific voltage. The memory layer 60 has a characteristic in which the electrical resistance changes with application of a specific voltage. In the third embodiment, the high resistance state is a state in which the resistance of the memory layer 60 at the read voltage is relatively high. In the third embodiment, the low resistance state is a state in which the resistance of the memory layer 60 at the read voltage is relatively low.

The memory layer 60 has a function of suppressing an increase in the semi-selected leakage current flowing through the semi-selected cells. The memory layer 60 also has a function of storing data by resistance changes. The memory layer 60 is a single layer and realizes the function of the switching layer 40 and the resistance change layer 50 of the first and second embodiments.

Figure 14 is an explanatory diagram of the current-voltage characteristics of the memory element of the third embodiment. The horizontal axis is the voltage applied to the memory element, and the vertical axis is the current flowing through the memory element. In Figure 14, the horizontal axis shows the voltage applied to the upper electrode 20 with the potential of the lower electrode 10 as the reference. Figure 14 shows the current-voltage characteristics of the memory layer 60 of the third embodiment. Figure 14 shows the current-voltage characteristics of the memory cell MC of the third embodiment.

The memory element of the third embodiment exhibits different current-voltage characteristics when a predetermined positive voltage is applied to the upper electrode 20 and when a predetermined negative voltage is applied to the upper electrode 20. In FIG. 14, the current-voltage characteristics when a predetermined positive voltage is applied to the upper electrode 20 are shown by a solid line, and the current-voltage characteristics when a predetermined negative voltage is applied to the upper electrode 20 are shown by a dotted line.

When a predetermined positive voltage is applied to the upper electrode 20, the current rises sharply on the positive voltage side at the first positive voltage side threshold voltage Vtpp. Also, when a predetermined positive voltage is applied to the upper electrode 20, the current rises sharply on the negative voltage side at the first negative voltage side threshold voltage Vtpn.

On the other hand, when a predetermined negative voltage is applied to the upper electrode 20, the current rises sharply on the positive voltage side at the second positive voltage side threshold voltage Vtnp. Also, when a predetermined negative voltage is applied to the upper electrode 20, the current rises sharply on the negative voltage side at the second negative voltage side threshold voltage Vtnn.

The first positive voltage side threshold voltage Vtpp is higher than the second positive voltage side threshold voltage Vtnp. Also, the first negative voltage side threshold voltage Vtpn is lower than the second negative voltage side threshold voltage Vtnn.

The memory element of the third embodiment can be in a high resistance state or a low resistance state on both the positive voltage side and the negative voltage side. When a predetermined positive voltage is applied to the upper electrode 20, it is in a high resistance state on both the positive voltage side and the negative voltage side. On the other hand, when a predetermined negative voltage is applied to the upper electrode 20, it is in a low resistance state on both the positive voltage side and the negative voltage side. Hereinafter, the high resistance state is defined as data "1" and the low resistance state is defined as data "0". The memory cell MC is capable of storing 1 bit of data, "0" and "1".

Figure 15 is an explanatory diagram of a first operation example of the memory operation of the storage device of the third embodiment. Figure 15 shows the positive write voltage Vwp, half the positive write voltage Vwp (Vwp/2), the negative write voltage Vwn, half the negative write voltage Vwn (Vwn/2), and the negative read voltage Vrn when performing memory operation.

In the first operation example, the high resistance state and low resistance state on the negative voltage side are used for memory operation. In the first operation example, the negative read voltage Vrn is used as the read voltage.

When writing data "1" to the selected cell, a positive write voltage Vwp is applied to the upper electrode 20. The positive write voltage Vwp is a voltage higher than the first positive voltage threshold voltage Vtpp. By applying the positive write voltage Vwp to the upper electrode 20, a high resistance state is realized on the negative voltage side, and data "1" is written to the selected cell.

When writing data "0" to the selected cell, a negative write voltage Vwn is applied to the upper electrode 20. The negative write voltage Vwn is a voltage lower than the first negative voltage threshold voltage Vtpn. By applying the negative write voltage Vwn to the upper electrode 20, a low resistance state is realized on the negative voltage side, and data "0" is written to the selected cell.

In the first operation example, when writing data "1" to a selected cell, if the data stored in the selected cell is data "0", even if the positive write voltage Vwp is lower than the first positive voltage threshold voltage Vtpp, current flows as long as it is higher than the second positive voltage threshold voltage Vtnp. Therefore, there is a possibility that data "1" can be written. Therefore, for example, by setting the positive write voltage Vwp to a voltage between the second positive voltage threshold voltage Vtnp and the first positive voltage threshold voltage Vtpp, it is possible to achieve low power consumption or high reliability of the memory device.

When a positive write voltage Vwp is applied to the selected cell, a voltage Vwp/2 is applied to the semi-selected cell. When a negative write voltage Vwn is applied to the selected cell, a voltage Vwn/2 is applied to the semi-selected cell. The voltage Vwp/2 is lower than the second positive voltage threshold voltage Vtnp. The voltage Vwn/2 is higher than the second negative voltage threshold voltage Vtnn.

Therefore, even when the half-selected cell is in a low resistance state, the half-selection leakage current flowing through the half-selected cell can be suppressed. Therefore, the memory element also functions as a switching element.

When reading data from a selected cell, a negative read voltage Vrn is applied to the selected cell. The data in the selected cell can be determined by detecting the change in current or potential caused by the difference in current flow between data "1" and data "0".

In the case of the first operation example, whether the data of the selected cell is data "1" or data "0", data destruction does not occur by applying the negative read voltage Vrn. In other words, in the case of the first operation example, non-destructive readout is possible whether the data of the selected cell is data "1" or data "0".

Figure 16 is an explanatory diagram of a second operation example of the memory operation of the storage device of the third embodiment. Figure 16 shows the positive write voltage Vwp, half the positive write voltage Vwp (Vwp/2), the negative write voltage Vwn, half the negative write voltage Vwn (Vwn/2), and the positive read voltage Vrp when performing memory operation.

In the second operation example, the high resistance state and low resistance state on the positive voltage side are used for memory operation. In the second operation example, the positive side read voltage Vrp is used as the read voltage.

When writing data "1" to the selected cell, a positive write voltage Vwp is applied to the upper electrode 20. The positive write voltage Vwp is a voltage higher than the first positive voltage threshold voltage Vtpp. By applying the positive write voltage Vwp to the upper electrode 20, a high resistance state is realized on the positive voltage side, and data "1" is written to the selected cell.

When writing data "0" to the selected cell, a negative write voltage Vwn is applied to the upper electrode 20. The negative write voltage Vwn is a voltage lower than the first negative voltage threshold voltage Vtpn. By applying the negative write voltage Vwn to the upper electrode 20, a low resistance state is realized on the positive voltage side, and data "0" is written to the selected cell.

In the second operation example, when writing data "1" to a selected cell, if the data stored in the selected cell is data "0", even if the positive write voltage Vwp is lower than the first positive voltage threshold voltage Vtpp, current flows as long as it is higher than the second positive voltage threshold voltage Vtnp. Therefore, there is a possibility that data "1" can be written. Therefore, for example, by setting the positive write voltage Vwp to a voltage between the second positive voltage threshold voltage Vtnp and the first positive voltage threshold voltage Vtpp, it is possible to achieve low power consumption or high reliability of the memory device.

When a positive write voltage Vwp is applied to the selected cell, a voltage Vwp/2 is applied to the semi-selected cell. When a negative write voltage Vwn is applied to the selected cell, a voltage Vwn/2 is applied to the semi-selected cell. The voltage Vwp/2 is lower than the second positive voltage threshold voltage Vtnp. The voltage Vwn/2 is higher than the second negative voltage threshold voltage Vtnn.

Therefore, even when the half-selected cell is in a low resistance state, the half-selection leakage current flowing through the half-selected cell can be suppressed. Therefore, the memory element also functions as a switching element.

When reading data from a selected cell, a positive read voltage Vrp is applied to the selected cell. The data in the selected cell can be determined by detecting the change in current or potential caused by the difference in current flow between data "1" and data "0".

In the case of the second operation example, if the data of the selected cell is data "1", the data is not destroyed by applying the positive read voltage Vrp. In other words, in the case of the second operation example, if the data of the selected cell is data "1", non-destructive reading is possible.

On the other hand, if the data of the selected cell is data "0", applying a positive read voltage Vrp higher than the second positive voltage threshold voltage Vtnp will cause a current to flow, which may change the data of the selected cell to data "1". In other words, in the case of the second operation example, if the data of the selected cell is data "0", a destructive read may occur. Therefore, if the data of the selected cell is data "0", after the data of the selected cell is read, it may be necessary to rewrite data "0" in order to maintain the data of the selected cell.

(First Modification)
The storage device of the first modified example of the third embodiment differs from the storage device of the third embodiment in that the current-voltage characteristics of the memory element are different.

Figure 17 is an explanatory diagram of the current-voltage characteristics of a memory element of the first modified example of the third embodiment. The horizontal axis is the voltage applied to the memory element, and the vertical axis is the current flowing through the memory element. In Figure 17, the horizontal axis shows the voltage applied to the upper electrode 20 with the potential of the lower electrode 10 as the reference. Figure 17 shows the current-voltage characteristics of the memory layer 60 of the first modified example of the third embodiment. Figure 17 shows the current-voltage characteristics of a memory cell MC of the first modified example of the third embodiment.

The memory element of the first modified example of the third embodiment exhibits different current-voltage characteristics when a predetermined positive voltage is applied to the upper electrode 20 and when a predetermined negative voltage is applied to the upper electrode 20. In FIG. 17, the current-voltage characteristics when a predetermined positive voltage is applied to the upper electrode 20 are shown by a solid line, and the current-voltage characteristics when a predetermined negative voltage is applied to the upper electrode 20 are shown by a dotted line.

When a predetermined positive voltage is applied to the upper electrode 20, the current rises sharply on the positive voltage side at the first positive voltage side threshold voltage Vtpp. Also, when a predetermined positive voltage is applied to the upper electrode 20, the current rises sharply on the negative voltage side at the first negative voltage side threshold voltage Vtpn.

On the other hand, when a predetermined negative voltage is applied to the upper electrode 20, the current rises sharply on the positive voltage side at the second positive voltage side threshold voltage Vtnp. Also, when a predetermined negative voltage is applied to the upper electrode 20, the current rises sharply on the negative voltage side at the second negative voltage side threshold voltage Vtnn.

The first positive voltage side threshold voltage Vtpp is lower than the second positive voltage side threshold voltage Vtnp. Also, the first negative voltage side threshold voltage Vtpn is higher than the second negative voltage side threshold voltage Vtnn.

The memory element of the first modified example of the third embodiment can be in a high resistance state or a low resistance state on both the positive voltage side and the negative voltage side. When a predetermined positive voltage is applied to the upper electrode 20, it is in a low resistance state on both the positive voltage side and the negative voltage side. On the other hand, when a predetermined negative voltage is applied to the upper electrode 20, it is in a high resistance state on both the positive voltage side and the negative voltage side. Hereinafter, the high resistance state is defined as data "1" and the low resistance state is defined as data "0". The memory cell MC is capable of storing 1 bit of data, "0" and "1".

Figure 18 is an explanatory diagram of a third operation example of the memory operation of the storage device of the first modified example of the third embodiment. Figure 18 shows the positive write voltage Vwp, half the positive write voltage Vwp (Vwp/2), the negative write voltage Vwn, half the negative write voltage Vwn (Vwn/2), and the negative read voltage Vrn when performing memory operation.

In the third operation example, the high resistance state and low resistance state on the negative voltage side are used for memory operation. In the third operation example, the negative read voltage Vrn is used as the read voltage.

When writing data "1" to the selected cell, a negative write voltage Vwn is applied to the upper electrode 20. The negative write voltage Vwn is a voltage lower than the second negative voltage threshold voltage Vtnn. By applying the negative write voltage Vwn to the upper electrode 20, a high resistance state is realized on the negative voltage side, and data "1" is written to the selected cell.

When writing data "0" to the selected cell, a positive write voltage Vwp is applied to the upper electrode 20. The positive write voltage Vwp is a voltage higher than the second positive voltage threshold voltage Vtnp. By applying the positive write voltage Vwp to the upper electrode 20, a low resistance state is achieved on the negative voltage side, and data "0" is written to the selected cell.

In the third operation example, when writing data "1" to a selected cell, if the data stored in the selected cell is data "0", even if the negative write voltage Vwn is higher than the second negative voltage side threshold voltage Vtnn, current flows as long as it is lower than the first negative voltage side threshold voltage Vtpn. Therefore, there is a possibility that data "1" can be written. Therefore, for example, by setting the negative write voltage Vwn to a voltage between the second negative voltage side threshold voltage Vtnn and the first negative voltage side threshold voltage Vtpn, it is possible to achieve low power consumption or high reliability of the memory device.

When a positive write voltage Vwp is applied to the selected cell, a voltage Vwp/2 is applied to the semi-selected cell. When a negative write voltage Vwn is applied to the selected cell, a voltage Vwn/2 is applied to the semi-selected cell. The voltage Vwp/2 is lower than the first positive voltage threshold voltage Vtpp. The voltage Vwn/2 is higher than the first negative voltage threshold voltage Vtpn.

Therefore, even when the half-selected cell is in a low resistance state, the half-selection leakage current flowing through the half-selected cell can be suppressed. Therefore, the memory element also functions as a switching element.

When reading data from a selected cell, a negative read voltage Vrn is applied to the selected cell. The data in the selected cell can be determined by detecting the change in current or potential caused by the difference in current flow between data "1" and data "0".

In the case of the third operation example, if the data of the selected cell is data "1", the data is not destroyed by applying the negative read voltage Vrn. In other words, in the case of the third operation example, if the data of the selected cell is data "1", non-destructive reading is possible.

On the other hand, if the data of the selected cell is data "0", applying a negative read voltage Vrn lower than the first negative voltage threshold voltage Vtpn may cause a current to flow and the data of the selected cell to change to data "1". In other words, in the case of the third operation example, if the data of the selected cell is data "0", a destructive read may occur. Therefore, if the data of the selected cell is data "0", after the data of the selected cell is read, it may be necessary to rewrite data "0" in order to maintain the data of the selected cell.

Figure 19 is an explanatory diagram of a fourth operation example of the memory operation of the storage device of the first modified example of the third embodiment. Figure 19 shows the positive write voltage Vwp, half the positive write voltage Vwp (Vwp/2), the negative write voltage Vwn, half the negative write voltage Vwn (Vwn/2), and the positive read voltage Vrp when performing memory operation.

In the fourth operation example, the high resistance state and low resistance state on the positive voltage side are used for memory operation. In the fourth operation example, the positive side read voltage Vrp is used as the read voltage.

When writing data "1" to the selected cell, a negative write voltage Vwn is applied to the upper electrode 20. The negative write voltage Vwn is a voltage lower than the second negative voltage threshold voltage Vtnn. By applying the negative write voltage Vwn to the upper electrode 20, a high resistance state is realized on the positive voltage side, and data "1" is written to the selected cell.

When writing data "0" to the selected cell, a positive write voltage Vwp is applied to the upper electrode 20. The positive write voltage Vwp is a voltage higher than the second positive voltage threshold voltage Vtnp. By applying the positive write voltage Vwp to the upper electrode 20, a low resistance state is realized on the positive voltage side, and data "0" is written to the selected cell.

In the fourth operation example, when writing data "1" to a selected cell, if the data stored in the selected cell is data "0", even if the negative write voltage Vwn is higher than the second negative voltage side threshold voltage Vtnn, current flows as long as it is lower than the first negative voltage side threshold voltage Vtpn. Therefore, there is a possibility that data "1" can be written. Therefore, for example, by setting the negative write voltage Vwn to a voltage between the second negative voltage side threshold voltage Vtnn and the first negative voltage side threshold voltage Vtpn, it is possible to achieve low power consumption or high reliability of the memory device.

When a positive write voltage Vwp is applied to the selected cell, a voltage Vwp/2 is applied to the semi-selected cell. When a negative write voltage Vwn is applied to the selected cell, a voltage Vwn/2 is applied to the semi-selected cell. The voltage Vwp/2 is lower than the first positive voltage threshold voltage Vtpp. The voltage Vwn/2 is higher than the first negative voltage threshold voltage Vtpn.

Therefore, even when the half-selected cell is in a low resistance state, the half-selection leakage current flowing through the half-selected cell can be suppressed. Therefore, the memory element also functions as a switching element.

When reading data from a selected cell, a positive read voltage Vrp is applied to the selected cell. The data in the selected cell can be determined by detecting the change in current or potential caused by the difference in current flow between data "1" and data "0".

In the case of the fourth operation example, whether the data of the selected cell is data "1" or data "0", data destruction does not occur by applying the positive read voltage Vrp. In other words, in the case of the fourth operation example, whether the data of the selected cell is data "1" or data "0", non-destructive readout is possible.

(Second Modification)
The storage device according to the second modification of the third embodiment differs from the storage device according to the third embodiment in that the current-voltage characteristics of the memory elements are different.

Figure 20 is an explanatory diagram of the current-voltage characteristics of a memory element of the second modified example of the third embodiment. The horizontal axis is the voltage applied to the memory element, and the vertical axis is the current flowing through the memory element. In Figure 20, the horizontal axis shows the voltage applied to the upper electrode 20 with the potential of the lower electrode 10 as the reference. Figure 20 shows the current-voltage characteristics of the memory layer 60 of the second modified example of the third embodiment. Figure 20 shows the current-voltage characteristics of a memory cell MC of the second modified example of the third embodiment.

The memory element of the second modified example of the third embodiment exhibits different current-voltage characteristics when a predetermined positive voltage is applied to the upper electrode 20 and when a predetermined negative voltage is applied to the upper electrode 20. In FIG. 20, the current-voltage characteristics when a predetermined positive voltage is applied to the upper electrode 20 are shown by a solid line, and the current-voltage characteristics when a predetermined negative voltage is applied to the upper electrode 20 are shown by a dotted line.

When a predetermined positive voltage is applied to the upper electrode 20, the current rises sharply on the positive voltage side at the first positive voltage side threshold voltage Vtpp. Also, when a predetermined positive voltage is applied to the upper electrode 20, the current rises sharply on the negative voltage side at the first negative voltage side threshold voltage Vtpn.

On the other hand, when a predetermined negative voltage is applied to the upper electrode 20, the current rises sharply on the positive voltage side at the second positive voltage side threshold voltage Vtnp. Also, when a predetermined negative voltage is applied to the upper electrode 20, the current rises sharply on the negative voltage side at the second negative voltage side threshold voltage Vtnn.

The first positive voltage side threshold voltage Vtpp is lower than the second positive voltage side threshold voltage Vtnp. Also, the first negative voltage side threshold voltage Vtpn is lower than the second negative voltage side threshold voltage Vtnn.

The memory element of the second modified example of the third embodiment can take a high resistance state and a low resistance state on both the positive voltage side and the negative voltage side. When a predetermined positive voltage is applied to the upper electrode 20, it becomes a low resistance state on the positive voltage side and a high resistance state on the negative voltage side. On the other hand, when a predetermined negative voltage is applied to the upper electrode 20, it becomes a high resistance state on the positive voltage side and a low resistance state on the negative voltage side. Hereinafter, the high resistance state is defined as data "1" and the low resistance state as data "0". The memory cell MC is capable of storing 1-bit data of "0" and "1".

Figure 21 is an explanatory diagram of a fifth operation example of the memory operation of the storage device of the second modified example of the third embodiment. Figure 21 shows the positive write voltage Vwp, half the positive write voltage Vwp (Vwp/2), the negative write voltage Vwn, half the negative write voltage Vwn (Vwn/2), and the negative read voltage Vrn when performing memory operation.

In the fifth operation example, the high resistance state and low resistance state on the negative voltage side are used for memory operation. In the fifth operation example, the negative read voltage Vrn is used as the read voltage.

When writing data "1" to the selected cell, a positive write voltage Vwp is applied to the upper electrode 20. The positive write voltage Vwp is a voltage higher than the second positive voltage threshold voltage Vtnp. By applying the positive write voltage Vwp to the upper electrode 20, a high resistance state is realized on the negative voltage side, and data "1" is written to the selected cell.

When writing data "0" to the selected cell, a negative write voltage Vwn is applied to the upper electrode 20. The negative write voltage Vwn is a voltage lower than the first negative voltage threshold voltage Vtpn. By applying the negative write voltage Vwn to the upper electrode 20, a low resistance state is realized on the negative voltage side, and data "0" is written to the selected cell.

When a positive write voltage Vwp is applied to the selected cell, a voltage Vwp/2 is applied to the semi-selected cell. When a negative write voltage Vwn is applied to the selected cell, a voltage Vwn/2 is applied to the semi-selected cell. The voltage Vwp/2 is lower than the first positive voltage threshold voltage Vtpp. The voltage Vwn/2 is higher than the second negative voltage threshold voltage Vtnn.

Therefore, even when the half-selected cell is in a low resistance state, the half-selection leakage current flowing through the half-selected cell can be suppressed. Therefore, the memory element also functions as a switching element.

When reading data from a selected cell, a negative read voltage Vrn is applied to the selected cell. The data in the selected cell can be determined by detecting the change in current or potential caused by the difference in current flow between data "1" and data "0".

In the case of the fifth operation example, whether the data of the selected cell is data "1" or data "0", data destruction does not occur by applying the negative read voltage Vrn. In other words, in the case of the fifth operation example, whether the data of the selected cell is data "1" or data "0", non-destructive readout is possible.

Figure 22 is an explanatory diagram of a sixth operation example of the memory operation of the storage device of the second modified example of the third embodiment. Figure 22 shows the positive write voltage Vwp, half the voltage of the positive write voltage Vwp (Vwp/2), the negative write voltage Vwn, half the voltage of the negative write voltage Vwn (Vwn/2), and the positive read voltage Vrp when performing memory operation.

In the sixth operation example, the high resistance state and low resistance state on the positive voltage side are used for memory operation. In the sixth operation example, the positive side read voltage Vrp is used as the read voltage.

When writing data "1" to the selected cell, a negative write voltage Vwn is applied to the upper electrode 20. The negative write voltage Vwn is a voltage lower than the first negative voltage threshold voltage Vtpn. By applying the negative write voltage Vwn to the upper electrode 20, a high resistance state is realized on the positive voltage side, and data "1" is written to the selected cell.

When writing data "0" to the selected cell, a positive write voltage Vwp is applied to the upper electrode 20. The positive write voltage Vwp is a voltage higher than the second positive voltage threshold voltage Vtnp. By applying the positive write voltage Vwp to the upper electrode 20, a low resistance state is realized on the positive voltage side, and data "0" is written to the selected cell.

When a positive write voltage Vwp is applied to the selected cell, a voltage Vwp/2 is applied to the semi-selected cell. When a negative write voltage Vwn is applied to the selected cell, a voltage Vwn/2 is applied to the semi-selected cell. The voltage Vwp/2 is lower than the first positive voltage threshold voltage Vtpp. The voltage Vwn/2 is higher than the second negative voltage threshold voltage Vtnn.

Therefore, even when the half-selected cell is in a low resistance state, the half-selection leakage current flowing through the half-selected cell can be suppressed. Therefore, the memory element also functions as a switching element.

When reading data from a selected cell, a positive read voltage Vrp is applied to the selected cell. The data in the selected cell can be determined by detecting the change in current or potential caused by the difference in current flow between data "1" and data "0".

In the case of the sixth operation example, whether the data of the selected cell is data "1" or data "0", the data is not destroyed by applying the positive read voltage Vrp. In other words, in the case of the sixth operation example, whether the data of the selected cell is data "1" or data "0", non-destructive readout is possible.

(Third Modification)
The storage device according to the third modification of the third embodiment differs from the storage device according to the third embodiment in that the current-voltage characteristics of the memory elements are different.

Figure 23 is an explanatory diagram of the current-voltage characteristics of a memory element of the third modified example of the third embodiment. The horizontal axis is the voltage applied to the memory element, and the vertical axis is the current flowing through the memory element. In Figure 23, the horizontal axis shows the voltage applied to the upper electrode 20 with the potential of the lower electrode 10 as the reference. Figure 23 shows the current-voltage characteristics of the memory layer 60 of the third modified example of the third embodiment. Figure 23 shows the current-voltage characteristics of a memory cell MC of the third modified example of the third embodiment.

The memory element of the third modified example of the third embodiment exhibits different current-voltage characteristics when a predetermined positive voltage is applied to the upper electrode 20 and when a predetermined negative voltage is applied to the upper electrode 20. In FIG. 23, the current-voltage characteristics when a predetermined positive voltage is applied to the upper electrode 20 are shown by a solid line, and the current-voltage characteristics when a predetermined negative voltage is applied to the upper electrode 20 are shown by a dotted line.

When a predetermined positive voltage is applied to the upper electrode 20, the current rises sharply on the positive voltage side at the first positive voltage side threshold voltage Vtpp. Also, when a predetermined positive voltage is applied to the upper electrode 20, the current rises sharply on the negative voltage side at the first negative voltage side threshold voltage Vtpn.

On the other hand, when a predetermined negative voltage is applied to the upper electrode 20, the current rises sharply on the positive voltage side at the second positive voltage side threshold voltage Vtnp. Also, when a predetermined negative voltage is applied to the upper electrode 20, the current rises sharply on the negative voltage side at the second negative voltage side threshold voltage Vtnn.

The first positive voltage side threshold voltage Vtpp is higher than the second positive voltage side threshold voltage Vtnp. Also, the first negative voltage side threshold voltage Vtpn is higher than the second negative voltage side threshold voltage Vtnn.

The memory element of the third modified example of the third embodiment can take a high resistance state and a low resistance state on both the positive voltage side and the negative voltage side. When a predetermined positive voltage is applied to the upper electrode 20, it becomes a high resistance state on the positive voltage side and a low resistance state on the negative voltage side. On the other hand, when a predetermined negative voltage is applied to the upper electrode 20, it becomes a low resistance state on the positive voltage side and a high resistance state on the negative voltage side. Hereinafter, the high resistance state is defined as data "1" and the low resistance state as data "0". The memory cell MC is capable of storing 1-bit data of "0" and "1".

Figure 24 is an explanatory diagram of a seventh operation example of the memory operation of the storage device of the third modified example of the third embodiment. Figure 24 shows the positive write voltage Vwp, half the positive write voltage Vwp (Vwp/2), the negative write voltage Vwn, half the negative write voltage Vwn (Vwn/2), and the negative read voltage Vrn when performing memory operation.

In the seventh operation example, the high resistance state and low resistance state on the negative voltage side are used for memory operation. In the seventh operation example, the negative read voltage Vrn is used as the read voltage.

When writing data "1" to the selected cell, a negative write voltage Vwn is applied to the upper electrode 20. The negative write voltage Vwn is a voltage lower than the second negative voltage threshold voltage Vtnn. By applying the negative write voltage Vwn to the upper electrode 20, a high resistance state is realized on the negative voltage side, and data "1" is written to the selected cell.

When writing data "0" to the selected cell, a positive write voltage Vwp is applied to the upper electrode 20. The positive write voltage Vwp is a voltage higher than the first positive voltage threshold voltage Vtpp. By applying the positive write voltage Vwp to the upper electrode 20, a low resistance state is realized on the negative voltage side, and data "0" is written to the selected cell.

In the seventh operation example, when writing data "1" to a selected cell, if the data stored in the selected cell is data "0", even if the negative write voltage Vwn is higher than the second negative voltage side threshold voltage Vtnn, a current flows as long as it is lower than the first negative voltage side threshold voltage Vtpn. Therefore, there is a possibility that data "1" can be written. Therefore, for example, by setting the negative write voltage Vwn to a voltage between the second negative voltage side threshold voltage Vtnn and the first negative voltage side threshold voltage Vtpn, it is possible to realize low power consumption or high reliability of the memory device.

In addition, in the seventh operation example, when writing data "0" to a selected cell, if the data stored in the selected cell is data "1", even if the positive write voltage Vwp is lower than the first positive voltage threshold voltage Vtpp, current flows as long as it is higher than the second positive voltage threshold voltage Vtnp. Therefore, there is a possibility that data "0" can be written. Therefore, for example, by setting the positive write voltage Vwp to a voltage between the second positive voltage threshold voltage Vtnp and the first positive voltage threshold voltage Vtpp, it is possible to realize low power consumption or high reliability of the memory device.

When a positive write voltage Vwp is applied to the selected cell, a voltage Vwp/2 is applied to the semi-selected cell. When a negative write voltage Vwn is applied to the selected cell, a voltage Vwn/2 is applied to the semi-selected cell. The voltage Vwp/2 is lower than the second positive voltage threshold voltage Vtnp. The voltage Vwn/2 is higher than the first negative voltage threshold voltage Vtpn.

Therefore, even when the half-selected cell is in a low resistance state, the half-selection leakage current flowing through the half-selected cell can be suppressed. Therefore, the memory element also functions as a switching element.

When reading data from a selected cell, a negative read voltage Vrn is applied to the selected cell. The data in the selected cell can be determined by detecting the change in current or potential caused by the difference in current flow between data "1" and data "0".

In the seventh operation example, if the data of the selected cell is data "1", applying the negative read voltage Vrn does not destroy the data. In other words, in the seventh operation example, if the data of the selected cell is data "1", non-destructive reading is possible.

On the other hand, if the data of the selected cell is data "0", applying a negative read voltage Vrn lower than the first negative voltage threshold voltage Vtpn may cause a current to flow and the data of the selected cell to change to data "1". In other words, in the seventh operation example, if the data of the selected cell is data "0", a destructive read may occur. Therefore, if the data of the selected cell is data "0", after the data of the selected cell is read, it may be necessary to rewrite data "0" in order to maintain the data of the selected cell.

Figure 25 is an explanatory diagram of an eighth operation example of the memory operation of the storage device of the third modified example of the third embodiment. Figure 25 shows the positive write voltage Vwp, half the positive write voltage Vwp (Vwp/2), the negative write voltage Vwn, half the negative write voltage Vwn (Vwn/2), and the positive read voltage Vrp when performing memory operation.

In the eighth operation example, the high resistance state and low resistance state on the positive voltage side are used for memory operation. In the eighth operation example, the positive side read voltage Vrp is used as the read voltage.

When writing data "1" to the selected cell, a positive write voltage Vwp is applied to the upper electrode 20. The positive write voltage Vwp is a voltage higher than the first positive voltage threshold voltage Vtpp. By applying the positive write voltage Vwp to the upper electrode 20, a high resistance state is realized on the positive voltage side, and data "1" is written to the selected cell.

When writing data "0" to the selected cell, a negative write voltage Vwn is applied to the upper electrode 20. The negative write voltage Vwn is a voltage lower than the second negative voltage threshold voltage Vtnn. By applying the negative write voltage Vwn to the upper electrode 20, a low resistance state is realized on the positive voltage side, and data "0" is written to the selected cell.

In the eighth operation example, when writing data "1" to a selected cell, if the data stored in the selected cell is data "0", even if the positive write voltage Vwp is lower than the first positive voltage threshold voltage Vtpp, current flows as long as it is higher than the second positive voltage threshold voltage Vtnp. Therefore, there is a possibility that data "1" can be written. Therefore, for example, by setting the positive write voltage Vwp to a voltage between the second positive voltage threshold voltage Vtnp and the first positive voltage threshold voltage Vtpp, it is possible to achieve low power consumption or high reliability of the memory device.

In the eighth operation example, when writing data "0" to a selected cell, if the data stored in the selected cell is data "1", even if the negative write voltage Vwn is higher than the second negative voltage side threshold voltage Vtnn, a current flows as long as it is lower than the first negative voltage side threshold voltage Vtpn. Therefore, there is a possibility that data "0" can be written. Therefore, for example, by setting the negative write voltage Vwn to a voltage between the second negative voltage side threshold voltage Vtnn and the first negative voltage side threshold voltage Vtpn, it is possible to achieve low power consumption or high reliability of the memory device.

When a positive write voltage Vwp is applied to the selected cell, a voltage Vwp/2 is applied to the semi-selected cell. When a negative write voltage Vwn is applied to the selected cell, a voltage Vwn/2 is applied to the semi-selected cell. The voltage Vwp/2 is lower than the second positive voltage threshold voltage Vtnp. The voltage Vwn/2 is higher than the first negative voltage threshold voltage Vtpn.

Therefore, even when the half-selected cell is in a low resistance state, the half-selection leakage current flowing through the half-selected cell can be suppressed. Therefore, the memory element also functions as a switching element.

When reading data from a selected cell, a positive read voltage Vrp is applied to the selected cell. The data in the selected cell can be determined by detecting the change in current or potential caused by the difference in current flow between data "1" and data "0".

In the eighth operation example, if the data of the selected cell is data "1", applying the positive read voltage Vrp does not destroy the data. In other words, in the eighth operation example, if the data of the selected cell is data "1", non-destructive reading is possible.

On the other hand, if the data of the selected cell is data "0", applying a positive read voltage Vrp higher than the second positive voltage threshold voltage Vtnp may cause a current to flow and the data of the selected cell to change to data "1". In other words, in the case of the eighth operation example, if the data of the selected cell is data "0", a destructive read may occur. Therefore, if the data of the selected cell is data "0", after the data of the selected cell is read, it may be necessary to rewrite data "0" in order to maintain the data of the selected cell.

In the memory device of the third embodiment and its modified example, the memory element of the memory cell MC has a switching function and a function of storing information. The memory layer 60 is a single layer and realizes the function of the switching layer 40 and the function of the resistance change layer 50 of the first and second embodiments. The memory layer 60 of the third embodiment is a single layer and has a switching function and a memory function, so that the structure of the memory cell MC can be made extremely simple.

The memory layer 60 of the memory device of the third embodiment and its modified example has a configuration similar to that of the switching layer 40 of the first and second embodiments. Therefore, according to the third embodiment and its modified example, like the first and second embodiments, it is possible to realize a memory device having excellent switching characteristics such as low semi-selection leakage current and high reliability.

The multiple current-voltage characteristics of the memory element shown in the third embodiment and its modified example can be realized, for example, by employing a memory layer 60 having an appropriate chemical composition.

Fourth Embodiment
The memory device of the fourth embodiment includes a memory cell including a first conductive layer, a second conductive layer, a third conductive layer provided between the first conductive layer and the second conductive layer, a resistance change layer provided between the first conductive layer and the third conductive layer, and a switching layer provided between the third conductive layer and the second conductive layer, and the switching layer includes a compound of an oxide of aluminum (Al) or an oxynitride of aluminum (Al), a first element which is at least one element selected from the group consisting of zinc (Zn), tin (Sn), gallium (Ga), indium (In), and bismuth (Bi), and a second element which is at least one element selected from the group consisting of tellurium (Te), sulfur (S), and selenium (Se). The memory device of the fourth embodiment is different from the memory device of the first embodiment in that the switching layer includes an oxide of aluminum (Al) or an oxynitride of aluminum (Al). Hereinafter, some of the contents that overlap with the first embodiment may be omitted.

The memory device of the fourth embodiment further includes a plurality of first wirings and a plurality of second wirings that intersect with the plurality of first wirings. The memory cell is provided in a region where one of the plurality of first wirings intersects with one of the plurality of second wirings.

Figure 26 is a schematic cross-sectional view of a memory cell of a memory device of the fourth embodiment. Figure 26 shows a cross-section of one memory cell MC in a memory cell array similar to the memory cell array 100 of Figure 1.

As shown in FIG. 26, the memory cell MC includes a lower electrode 10, an upper electrode 20, an intermediate electrode 30, a switching layer 140, and a resistance change layer 50. The resistance change layer 50 includes a fixed layer 51, a tunnel layer 52, and a free layer 53.

The lower electrode 10 is an example of a first conductive layer. The upper electrode 20 is an example of a second conductive layer. The middle electrode 30 is an example of a third conductive layer.

The lower electrode 10, the switching layer 140, and the intermediate electrode 30 constitute the switching element of the memory cell MC. The intermediate electrode 30, the resistance change layer 50, and the upper electrode 20 constitute the resistance change element of the memory cell MC.

The bottom electrode 10 is connected to the word line 102. The bottom electrode 10 is, for example, a metal. The bottom electrode 10 includes, for example, at least one material selected from the group consisting of carbon, carbon nitride, tungsten, tungsten carbide, and tungsten nitride. The bottom electrode 10 may be part of the word line 102.

The upper electrode 20 is connected to the bit line 103. The upper electrode 20 is, for example, a metal. The upper electrode 20 includes, for example, at least one material selected from the group consisting of carbon, carbon nitride, tungsten, tungsten carbide, and tungsten nitride. The upper electrode 20 may be part of the bit line 103.

The intermediate electrode 30 is provided between the lower electrode 10 and the upper electrode 20. The intermediate electrode 30 is, for example, a metal. The intermediate electrode 30 includes, for example, at least one material selected from the group consisting of carbon, carbon nitride, tungsten, tungsten carbide, and tungsten nitride.

The switching layer 140 is provided between the lower electrode 10 and the intermediate electrode 30. The thickness of the switching layer 140 in the first direction from the lower electrode 10 to the upper electrode 20 is, for example, 5 nm or more and 50 nm or less. It is more preferable that the thickness of the switching layer 140 in the first direction from the lower electrode 10 to the upper electrode 20 is, for example, 5 nm or more and 20 nm or less.

The switching layer 140 has the function of suppressing an increase in the semi-selected leakage current flowing through the semi-selected cells. The switching layer 140 has a non-linear current-voltage characteristic in which the current rises sharply at a specific threshold voltage.

The switching layer 140 includes an oxide of aluminum (Al) or an oxynitride of aluminum (Al), and a chalcogenide. A chalcogenide is a compound in which the chalcogen element tellurium (Te), sulfur (S), or selenium (Se) is combined with another element.

The switching layer 140 includes an oxide of aluminum (Al) or an oxynitride of aluminum (Al). The switching layer 140 may include both an oxide of aluminum (Al) and an oxynitride of aluminum (Al). The switching layer 140 includes, for example, aluminum oxide or aluminum oxynitride.

Whether the switching layer 140 contains an oxide of aluminum (Al) or an oxynitride of aluminum (Al) can be determined, for example, by using X-ray photoelectron spectroscopy (XPS) or electron energy loss spectroscopy (EELS).

The atomic concentration of aluminum (Al) in the switching layer 140 is, for example, greater than 1% and less than 40%.

The switching layer 140 may contain an oxide of a third element or an oxynitride of a third element, which is at least one element selected from the group consisting of zirconium (Zr), hafnium (Hf), yttrium (Y), tantalum (Ta), lanthanum (La), cerium (Ce), magnesium (Mg), titanium (Ti), scandium (Sc), vanadium (V), and niobium (Nb).

In the switching layer 140, the ratio of the atomic concentration of oxygen (O) to the atomic concentration of aluminum (Al) is, for example, 0.5 or more and 5.0 or less. In the switching layer 140, the ratio of the atomic concentration of oxygen (O) to the atomic concentration of aluminum (Al) is more preferably 0.5 or more and 3.0 or less.

The switching layer 140 includes a chalcogenide, which is a compound of a first element, which is at least one element selected from the group consisting of zinc (Zn), tin (Sn), gallium (Ga), indium (In), and bismuth (Bi), and a second element, which is at least one element selected from the group consisting of tellurium (Te), sulfur (S), and selenium (Se). The switching layer 140 includes a chalcogenide of the first element. The switching layer 140 includes at least one chalcogenide selected from the group consisting of, for example, zinc telluride, tin telluride, gallium telluride, indium telluride, bismuth telluride, zinc sulfide, tin sulfide, gallium sulfide, indium sulfide, bismuth sulfide, zinc selenide, tin selenide, gallium selenide, indium selenide, and bismuth selenide. The second element is preferably tellurium (Te), and the switching layer 140 preferably contains at least one chalcogenide selected from the group consisting of zinc telluride, tin telluride, gallium telluride, indium telluride, and bismuth telluride. Tellurides have a smaller band gap than sulfides and selenides, and therefore have the advantage of being able to relatively reduce the write voltage and suppress characteristic fluctuations such as fluctuations in semi-selection leakage current and on-current when writing is repeated.

Whether the switching layer 140 contains a chalcogenide of the first element can be determined, for example, by using X-ray absorption fine structure analysis (XAFS), Raman spectroscopy (Raman), or electron energy loss spectroscopy (EELS).

The oxide, oxynitride, and chalcogenide are, for example, the main components of the switching layer 140. The fact that the oxide, oxynitride, and chalcogenide are the main components of the switching layer 140 means that, among the substances contained in the switching layer 140, there is no substance that has a higher mole fraction than the oxide, oxynitride, or chalcogenide.

The sum of the atomic concentrations of aluminum (Al), the first element, the second element, and oxygen (O) in the switching layer 140 is, for example, 90% or more.

The switching layer 140 includes, for example, a mixture of the oxide or the oxynitride and the chalcogenide. The oxide or the oxynitride and the chalcogenide are present in the switching layer 140, for example, in a mixed state.

In the switching layer 140, the ratio of the sum of the atomic concentrations of aluminum (Al) and oxygen (O) to the sum of the atomic concentrations of aluminum (Al), the first element, the second element, and oxygen (O) is, for example, 3% or more and 97% or less. For example, when the first element is zinc (Zn) and the second element is tellurium (Te), the ratio of the sum of the atomic concentrations of aluminum (Al) and oxygen (O) to the sum of the atomic concentrations of aluminum (Al), zinc (Zn), tellurium (Te), and oxygen (O) in the switching layer 140 ((Al+O)/(Al+Zn+Te+O)) is, for example, 3% or more and 97% or less.

In the switching layer 140, the ratio of the sum of the atomic concentrations of aluminum (Al) and oxygen (O) to the sum of the atomic concentrations of aluminum (Al), the first element, the second element, and oxygen (O) is, for example, 5% or more and less than 80%. In addition, the ratio of the absolute value of the difference between the atomic concentration of the second element and the atomic concentration of the first element to the sum of the atomic concentrations of aluminum (Al), the first element, the second element, and oxygen (O) is, for example, 20% or less.

The ratio (Al+O)/(Al+Zn+Te+O) of the sum of the atomic concentrations of aluminum (Al) and oxygen (O) to the sum of the atomic concentrations of aluminum (Al), zinc (Zn), tellurium (Te), and oxygen (O) is, for example, 5% or more and less than 80%. And, for example, the ratio (|Te-Zn|)/(Al+Zn+Te+O) of the absolute value of the difference between the atomic concentration of tellurium (Te) and the atomic concentration of zinc (Zn) to the sum of the atomic concentrations of aluminum (Al), zinc (Zn), tellurium (Te), and oxygen (O) is, for example, 20% or less.

The atomic concentration of the second element in the switching layer 140 is, for example, higher than the atomic concentration of the first element. For example, if the first element is zinc (Zn) and the second element is tellurium (Te), the atomic concentration of tellurium (Te) in the switching layer 140 is, for example, higher than the atomic concentration of zinc (Zn).

In the switching layer 140, for example, a chalcogenide formed by combining a first element with a second element, and an excess of the second element that does not form a chalcogenide are present. For example, if the first element is zinc (Zn) and the second element is tellurium (Te), zinc telluride and excess tellurium (Te) coexist in the switching layer 140.

For example, at least a portion of the aluminum (Al) oxide or aluminum (Al) oxynitride contained in the switching layer 140 is crystalline. Whether or not at least a portion of the aluminum (Al) oxide or aluminum (Al) oxynitride contained in the switching layer 140 is crystalline can be determined, for example, by using an electron beam diffraction method. Note that a portion of the chalcogenide contained in the switching layer 140 may be crystalline.

The switching layer 140 includes a fourth element, which is at least one element selected from the group consisting of carbon (C), boron (B), nitrogen (N), germanium (Ge), and silicon (Si). The atomic concentration of the fourth element included in the switching layer 140 is, for example, 5% or more and 20% or less.

The switching layer 140 includes a fifth element, which is at least one element selected from the group consisting of chromium (Cr), niobium (Nb), and vanadium (V). The atomic concentration of the fifth element included in the switching layer 140 is, for example, 1% or more and 10% or less.

The switching layer 140 can be formed, for example, by a sputtering method. The switching layer 140 including an oxide of aluminum (Al) or an oxynitride of aluminum (Al) and a chalcogenide of the first element can be formed, for example, by a co-sputtering method using a target made of an oxide of aluminum (Al) or an oxynitride of aluminum (Al) and a target made of a chalcogenide of the first element. The switching layer 140 can also be formed, for example, by a sputtering method using a target made of a mixture of an oxide of aluminum (Al) or an oxynitride of aluminum (Al) and a chalcogenide of the first element.

The resistance change layer 50 is provided between the intermediate electrode 30 and the upper electrode 20. The resistance change layer 50 has a fixed layer 51, a tunnel layer 52, and a free layer 53. The resistance change layer 50 includes a magnetic tunnel junction composed of the fixed layer 51, the tunnel layer 52, and the free layer 53.

The resistance change layer 50 has the function of storing data by changing the resistance. For example, the resistance change layer 50 has a characteristic that the electrical resistance changes when a predetermined voltage is applied.

Next, the operation and effects of the storage device of the fourth embodiment will be described.

The switching layer 140 of the switching element of the fourth embodiment includes an oxide of aluminum (Al) or an oxynitride of aluminum (Al) and a chalcogenide of the first element. Since the switching layer 140 includes an oxide of aluminum (Al) or an oxynitride of aluminum (Al) and a chalcogenide of the first element, a low semi-selective leakage current and suppression of characteristic fluctuations can be achieved, similar to the switching element of the first embodiment. Note that the first element, the second element, and the third element in the switching element of the fourth embodiment correspond to the second element, the third element, and the first element in the switching element of the first embodiment, respectively.

The switching element of the fourth embodiment has a switching layer 140 containing an oxide of aluminum (Al) or an oxynitride of aluminum (Al), and therefore, compared to the switching element of the first embodiment, the rate of reduction in the semi-selective leakage current is greater when the area of the switching element is reduced. Therefore, the switching element of the fourth embodiment can further reduce the semi-selective leakage current compared to the switching element of the first embodiment.

The atomic concentration of aluminum (Al) in the switching layer 140 is preferably greater than 1% and less than 40%. By satisfying the above range, the characteristics of the switching element are further improved.

In the switching layer 140, the ratio of the atomic concentration of oxygen (O) to the atomic concentration of aluminum (Al) is preferably 0.5 to 5.0, more preferably 0.5 to 3.0. By satisfying the above range, the characteristics of the switching element are further improved.

In the switching layer 140, the ratio of the sum of the atomic concentrations of aluminum (Al) and oxygen (O) to the sum of the atomic concentrations of aluminum (Al), the first element, the second element, and oxygen (O) is, for example, preferably 3% or more and 97% or less, more preferably 5% or more and less than 80%, even more preferably 10% or more and less than 60%, and most preferably 20% or more and less than 50%. By satisfying the above range, the characteristics of the switching element are further improved.

In addition, the ratio of the sum of the atomic concentrations of aluminum (Al) and oxygen (O) to the sum of the atomic concentrations of aluminum (Al), the first element, the second element, and oxygen (O) in the switching layer 140 is preferably, for example, 5% or more and less than 80%. In addition, the ratio of the absolute value of the difference between the atomic concentration of the second element and the atomic concentration of the first element to the sum of the atomic concentrations of aluminum (Al), the first element, the second element, and oxygen (O) is preferably 20% or less, more preferably 10% or less, and even more preferably 5% or less. By satisfying the above range, the characteristics of the switching element are further improved.

In the switching layer 140, the atomic concentration of tellurium (Te) is higher than the atomic concentration of zinc (Zn), and the ratio of the sum of the atomic concentrations of aluminum (Al) and oxygen (O) to the sum of the atomic concentrations of aluminum (Al), zinc (Zn), tellurium (Te), and oxygen (O) is 5% or more and less than 80%, and it is preferable that the ratio of the difference between the atomic concentration of tellurium (Te) and the atomic concentration of zinc (Zn) to the sum of the atomic concentrations of aluminum (Al), zinc (Zn), tellurium (Te), and oxygen (O) is 5% or more and 20% or less.

It is preferable that the atomic concentration of the second element in the switching layer 140 is higher than the atomic concentration of the first element. When the atomic concentration of the second element is higher than the atomic concentration of the first element, the characteristics of the switching element are further improved.

From the viewpoint of further improving the characteristics of the switching element, it is preferable that the switching layer 140 contains a fourth element which is at least one element selected from the group consisting of carbon (C), boron (B), nitrogen (N), germanium (Ge), and silicon (Si). From the viewpoint of further improving the characteristics of the switching element, it is preferable that the atomic concentration of the fourth element contained in the switching layer 140 is 5% or more and 20% or less.

From the viewpoint of further improving the characteristics of the switching element, it is preferable that the switching layer 140 contains a fifth element which is at least one element selected from the group consisting of chromium (Cr), niobium (Nb), and vanadium (V). From the viewpoint of further improving the characteristics of the switching element, it is preferable that the atomic concentration of the fifth element contained in the switching layer 140 is 1% or more and 10% or less. It is believed that the aggregation of the chalcogenide of the first element is suppressed by the switching layer 140 containing the fifth element.

In particular, when the switching layer 140 contains an oxynitride of aluminum (Al), the switching layer 140 further improves the characteristics of the switching element by containing a fifth element, which is at least one element selected from the group consisting of chromium (Cr), niobium (Nb), and vanadium (V).

From the viewpoint of further improving the characteristics of the switching element, it is preferable that at least a portion of the aluminum (Al) oxide or aluminum (Al) oxynitride contained in the switching layer 140 is crystalline. By making at least a portion of the aluminum (Al) oxide or aluminum (Al) oxynitride crystalline, it is believed that the diffusion of aluminum (Al) is suppressed, and an increase in leakage current caused by separated aluminum (Al) can be suppressed.

(First Modification)
The memory device of the first variant of the fourth embodiment differs from the memory device of the fourth embodiment in that the first conductive layer includes a first portion and a second portion, and the first portion includes at least one element selected from hafnium (Hf), aluminum (Al), magnesium (Mg), zirconium (Zr), and titanium (Ti).

Figure 27 is a schematic cross-sectional view of a memory cell of a memory device according to a first modified example of the fourth embodiment. Figure 27 corresponds to Figure 26 of the fourth embodiment.

The lower electrode 10 includes a first portion 11 and a second portion 12. The second portion 12 is provided between the first portion 11 and the switching layer 140.

The first portion 11 includes at least one element selected from hafnium (Hf), aluminum (Al), magnesium (Mg), zirconium (Zr), and titanium (Ti). The first portion 11 includes, for example, a boride of the above element. The first portion 11 includes, for example, at least one substance selected from the group consisting of hafnium, hafnium boride, aluminum magnesium boride, zirconium, zirconium boride, and titanium boride.

The second portion 12 includes, for example, at least one material selected from the group consisting of carbon, carbon nitride, tungsten, tungsten carbide, and tungsten nitride.

In the memory device of the first modification of the fourth embodiment, the first portion 11 of the lower electrode 10 contains at least one element selected from hafnium (Hf), aluminum (Al), magnesium (Mg), zirconium (Zr), and titanium (Ti), thereby suppressing deterioration of the characteristics of the resistance change element. In addition, the first portion 11 is not in contact with the switching layer 140, thereby suppressing detachment of oxygen (O) from the switching layer 140 and suppressing deterioration of the characteristics of the switching element.

As described above, according to the first modification of the fourth embodiment, a switching element having excellent characteristics such as low semi-selection leakage current and high reliability can be realized, similar to the fourth embodiment.

(Second Modification)
A memory device of the second variant of the fourth embodiment differs from the memory device of the fourth embodiment in that the first conductive layer includes a first portion and a second portion, the first portion including at least one element selected from among hafnium (Hf), aluminum (Al), magnesium (Mg), zirconium (Zr), and titanium (Ti), the second conductive layer includes at least one element selected from among hafnium (Hf), aluminum (Al), magnesium (Mg), zirconium (Zr), and titanium (Ti), and the third conductive layer includes a third portion and a fourth portion, the fourth portion including at least one element selected from among hafnium (Hf), aluminum (Al), magnesium (Mg), zirconium (Zr), and titanium (Ti).

Figure 28 is a schematic cross-sectional view of a memory cell of a memory device according to a second modification of the fourth embodiment. Figure 28 corresponds to Figure 26 of the fourth embodiment.

The lower electrode 10 includes a first portion 11 and a second portion 12. The second portion 12 is provided between the first portion 11 and the switching layer 140.

The first portion 11 includes at least one element selected from hafnium (Hf), aluminum (Al), magnesium (Mg), zirconium (Zr), and titanium (Ti). The first portion 11 includes, for example, a boride of the above element. The first portion 11 includes, for example, at least one substance selected from the group consisting of hafnium, hafnium boride, aluminum magnesium boride, zirconium, zirconium boride, and titanium boride.

The second portion 12 includes, for example, at least one material selected from the group consisting of carbon, carbon nitride, tungsten, tungsten carbide, and tungsten nitride.

The upper electrode 20 includes at least one element selected from hafnium (Hf), aluminum (Al), magnesium (Mg), zirconium (Zr), and titanium (Ti). The upper electrode 20 includes, for example, a boride of the above element. The upper electrode 20 includes, for example, at least one material selected from the group consisting of hafnium, hafnium boride, aluminum magnesium boride, zirconium, zirconium boride, and titanium boride.

The intermediate electrode 30 includes a third portion 31 and a fourth portion 32. The third portion 31 is provided between the fourth portion 32 and the switching layer 140.

The third portion 31 includes, for example, at least one material selected from the group consisting of carbon, carbon nitride, tungsten, tungsten carbide, and tungsten nitride.

The fourth portion 32 includes at least one element selected from hafnium (Hf), aluminum (Al), magnesium (Mg), zirconium (Zr), and titanium (Ti). The fourth portion 32 includes, for example, a boride of the above element. The fourth portion 32 includes, for example, at least one substance selected from the group consisting of hafnium, hafnium boride, aluminum magnesium boride, zirconium, zirconium boride, and titanium boride.

In the memory device of the second modification of the fourth embodiment, the first portion 11 of the lower electrode 10, the upper electrode 20, and the fourth portion 32 of the intermediate electrode 30 contain at least one element selected from hafnium (Hf), aluminum (Al), magnesium (Mg), zirconium (Zr), and titanium (Ti), thereby suppressing deterioration of the characteristics of the resistance change element. In addition, the first portion 11 of the lower electrode 10, the upper electrode 20, and the fourth portion 32 of the intermediate electrode 30 are not in contact with the switching layer 140, thereby suppressing detachment of oxygen (O) from the switching layer 140 and suppressing deterioration of the characteristics of the switching element.

As described above, according to the second modification of the fourth embodiment, a switching element having excellent characteristics such as low semi-selection leakage current and high reliability can be realized, similar to the fourth embodiment.

(Third Modification)
A memory device of the third modification of the fourth embodiment differs from the memory device of the fourth embodiment in that the first conductive layer includes a first portion, a second portion, and a fifth portion, the first portion including at least one element selected from among hafnium (Hf), aluminum (Al), magnesium (Mg), zirconium (Zr), and titanium (Ti), the second conductive layer includes at least one element selected from among hafnium (Hf), aluminum (Al), magnesium (Mg), zirconium (Zr), and titanium (Ti), and the third conductive layer includes a third portion and a fourth portion, the fourth portion including at least one element selected from among hafnium (Hf), aluminum (Al), magnesium (Mg), zirconium (Zr), and titanium (Ti).

Figure 29 is a schematic cross-sectional view of a memory cell of a memory device according to a third modification of the fourth embodiment. Figure 29 corresponds to Figure 26 of the fourth embodiment.

The lower electrode 10 includes a first portion 11, a second portion 12, and a fifth portion 13. The second portion 12 is provided between the first portion 11 and the switching layer 140. The first portion 11 is provided between the fifth portion 13 and the second portion 12.

The first portion 11 includes at least one element selected from hafnium (Hf), aluminum (Al), magnesium (Mg), zirconium (Zr), and titanium (Ti). The first portion 11 includes, for example, a boride of the above element. The first portion 11 includes, for example, at least one substance selected from the group consisting of hafnium, hafnium boride, aluminum magnesium boride, zirconium, zirconium boride, and titanium boride.

The second portion 12 and the fifth portion 13 contain, for example, at least one material selected from the group consisting of carbon, carbon nitride, tungsten, tungsten carbide, and tungsten nitride.

The upper electrode 20 includes at least one element selected from hafnium (Hf), aluminum (Al), magnesium (Mg), zirconium (Zr), and titanium (Ti). The upper electrode 20 includes, for example, a boride of the above element. The upper electrode 20 includes, for example, at least one material selected from the group consisting of hafnium, hafnium boride, aluminum magnesium boride, zirconium, zirconium boride, and titanium boride.

The intermediate electrode 30 includes a third portion 31 and a fourth portion 32. The third portion 31 is provided between the fourth portion 32 and the switching layer 140.

The third portion 31 includes, for example, at least one material selected from the group consisting of carbon, carbon nitride, tungsten, tungsten carbide, and tungsten nitride.

The fourth portion 32 includes at least one element selected from hafnium (Hf), aluminum (Al), magnesium (Mg), zirconium (Zr), and titanium (Ti). The fourth portion 32 includes, for example, a boride of the above element. The fourth portion 32 includes, for example, at least one substance selected from the group consisting of hafnium, hafnium boride, aluminum magnesium boride, zirconium, zirconium boride, and titanium boride.

In the memory device of the third modified example of the fourth embodiment, the first portion 11 of the lower electrode 10, the upper electrode 20, and the fourth portion 32 of the intermediate electrode 30 contain at least one element selected from hafnium (Hf), aluminum (Al), magnesium (Mg), zirconium (Zr), and titanium (Ti), thereby suppressing deterioration of the characteristics of the resistance change element. In addition, the first portion 11 of the lower electrode 10, the upper electrode 20, and the fourth portion 32 of the intermediate electrode 30 are not in contact with the switching layer 140, thereby suppressing detachment of oxygen (O) from the switching layer 140 and suppressing deterioration of the characteristics of the switching element.

As described above, according to the third modification of the fourth embodiment, a switching element having excellent characteristics such as low semi-selection leakage current and high reliability can be realized, similar to the fourth embodiment.

According to the fourth embodiment and the modification, a switching element having excellent characteristics such as a low semi-selection leakage current and high reliability can be realized. Therefore, according to the fourth embodiment and the modification, a memory device having a switching element with excellent characteristics can be realized.

Fifth Embodiment
The storage device of the fifth embodiment differs from the storage device of the fourth embodiment in that the storage device of the fifth embodiment is a resistive random access memory (ReRAM).

Figure 30 is a schematic cross-sectional view of a memory cell of a memory device of the fifth embodiment. Figure 30 shows a cross-section of one memory cell MC in a memory cell array similar to the memory cell array 100 of Figure 1.

As shown in FIG. 30, the memory cell MC includes a lower electrode 10, an upper electrode 20, an intermediate electrode 30, a switching layer 140, and a resistance change layer 50. The resistance change layer 50 includes a high resistance layer 50x and a low resistance layer 50y.

The lower electrode 10 is an example of a first conductive layer. The upper electrode 20 is an example of a second conductive layer. The middle electrode 30 is an example of a third conductive layer.

The lower electrode 10, the switching layer 140, and the intermediate electrode 30 constitute the switching element of the memory cell MC. The intermediate electrode 30, the resistance change layer 50, and the upper electrode 20 constitute the resistance change element of the memory cell MC.

The configuration of the switching layer 140 is the same as that of the memory device of the fourth embodiment.

The resistance change layer 50 includes a high resistance layer 50x and a low resistance layer 50y.

The high resistance layer 50x is, for example, a metal oxide. The high resistance layer 50x is, for example, aluminum oxide, hafnium oxide, zirconium oxide, tantalum oxide, or niobium oxide.

The low resistance layer 50y is, for example, a metal oxide. The low resistance layer 50y is, for example, titanium oxide, niobium oxide, tantalum oxide, or tungsten oxide.

The resistance change layer 50 has the function of storing data by changing the resistance. For example, the resistance change layer 50 has a characteristic that the electrical resistance changes when a predetermined voltage is applied.

As described above, according to the memory device of the fifth embodiment, a switching element having excellent characteristics such as a low semi-selection leakage current and high reliability can be realized, as in the fourth embodiment. Therefore, according to the fifth embodiment, a memory device having a switching element with excellent characteristics can be realized.

Sixth Embodiment
The memory device of the sixth embodiment includes a memory cell including a first conductive layer, a second conductive layer, and a memory layer provided between the first conductive layer and the second conductive layer, and the memory layer includes a compound of an oxide of aluminum (Al) or an oxynitride of aluminum (Al), a first element which is at least one element selected from the group consisting of zinc (Zn), tin (Sn), gallium (Ga), indium (In), and bismuth (Bi), and a second element which is at least one element selected from the group consisting of tellurium (Te), sulfur (S), and selenium (Se). The memory device of the sixth embodiment is different from the memory device of the third embodiment in that the memory layer includes an oxide of aluminum (Al) or an oxynitride of aluminum (Al). Hereinafter, some of the contents overlapping with the third embodiment may be omitted.

The memory device of the sixth embodiment further includes a plurality of first wirings and a plurality of second wirings that intersect with the plurality of first wirings. The memory cell is provided in a region where one of the plurality of first wirings intersects with one of the plurality of second wirings.

The memory device of the sixth embodiment differs from the memory devices of the fourth and fifth embodiments in that the memory cell does not include a third conductive layer and a resistance change layer, but includes a configuration similar to the switching layer of the fourth and fifth embodiments as a memory layer. Below, some of the description that overlaps with the fourth and fifth embodiments will be omitted.

Figure 31 is a schematic cross-sectional view of a memory cell of a memory device of the sixth embodiment. Figure 31 shows a cross-section of one memory cell MC in a memory cell array similar to the memory cell array 100 of Figure 1.

As shown in FIG. 31, the memory cell MC includes a lower electrode 10, an upper electrode 20, and a memory layer 160.

The lower electrode 10 is an example of a first conductive layer. The upper electrode 20 is an example of a second conductive layer.

The lower electrode 10, the memory layer 160, and the upper electrode 20 constitute the memory element of the memory cell MC. The memory element of the memory cell MC has a switching function and a function of storing information.

The memory layer 160 has a configuration similar to that of the switching layer 140 of the fourth and fifth embodiments. That is, the memory layer 160 includes a compound of an oxide of aluminum (Al) or an oxynitride of aluminum (Al), a first element which is at least one element selected from the group consisting of zinc (Zn), tin (Sn), gallium (Ga), indium (In), and bismuth (Bi), and a second element which is at least one element selected from the group consisting of tellurium (Te), sulfur (S), and selenium (Se).

The memory layer 160 has a nonlinear current-voltage characteristic in which the current rises sharply at a specific threshold voltage. The memory layer 160 also has a characteristic in which the threshold voltage changes with application of a specific voltage. The memory layer 160 has a characteristic in which the electrical resistance changes with application of a specific voltage. In the sixth embodiment, the high resistance state is a state in which the resistance of the memory layer 160 at the read voltage is relatively high. In the sixth embodiment, the low resistance state is a state in which the resistance of the memory layer 160 at the read voltage is relatively low.

The memory layer 160 has a function of suppressing an increase in the half-selected leakage current flowing through the half-selected cells. The memory layer 160 also has a function of storing data by resistance changes. The memory layer 160 is a single layer and combines the function of the switching layer 140 and the function of the resistance change layer 50 of the fourth and fifth embodiments.

In the sixth embodiment, the memory element of the memory cell MC has a switching function and a function of storing information. The memory layer 160 is a single layer and realizes the function of the switching layer 140 and the function of the resistance change layer 50 of the fourth and fifth embodiments. The memory layer 160 of the sixth embodiment is a single layer and has a switching function and a memory function, so that the structure of the memory cell MC can be made extremely simple.

The memory layer 160 of the sixth embodiment has a configuration similar to that of the switching layer 140 of the fourth and fifth embodiments. Therefore, according to the sixth embodiment, like the fourth and fifth embodiments, a memory device having excellent switching characteristics such as low semi-selection leakage current and high reliability can be realized.

Seventh Embodiment
A seventh embodiment of the memory device includes a memory cell including a first conductive layer, a second conductive layer, a third conductive layer provided between the first conductive layer and the second conductive layer, a resistance change layer provided between the first conductive layer and the third conductive layer, and a switching layer provided between the third conductive layer and the second conductive layer, and the switching layer includes an oxide of a first element, which is at least one element selected from the group consisting of silicon (Si), boron (B), and germanium (Ge), or an oxynitride of the first element, a second element, which is at least one element selected from the group consisting of zinc (Zn), tin (Sn), gallium (Ga), indium (In), and bismuth (Bi), and a compound of a third element, which is at least one element selected from the group consisting of tellurium (Te), sulfur (S), and selenium (Se). The storage device of the seventh embodiment differs from the storage device of the first embodiment in that the switching layer contains an oxide of a first element or an oxynitride of the first element, the first element being at least one element selected from the group consisting of silicon (Si), boron (B), and germanium (Ge). In the following, some of the contents that overlap with the first embodiment may be omitted.

The seventh embodiment of the memory device further includes a plurality of first wirings and a plurality of second wirings that intersect with the plurality of first wirings. The memory cell is provided in a region where one of the plurality of first wirings intersects with one of the plurality of second wirings.

Figure 32 is a schematic cross-sectional view of a memory cell of a memory device of the seventh embodiment. Figure 32 shows a cross-section of one memory cell MC in a memory cell array similar to the memory cell array 100 of Figure 1.

As shown in FIG. 32, the memory cell MC includes a lower electrode 10, an upper electrode 20, an intermediate electrode 30, a switching layer 240, and a resistance change layer 50. The resistance change layer 50 includes a fixed layer 51, a tunnel layer 52, and a free layer 53.

The lower electrode 10 is an example of a first conductive layer. The upper electrode 20 is an example of a second conductive layer. The middle electrode 30 is an example of a third conductive layer.

The lower electrode 10, the switching layer 240, and the intermediate electrode 30 constitute the switching element of the memory cell MC. The intermediate electrode 30, the resistance change layer 50, and the upper electrode 20 constitute the resistance change element of the memory cell MC.

The bottom electrode 10 is connected to the word line 102. The bottom electrode 10 is, for example, a metal. The bottom electrode 10 includes, for example, at least one material selected from the group consisting of carbon, carbon nitride, tungsten, tungsten carbide, and tungsten nitride. The bottom electrode 10 may be part of the word line 102.

The upper electrode 20 is connected to the bit line 103. The upper electrode 20 is, for example, a metal. The upper electrode 20 includes, for example, at least one material selected from the group consisting of carbon, carbon nitride, tungsten, tungsten carbide, and tungsten nitride. The upper electrode 20 may be part of the bit line 103.

The intermediate electrode 30 is provided between the lower electrode 10 and the upper electrode 20. The intermediate electrode 30 is, for example, a metal. The intermediate electrode 30 includes, for example, at least one material selected from the group consisting of carbon, carbon nitride, tungsten, tungsten carbide, and tungsten nitride.

The switching layer 240 is provided between the lower electrode 10 and the intermediate electrode 30. The thickness of the switching layer 240 in the first direction from the lower electrode 10 to the upper electrode 20 is, for example, 5 nm or more and 50 nm or less. It is more preferable that the thickness of the switching layer 240 in the first direction from the lower electrode 10 to the upper electrode 20 is, for example, 5 nm or more and 20 nm or less.

The switching layer 240 has the function of suppressing an increase in the semi-selected leakage current flowing through the semi-selected cells. The switching layer 240 has a non-linear current-voltage characteristic in which the current rises sharply at a specific threshold voltage.

The switching layer 240 includes an oxide or oxynitride and a chalcogenide. A chalcogenide is a compound in which the chalcogen element tellurium (Te), sulfur (S), or selenium (Se) is combined with another element.

The switching layer 240 includes an oxide of a first element, which is at least one element selected from the group consisting of silicon (Si), boron (B), and germanium (Ge), or an oxynitride of the first element. The switching layer 240 may include both an oxide of the first element and an oxynitride of the first element. The switching layer 240 includes at least one oxide selected from the group consisting of, for example, silicon oxide, boron oxide, and germanium oxide. The switching layer 240 includes at least one oxynitride selected from the group consisting of, for example, silicon oxynitride, boron oxynitride, and germanium oxynitride.

Whether the switching layer 240 contains an oxide of the first element or an oxynitride of the first element can be determined, for example, by using X-ray photoelectron spectroscopy (XPS) or electron energy loss spectroscopy (EELS).

In the switching layer 240, the ratio of the atomic concentration of oxygen (O) to the atomic concentration of the first element is, for example, 0.5 or more and 4.0 or less. In the switching layer 240, the ratio of the atomic concentration of oxygen (O) to the atomic concentration of the first element is more preferably 0.5 or more and 3.0 or less.

The switching layer 240 may contain an oxide of at least one element selected from the group consisting of zirconium (Zr), hafnium (Hf), yttrium (Y), tantalum (Ta), lanthanum (La), cerium (Ce), magnesium (Mg), titanium (Ti), scandium (Sc), vanadium (V), and niobium (Nb), or an oxynitride of at least one of the above elements.

The switching layer 240 includes a chalcogenide which is a compound of a second element which is at least one element selected from the group consisting of zinc (Zn), tin (Sn), gallium (Ga), indium (In), and bismuth (Bi) and a third element which is at least one element selected from the group consisting of tellurium (Te), sulfur (S), and selenium (Se). The switching layer 240 includes a chalcogenide of the second element. The switching layer 240 includes at least one chalcogenide selected from the group consisting of, for example, zinc telluride, tin telluride, gallium telluride, indium telluride, bismuth telluride, zinc sulfide, tin sulfide, gallium sulfide, indium sulfide, bismuth sulfide, zinc selenide, tin selenide, gallium selenide, indium selenide, and bismuth selenide. The third element is preferably tellurium (Te), and the switching layer 240 preferably contains at least one chalcogenide selected from the group consisting of zinc telluride, tin telluride, gallium telluride, indium telluride, and bismuth telluride. Tellurides have a smaller band gap than sulfides and selenides, and therefore have the advantage of being able to relatively reduce the write voltage and suppress characteristic fluctuations such as fluctuations in semi-selection leakage current and on-current when writing is repeated.

Whether the switching layer 240 contains a chalcogenide of the second element can be determined, for example, by using X-ray absorption fine structure analysis (XAFS), Raman spectroscopy (Raman), or electron energy loss spectroscopy (EELS).

The oxide, oxynitride, and chalcogenide are, for example, the main components of the switching layer 240. The fact that the oxide, oxynitride, and chalcogenide are the main components of the switching layer 240 means that, among the substances contained in the switching layer 240, there is no substance that has a higher mole fraction than the oxide or chalcogenide.

The sum of the atomic concentrations of the first element, the second element, the third element, and oxygen (O) in the switching layer 240 is, for example, 90% or more.

The switching layer 240 includes, for example, a mixture of the oxide or the oxynitride and the chalcogenide. The oxide or the oxynitride and the chalcogenide are present in the switching layer 240, for example, in a mixed state.

In the switching layer 240, the ratio of the sum of the atomic concentrations of the first element and oxygen (O) to the sum of the atomic concentrations of the first element, the second element, the third element, and oxygen (O) is, for example, 3% or more and 97% or less.

The atomic concentration of the third element in the switching layer 240 is, for example, higher than the atomic concentration of the second element. For example, if the second element is zinc (Zn) and the third element is tellurium (Te), the atomic concentration of tellurium (Te) in the switching layer 240 is, for example, higher than the atomic concentration of zinc (Zn).

In the switching layer 240, for example, there exists a chalcogenide formed by combining a second element with a third element, and an excess of the third element that does not form a chalcogenide. For example, when the second element is zinc (Zn) and the third element is tellurium (Te), zinc telluride and excess tellurium (Te) coexist in the switching layer 240.

For example, at least a portion of the oxide or oxynitride contained in the switching layer 240 is crystalline. Whether or not at least a portion of the oxide or oxynitride contained in the switching layer 240 is crystalline can be determined, for example, by using an electron beam diffraction method. Note that a portion of the chalcogenide contained in the switching layer 240 may be crystalline.

The switching layer 240 contains, for example, carbon (C). The atomic concentration of carbon (C) contained in the switching layer 240 is, for example, 5% or more and 20% or less.

The switching layer 240 includes a fifth element, which is at least one element selected from the group consisting of chromium (Cr), niobium (Nb), and vanadium (V). The atomic concentration of the fifth element included in the switching layer 240 is, for example, 1% or more and 10% or less.

The switching layer 240 can be formed, for example, by a sputtering method. The switching layer 240 including an oxide of a first element and a chalcogenide of a second element can be formed, for example, by a co-sputtering method using a target made of an oxide of the first element and a target made of a chalcogenide of the second element. The switching layer 240 can also be formed, for example, by a sputtering method using a target made of a mixture of an oxide of a first element and a chalcogenide of a second element.

The resistance change layer 50 is provided between the intermediate electrode 30 and the upper electrode 20. The resistance change layer 50 has a fixed layer 51, a tunnel layer 52, and a free layer 53. The resistance change layer 50 includes a magnetic tunnel junction composed of the fixed layer 51, the tunnel layer 52, and the free layer 53.

The resistance change layer 50 has the function of storing data by changing the resistance. For example, the resistance change layer 50 has a characteristic that the electrical resistance changes when a predetermined voltage is applied.

Next, the operation and effects of the seventh embodiment of the storage device will be described.

The switching layer 240 of the switching element of the seventh embodiment includes an oxide of a first element or an oxynitride of the first element, which is at least one element selected from the group consisting of silicon (Si), boron (B), and germanium (Ge), and a chalcogenide of a second element. Since the switching layer 240 includes an oxide of the first element or an oxynitride of the first element and a chalcogenide of the second element, a low semi-selective leakage current and suppression of characteristic fluctuations can be achieved, similar to the switching element of the first embodiment.

The switching element of the seventh embodiment is easy to maintain amorphous because the switching layer 240 contains an oxide of a first element or an oxynitride of a first element, which is at least one element selected from the group consisting of silicon (Si), boron (B), and germanium (Ge), which has a particularly high glass-forming ability. Therefore, the switching element of the seventh embodiment can achieve a lower semi-selective leakage current and further suppression of characteristic fluctuations compared to the switching element of the first embodiment.

In the switching layer 240, the ratio of the atomic concentration of oxygen (O) to the atomic concentration of the first element is preferably 0.5 to 4.0, more preferably 0.5 to 3.0. By satisfying the above range, the characteristics of the switching element are further improved.

In the switching layer 240, the ratio of the sum of the atomic concentrations of the first element and oxygen (O) to the sum of the atomic concentrations of the first element, the second element, the third element, and oxygen (O) is, for example, preferably 3% or more and 97% or less, more preferably 5% or more and less than 80%, even more preferably 10% or more and less than 60%, and most preferably 20% or more and less than 50%. By satisfying the above range, the characteristics of the switching element are further improved.

In addition, in the switching layer 240, the ratio of the sum of the atomic concentrations of the first element and oxygen (O) to the sum of the atomic concentrations of the first element, the second element, the third element, and oxygen (O) is preferably, for example, 5% or more and less than 80%. In addition, the ratio of the absolute value of the difference between the atomic concentration of the third element and the atomic concentration of the second element to the sum of the atomic concentrations of the first element, the second element, the third element, and oxygen (O) is preferably 20% or less, more preferably 10% or less, and even more preferably 5% or less. By satisfying the above range, the characteristics of the switching element are further improved.

In the switching layer 240, the atomic concentration of tellurium (Te) is higher than the atomic concentration of zinc (Zn), and the ratio of the sum of the atomic concentrations of the first element and oxygen (O) to the sum of the atomic concentrations of the first element, zinc (Zn), tellurium (Te), and oxygen (O) is 5% or more and less than 80%, and it is preferable that the ratio of the difference between the atomic concentration of tellurium (Te) and the atomic concentration of zinc (Zn) to the sum of the atomic concentrations of the first element, zinc (Zn), tellurium (Te), and oxygen (O) is 5% or more and 20% or less.

The atomic concentration of the third element in the switching layer 240 is preferably higher than the atomic concentration of the second element. When the atomic concentration of the third element is higher than the atomic concentration of the second element, the characteristics of the switching element are further improved.

From the viewpoint of further improving the characteristics of the switching element, it is preferable that the switching layer 240 contains carbon (C). From the viewpoint of further improving the characteristics of the switching element, it is preferable that the atomic concentration of carbon (C) contained in the switching layer 240 is 5% or more and 20% or less.

From the viewpoint of further improving the characteristics of the switching element, it is preferable that the switching layer 240 contains a fifth element which is at least one element selected from the group consisting of chromium (Cr), niobium (Nb), and vanadium (V). From the viewpoint of further improving the characteristics of the switching element, it is preferable that the atomic concentration of the fifth element contained in the switching layer 240 is 1% or more and 10% or less. It is believed that the aggregation of the chalcogenide of the second element is suppressed by the switching layer 240 containing the fifth element.

In particular, when the switching layer 240 contains an oxynitride of the first element, the switching layer 240 further improves the characteristics of the switching element by containing a fifth element, which is at least one element selected from the group consisting of chromium (Cr), niobium (Nb), and vanadium (V).

From the viewpoint of further improving the characteristics of the switching element, it is preferable that at least a portion of the oxide of the first element or the oxynitride of the first element contained in the switching layer 240 is crystalline. It is believed that by making at least a portion of the oxide of the first element or the oxynitride of the first element crystalline, the diffusion of the first element is suppressed, and an increase in leakage current caused by the separated first element can be suppressed.

According to the seventh embodiment, a switching element having excellent characteristics such as a low semi-selection leakage current and high reliability can be realized. Therefore, according to the seventh embodiment, a memory device having a switching element with excellent characteristics can be realized.

Eighth embodiment
The storage device of the eighth embodiment differs from the storage device of the seventh embodiment in that the storage device of the eighth embodiment is a resistive random access memory (ReRAM).

Figure 33 is a schematic cross-sectional view of a memory cell of a memory device of the eighth embodiment. Figure 33 shows a cross-section of one memory cell MC in a memory cell array similar to the memory cell array 100 of Figure 1.

As shown in FIG. 33, the memory cell MC includes a lower electrode 10, an upper electrode 20, an intermediate electrode 30, a switching layer 240, and a resistance change layer 50. The resistance change layer 50 includes a high resistance layer 50x and a low resistance layer 50y.

The lower electrode 10 is an example of a first conductive layer. The upper electrode 20 is an example of a second conductive layer. The middle electrode 30 is an example of a third conductive layer.

The lower electrode 10, the switching layer 240, and the intermediate electrode 30 constitute the switching element of the memory cell MC. The intermediate electrode 30, the resistance change layer 50, and the upper electrode 20 constitute the resistance change element of the memory cell MC.

The configuration of the switching layer 240 is the same as that of the seventh embodiment of the memory device.

The resistance change layer 50 includes a high resistance layer 50x and a low resistance layer 50y.

The high resistance layer 50x is, for example, a metal oxide. The high resistance layer 50x is, for example, aluminum oxide, hafnium oxide, zirconium oxide, tantalum oxide, or niobium oxide.

The low resistance layer 50y is, for example, a metal oxide. The low resistance layer 50y is, for example, titanium oxide, niobium oxide, tantalum oxide, or tungsten oxide.

The resistance change layer 50 has the function of storing data by changing the resistance. For example, the resistance change layer 50 has a characteristic that the electrical resistance changes when a predetermined voltage is applied.

As described above, according to the memory device of the eighth embodiment, a switching element having excellent characteristics such as a low semi-selection leakage current and high reliability can be realized, as in the seventh embodiment. Therefore, according to the eighth embodiment, a memory device having a switching element with excellent characteristics can be realized.

Ninth embodiment
The memory device of the ninth embodiment includes a memory cell including a first conductive layer, a second conductive layer, and a memory layer provided between the first conductive layer and the second conductive layer, and the memory layer includes a compound of an oxide of a first element, which is at least one element selected from the group consisting of silicon (Si), boron (B), and germanium (Ge), or an oxynitride of the first element, a second element, which is at least one element selected from the group consisting of zinc (Zn), tin (Sn), gallium (Ga), indium (In), and bismuth (Bi), and a third element, which is at least one element selected from the group consisting of tellurium (Te), sulfur (S), and selenium (Se). The memory device of the ninth embodiment is different from the memory device of the third embodiment in that the memory layer includes an oxide of a first element, which is at least one element selected from the group consisting of silicon (Si), boron (B), and germanium (Ge), or an oxynitride of the first element. Hereinafter, some of the contents that overlap with the third embodiment may be omitted.

The memory device of the ninth embodiment further includes a plurality of first wirings and a plurality of second wirings that intersect with the plurality of first wirings. The memory cell is provided in a region where one of the plurality of first wirings intersects with one of the plurality of second wirings.

The memory device of the ninth embodiment differs from the memory devices of the seventh and eighth embodiments in that the memory cell does not include a third conductive layer and a resistance change layer, but includes a configuration similar to the switching layer of the seventh and eighth embodiments as a memory layer. Below, some of the description that overlaps with the seventh and eighth embodiments will be omitted.

Figure 34 is a schematic cross-sectional view of a memory cell of a memory device of the ninth embodiment. Figure 34 shows a cross-section of one memory cell MC in a memory cell array similar to the memory cell array 100 of Figure 1.

As shown in FIG. 34, the memory cell MC includes a lower electrode 10, an upper electrode 20, and a memory layer 260.

The lower electrode 10 is an example of a first conductive layer. The upper electrode 20 is an example of a second conductive layer.

The lower electrode 10, the memory layer 260, and the upper electrode 20 constitute the memory element of the memory cell MC. The memory element of the memory cell MC has a switching function and a function of storing information.

The memory layer 260 has a configuration similar to that of the switching layer 240 of the seventh and eighth embodiments. That is, the memory layer 260 includes an oxide or an oxynitride of a first element, which is at least one element selected from the group consisting of silicon (Si), boron (B), and germanium (Ge), a second element, which is at least one element selected from the group consisting of zinc (Zn), tin (Sn), gallium (Ga), indium (In), and bismuth (Bi), and a compound of a third element, which is at least one element selected from the group consisting of tellurium (Te), sulfur (S), and selenium (Se).

The memory layer 260 has a nonlinear current-voltage characteristic in which the current rises steeply at a specific threshold voltage. The memory layer 260 also has a characteristic in which the threshold voltage changes with application of a specific voltage. The memory layer 260 has a characteristic in which the electrical resistance changes with application of a specific voltage. In the ninth embodiment, the high resistance state is a state in which the resistance of the memory layer 260 at the read voltage is relatively high. In the ninth embodiment, the low resistance state is a state in which the resistance of the memory layer 260 at the read voltage is relatively low.

The memory layer 260 has a function of suppressing an increase in the semi-selected leakage current flowing through the semi-selected cells. The memory layer 260 also has a function of storing data by resistance changes. The memory layer 260 is a single layer and combines the function of the switching layer 240 and the function of the resistance change layer 50 of the seventh and eighth embodiments.

In the ninth embodiment, the memory element of the memory cell MC has a switching function and a function of storing information. The memory layer 260 is a single layer and realizes the function of the switching layer 240 and the function of the resistance change layer 50 of the seventh and eighth embodiments. The memory layer 260 of the ninth embodiment is a single layer and has a switching function and a memory function, so that the structure of the memory cell MC can be made extremely simple.

The memory layer 260 of the ninth embodiment has a configuration similar to that of the switching layer 240 of the seventh and eighth embodiments. Therefore, according to the ninth embodiment, like the seventh and eighth embodiments, a memory device having excellent switching characteristics, such as low semi-selection leakage current and high reliability, can be realized.

In the first, fourth, and seventh embodiments, a magnetoresistive memory is used as an example of a two-terminal memory device, and in the second, fifth, and eighth embodiments, a resistance change memory is used as an example of a memory device, but the present invention can be applied to other two-terminal memory devices. For example, the present invention can be applied to a phase change memory (PCM) or a ferroelectric random access memory (FeRAM).

In the first, second, and third embodiments, the switching layer or memory layer includes an oxide of a first element that is at least one element selected from the group consisting of zirconium (Zr), yttrium (Y), tantalum (Ta), lanthanum (La), cerium (Ce), titanium (Ti), hafnium (Hf), and magnesium (Mg). However, the switching layer or memory layer may include an oxide of a first element that is at least one element selected from the group consisting of zirconium (Zr), yttrium (Y), tantalum (Ta), lanthanum (La), cerium (Ce), titanium (Ti), hafnium (Hf), magnesium (Mg), scandium (Sc), vanadium (V), and niobium (Nb).

Although several embodiments of the present invention have been described above, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the gist of the invention. For example, components of one embodiment may be replaced or modified with components of another embodiment. These embodiments and their modifications are included within the scope and gist of the invention, and are included in the scope of the invention and its equivalents as set forth in the claims.

10 Lower electrode (first conductive layer)
20 Upper electrode (second conductive layer)
30 Intermediate electrode (third conductive layer)
40 Switching layer 50 Resistance change layer 60 Memory layer 102 Word line (first wiring)
103 bit line (second wiring)
140 Switching layer 160 Memory layer 240 Switching layer 260 Memory layer MC Memory cell

Claims (46)

A first conductive layer; and
A second conductive layer; and
a third conductive layer provided between the first conductive layer and the second conductive layer;
a resistance change layer provided between the first conductive layer and the third conductive layer;
a switching layer provided between the third conductive layer and the second conductive layer;
The switching layer comprises:
an oxide of a first element, which is at least one element selected from the group consisting of zirconium (Zr), yttrium (Y), tantalum (Ta), lanthanum (La), cerium (Ce), titanium (Ti), hafnium (Hf), and magnesium (Mg);
a compound of a second element which is at least one element selected from the group consisting of zinc (Zn), tin (Sn), gallium (Ga), indium (In), and bismuth (Bi) and a third element which is at least one element selected from the group consisting of tellurium (Te), sulfur (S), and selenium (Se);
2. A storage device comprising: The storage device according to claim 1, wherein the third element is tellurium (Te). The storage device of claim 1, wherein the switching layer further includes a fourth element that is at least one element selected from the group consisting of carbon (C), boron (B), nitrogen (N), germanium (Ge), silicon (Si), and aluminum (Al). The storage device according to claim 1, wherein the ratio of the sum of the atomic concentrations of the first element and oxygen (O) to the sum of the atomic concentrations of the first element, the second element, the third element, and oxygen (O) in the switching layer is 3% or more and 97% or less. a ratio of a sum of atomic concentrations of the first element and oxygen (O) to a sum of atomic concentrations of the first element, the second element, the third element, and oxygen (O) in the switching layer is 5% or more and less than 80%,
2. The storage device according to claim 1, wherein a ratio of an absolute value of a difference between an atomic concentration of the third element and an atomic concentration of the second element to a sum of atomic concentrations of the first element, the second element, the third element, and oxygen (O) is 20% or less. an atomic concentration of the third element in the switching layer is higher than an atomic concentration of the second element;
a ratio of the sum of the atomic concentrations of the first element and oxygen (O) to the sum of the atomic concentrations of the first element, the second element, the third element, and oxygen (O) is 5% or more and less than 80%,
2. The storage device according to claim 1, wherein a ratio of a difference between the atomic concentration of the third element and the atomic concentration of the second element to a sum of the atomic concentrations of the first element, the second element, the third element, and oxygen (O) is 5% or more and 20% or less. a ratio of a sum of atomic concentrations of the first element and oxygen (O) to a sum of atomic concentrations of the first element, the second element, the third element, and oxygen (O) in the switching layer is 5% or more and less than 80%,
2. The memory device according to claim 1, wherein the atomic concentration of the third element in the switching layer is higher than the atomic concentration of the second element. a ratio of a sum of atomic concentrations of the first element and oxygen (O) to a sum of atomic concentrations of the first element, the second element, the third element, and oxygen (O) in the switching layer is 5% or more and less than 80%,
2. The storage device according to claim 1, wherein a ratio of an absolute value of a difference between the atomic concentration of the third element and the atomic concentration of the second element to a sum of atomic concentrations of the first element, the second element, the third element, and oxygen (O) is 5% or less. The memory device according to claim 1, wherein the sum of the atomic concentrations of the first element, the second element, the third element, and oxygen (O) in the switching layer is 90% or more. The memory device of claim 1, wherein at least a portion of the oxide is crystalline. The memory device of claim 1, wherein the switching layer includes a mixture of the oxide and the compound. The storage device of claim 1, wherein the first conductive layer, the second conductive layer, or the third conductive layer includes at least one material selected from the group consisting of carbon, carbon nitride, tungsten, tungsten carbide, and tungsten nitride. The storage device of claim 1, wherein the first conductive layer, the second conductive layer, or the third conductive layer includes at least one material selected from the group consisting of hafnium, hafnium boride, aluminum magnesium boride, zirconium, zirconium boride, and titanium boride. The memory device of claim 1, wherein the resistance change layer includes a magnetic tunnel junction. The resistance change layer changes electrical resistance when a predetermined voltage is applied thereto.
The storage device according to claim 1 , wherein the switching layer has a nonlinear current-voltage characteristic in which a current rises at a specific threshold voltage. A plurality of first wirings;
a plurality of second wirings intersecting the plurality of first wirings;
2. The memory device according to claim 1, wherein said memory cell is provided in a region where one of said plurality of first wirings and one of said plurality of second wirings intersect. A first conductive layer; and
A second conductive layer; and
a memory layer provided between the first conductive layer and the second conductive layer;
The memory layer comprises:
an oxide of a first element, which is at least one element selected from the group consisting of zirconium (Zr), yttrium (Y), tantalum (Ta), lanthanum (La), cerium (Ce), titanium (Ti), hafnium (Hf), and magnesium (Mg);
a compound of a second element which is at least one element selected from the group consisting of zinc (Zn), tin (Sn), gallium (Ga), indium (In), and bismuth (Bi) and a third element which is at least one element selected from the group consisting of tellurium (Te), sulfur (S), and selenium (Se);
2. A storage device comprising: The storage device according to claim 17, wherein the third element is tellurium (Te). The memory device according to claim 17, wherein the memory layer has a nonlinear current-voltage characteristic in which a current rises at a specific threshold voltage, and the threshold voltage changes when a specific voltage is applied. A plurality of first wirings;
a plurality of second wirings intersecting the plurality of first wirings;
18. The memory device according to claim 17, wherein the memory cell is provided in a region where one of the plurality of first wirings and one of the plurality of second wirings intersect. A first conductive layer; and
A second conductive layer; and
a third conductive layer provided between the first conductive layer and the second conductive layer;
a resistance change layer provided between the first conductive layer and the third conductive layer;
a switching layer provided between the third conductive layer and the second conductive layer;
The switching layer comprises:
an oxide of aluminum (Al) or an oxynitride of aluminum (Al);
A compound of a first element, which is at least one element selected from the group consisting of zinc (Zn), tin (Sn), gallium (Ga), indium (In), and bismuth (Bi), and a second element, which is at least one element selected from the group consisting of tellurium (Te), sulfur (S), and selenium (Se);
2. A storage device comprising: 22. The storage device of claim 21, wherein the switching layer further includes an oxide of a third element, which is at least one element selected from the group consisting of zirconium (Zr), hafnium (Hf), yttrium (Y), tantalum (Ta), lanthanum (La), cerium (Ce), magnesium (Mg), titanium (Ti), scandium (Sc), vanadium (V), and niobium (Nb), or an oxynitride of the third element. The storage device of claim 21, wherein the second element is tellurium (Te). The memory device of claim 21, wherein the atomic concentration of aluminum (Al) in the switching layer is greater than 1%. The storage device of claim 21, wherein the switching layer further includes a fourth element that is at least one element selected from the group consisting of carbon (C), boron (B), nitrogen (N), germanium (Ge), and silicon (Si). The storage device according to claim 21, wherein the ratio of the sum of the atomic concentrations of aluminum (Al) and oxygen (O) to the sum of the atomic concentrations of aluminum (Al), the first element, the second element, and oxygen (O) in the switching layer is 3% or more and 97% or less. In the switching layer, a ratio of the sum of atomic concentrations of aluminum (Al) and oxygen (O) to the sum of atomic concentrations of aluminum (Al), the first element, the second element, and oxygen (O) is 5% or more and less than 80%,
22. The storage device according to claim 21, wherein a ratio of an absolute value of a difference between an atomic concentration of the second element and an atomic concentration of the first element to a sum of atomic concentrations of aluminum (Al), the first element, the second element, and oxygen (O) is 20% or less. an atomic concentration of the second element in the switching layer is higher than an atomic concentration of the first element;
A ratio of the sum of atomic concentrations of aluminum (Al) and oxygen (O) to the sum of atomic concentrations of aluminum (Al), the first element, the second element, and oxygen (O) is 5% or more and less than 80%,
22. The storage device according to claim 21, wherein a ratio of a difference between an atomic concentration of the second element and an atomic concentration of the first element to a sum of atomic concentrations of aluminum (Al), the first element, the second element, and oxygen (O) is 5% or more and 20% or less. In the switching layer, a ratio of a sum of atomic concentrations of aluminum (Al) and oxygen (O) to a sum of atomic concentrations of aluminum (Al), the first element, the second element, and oxygen (O) is 5% or more and less than 80%,
22. The memory device of claim 21, wherein the atomic concentration of the second element in the switching layer is higher than the atomic concentration of the first element. In the switching layer, a ratio of a sum of atomic concentrations of aluminum (Al) and oxygen (O) to a sum of atomic concentrations of aluminum (Al), the first element, the second element, and oxygen (O) is 5% or more and less than 80%,
22. The storage device according to claim 21, wherein a ratio of an absolute value of a difference between an atomic concentration of the second element and an atomic concentration of the first element to a sum of atomic concentrations of aluminum (Al), the first element, the second element, and oxygen (O) is 5% or less. The memory device according to claim 21, wherein the sum of the atomic concentrations of aluminum (Al), the first element, the second element, and oxygen (O) in the switching layer is 90% or more. The memory device of claim 21, wherein at least a portion of the oxide is crystalline. The storage device of claim 21, wherein the switching layer includes a mixture of the oxide or the oxynitride and the compound. The storage device of claim 21, wherein the switching layer further includes a fifth element that is at least one element selected from the group consisting of chromium (Cr), niobium (Nb), and vanadium (V). 22. The storage device of claim 21, wherein the first conductive layer, the second conductive layer, or the third conductive layer includes at least one material selected from the group consisting of carbon, carbon nitride, tungsten, tungsten carbide, and tungsten nitride. 22. The storage device of claim 21, wherein the first conductive layer, the second conductive layer, or the third conductive layer includes at least one material selected from the group consisting of hafnium, hafnium boride, aluminum magnesium boride, zirconium, zirconium boride, and titanium boride. The memory device of claim 21, wherein the resistance change layer includes a magnetic tunnel junction. The resistance change layer changes electrical resistance when a predetermined voltage is applied thereto.
22. The storage device according to claim 21, wherein the switching layer has a nonlinear current-voltage characteristic in which a current rises at a specific threshold voltage. A plurality of first wirings;
a plurality of second wirings intersecting the plurality of first wirings;
22. The memory device according to claim 21, wherein the memory cell is provided in a region where one of the plurality of first wirings and one of the plurality of second wirings intersect. A first conductive layer; and
A second conductive layer; and
a memory layer provided between the first conductive layer and the second conductive layer;
The memory layer comprises:
an oxide of aluminum (Al) or an oxynitride of aluminum (Al);
A compound of a first element, which is at least one element selected from the group consisting of zinc (Zn), tin (Sn), gallium (Ga), indium (In), and bismuth (Bi), and a second element, which is at least one element selected from the group consisting of tellurium (Te), sulfur (S), and selenium (Se);
2. A storage device comprising: The storage device of claim 40, wherein the memory layer further includes an oxide of a third element, which is at least one element selected from the group consisting of zirconium (Zr), hafnium (Hf), yttrium (Y), tantalum (Ta), lanthanum (La), cerium (Ce), magnesium (Mg), titanium (Ti), scandium (Sc), vanadium (V), and niobium (Nb), or an oxynitride of the third element. The storage device of claim 40, wherein the second element is tellurium (Te). The memory device according to claim 40, wherein the memory layer has a nonlinear current-voltage characteristic in which a current rises at a specific threshold voltage, and the threshold voltage changes when a specific voltage is applied. A plurality of first wirings;
a plurality of second wirings intersecting the plurality of first wirings;
41. The memory device according to claim 40, wherein the memory cell is provided in a region where one of the plurality of first wirings and one of the plurality of second wirings intersect. A first conductive layer; and
A second conductive layer; and
a third conductive layer provided between the first conductive layer and the second conductive layer;
a resistance change layer provided between the first conductive layer and the third conductive layer;
a switching layer provided between the third conductive layer and the second conductive layer;
The switching layer comprises:
an oxide of a first element, which is at least one element selected from the group consisting of zirconium (Zr), yttrium (Y), tantalum (Ta), lanthanum (La), cerium (Ce), titanium (Ti), hafnium (Hf), magnesium (Mg), scandium (Sc), vanadium (V), and niobium (Nb);
a compound of a second element which is at least one element selected from the group consisting of zinc (Zn), tin (Sn), gallium (Ga), indium (In), and bismuth (Bi) and a third element which is at least one element selected from the group consisting of tellurium (Te), sulfur (S), and selenium (Se);
2. A storage device comprising: A first conductive layer; and
A second conductive layer; and
a memory layer provided between the first conductive layer and the second conductive layer;
The memory layer comprises:
an oxide of a first element, which is at least one element selected from the group consisting of zirconium (Zr), yttrium (Y), tantalum (Ta), lanthanum (La), cerium (Ce), titanium (Ti), hafnium (Hf), magnesium (Mg), scandium (Sc), vanadium (V), and niobium (Nb);
a compound of a second element which is at least one element selected from the group consisting of zinc (Zn), tin (Sn), gallium (Ga), indium (In), and bismuth (Bi) and a third element which is at least one element selected from the group consisting of tellurium (Te), sulfur (S), and selenium (Se);
2. A storage device comprising:

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