JP2024083703A - Neutral point potential control device and neutral point potential control method for three-level inverter - Google Patents

Abstract

The present invention provides a three-level inverter that maintains a balance of neutral point potentials.
[Solution] A voltage command for the inverter is generated (dq inverse converter 13) based on the deviation (output of subtractors 8, 9) between a current command value obtained by adding a negative-phase fifth-order harmonic current command value and a positive-phase fundamental current command value, and a detected current obtained by detecting the output current of the inverter. A DC zero-phase voltage is calculated based on the deviation between the voltage of the upper capacitor and the voltage of the lower capacitor of the DC part of the inverter and the negative-phase fifth-order harmonic current command value (multiplier 19). A sixth-order harmonic zero-phase voltage is calculated based on the deviation between the voltage of the upper capacitor and the voltage of the lower capacitor, the generated sixth-order sine wave signal, and the negative-phase fifth-order harmonic current command value (multiplier 22). The DC zero-phase voltage and the sixth-order harmonic zero-phase voltage are superimposed on the voltage command for the inverter (adders 23, 24). A gate signal is generated based on the superimposed voltage to PWM-control the switching elements of the inverter.
[Selected figure] Figure 3

Description

The present invention relates to neutral point potential balance control in a three-level neutral point clamped multilevel inverter.

Figure 1 shows the configuration of a neutral-point clamped three-level inverter, and Figure 2 shows the configuration of a T-type three-level inverter. In Figure 1, P and N are the positive and negative terminals of a DC power supply (not shown). Between the positive terminal P and the negative terminal N, the upper capacitor C1 and the lower capacitor C2 of the DC section are connected in series.

In addition, a series circuit of switching elements S1 to S4, a series circuit of switching elements S5 to S8, and a series circuit of switching elements S9 to S12 are connected in parallel between the positive terminal P and the negative terminal N.

Diodes D1 and D2 are connected in series between the common connection point of switching elements S1 and S2 and the common connection point of switching elements S3 and S4, diodes D3 and D4 are connected in series between the common connection point of switching elements S5 and S6 and the common connection point of switching elements S7 and S8, and diodes D5 and D6 are connected in series between the common connection point of switching elements S9 and S10 and the common connection point of switching elements S11 and S12.

The common connection point (neutral point O) of the upper capacitor C1 and the lower capacitor C2 is connected to the common connection point of diodes D1 and D2, the common connection point of diodes D3 and D4, and the common connection point of diodes D5 and D6, respectively.

The common connection point of switching elements S2 and S3 is connected to U-phase terminal U, the common connection point of switching elements S6 and S7 is connected to V-phase terminal V, and the common connection point of switching elements S10 and S11 is connected to W-phase terminal W.

In FIG. 2, P and N are the positive and negative terminals of a DC power supply (not shown). Between the positive terminal P and the negative terminal N, the upper capacitor C1 and the lower capacitor C2 of the DC section are connected in series.

In addition, a series circuit of switching elements S1 and S4, a series circuit of switching elements S5 and S8, and a series circuit of switching elements S9 and S12 are connected in parallel between the positive terminal P and the negative terminal N.

Switching elements S2 and S3 are connected in series between the common connection point (neutral point O) of the upper capacitor C1 and the lower capacitor C2 and the common connection point of the switching elements S1 and S4, switching elements S6 and S7 are connected in series between the neutral point O and the common connection point of the switching elements S5 and S8, and switching elements S10 and S11 are connected in series between the neutral point O and the common connection point of the switching elements S9 and S12.

The common connection point of switching elements S1 and S4 is connected to U-phase terminal U, the common connection point of switching elements S5 and S8 is connected to V-phase terminal V, and the common connection point of switching elements S9 and S12 is connected to W-phase terminal W.

Switching elements S1 to S12 are composed of semiconductor switching elements such as IGBTs.

In Figs. 1 and 2, _VDCP represents the upper capacitor voltage, _VDCN represents the lower capacitor voltage, _iNP represents the neutral point current, _iNPU represents the neutral point current of the U phase, and _iU represents the U phase output current.

In such inverters, an imbalance in the neutral point potential can occur due to conditions such as the load, and variations in the characteristics of the switching elements and DC capacitors. This imbalance can cause problems such as distortion of the voltage and current waveforms output from the inverter, adversely affecting the load and system, or excessive voltage being applied to the switching elements, destroying the elements.

Conventional technology allows the neutral point potential to be controlled by superimposing a zero-sequence voltage on the inverter output voltage during input and output of active power and reactive power. However, in applications that barely handle active or reactive power, it is difficult to control the neutral point potential even with these technologies, and neutral point clamping or T-type three-level inverters cannot be applied. Examples of such applications include active filters connected to a grid and negative-sequence current compensation devices.

Non-Patent Document 1 also reports an example in which the relevant inverter is connected in parallel to an inverter with a lower switching frequency, absorbing harmonic currents and reducing the impact on the outside while improving the efficiency of the entire device.

Non-patent document 2 proposes a method of controlling the neutral point potential by superimposing a DC zero-phase voltage on the inverter output voltage when a neutral point clamped three-level inverter or a T-type three-level inverter is outputting active power.

Patent documents 1 and 2 propose a method of controlling the neutral point potential by superimposing a sixth-order sine wave zero-phase voltage on the inverter output voltage when reactive power is being output.

Patent document 3 combines non-patent document 2 and patent documents 1 and 2 to enable control of the neutral point potential when the inverter is operating at an arbitrary power factor.

Patent document 4 proposes a method of controlling the neutral point potential using a negative-sequence second harmonic current, without using a zero-sequence voltage.

"Three-phase grid-connected inverter with parallel connection of instantaneous reactive power compensator", Journal of the Institute of Electrical Engineers of Japan, Vol. 138, No. 6, pp. 530-537 (2018) "Analysis of neutral point potential fluctuations in neutral point clamp voltage type PWM inverters," Institute of Electrical Engineers of Japan, Transactions on Power Supply, Vol. 113, No. 1, pp. 41-48 (1993)

Japanese Patent Application Laid-Open No. 07-079574 Japanese Patent Application Laid-Open No. 07-135782 JP 2013-255317 A JP 2017-60272 A

Non-patent document 2 and patent documents 1 to 3 are methods that are only effective when a positive-phase fundamental current is being output. If the output current is a fundamental wave but has a negative phase or is dominated by harmonics, the neutral point potential cannot be controlled.

Patent Document 4 makes it possible to control the neutral point potential even in such cases. In particular, under light load conditions where the output current is close to zero, disturbances to the neutral point potential are small, but Non-Patent Document 2 and Patent Documents 1 to 3 make it difficult to control the neutral point potential. By applying Patent Document 4, the stability of the neutral point potential can be significantly improved under light load conditions simply by blocking unnecessary negative-sequence second harmonic current, and furthermore, the neutral point potential can be controlled without any problems by outputting a very small amount of negative-sequence second harmonic current of the appropriate phase.

However, if the output current increases, the disturbance to the neutral point potential will become greater, and the negative-sequence second harmonic current required to maintain the neutral point potential will increase, increasing the risk of adverse effects on the system and load.

The present invention aims to solve the above problems, and its purpose is to provide a neutral point potential control device for a three-level inverter that can maintain the balance of the neutral point potential even when the majority of the output current is a harmonic or a negative phase and almost no positive-phase fundamental current is output.

In order to solve the above problem, a neutral point potential control device for a three-level inverter according to claim 1 comprises:
A neutral point potential control device for a three-level inverter that outputs a harmonic current, by superimposing a zero-phase sequence voltage on an output voltage of the inverter, comprising:
a current control unit that generates a voltage command for the inverter based on a deviation between a command value of at least one of harmonic currents of negative phase fifth order, positive phase seventh order, negative phase eleventh order, and positive phase thirteenth order and a detected current obtained by detecting an output current of the inverter;
a neutral point potential balance controller that calculates a DC zero-phase-sequence voltage or a sixth-order harmonic zero-phase-sequence voltage based on a deviation between a voltage of an upper capacitor and a voltage of a lower capacitor which divide a DC voltage of a DC section of an inverter and a command value of the harmonic current, and superimposes the calculated DC zero-phase-sequence voltage or the sixth-order harmonic zero-phase-sequence voltage on a voltage command of the inverter generated by the current control section,
The neutral point potential balance controller generates a gate signal based on the superimposed voltage, and the switching elements of the inverter are PWM-controlled by the gate signal.

The neutral point potential control device for a three-level inverter according to claim 2 is the device according to claim 1,
the current control unit generates a voltage command for the inverter based on a deviation between a current command value obtained by adding a negative-phase fifth harmonic current command value and a positive-phase fundamental current command value and a detected current obtained by detecting an output current of the inverter;
The neutral point potential balance controller calculates a DC zero-phase voltage based on the deviation between the voltage of the upper capacitor and the voltage of the lower capacitor which divide the DC voltage of the DC part of the inverter and the negative-phase fifth-order harmonic current command value, calculates a sixth-order harmonic zero-phase voltage based on the deviation between the voltage of the upper capacitor and the voltage of the lower capacitor which divide the DC voltage of the DC part of the inverter, the generated sixth-order sine wave signal, and the negative-phase fifth-order harmonic current command value, and superimposes the calculated DC zero-phase voltage and sixth-order harmonic zero-phase voltage on the inverter voltage command generated by the current control unit.

The neutral point potential control device for a three-level inverter according to claim 3 is the device according to claim 2,
The current control unit is
a current command value adder that adds values on a rotating coordinate system synchronized with ωt obtained by dq transforming a d-axis current command value I _d-5 ^* and a q-axis current command value I _q-5 ^* of the negative-phase fifth harmonic using 6ωt, which is six times the voltage phase ωt of the system voltage, to a positive-phase d-axis current command value I _d1 ^* and a positive-phase q-axis current command value I _q1 ^* ;
a subtractor for calculating a deviation between a value on a rotating coordinate system synchronized with ωt, the value being obtained by performing dq transformation on an output current detection signal of an inverter using a voltage phase ωt of a system voltage, and an output of the current command value adder;
a PI amplifier that amplifies the output of the subtractor and outputs a voltage command on a rotating coordinate system that is synchronized with the voltage phase ωt;
a dq inverse converter that performs dq inverse conversion on a voltage command obtained by adding a reference voltage to the output of the PI amplifier, and outputs voltage command values vu ^* , vv ^* , vw ^* of an inverter on a fixed coordinate system;
The neutral point potential balance controller includes:
a d-axis side sign detector that detects the value of the d-axis current command value I _d-5 ^* of the negative-phase fifth harmonic and outputs a sign corresponding to the detected value;
a q-axis side sign detector that detects the value of the q-axis current command value I _q-5 ^* of the negative-phase fifth harmonic and outputs a sign corresponding to the detected value;
a d-axis side multiplier for multiplying a difference between a voltage of an upper capacitor and a voltage of a lower capacitor of a DC section of the inverter by a sign output from the d-axis side sign detector to obtain a DC zero-phase voltage α;
and a q-axis side multiplier that multiplies the voltage phase ωt of the system voltage by six to obtain a sine wave of the corresponding phase, sin6ωt, by the code output from the q-axis side code detector, and by the deviation between the voltage of the upper capacitor and the voltage of the lower capacitor of the DC part of the inverter, to obtain a zero-phase voltage γ of the sixth harmonic.

The neutral point potential control device for a three-level inverter according to claim 4 is the device according to claim 1,
the current control unit includes a current command value adder that adds a value on a rotating coordinate system synchronized with a voltage phase ωt of a system voltage, the value being obtained by dq transforming a d-axis current command value and a q-axis current command value of a 1±6n-th harmonic (n is an integer), to a positive-phase d-axis current command value I _d1 ^* and a positive-phase q-axis current command value I _q1 ^* ;
a subtractor for calculating a deviation between a value on a rotating coordinate system synchronized with ωt, the value being obtained by performing dq transformation on an output current detection signal of an inverter using a voltage phase ωt of a system voltage, and an output of the current command value adder;
a PI amplifier that amplifies the output of the subtractor and outputs a voltage command on a rotating coordinate system that is synchronized with the voltage phase ωt;
a dq inverse converter that performs dq inverse conversion on a voltage command obtained by adding a reference voltage to the output of the PI amplifier, and outputs voltage command values vu ^* , vv ^* , vw ^* of an inverter on a fixed coordinate system;
The neutral point potential balance controller includes:
a d-axis side sign detector that multiplies the d-axis current command values of the 1±6n-th harmonic by respective coefficients, detects the sum of the multiplication outputs, and outputs a sign corresponding to the detected value;
a q-axis side sign detector that multiplies the q-axis current command values of the 1±6n-th harmonic by respective coefficients, detects the sum of the multiplication outputs, and outputs a sign corresponding to the detected value;
a d-axis side multiplier for multiplying a difference between a voltage of an upper capacitor and a voltage of a lower capacitor of a DC section of the inverter by a sign output from the d-axis side sign detector to obtain a DC zero-phase voltage α;
and a q-axis side multiplier that multiplies the voltage phase ωt of the system voltage by the order of the harmonic, and multiplies the sine wave of the corresponding phase by the code output from the q-axis side code detector, and the deviation between the voltage of the upper capacitor and the voltage of the lower capacitor of the DC section of the inverter, to obtain the zero-phase voltage of the 1±6n-th harmonic.

The neutral point potential control device for a three-level inverter according to claim 5 is the device according to claim 4,
The d-axis current command value and the q-axis current command value of the harmonics added by the current command value adder of the current control unit include at least one of a negative-phase fifth harmonic, a positive-phase seventh harmonic, a negative-phase eleventh harmonic, and a positive-phase thirteenth harmonic,
The d-axis side multiplier of the neutral point potential balance controller is characterized in that, instead of the DC zero-phase-sequence voltage α, it multiplies the deviation between the voltage of the upper capacitor and the voltage of the lower capacitor of the DC section of the inverter, the sign output from the d-axis side sign detector, and the voltage phase ωt of the system voltage by the order of the harmonic and a cosine wave of the corresponding phase to obtain a harmonic zero-phase-sequence voltage that is 90° out of phase with the zero-phase-sequence voltage obtained by the q-axis side multiplier.

The neutral point potential control device for a three-level inverter according to claim 6 is the device according to claim 3,
the current command value adder of the current control unit further adds the negative-phase fundamental wave d-axis current command value I _d-1 ^* and the negative-phase fundamental wave q-axis current command value I _q-1 ^* ;
The neutral point potential balance controller includes:
a negative-phase-sequence fundamental wave d-axis side sign detector that detects the value of the negative-phase-sequence fundamental wave d-axis current command value I _d−1 ^* and outputs a sign corresponding to the detected value;
a negative-phase fundamental wave q-axis side sign detector that detects the value of the negative-phase fundamental wave q-axis current command value I _q-1 ^* and outputs a sign corresponding to the detected value;
a negative-phase-sequence fundamental wave d-axis side multiplier for multiplying a deviation between the voltage of the upper capacitor and the voltage of the lower capacitor of the DC section of the inverter, the code output from the negative-phase-sequence fundamental wave d-axis side code detector, and cos2ωt obtained by doubling the voltage phase ωt of the system voltage and obtaining a cosine wave of a corresponding phase, thereby obtaining a zero-phase voltage ε of a second harmonic;
a negative-phase-sequence fundamental wave q-axis side multiplier that multiplies a difference between a voltage of an upper capacitor and a voltage of a lower capacitor of a DC section of the inverter by a code output from the negative-phase-sequence fundamental wave q-axis side code detector, and sin2ωt obtained by doubling a voltage phase ωt of a system voltage and obtaining a sine wave of a corresponding phase, thereby obtaining a zero-phase-sequence voltage ζ of a second harmonic having a phase difference of 90° from the zero-phase-sequence voltage ε,
The d-axis side multiplier of the neutral point potential balance controller is characterized in that, instead of the DC zero-phase sequence voltage α, it multiplies the deviation between the voltage of the upper capacitor and the voltage of the lower capacitor of the DC section of the inverter, the detection code output from the d-axis side code detector, and cos6ωt, which is obtained by multiplying the voltage phase ωt of the system voltage by six and determining a cosine wave of the corresponding phase, to determine a sixth-order harmonic zero-phase sequence voltage δ that is 90° out of phase with the zero-phase sequence voltage γ.

The neutral point potential control device for a three-level inverter according to claim 7 comprises:
The neutral point potential control device according to claim 4 ;
The neutral point potential control device according to claim 5 ;
The neutral point potential control device further includes a switching unit that switches to either the neutral point potential control device according to claim 4 or the neutral point potential control device according to claim 5 when a set switching condition is satisfied.

A method for controlling a neutral point potential of a three-level inverter according to claim 8,
A method for controlling a neutral point potential of a three-level inverter that outputs a harmonic current by superimposing a zero-phase sequence voltage on an output voltage of the inverter, comprising:
a current control step in which the current control unit generates a voltage command for the inverter based on a deviation between a command value of at least one of harmonic currents of negative phase fifth order, positive phase seventh order, negative phase eleventh order, and positive phase thirteenth order and a detected current obtained by detecting an output current of the inverter;
a neutral point potential balance control step in which a neutral point potential balance controller determines a DC zero-phase voltage or a sixth harmonic zero-phase voltage based on a deviation between a voltage of an upper capacitor and a voltage of a lower capacitor which divide a DC voltage of a DC section of an inverter and a command value of the harmonic current, and superimposes the determined DC zero-phase voltage or the sixth harmonic zero-phase voltage on a voltage command of the inverter generated by the current control unit;
The method is characterized in that the switching elements of the inverter are PWM-controlled by a gate signal generated based on the voltage superimposed in the neutral point potential balance control step.

(1) According to the inventions described in claims 1 to 8, the balance of neutral point potentials can be maintained even when the majority of the output current of a three-level inverter is harmonics or negative phase and almost no positive-phase fundamental current is output. This makes it possible to suppress distortion of the output voltage and current caused by the imbalance of neutral point potentials and to equalize the voltages applied to the switching elements.
(2) According to the invention as set forth in claims 2 and 3, even when the majority of the output current of the three-level inverter is a negative-phase fifth harmonic current, the balance of the neutral point potential can be maintained.
(3) According to the invention described in claims 4 and 5, the balance of the neutral point potential can be maintained even when the output current of the three-level inverter contains a mixture of a positive-phase fundamental current, a negative-phase fifth harmonic current, and a positive-phase seventh harmonic current. By extending the invention in the same manner, the invention can also be used for a negative-phase eleventh harmonic current and a positive-phase thirteenth harmonic current.
(4) According to the invention described in claim 4, a high effect of maintaining the balance of neutral point potential can be obtained, particularly when applied to applications in which a certain degree of input and output of effective power is expected.
(5) According to the invention as set forth in claim 5, a high neutral point potential balance maintaining effect can be obtained, particularly when applied to applications in which the input and output of effective power is very small.
(6) According to the invention as set forth in claim 6, even when the majority of the output current of the three-level inverter is a negative-phase fundamental current, the balance of the neutral point potential can be maintained.

This is a main circuit configuration diagram of a neutral point clamped three-level inverter. FIG. 1 is a diagram showing the main circuit configuration of a T-type three-level inverter. FIG. 2 is a control block diagram of the first embodiment of the present invention. FIG. 11 is a control block diagram of a second embodiment of the present invention. FIG. 11 is a control block diagram of a third embodiment of the present invention. FIG. 11 is a control block diagram of a fourth embodiment of the present invention. FIG. 4 is an explanatory diagram showing simulation conditions when the effects of the present invention are confirmed by simulation. FIG. 4 is a waveform diagram showing a simulation result of the first embodiment of the present invention. FIG. 11 is a waveform diagram showing a simulation result of the third embodiment of the present invention. FIG. 11 is a waveform diagram showing a simulation result of the fourth embodiment of the present invention.

The following describes embodiments of the present invention with reference to the drawings, but the present invention is not limited to the following embodiments. In the following Examples 1 to 4, it is assumed that current control is applied to an inverter.

Figure 3 shows a control block diagram of the first embodiment. In Figure 3, a current control block (current control unit) and a neutral point potential balance controller are provided. First, the configuration of the current control block will be described.

Reference numeral 1 denotes a PLL (Phase Locked Loop) circuit that receives the detection signal Vs of the system voltage (the voltage of the system to which the three-level inverter is connected) as input and outputs the voltage phase ωt. Reference numeral 2 denotes a low-pass filter (LPF) that receives the three-phase inverter output current detection signal I as input and removes noise, switching ripple, etc. from the detection current I.

3 is a dq converter that inputs the output of the low-pass filter 2 and converts the inverter output current detection signal into a value on a rotating coordinate system synchronized with the voltage phase ωt. The d-axis component of the output of the dq converter 3 is Id, and the q-axis component is Iq.

I _d-5 ^* is the negative-phase fifth-order d-axis current command value, I _q-5 ^* is the negative-phase fifth-order q-axis current command value, I _d1 ^* is the positive-phase d-axis current command value, and I _q1 ^* is the positive-phase q-axis current command value.

Reference numeral 4 denotes a multiplier that multiplies the voltage phase ωt by 6 and outputs 6ωt, and reference numeral 5 denotes a dq converter that converts the current command values I _d-5 ^* and I _q-5 ^* , which are DC values, into values on a rotating coordinate synchronized with the voltage phase ωt using 6ωt.

6 is an adder that adds the dq transformed value of the negative-phase fifth-order d-axis current command value I _d-5 ^* and the positive-phase d-axis current command value I _d1 ^* , and 7 is an adder that adds the dq transformed value of the negative-phase fifth-order q-axis current command value I _q-5 ^* and the positive-phase q-axis current command value I _q1 ^* .

Reference numeral 8 denotes a subtractor which obtains the deviation between the output of the adder 6 and the d-axis component _Id , and reference numeral 9 denotes a subtractor which obtains the deviation between the output of the adder 7 and the q-axis component _Iq .

10 is a PI amplifier that amplifies the d-axis deviation (output of subtractor 8) and outputs a voltage command value on a rotating coordinate system synchronized with the voltage phase ωt, and 11 is a PI amplifier that amplifies the q-axis deviation (output of subtractor 9) and outputs a voltage command value on a rotating coordinate system synchronized with the voltage phase ωt.

12 is an adder that adds a reference voltage to the output of the PI amplifier 10 on the d-axis side. This reference voltage may be a fixed value that represents the rated amplitude of the system voltage, or it may be the amplitude detected from the detection signal Vs of the system voltage and added. Vs may also be dq converted and added to both the d-axis and q-axis.

A dq inverse converter 13 receives a voltage command value on a rotating coordinate system and converts it into a value on a fixed coordinate system using a voltage phase ωt. The output of the dq inverse converter 13 is the voltage command values vu ^* , vv ^* , vw ^* .

Next, the configuration of the neutral point potential balance controller will be described. Reference numeral 14 denotes a sign detector (d-axis side sign detector) that detects the value of the negative-phase fifth-order d-axis current command value I _d-5 ^* and outputs 1 if it is positive, -1 if it is negative, and 0 if it is zero.

Reference numeral 15 denotes a sign detector (q-axis side sign detector) which detects the value of the negative-phase fifth-order q-axis current command value I _q-5 ^* and outputs 1 if it is positive, -1 if it is negative, and 0 if it is zero.

Reference numeral 16 denotes a subtractor which determines the deviation between the detection signal of the upper capacitor voltage V _DCP of the DC section of the inverter and the detection signal of the lower capacitor voltage V _DCN .

17 is a low-pass filter (LPF) that removes noise, switching ripple, and third-harmonic ripple that is superimposed in principle from the deviation calculated by the subtractor 16, and 18 is a multiplier that multiplies the output of the low-pass filter 17 by a gain G.

Reference numeral 19 denotes a multiplier (d-axis side multiplier) that obtains the product of the sign of the negative-phase fifth-order d-axis current command value I _d-5 ^* output from the sign detector 14 and a value (output of the multiplier 18) obtained by multiplying the deviation between the upper capacitor voltage V _DCP and the lower capacitor voltage V _DCN by a gain G. The output of the multiplier 19 is a DC zero-phase voltage α, described later, that is superimposed on the inverter voltage command (output of the dq inverter 13).

20 is a multiplier that multiplies the voltage phase ωt by six and outputs 6ωt, and 21 is a sine wave generator that inputs 6ωt and outputs a sine wave of the corresponding phase (sin6ωt).

Reference numeral 22 denotes a multiplier (q-axis side multiplier) that obtains the product of the sign of the negative-phase fifth-order q-axis current command value _Iq-5 ^* output from the sign detector ₁₅ , the output sin6ωt of the sine wave generator 21, and a value (output of the multiplier 18) obtained by multiplying the deviation between the upper capacitor voltage VDCP and the lower capacitor voltage _VDCN by a gain G. The output of the multiplier 22 is a sixth-order harmonic zero-phase voltage γsin6ωt (described later) that is superimposed on the inverter voltage command (output of the dq inverter 13).

An adder 23 obtains the sum of the output of the multiplier 19 and the output of the multiplier 22, and the output of this adder 23 becomes the output of the neutral point potential balance controller.
The output of the adder 23 is added in an adder 24 to all of the voltage command values vu ^* , vv ^* , vw ^* which are the outputs of the dq inverse transformer 13 .

25 is a PWM modulator that PWM-modulates the output of the adder 24, adds dead time, converts it into a gate signal for the inverter's switching element, and outputs it.

Next, the operation of the first embodiment will be described. First, the relationship between the inverter output voltage/current and the current flowing out from the neutral point will be clarified. The U-phase output voltage command value is _vU ^* , and the U-phase output current is _iUn , which are defined as in the following equation (1).

V is the amplitude of the voltage command value, and it is assumed that -1≦V≦1. ω is the angular frequency of the fundamental wave. α is the DC zero-phase voltage, and γ and δ are the amplitudes of the sixth harmonic zero-phase voltage that are 90° out of phase with each other. β is the amplitude of the third harmonic zero-phase voltage that is superimposed to improve the voltage utilization rate. n represents the harmonic order of the current and is an integer including negative values. n=1 represents the positive-phase fundamental current, and n=-5 represents the negative-phase fifth harmonic current. _φn is the phase difference of the current with respect to the voltage.

Calculate the average value of the neutral point current of the U phase per one period. If vu ^* = 0, the middle arm (switching elements S2, S3, S6, S7, S10, and S11 in the circuits of Figures 1 and 2) is in the ON state, and the U phase output current _iU all flows out from the neutral point (O).

When v _U ^* =±1, i _U passes through the switching elements of the upper and lower arms (S 1 , S 5 , S 9 , S 4 , S 8 , S 12 ) and no current flows to the neutral point O.

If vu ^* = 0.3, 70% of _iU passes through the neutral point O, and the remaining 30% passes through the upper arm switching element. The proportion of this output current passing through the neutral point can be expressed by the following equation (2).

The U-phase neutral point current _iNPUn due to the n-th harmonic is the product of the rate at which the output current passes through the neutral point and _iU , and can be calculated by the following equation (3).

The average value I _NPUn of the U-phase neutral current per period can be found by integrating i _NPUn . However, the absolute value must be evaluated by dividing the integration interval. Here, the case is divided into phase angles of ±π/2 and ±3π/2, but this only works as an approximate solution when α, β, γ, and δ are close to 0. The average value I _NPU1 of the U-phase neutral current when n=1 is given by the following equation (4).

The neutral point currents of the V and W phases can be calculated in the same manner, and the average value _INPn of the neutral point currents of the three phases combined per one period can also be calculated. Furthermore, _Idn and _Iqn are defined as in the following equation (5).

By substituting the order of a harmonic that is likely to appear in n to find I _NPn and substituting φ _n into equation (5), the following equation (6) is obtained.

As shown in Non-Patent Document 2, it is indeed possible to generate a neutral point current by superimposing a DC zero-phase voltage when a positive-phase fundamental wave d-axis current, i.e., active power, is input and output, and this can be used to control the neutral point potential.

As shown in Patent Documents 1 and 2, when a positive-phase fundamental wave q-axis current, i.e., reactive power, is input and output, a neutral point current can be generated by superimposing a sixth-order zero-phase voltage. Although a neutral point current can be generated by superimposing a sixth-order zero-phase voltage during input and output of active power, it can also be seen that the obtained neutral point current is only 1/35 of that of a DC zero-phase voltage, and the effect of controlling the neutral point potential is very low.

It has also been shown that the control methods of Non-Patent Document 2 and Patent Documents 1 and 2 do not interfere with each other, and that both can be used in combination, as in Patent Document 3. As Patent Document 4 shows, a negative-phase second harmonic current directly affects the neutral point current (or the neutral point current can be manipulated) without superimposing a zero-phase voltage, and there is an effect when a third harmonic is superimposed on a zero-phase voltage, but there is no effect on a zero-phase voltage of a direct current or sixth harmonic. Therefore, Patent Document 4 and Non-Patent Document 2 and Patent Documents 1 to 3 can be used in combination without interfering with each other.

On the other hand, equation (6) shows that when a DC zero-phase voltage is superimposed, a neutral point current can be generated if the d-axis current is a negative-phase fifth or positive-phase seventh harmonic.

A neutral point current can also be generated by combining a sixth-order zero-phase voltage with a negative-phase fifth-order or positive-phase seventh-order harmonic. In particular, when superimposing a sixth-order zero-phase voltage, the coefficient of equation (6) becomes larger when combined with a negative-phase fifth-order or positive-phase seventh-order harmonic current rather than the fundamental wave. This indicates that a larger neutral point current can be obtained, making it easier to control the neutral point potential.

Based on the above results, in Example 1, the neutral point potential is controlled by a combination of the d-axis negative-phase fifth harmonic and DC zero-phase voltage (α), and the q-axis negative-phase fifth harmonic and sixth harmonic zero-phase voltage (γ).

That is, the current control unit uses subtractors 8 and 9 to calculate the deviation between the current command value (output of adders 6 and 7) obtained by adding the negative-phase fifth harmonic current command value and the positive-phase fundamental current command value and the detected current (output of dq converter 3) that detects the inverter output current, and generates a voltage command for the inverter based on this deviation (dq inverse converter 13). The neutral point potential balance controller calculates the DC zero-phase voltage α using the d-axis side multiplier 19 and the sixth harmonic zero-phase voltage γ using the q-axis side multiplier 22, and superimposes the sum of the zero-phase voltages α and γ on the inverter voltage command (output of dq inverse converter 13).

When the negative-phase fifth-order d-axis current command value _Id-5 ^* is _Id-5 ^* >0 and _VDCP > _VDCN , a positive DC zero-phase voltage (α: output of multiplier 19) is superimposed on the voltage command values vu ^* , vv ^* , vw ^* by the block in Fig. 3. That is, α>0 in equation (1). At this time, _INP-5 <0 from equation (6), and a negative neutral point current is generated, which flows from the system side to the inverter when the inverter is connected to the system. This neutral point current discharges the upper capacitor (C1) and charges the lower capacitor (C2), and the difference between _VDCP and _VDCN becomes small.

Similarly, when V _DCP > V _DC but I _d-5 ^* < 0, the output of the code detector 14 becomes negative and α < 0 in equation (1). Therefore, I _NP-5 < 0 remains unchanged and operates to reduce the difference between V _DCP and V _DCN .

When I _q-5 ^* >0 and V _DCP >V _DCN , a sixth-order sine wave is superimposed as a zero-phase voltage (γ: output of multiplier 22) such that γ > 0. According to equation (6), a negative neutral point current is generated and the difference between V _DCP and V _DCN becomes small.

This allows the neutral point potential balance to be maintained, suppressing distortion of the output voltage and current caused by an imbalance in the neutral point potential, and making the voltage applied to the switching elements uniform.

In general harmonic loads, the current is often smaller for higher order harmonics. Example 1 is a method for controlling the neutral point potential assuming a device that outputs mainly negative-phase fifth harmonic, such as an active filter connected to the same system as such a load.

In the first embodiment, for example, a case will be considered in which a negative-phase-sequence fifth-order d-axis current of 0.5 pu is being output (I _d-5 =0.5) and a DC zero-phase-sequence voltage (α) is superimposed to generate I _NP-5 and control the neutral point potential.

At this time, if the positive-phase fundamental d-axis current _Id1 is also output, _INP1 is also generated, but if _Id1 > -0.1 pu, then _INP-5 and _INP1 have the same direction, or the absolute value of _INP-5 is larger than the absolute value of _INP1 , so the neutral point potential can be controlled without any problem.

However, when I _d1 < -0.1 pu, the directions of I _NP-5 and I _NP1 are opposite and the absolute value of I _NP-5 is smaller than the absolute value of I _NP1 , so that a neutral point current flows in the opposite direction to the intention, making it impossible to control the neutral point potential and instead promoting a deterioration of the balance.

In such a case, the direction of the DC voltage to be added as a zero-phase sequence voltage to the voltage command values vu ^* , vv ^* , vw ^* must be determined based on whether _Id1 is larger or smaller than -Id _-5 /5.

In the second embodiment, a measure to solve the above problem is applied to the first embodiment. Fig. 4 shows a control block of the second embodiment. In Fig. 4, the same parts as those in Fig. 3 are denoted by the same reference numerals. The current control block in Fig. 4 differs from the configuration in Fig. 3 in that a positive-phase seventh current command value is added as a current command value that takes a deviation from the detected currents ( _{Id, Iq} ) of the inverter.

That is, the following are added: a multiplier 31 which multiplies the voltage phase ωt by -6 and outputs -6ωt; a dq converter 32 which converts the positive-phase seventh-order d-axis current command value I _d7 ^* and the q-axis current command value I _q7 ^* , which are DC values, into values on a rotating coordinate synchronized with ωt using -6ωt; and adders 33 and 34 which add the output of the dq converter 32 to the dq-converted values of the negative-phase fifth-order d-axis current command value I _d-5 ^* and the q-axis current command value I _q-5 ^* , respectively.

The neutral point potential balance controller in FIG. 4 differs from the configuration in FIG. 3 in that each current command value is multiplied by a coefficient, and the sum of these coefficients determines the signs of the DC zero-phase voltage α and the sixth harmonic zero-phase voltage γ.

That is, a multiplier 35 for multiplying the positive-phase seventh-order d-axis current command value I _d7 ^* by a coefficient -1/7, a multiplier 36 for multiplying the negative-phase fifth-order d-axis current command value I _d-5 ^* by a coefficient 1/5, and an adder 37 for summing the output values of the multipliers 35 and 36 and the positive-phase d-axis current command value I _d1 are provided, the output of the adder 37 is input to the sign detector 14, a multiplier 38 for multiplying the positive-phase seventh-order q-axis current command value I _q7 ^* by a coefficient -1/13, a multiplier 39 for multiplying the negative-phase fifth-order q-axis current command value I _q-5 ^* by a coefficient 1/11, a multiplier 40 for multiplying the positive-phase q-axis current command value I _q1 ^* by a coefficient -1/35, and an adder 41 for summing the output values of the multipliers 38, 39, and 40 are provided, and the output of the adder 41 is input to the sign detector 15. Other parts are configured in the same manner as in FIG.

In the second embodiment, the sign of the DC zero-phase-sequence voltage α (output of the d-axis multiplier 19) is determined depending on whether the output of the adder 37 input to the sign detector 14 on the d-axis side, i.e., I _d1 +I _d-5 /5-I _d7 /7, is greater than or less than zero. In the above example, when I _d-5 =0.5 and I _d7 =0, when I _d1 is less than -0.1, the sign of α is reversed and an appropriate zero-phase-sequence voltage can be superimposed. In the second embodiment, this measure is also applied to the q-axis.

In other words, the sign of the sixth harmonic zero-phase voltage γ (the output of the q-axis multiplier 22) is determined by whether the output of the adder 41 input to the sign detector 15 is greater than or less than zero.

Therefore, the second embodiment can be applied to devices that also output a positive-phase fundamental current or that output mainly a positive-phase seventh harmonic current rather than a negative-phase fifth harmonic current, and neutral point potential control can be performed. Similarly, it can be extended to harmonics of the tenth order and higher.

In other words, an adder is added to the current control block in Figure 4 to add the d-axis and q-axis current command values of the 1±6n-th harmonic (n is an integer), and the neutral point potential balance controller is provided with a multiplier that multiplies the coefficient, an adder that calculates the total value, a sign detector, and a q-axis multiplier similar to those described above, corresponding to the 1±6n-th harmonic, to calculate the zero-phase voltage of the 1±6n-th harmonic and superimpose it on the inverter voltage command (output of the dq inverse converter 13).

Therefore, according to the second embodiment, the balance of the neutral point potential can be maintained even when the output current of the three-level inverter contains a mixture of a positive-phase fundamental current, a negative-phase fifth harmonic current, a positive-phase seventh harmonic current, and 1±6n harmonics, for example, a negative-phase eleventh harmonic current and a positive-phase thirteenth harmonic current.

In the first and second embodiments, the neutral point potential is controlled by a combination of the d-axis current and the DC zero-phase voltage (α). In contrast, in the third embodiment, the neutral point potential is controlled by a combination of the d-axis current and the sixth-order zero-phase voltage (δ). Comparing the α and δ terms of I _d1 and I _d-5 in the above formula (6), the term with the largest coefficient is the α term of I _d1 , and the term with the next largest coefficient is the δ term of I _d-5 . Therefore, for applications where a certain amount of input and output of active power is expected even if the harmonic current is larger, such as adding an active filter function to a power storage converter, the neutral point potential control using the DC zero-phase voltage (α) according to the second embodiment is effective.

However, for applications where the input and output of effective power is very small, such as converters with only an active filter function, neutral point potential control using the sixth harmonic zero-phase voltage (δ) is more effective. Example 3 is a neutral point potential control method suitable for such applications.

A control block diagram of the third embodiment is shown in Fig. 5. In Fig. 5, the same parts as those in Fig. 4 are denoted by the same reference numerals. The neutral point potential balance controller in Fig. 5 differs from the configuration in Fig. 4 in that, instead of the multipliers 35 and 36 that multiply the coefficients and the adder 37 that calculates the sum, a multiplier 51 that multiplies the positive-phase seventh-order d-axis current command value _Id7 ^* by a coefficient 7/13, a multiplier 52 that multiplies the negative-phase fifth-order d-axis current command value Id _-5 ^* by a coefficient 5/11, and a multiplier 53 that multiplies the positive-phase d-axis current command value _Id1 A multiplier 53 that multiplies ^* by a coefficient 1/35 and an adder 54 that sums up the output values of each multiplier are provided, and further a multiplier 55 that multiplies the voltage phase ωt by six to output 6ωt and a cosine wave generator 56 that inputs 6ωt and outputs a cosine wave (cos6ωt) of a corresponding phase are provided, and the output (cos6ωt) of the cosine wave generator 56 is multiplied by the multiplier 19 (d-axis side multiplier) to obtain a sixth harmonic zero-phase voltage δcos6ωt that is 90° out of phase with the zero-phase voltage γsin6ωt. Other parts are configured in the same manner as in FIG. 4.

The configuration of FIG. 5 (Example 3) can also be extended to harmonics of the 10th order and higher (1±6n-th order harmonics) in the same way as in the case of FIG. 4 (Example 2).

Therefore, according to the third embodiment, the neutral point potential balance can be maintained even when a positive-phase fundamental current and multiple harmonic currents are mixed, as in the second embodiment, and further, when applied to applications in which the input and output of active power is very small, a high neutral point potential balance can be maintained.

Incidentally, the second and third embodiments may be suitably switched by a switching unit according to the output of the active power. The switching conditions may be, for example, a simple method of comparing the command value of the fundamental d-axis current with a fixed threshold value and using the second embodiment if |I _d1 ^* |>0.1 holds. Alternatively, the coefficients of the above formula (6) may be compared and switching to the second embodiment may be performed if |I _d1 ^* |>5|I _d-5 ^* |/11 holds. More precisely, the magnitude of the sum of the neutral point currents due to the respective harmonics at α=δ may be compared to use the following formula (7).

If it is true, switch to Example 2; if it is false, switch to Example 3.

In the first to third embodiments, when only the negative-phase fundamental current is output, the neutral point potential cannot be controlled. This is because, as shown by I _NP-1 in the above-mentioned equation (6), when n=-1, the neutral point potential cannot be controlled even if a DC or third- or sixth-order harmonic voltage is superimposed as a zero-phase voltage. Here, let us consider superimposing a second-order zero-phase voltage as shown in the following equation (8).

εcos2ωt and ζsin2ωt are second harmonic zero-sequence voltages that are 90° out of phase with each other.

Then, if we calculate the neutral current at n=-1 again, we get the following equation (9):

From this result, it can be seen that the neutral point potential can be controlled by superimposing a second harmonic on the zero-phase voltage when a negative-phase fundamental current is output. Based on the above results, in Example 4, it is possible to control the neutral point potential even when a negative-phase fundamental current is output. A function is added to Example 1 to superimpose a second-order cosine wave when a negative-phase fundamental d-axis current flows, and to superimpose a second-order sine wave on the q-axis current. Also, unlike the DC zero-phase voltage α of Example 1, a combination of a d-axis negative-phase fifth harmonic and a sixth-order zero-phase voltage (δ) is applied. As a result, when a negative-phase fifth harmonic or a negative-phase fundamental current is output, a neutral point current can be generated and the neutral point potential can be controlled.

A control block diagram of the fourth embodiment is shown in Fig. 6. In Fig. 6, the same parts as those in Fig. 3 are denoted by the same reference numerals. The current control block in Fig. 6 differs from the configuration in Fig. 3 in that a multiplier 61 that doubles the voltage phase ωt to output 2ωt, a dq converter 62 that converts the d-axis current command value I _d-1 ^* and the q-axis current command value I _q-1 ^* of the negative-phase fundamental wave, which are DC values, into values on the rotating coordinate system synchronized with ωt by using 2ωt, and adders 63 and 64 that add the output of the dq converter 62 to the dq-converted values of the negative-phase fifth-order d-axis current command value I d- ₅ ^* and the q-axis current command value I _q-5 ^* , respectively.

The neutral point potential balance controller in Fig. 6 has the following additional configuration to the neutral point potential balance controller in Fig. 3. Reference numeral 65 denotes a sign detector (negative-phase fundamental d-axis side sign detector) that detects the value of the negative-phase-sequence fundamental d-axis current command value I _d-1 ^* and outputs a sign corresponding to the detected value (1 if positive, -1 if negative, 0 if zero).

Reference numeral 66 denotes a sign detector (negative-phase fundamental q-axis side sign detector) that detects the value of the negative-phase fundamental q-axis current command value I _q-1 ^* and outputs a sign corresponding to the detected value (1 if positive, -1 if negative, 0 if zero).

67 is a multiplier that doubles the voltage phase ωt and outputs 2ωt, and 68 is a cosine wave generator that inputs 2ωt and outputs a cosine wave of the corresponding phase (cos2ωt).

Reference numeral 69 denotes a multiplier (negative-phase fundamental d-axis side multiplier) _that calculates the product of the sign of the negative-phase fundamental d-axis current command value I _d-1 ^* output from the sign detector 65, the output cos2ωt of the cosine wave generator 68, and a value (output of the multiplier 18) obtained by multiplying the deviation between the upper capacitor voltage V DCP and the lower capacitor voltage V _DCN by a gain G. The output of the multiplier 69 is the zero-phase voltage ε of the second harmonic.

70 is a multiplier that doubles the voltage phase ωt and outputs 2ωt, and 71 is a sine wave generator that inputs 2ωt and outputs a sine wave of the corresponding phase (sin2ωt).

Reference numeral 72 denotes a multiplier (negative-phase fundamental q-axis side multiplier) that obtains the product of the sign of the negative-phase fundamental q-axis current command value I _q-1 ^* output from the sign detector ₆₆ , the output sin2ωt of the sine wave generator 71, and a value (output of the multiplier 18) obtained by multiplying the deviation between the upper capacitor voltage V DCP and the lower capacitor voltage V _DCN by a gain G. The output of the multiplier 72 is the zero-phase voltage ζ of the second harmonic that is 90° out of phase with the ε.

73 is an adder that adds the output of adder 23 and the output of multiplier 69, and 74 is an adder that adds the output of adder 73 and the output of multiplier 72, and is configured so that the output of adder 74 and the output of the dq inverse transformer 13 are added in adder 24.

Furthermore, multiplier 19 (d-axis side multiplier) in FIG. 6 is configured to calculate the product of the sign of the negative-phase fifth-order d-axis current command value I _d-5 ^* output from sign detector 14, the output cos6ωt of cosine wave generator 56, and the value obtained by multiplying the deviation between the upper capacitor voltage V _DCP and the lower capacitor voltage V _DCN by gain G (output of multiplier 18), to obtain the zero-phase voltage δ of the sixth harmonic.

In addition, Example 4 can be combined with Example 2 or Example 3 to perform neutral point potential control even when a positive-phase seventh harmonic current or a positive-phase fundamental current is output.

In addition, Example 4 can be used in conjunction with Examples 1 to 3 because it does not interfere with them, and the balance of the neutral point potential can be maintained even when negative-phase fundamental current and harmonic current are mixed.

In the first to third embodiments, as shown in equation (6), there is no interference with the negative-phase second harmonic current. Also, in the third embodiment, even if the voltage command value defined in equation (8) is used to calculate the neutral point current at n = -2, the following equation (10) is obtained.

Therefore, there is no interference with the zero-phase second harmonic current. Therefore, the present invention can be used in conjunction with Patent Document 4, which makes it possible to maintain the balance of the neutral point potential even when the output current is close to zero.

Next, we will describe the results of a simulation confirming the effects of the present invention. The main circuit conditions used in the simulation are shown in Figure 7.

In Figure 7, the output side of the three-level inverter 70 is connected to the system power supply 100 via a filter circuit 80 consisting of a reactor and a capacitor. This is a model assuming a 415V, 500kVA neutral point clamped three-level inverter (e.g. Figure 1).

71 is a DC power supply for a three-level inverter 70, and a 32 Ω resistor 73 is connected between the positive terminal and neutral point O via a switch 72.

In this simulation, the controls of Examples 1, 3, and 4 were enabled to output current, and at time 0.05 seconds, a 32 Ω resistor 73 was turned on by switch 72 as a voltage balance disturbance. Furthermore, at time 0.15 seconds, the balance control was disabled.

Figure 8 shows the simulation results of Example 1 (Figure 3). The output current is (a) a negative-phase fifth harmonic of the d-axis of 1 pu, and (b) a negative-phase fifth harmonic of the q-axis. However, a 300 Hz resonant amplifier is also used in conjunction with the current-controlled PI amplifier (10, 11). The superimposed zero-phase voltage is DC (α) in (a) and sixth harmonic (γ) in (b).

When resistor 73 is turned on, a deviation occurs in the neutral point balance, but it remains constant and stable operation continues. When balance control is disabled, the deviation continues to increase and the system becomes unstable. Comparing (a) and (b), the deviation when resistor is turned on is larger in (a).

Since there is no difference in the control parameters and the amplitude of the superimposed zero-phase voltage is proportional to the deviation, the amplitude of the zero-phase voltage required to generate the same magnitude of neutral point current is smaller in (b), which indicates that it is easier to control the neutral point potential. Looking at equation (6), the coefficient of γ is larger than the coefficient of α in _INP-5 , showing the same tendency.

In Example 3 (Figure 5), we proposed superimposing a zero-phase voltage of the sixth harmonic (δ) instead of DC during the output of the negative-phase fifth harmonic on the d-axis. The effect of this was also confirmed by simulation. Figure 9 shows the results of neutral point potential control using a zero-phase voltage of the sixth harmonic during the output of a 1 p.u. negative-phase fifth harmonic on the d-axis.

Compared with FIG. 8(a), the deviation when the resistor is turned on is smaller, and as shown in the difference between the coefficients α and δ in I _NP-5 of equation (6), this shows that it is easier to control the neutral point potential in Example 3 with respect to the negative-phase fifth harmonic on the d axis.

Figure 10 shows the simulation results for Example 4 (Figure 6). The output current is a fundamental wave of 1 pu inverse phase on the d-axis or q-axis. However, the frequency of the current-controlled resonant amplifier is changed to 100 Hz. The results are the same as those in Figure 8, and if the control is enabled, the balance of the neutral point potential can be maintained even if resistor 73 is inserted. If the control is disabled, divergence occurs.

1...PLL circuit 2,17...Low-pass filter 3,5,32,62...dq converter 4,18,19,20,22,31,35,36,38,39,40,51,52,53,55,67,69,70,72...Multiplier 6,7,12,23,24,33,37,34,41,54,63,64,73,74...Adder 8,9,16...Subtractor 10,11...PI amplifier 13...dq inverse converter 14,15,65,66...Code detector 21,71...Sine wave generator 56,68...Cosine wave generator

Claims (8)

A neutral point potential control device for a three-level inverter that outputs a harmonic current, by superimposing a zero-phase sequence voltage on an output voltage of the inverter, comprising:
a current control unit that generates a voltage command for the inverter based on a deviation between a command value of at least one of harmonic currents of negative phase fifth order, positive phase seventh order, negative phase eleventh order, and positive phase thirteenth order and a detected current obtained by detecting an output current of the inverter;
a neutral point potential balance controller that calculates a DC zero-phase-sequence voltage or a sixth-order harmonic zero-phase-sequence voltage based on a deviation between a voltage of an upper capacitor and a voltage of a lower capacitor which divide a DC voltage of a DC section of an inverter and a command value of the harmonic current, and superimposes the calculated DC zero-phase-sequence voltage or the sixth-order harmonic zero-phase-sequence voltage on a voltage command of the inverter generated by the current control section,
A neutral point potential control device for a three-level inverter, characterized in that a switching element of the inverter is PWM-controlled by a gate signal generated based on the voltage superimposed by the neutral point potential balance controller. the current control unit generates a voltage command for the inverter based on a deviation between a current command value obtained by adding a negative-phase fifth harmonic current command value and a positive-phase fundamental current command value and a detected current obtained by detecting an output current of the inverter;
2. The neutral point potential balance controller according to claim 1, wherein the neutral point potential balance controller calculates a DC zero-phase sequence voltage based on a deviation between a voltage of an upper capacitor and a voltage of a lower capacitor which divide a DC voltage of a DC part of the inverter and the negative-phase fifth-order harmonic current command value, calculates a sixth-order harmonic zero-phase sequence voltage based on a deviation between a voltage of an upper capacitor and a voltage of a lower capacitor which divides a DC voltage of a DC part of the inverter, a generated sixth-order sine wave signal, and the negative-phase fifth-order harmonic current command value, and superimposes the calculated DC zero-phase sequence voltage and the sixth-order harmonic zero-phase sequence voltage on the inverter voltage command generated by the current control unit. The current control unit is
a current command value adder that adds values on a rotating coordinate system synchronized with ωt obtained by dq transforming a d-axis current command value I _d-5 ^* and a q-axis current command value I _q-5 ^* of the negative-phase fifth harmonic using 6ωt, which is six times the voltage phase ωt of the system voltage, to a positive-phase d-axis current command value I _d1 ^* and a positive-phase q-axis current command value I _q1 ^* ;
a subtractor for calculating a deviation between a value on a rotating coordinate system synchronized with ωt, the value being obtained by performing dq transformation on an output current detection signal of an inverter using a voltage phase ωt of a system voltage, and an output of the current command value adder;
a PI amplifier that amplifies the output of the subtractor and outputs a voltage command on a rotating coordinate system that is synchronized with the voltage phase ωt;
a dq inverse converter that performs dq inverse conversion on a voltage command obtained by adding a reference voltage to the output of the PI amplifier, and outputs voltage command values vu ^* , vv ^* , vw ^* of an inverter on a fixed coordinate system;
The neutral point potential balance controller includes:
a d-axis side sign detector that detects the value of the d-axis current command value I _d-5 ^* of the negative-phase fifth harmonic and outputs a sign corresponding to the detected value;
a q-axis side sign detector that detects the value of the q-axis current command value _Iq-5 ^* of the negative-phase fifth harmonic and outputs a sign corresponding to the detected value;
a d-axis side multiplier for multiplying a difference between a voltage of an upper capacitor and a voltage of a lower capacitor of a DC section of the inverter by a sign output from the d-axis side sign detector to obtain a DC zero-phase voltage α;
3. The neutral point potential control device for a three-level inverter according to claim 2, further comprising: a q-axis side multiplier that multiplies a voltage phase ωt of a system voltage by six to obtain a sine wave of a corresponding phase, sin6ωt, by the code output from the q-axis side code detector, and by a deviation between the voltage of the upper capacitor and the voltage of the lower capacitor of the DC section of the inverter, to obtain a zero-phase voltage γ of a sixth harmonic. the current control unit includes a current command value adder that adds a value on a rotating coordinate system synchronized with a voltage phase ωt of a system voltage, the value being obtained by dq transforming a d-axis current command value and a q-axis current command value of a 1±6n-th harmonic (n is an integer), to a positive-phase d-axis current command value I _d1 ^* and a positive-phase q-axis current command value I _q1 ^* ;
a subtractor for calculating a deviation between a value on a rotating coordinate system synchronized with ωt, the value being obtained by performing dq transformation on an output current detection signal of an inverter using a voltage phase ωt of a system voltage, and an output of the current command value adder;
a PI amplifier that amplifies the output of the subtractor and outputs a voltage command on a rotating coordinate system that is synchronized with the voltage phase ωt;
a dq inverse converter that performs dq inverse conversion on a voltage command obtained by adding a reference voltage to the output of the PI amplifier, and outputs voltage command values vu ^* , vv ^* , vw ^* of an inverter on a fixed coordinate system;
The neutral point potential balance controller includes:
a d-axis side sign detector that multiplies the d-axis current command values of the 1±6n-th harmonic by respective coefficients, detects the sum of the multiplication outputs, and outputs a sign corresponding to the detected value;
a q-axis side sign detector that multiplies the q-axis current command values of the 1±6n-th harmonic by respective coefficients, detects the sum of the multiplication outputs, and outputs a sign corresponding to the detected value;
a d-axis side multiplier for multiplying a difference between a voltage of an upper capacitor and a voltage of a lower capacitor of a DC section of the inverter by a sign output from the d-axis side sign detector to obtain a DC zero-phase voltage α;
2. The neutral point potential control device for a three-level inverter according to claim 1, further comprising: a q-axis side multiplier that multiplies a voltage phase ωt of a system voltage by an order number of the harmonic, and multiplies a sine wave of a corresponding phase by the code output from the q-axis side code detector, and a deviation between the voltage of the upper capacitor and the voltage of the lower capacitor of a DC section of the inverter, to obtain a zero-phase voltage of a 1±6n-th harmonic. The d-axis current command value and the q-axis current command value of the harmonics added by the current command value adder of the current control unit include at least one of a negative-phase fifth harmonic, a positive-phase seventh harmonic, a negative-phase eleventh harmonic, and a positive-phase thirteenth harmonic,
5. The neutral point potential control device for a three-level inverter according to claim 4, wherein the d-axis side multiplier of the neutral point potential balance controller obtains a harmonic zero-phase voltage having a phase difference of 90° from the zero-phase voltage obtained by the q-axis side multiplier by a deviation between the voltage of the upper capacitor and the voltage of the lower capacitor of the DC section of the inverter, a sign output from the d-axis side sign detector, and a voltage phase ωt of the system voltage multiplied by the order of the harmonic and multiplied by a cosine wave of a corresponding phase. the current command value adder of the current control unit further adds the negative-phase fundamental wave d-axis current command value I _d-1 ^* and the negative-phase fundamental wave q-axis current command value I _q-1 ^* ;
The neutral point potential balance controller includes:
a negative-phase-sequence fundamental wave d-axis side sign detector that detects the value of the negative-phase-sequence fundamental wave d-axis current command value I _d-1 ^* and outputs a sign corresponding to the detected value;
a negative-phase fundamental wave q-axis side sign detector that detects the value of the negative-phase fundamental wave q-axis current command value I _q-1 ^* and outputs a sign corresponding to the detected value;
a negative-phase-sequence fundamental wave d-axis side multiplier for multiplying a deviation between the voltage of the upper capacitor and the voltage of the lower capacitor of the DC section of the inverter, the code output from the negative-phase-sequence fundamental wave d-axis side code detector, and cos2ωt obtained by doubling the voltage phase ωt of the system voltage and obtaining a cosine wave of a corresponding phase, thereby obtaining a zero-phase voltage ε of a second harmonic;
a negative-phase-sequence fundamental wave q-axis side multiplier that multiplies a difference between a voltage of an upper capacitor and a voltage of a lower capacitor of a DC section of the inverter by a code output from the negative-phase-sequence fundamental wave q-axis side code detector, and sin2ωt obtained by doubling a voltage phase ωt of a system voltage and obtaining a sine wave of a corresponding phase, thereby obtaining a zero-phase-sequence voltage ζ of a second harmonic having a phase difference of 90° from the zero-phase-sequence voltage ε,
4. The neutral point potential control device for a three-level inverter according to claim 3, wherein the d-axis side multiplier of the neutral point potential balance controller multiplies, instead of the DC zero-phase sequence voltage α, a deviation between the voltage of the upper capacitor and the voltage of the lower capacitor of the DC section of the inverter, a detection code output from the d-axis side code detector, and cos6ωt, which is a cosine wave obtained by multiplying the voltage phase ωt of the system voltage by six and determining a cosine wave of a corresponding phase, to determine a sixth-order harmonic zero-phase sequence voltage δ having a phase difference of 90° from the zero-phase sequence voltage γ. The neutral point potential control device according to claim 4 ;
The neutral point potential control device according to claim 5 ;
A neutral point potential control device for a three-level inverter comprising: a switching unit that switches to either the neutral point potential control device according to claim 4 or the neutral point potential control device according to claim 5 when a set switching condition is satisfied. A method for controlling a neutral point potential of a three-level inverter that outputs a harmonic current by superimposing a zero-phase sequence voltage on an output voltage of the inverter, comprising:
a current control step in which the current control unit generates a voltage command for the inverter based on a deviation between a command value of at least one of harmonic currents of negative phase fifth order, positive phase seventh order, negative phase eleventh order, and positive phase thirteenth order and a detected current obtained by detecting an output current of the inverter;
a neutral point potential balance control step in which a neutral point potential balance controller determines a DC zero-phase voltage or a sixth harmonic zero-phase voltage based on a deviation between a voltage of an upper capacitor and a voltage of a lower capacitor which divide a DC voltage of a DC section of an inverter and a command value of the harmonic current, and superimposes the determined DC zero-phase voltage or the sixth harmonic zero-phase voltage on a voltage command of the inverter generated by the current control unit;
A method for controlling a neutral point potential of a three-level inverter, comprising PWM-controlling a switching element of the inverter by a gate signal generated based on the voltage superimposed in the neutral point potential balance control step.

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