JP2024081093A - Integrated circuit - Google Patents

Abstract

To solve the problem that no means is proposed at present for realizing a basic logic circuit requiring a series/parallel connection of transistor such as a NOR or NAND logic requiring a plurality of different input signals from a plurality of lateral FETs of the same conductivity type in channel portions laminated in at the same position on the same plane in a longitudinal direction.SOLUTION: In a plurality of lateral FETs of the same conductivity type in channel portions laminated at the same position on the same plane in a longitudinal direction, gate signal electrodes of the plurality of lateral FETs are laminated via insulator films in the longitudinal direction. As a result, a pattern area is reduced in relative to a conventional system, thereby accelerating and reducing in cost an integrated circuit using gate all-around type transistors laminated in the longitudinal direction which cannot be implemented conventionally.SELECTED DRAWING: Figure 1

Description

This relates to an integrated circuit using gate-all-around transistors.

In the past, LSIs have progressed in accordance with Moore's Law as planar transistors have become increasingly miniaturized, and there has been steady progress in increasing capacity, reducing costs, increasing speed, and reducing power consumption.

As a result, MPUs, which are representative of logic LSIs, have achieved GHz operation using more than 1 billion planar transistors, and NAND flash memory, which uses planar transistors and is the memory LSI with the highest capacity, has been increased to 64 Gbit (Reference 1).

However, miniaturization of this planar transistor has been approaching its limit in recent years due to short channel effects and the like.

To solve this problem, three-dimensional transistors that are resistant to the short channel effect have been developed, a representative example of which is the FinFET.

FinFETs have the advantage that they can be miniaturized and are resistant to short channel effects because three sides can be used for the channel, instead of one side of a planar transistor. In recent years, gate-around-type transistors (hereafter abbreviated as GAA) that can use four sides for the channel and can control the short channel effect even more than FinFETs, and MBCFETs (Multi Bridge Channel FETs) that are stacked vertically and are more suitable for high speed than GAA have been proposed.

In these structures, the source, channel, and drain of the transistor are arranged horizontally (hereafter abbreviated as lateral FET or lateral GAA), so that by optimizing the manufacturing technology, it is relatively easy to stack multiple lateral FETs of the same conductivity type vertically in the same position on the same plane. This has the advantage of not only increasing speed but also reducing costs by reducing the pattern area on the plane.

However, when the conductivity type of the channel portion is the same (all N-type or all P-type), the gate electrode is common to the multiple stacked lateral FETs, so basic logic circuits such as NOR and NAND logic, which require multiple different input signals, could not be realized by multiple lateral FETs stacked vertically in the same position on the same plane.As a result, there was a problem in the past that it was not possible to achieve the high speed and low cost that would be achieved by doing so.

Reference 1

M. Sako et al., "A Low-Power 64Gb MLC NAND-Flash Memory in 15nm CMOS Technology," ISSCC Dig. Tech. Papers, 2015.

Problem that the invention is trying to solve

At present, there is no proposed means for implementing basic logic circuits such as NOR and NAND logic, which require multiple different input signals, using multiple lateral FETs with the same conductivity type in their channel portions stacked vertically in the same position on the same plane.

Means for solving the problem

This is achieved by stacking a plurality of lateral FETs having the same conductivity type of their channel portions vertically at the same position on the same plane, and vertically stacking the gate signal electrodes of the plurality of lateral FETs via an insulating film.

Effect of the invention

This invention has made it possible for the first time to realize basic logic circuits such as NOR and NAND logic, which require multiple different input signals, using multiple lateral FETs with the same conductivity type in the channel portion stacked vertically at the same position on the same plane. As a result, by reducing the pattern area compared to the conventional method, it is possible to increase the speed and reduce the cost of integrated circuits using vertically stacked gate-all-around transistors, which was not possible to realize in the past.

A first embodiment of an integrated circuit according to the present invention will now be described with reference to the drawings.
[First embodiment]
(Configuration of the First Embodiment)

A first embodiment of the present invention will now be described.
Figure 1 (right) shows three horizontal GAA 116, 216, 316 stacked vertically at the same position on the same plane. The gate signals 119, 219, 319 are separated from each other by insulating films, and independent signals can be input. The source electrodes 117, 217, 317 of the three horizontal GAA can be either common or independent, depending on the manufacturing method. In Figure 1, this situation is shown by a fine dashed line 414. Similarly, the drain electrodes 118, 218, 318 of the three horizontal GAA can be either common or independent, depending on the manufacturing method. In Figure 1, this situation is shown by a fine dashed line 415.

Figure 1 (left) shows a cross-sectional view of the gate portion 16 in the top view (Figure 2) of this embodiment in which three horizontal GAA are stacked. 112, 212, 312 are the channel portions of the first, second, and third GAA layers, respectively, 111, 211, 311 are the gate insulating films of the first, second, and third GAA layers, respectively, and 101, 201, 301 are the gate electrodes of the first, second, and third GAA layers, respectively. 112, 212, and 312 have the same conductivity type. The stacked electrodes are insulated by insulating films 213 and 313.
The three types of gate electrodes are drawn out laterally from the side surfaces of the lateral GAA in an independent and separate form as 115, 215, and 315. They are separated from each other by insulating films 214 and 314.

3 (left) shows a cross-sectional view of the source part (part 15 in FIG. 2) of the vertically stacked GAA, and FIG 3 (right) shows a cross-sectional view of the drain part (part 14 in FIG. 2) of the vertically stacked GAA. The source parts 120, 220, and 320 of the stacked GAA are separated from each other by insulating films 221 and 321.

When connecting source parts stacked vertically, holes are made in the insulating film at the part where vertical metal wiring is connected vertically, as shown at 414. Figure 3 (left) shows the case where all three layers are connected vertically. Similarly, drain parts 121, 221, 321 of stacked GAA are separated from each other by insulating films 222, 322. When connecting drain parts stacked vertically, holes are made in the insulating film at the part where vertical metal wiring is connected vertically, as shown at 415. Figure 3 (left) shows the case where all three layers are connected vertically.

1 (left), first, the insulating film 113 is laminated as the first layer, then the conductive film 101 (to be removed by etching later), the semiconductor portion 112 that will become the channel, and the conductive film 101 (to be removed by etching later), then the second and third layers are laminated in the same manner, and then the conductive films 101, 201, and 301 are removed by etching.Then, the semiconductor portion that will become the channel is oxidized to form a gate insulating film (111 in the first layer).

Next, the insulating film 114 corresponding to the first layer is formed next to the horizontal GAA, and then the gate electrode 115 is formed. If polysilicon, which is easy to diffuse in the horizontal and vertical directions in the cavity, is used for the gate electrode, 101, which will become the gate electrode of the horizontal GAA, can be formed at the same time as forming 115. Next, in the second layer, the insulating film 214 is formed, the gate electrode 215 (and 201 at the same time), and finally, in the third layer, the insulating film 314 is formed, and the gate electrode 315 (and 301 at the same time) is formed. In the method described above, the gate electrodes of the first, second, and third layers are formed in separate processes, but it is possible that they can be formed in the same process from the right side of Figure 1 (left) by devising the manufacturing process.

Figure 4 shows the most characteristic case of the first embodiment, where all source electrodes of vertically stacked GAA are connected vertically 514 and all drain electrodes are connected vertically 515. The rough dashed lines 514 and 515 indicate the vertically connected parts. This allows the realization of a so-called NOR circuit in which three horizontal GAA are connected in parallel. Compared to the conventional case where only one type of gate electrode could be realized vertically, stacking three layers reduces the pattern area to one-third and the manufacturing cost to about one-third.

The effect of this cost reduction becomes greater as the number of GAA stacked vertically increases. For example, when about 1000 GAA are stacked vertically, by using an FeFET using a ferroelectric film capable of storing nonvolatile information in the gate electrode, an FeRAM (nonvolatile ferroelectric memory) using parallel-connected FeFETs with a pattern area reduced to 1/1000 of the conventional one can be realized.

Alternatively, by storing an analog value in the FeFET and inputting a gate voltage controlled by the analog value to the gate, it is possible to realize the multiplication and accumulation operation, which is the most important component of an AI LSI, with a pattern area 1/1000 of the conventional size. The gate voltage is input with a value controlled by the analog value stored in the FeFET. For example, when the analog value (resistance value of the FeFET) is large, the input signal to the gate is increased, and when the analog value is small, the input signal to the gate is decreased, so that the multiplication and accumulation operation between FeFETs with different stored analog values can be performed accurately.

Figure 5 shows a modification of Figure 4. Only the drain electrode side is common at 914, and the source side is an independent electrode at 918, 928, and 938. By storing analog values in the FeFET and inputting a voltage to the source, it is possible to realize product-sum calculations, the most important component of AI LSI, in a pattern area 1/1000 the size of the conventional one. The source electrode area is larger than that of the method in Figure 4, but it has the characteristic that the control of the source voltage is simplified (it does not depend on the weight of the FeFET).

6 shows an example of vertically stacked GAA connected in series. This is realized by connecting the source electrodes of the first and second layers with vertical wiring 714, and connecting the drain electrodes of the second and third layers with 715. This method is effective when realizing a NAND circuit or NAND type memory.

Figure 7 shows the case where three vertically stacked layers of GAA are used in a two-input parallel connection circuit. This method is effective when there are circuits with different numbers of input signals on an integrated circuit or when transistors with high current driving capacity are required.

Effects of the embodiment

In the present invention, it has become possible for the first time to realize basic logic circuits such as NOR and NAND logic, which require multiple different input signals, using multiple lateral FETs with the same conductivity type of the channel part stacked vertically at the same position on the same plane. As a result, by reducing the pattern area compared to the conventional method, it becomes possible to increase the speed and reduce the cost of integrated circuits using vertically stacked gate-all-around type transistors, which was not possible to realize in the past. The pattern area can be set to a value (value for one layer) that is independent of the number of lateral FETs stacked vertically. Therefore, the more the number of layers, the cheaper the cost of one lateral FET becomes (in an ideal case, it can be reduced to 1/N by stacking N layers).

Other Examples

Industrial applicability

The present invention is not limited to series and parallel connections of transistors. By arranging N-type transistors connected in series and P-type transistors connected in parallel at different positions on the same plane and sharing the stacked gate electrode between them, a CMOS NAND circuit can be easily realized. By connecting in the opposite manner, a CMOS NOR circuit can be easily realized. By ingeniously adjusting the wiring, even more complex composite gate circuits can be realized. As a result, the present invention can be applied to all currently commercialized integrated circuits such as system LSIs, logic LSIs, and FPGAs.

1A and 1B are a gate cross-sectional view and a circuit diagram of a first embodiment of a stacked GAA of an integrated circuit according to the present invention; 1 is a top view of a first embodiment of a stacked GAA of an integrated circuit according to the present invention; 1 is a cross-sectional view of a source/drain portion of a first embodiment of a stacked GAA of an integrated circuit according to the present invention; FIG. 1 is a diagram showing a first embodiment of a stacked GAA of an integrated circuit according to the present invention in which the source and drain electrodes are all common. FIG. 1 is a diagram showing a first embodiment of a stacked GAA of an integrated circuit according to the present invention in which all drain electrodes are common. FIG. 1 is a diagram showing a first embodiment of a stacked GAA of an integrated circuit according to the present invention, in which the GAA is connected in series. FIG. 1 is a diagram showing a modified example of the first embodiment of the stacked GAA of the integrated circuit according to the present invention.

Reference numerals 112, 212, and 312 denote channel portions of the first, second, and third GAA layers, 111, 211, and 311 denote gate insulating films of the first, second, and third GAA layers, and 101, 201, and 301 denote gate electrodes of the first, second, and third GAA layers. The stacked electrodes are insulated by insulating films 213 and 313.
Reference numerals 111, 211, and 311 denote gate insulating films of the first, second, and third GAA layers, respectively, and reference numerals 101, 201, and 301 denote gate electrodes of the first, second, and third GAA layers, respectively. The stacked electrodes are insulated from each other by insulating films 213 and 313.
The gate electrodes are drawn out laterally from the side surfaces of the lateral GAA in the form of independent and separate gate electrodes 115, 215, and 315. They are separated from each other by insulating films 214 and 314.
The GAA source portions 120, 220, 320 are separated from each other by insulating films 221, 321.
The source portions 120, 220, 320 of the stacked GAA are separated from each other by insulating films 221, 321. The drain portions 121, 221, 321 of the stacked GAA are separated from each other by insulating films 222, 322.
414, 415, 514, 515, 714, 715, 814, 815, and 914 are vertical connection wirings for the source-drain portions.

Claims (3)

An integrated circuit comprising a plurality of lateral FETs having the same conductivity type of channel portion vertically stacked at the same position on the same plane, the lateral FETs being characterized in that the gate signal electrodes of the plurality of lateral FETs are stacked vertically via an insulating film. 2. The integrated circuit according to claim 1, wherein the lateral FET is a gate-around type FET using four sides as a channel, or a plurality of lateral FETs stacked vertically or horizontally. 3. The integrated circuit according to claim 1, wherein the plurality of lateral FETs are connected in series or in parallel.