JP2024073177A - Semiconductor device and its manufacturing method - Google Patents

Abstract

The present invention suppresses deterioration of an interlayer insulating film.
[Solution] A method for manufacturing a semiconductor device includes the steps of: preparing a wafer having a trench provided on an upper surface of a semiconductor substrate, a gate electrode disposed in the trench, and an interlayer insulating film disposed in the trench and covering an upper surface of the gate electrode; forming a first metal layer on the upper surface of the semiconductor substrate and the upper surface of the interlayer insulating film; silicidating the first metal layer by heating the wafer, wherein the first metal layer is silicided at a portion in contact with the upper surface of the semiconductor substrate and is not silicided at a portion in contact with the upper surface of the interlayer insulating film; forming a barrier metal layer on the first metal layer on an upper portion of the upper surface of the semiconductor substrate and on an upper portion of the interlayer insulating film; and forming a second metal layer on the barrier metal layer.
[Selected Figure] Figure 1

Description

The technology disclosed in this specification relates to a semiconductor device and a manufacturing method thereof.

The semiconductor device disclosed in Patent Document 1 has a gate electrode disposed in a trench, and an interlayer insulating film that is also disposed in the trench and covers the upper surface of the gate electrode. By providing the interlayer insulating film in the trench in this manner, the entire upper surface of the semiconductor substrate is exposed from the interlayer insulating film. Therefore, the upper electrode can be brought into contact with the upper surface of the semiconductor substrate without forming a contact hole. Since no contact hole is required, there is no need to align the contact hole and the trench. Therefore, it is possible to narrow the spacing between the trenches, making it possible to miniaturize the semiconductor device.

JP 2019-003967 A

In a structure in which an interlayer insulating film is provided in a trench, conventionally, an upper electrode is formed as shown in FIG. 10. First, as shown in FIG. 10(a), a metal layer 140 is formed on the upper surface of the semiconductor substrate 120 and the upper surface of the interlayer insulating film 130. Next, as shown in FIG. 10(b), the semiconductor substrate 120 is heated to silicidize the metal layer 140 in the portion in contact with the semiconductor substrate 120. Next, as shown in FIG. 10(c), the metal layer 140 that is not silicided on the upper portion of the interlayer insulating film 130 is removed by etching. Next, as shown in FIG. 10(d), a barrier metal layer 150 is formed on the surface of the metal layer 140 and the surface of the interlayer insulating film 130 by sputtering or the like. At this time, since there is a step between the surface of the metal layer 140 and the surface of the interlayer insulating film 130, the barrier metal layer 150 formed on the surface of the metal layer 140 and the barrier metal layer 150 formed on the surface of the interlayer insulating film 130 are separated. As a result, a protrusion 150a that overhangs toward the upper portion of the interlayer insulating film 130 is formed in the barrier metal layer 150 formed on the surface of the metal layer 140. Therefore, a slit-shaped gap 160 is formed between the protrusion 150a and the barrier metal layer 150 below it. Then, as shown in FIG. 10(e), a metal layer 170 is formed on the barrier metal layer 150. The metal layer 170 fills the gap 160.

When the semiconductor device is in use, it repeatedly generates heat. If the gap 160 is filled with a metal layer 170 as shown in FIG. 10(e), high thermal stress occurs near the gap 160 due to thermal expansion of the metal layer 170 in the gap 160 when the semiconductor device generates heat. As a result, cracks may occur in the interlayer insulating film 130, and the insulating properties of the interlayer insulating film 130 may deteriorate. In this way, the interlayer insulating film is easily deteriorated in semiconductor devices manufactured by conventional manufacturing methods. This specification proposes a manufacturing method for a semiconductor device in which the interlayer insulating film is less likely to deteriorate.

The method for manufacturing a semiconductor device disclosed in this specification includes a wafer preparation step, a first metal layer formation step, a silicidation step, a barrier metal layer formation step, and a second metal layer formation step. In the wafer preparation step, a wafer is prepared. The wafer has a semiconductor substrate, a gate electrode, and an interlayer insulating film. The semiconductor substrate contains silicon. A trench is provided on the upper surface of the semiconductor substrate. The gate electrode is disposed in the trench. The interlayer insulating film is disposed in the trench and covers the upper surface of the gate electrode. The upper surface of the interlayer insulating film is located lower than the upper surface of the semiconductor substrate. In the first metal layer formation step, a first metal layer is formed on the upper surface of the semiconductor substrate and the upper surface of the interlayer insulating film. In the silicidation step, the first metal layer is reacted with the semiconductor substrate by heating the wafer to silicidize the first metal layer. In the silicidation step, the first metal layer is silicided at a portion in contact with the upper surface of the semiconductor substrate and is not silicided at a portion in contact with the upper surface of the interlayer insulating film. In the barrier metal layer forming process, a barrier metal layer is formed on the first metal layer above the upper surface of the semiconductor substrate and above the interlayer insulating film. In the second metal layer forming process, a second metal layer is formed on the barrier metal layer.

In the silicidation process, the entire first metal layer covering the upper surface of the semiconductor substrate may be silicided, or a portion of the first metal layer covering the upper surface of the semiconductor substrate (i.e., the portion in contact with the upper surface of the semiconductor substrate) may be silicided, with an unsilicided portion remaining above the silicided portion.

In this manufacturing method, a first metal layer is formed on the upper surface of the semiconductor substrate and the upper surface of the interlayer insulating film, and then the first metal layer is silicided. At this time, the first metal layer is not silicided in the portion in contact with the upper surface of the interlayer insulating film. Next, a barrier metal layer is formed on the first metal layer on the upper part of the upper surface of the semiconductor substrate and the upper part of the interlayer insulating film without removing the first metal layer on the upper part of the interlayer insulating film. Since the first metal layer on the upper part of the interlayer insulating film is not removed, the height of the step between the upper part of the interlayer insulating film and the upper part of the semiconductor substrate is low. Therefore, the barrier metal layer can be formed in a state in which it is connected to the upper part of the upper surface of the semiconductor substrate and the upper part of the interlayer insulating film. Therefore, a protruding part that protrudes in an overhanging shape is not formed in the barrier metal layer. Therefore, a slit-shaped gap such as the gap 160 in FIG. 10(d) is not formed on the upper part of the interlayer insulating film. Next, a second metal layer is formed on the barrier metal layer. Since there is no slit-shaped gap on the upper part of the interlayer insulating film, the second metal layer is not filled in the slit-shaped gap. Therefore, in semiconductor devices manufactured using this manufacturing method, the interlayer insulating film is less likely to deteriorate.

This specification discloses a semiconductor device. The semiconductor device includes a semiconductor substrate, a gate electrode, an interlayer insulating film, a first electrode layer, a second electrode layer, a barrier metal layer, and a third electrode layer. The semiconductor substrate includes silicon. A trench is provided on the upper surface of the semiconductor substrate. The gate electrode is disposed in the trench. The interlayer insulating film is disposed in the trench and covers the upper surface of the gate electrode. The upper surface of the interlayer insulating film is located lower than the upper surface of the semiconductor substrate. The first electrode layer covers the upper surface of the semiconductor substrate, and has a silicide layer made of an alloy of a first metal and silicon in a portion that contacts the upper surface of the semiconductor substrate. The second electrode layer is disposed in the trench, covers the upper surface of the interlayer insulating film, and is made of the first metal. The upper surface of the second electrode layer is located lower than the upper surface of the first electrode layer. The barrier metal layer covers the first electrode layer and the second electrode layer. The third electrode layer covers the barrier metal layer.

This semiconductor device can be manufactured by the manufacturing method disclosed in this specification. Therefore, in this semiconductor device, the interlayer insulating film is less likely to deteriorate.

FIG. 1A to 1C are explanatory diagrams of a method for manufacturing a semiconductor device. 1A to 1C are explanatory diagrams of a method for manufacturing a semiconductor device. 1A to 1C are explanatory diagrams of a method for manufacturing a semiconductor device. 1A to 1C are explanatory diagrams of a method for manufacturing a semiconductor device. 1A to 1C are explanatory diagrams of a method for manufacturing a semiconductor device. An explanatory diagram of an overhang. 1A to 1C are explanatory diagrams of a method for manufacturing a semiconductor device. 1A to 1C are explanatory diagrams of a method for manufacturing a semiconductor device. 1A to 1C are explanatory diagrams of a conventional method for manufacturing a semiconductor device.

In one example of a semiconductor device disclosed in this specification, the thickness of the laminated portion of the first metal layer and the barrier metal layer in the upper part of the interlayer insulating film may be thicker than the height of the step between the upper surface of the interlayer insulating film and the upper surface of the semiconductor substrate.

In one example of a semiconductor device disclosed in this specification, the thickness of the laminated portion of the second electrode layer and the barrier metal layer in the upper part of the interlayer insulating film may be thicker than the height of the step between the upper surface of the interlayer insulating film and the upper surface of the semiconductor substrate.

The semiconductor device 10 of the embodiment shown in FIG. 1 is a MOSFET (metal-oxide-semiconductor field effect transistor). The semiconductor device 10 has a semiconductor substrate 12. The semiconductor substrate 12 is made of a semiconductor material containing Si, such as SiC or Si. A plurality of trenches 14 are formed in an upper surface 12a of the semiconductor substrate 12. The trenches 14 are arranged at intervals in the left-right direction in FIG. 1. Each trench 14 extends long in the depth direction in FIG. 1.

A gate insulating film 20, a gate electrode 22, and an interlayer insulating film 24 are arranged in each trench 14. The gate insulating film 20 covers the inner surface of the trench 14. The gate electrode 22 is arranged in a range surrounded by the gate insulating film 20. The gate electrode 22 is insulated from the semiconductor substrate 12 by the gate insulating film 20. The interlayer insulating film 24 is made of silicon oxide. The interlayer insulating film 24 covers the upper surface of the gate electrode 22. The upper surface 24a of the interlayer insulating film 24 is located lower than the upper surface 12a of the semiconductor substrate 12. In other words, the upper surface 24a of the interlayer insulating film 24 is arranged in the trench 14. Therefore, a step is formed between the upper surface 12a of the semiconductor substrate 12 and the upper surface 24a of the interlayer insulating film 24. In FIG. 1, height H1 is the height of the step between the upper surface 12a of the semiconductor substrate 12 and the upper surface 24a of the interlayer insulating film 24.

An upper electrode 30 is provided on the upper part of the semiconductor substrate 12. The upper electrode 30 has a first electrode layer 31, a second electrode layer 32, a third electrode layer 33, and a barrier metal layer 34.

The first electrode layer 31 is composed of nickel silicide (i.e., NiSi) or titanium silicide (TiSi). The first electrode layer 31 covers the upper surface 12a of the semiconductor substrate 12.

The second electrode layer 32 is made of nickel or titanium. If the first electrode layer 31 is nickel silicide, the second electrode layer 32 is nickel, and if the first electrode layer 31 is titanium silicide, the second electrode layer 32 is titanium. The second electrode layer 32 is disposed in the trench 14. The second electrode layer 32 covers the upper surface 24a of the interlayer insulating film 24. The upper surface 32a of the second electrode layer 32 is disposed below the upper surface 12a of the semiconductor substrate 12. In other words, the upper surface 32a of the second electrode layer 32 is disposed in the trench 14.

The barrier metal layer 34 covers the upper surface of the first electrode layer 31 and the upper surface 32a of the second electrode layer 32. The barrier metal layer 34 is continuously distributed across the upper surface of the first electrode layer 31 and the upper surface 32a of the second electrode layer 32. The barrier metal layer 34 may be composed of a single layer of TiN, or may be composed of two layers of a Ti layer and a TiN layer. When the barrier metal layer 34 has a two-layer structure, the Ti layer covers the upper surface of the first electrode layer 31 and the upper surface 32a of the second electrode layer 32, and the TiN layer covers the upper surface of the Ti layer. When the first electrode layer 31 is composed of nickel silicide, the characteristics of the semiconductor device 10 are more stable when the barrier metal layer 34 has a two-layer structure of a Ti layer and a TiN layer. When the first electrode layer 31 is composed of titanium silicide, the barrier metal layer 34 may be either a single layer of TiN or a two-layer structure of Ti/TiN.

The third electrode layer 33 is composed of an alloy film (e.g., AlSi) whose main component is aluminum. The third electrode layer 33 covers the upper surface of the barrier metal layer 34.

The thickness T1 shown in FIG. 1 is the thickness of the laminated portion of the second electrode layer 32 and the barrier metal layer 34 on the upper part of the interlayer insulating film 24. In other words, the thickness T1 is the sum of the thickness of the second electrode layer 32 and the thickness of the barrier metal layer 34. The thickness T1 is thicker than the height H1. Therefore, the upper surface of the barrier metal layer 34 on the upper part of the interlayer insulating film 24 is located above the upper surface 12a of the semiconductor substrate 12. When the thickness T1 of the laminated portion is thicker than the height H1 of the step, the barrier metal layer 34 is less likely to be interrupted at the step, and the barrier metal layer 34 can be provided continuously on the upper part of the interlayer insulating film 24 and the upper part of the upper surface 12a of the semiconductor substrate 12.

A lower electrode 40 is provided on the lower part of the semiconductor substrate 12. The lower electrode 40 is in contact with the lower surface 12b of the semiconductor substrate 12.

A source region 50, a contact region 52, a body region 54, a drift region 56, and a drain region 58 are provided inside the semiconductor substrate 12.

The source region 50 is an n-type region with a high concentration of n-type impurities. The source region 50 is in contact with the first electrode layer 31. The source region 50 is also in contact with the gate insulating film 20 on the side of the trench 14.

The contact region 52 is a p-type region with a high concentration of p-type impurities. The contact region 52 is in contact with the first electrode layer 31.

The body region 54 is a p-type region having a lower p-type impurity concentration than the contact region 52. The body region 54 contacts the source region 50 and the contact region 52 from below. The body region 54 contacts the gate insulating film 20 below the source region 50.

The drift region 56 is an n-type region having a lower n-type impurity concentration than the source region 50. The drift region 56 contacts the body region 54 from below. The drift region 56 contacts the gate insulating film 20 on the lower side of the body region 54.

The drain region 58 is an n-type region having a higher n-type impurity concentration than the drift region 56. The drain region 58 contacts the drift region 56 from below. The drain region 58 contacts the lower electrode 40.

Next, a method for manufacturing the semiconductor device 10 will be described. First, the source region 50, contact region 52, body region 54, drift region 56, and drain region 58 are formed by performing epitaxial growth, ion implantation, and the like on the semiconductor substrate 12. Next, the upper surface 12a of the semiconductor substrate 12 is selectively etched to form a trench 14. Next, as shown in FIG. 2, a gate electrode 22 and a gate insulating film 20 are formed in the trench 14.

Next, as shown in FIG. 3, a thick interlayer insulating film 24 is formed on the semiconductor substrate 12. Here, the interlayer insulating film 24 is grown so that the trench 14 is filled with the interlayer insulating film 24 above the gate electrode 22. Next, as shown in FIG. 4, the interlayer insulating film 24 is etched to remove the interlayer insulating film 24 on the upper surface 12a of the semiconductor substrate 12. Here, the interlayer insulating film 24 is left in the trench 14. Therefore, the upper surface 24a of the interlayer insulating film 24 after etching is located lower than the upper surface 12a of the semiconductor substrate 12. The interlayer insulating film 24 after etching covers the upper surface of the gate electrode 22.

Next, as shown in FIG. 5, a first metal layer 61 is grown on the wafer by sputtering. The first metal layer 61 is made of nickel or titanium. Here, the first metal layer 61 is formed so as to cover the upper surface 24a of the interlayer insulating film 24 and the upper surface 12a of the semiconductor substrate 12.

Next, the wafer is heated to react the first metal layer 61 with the semiconductor substrate 12. As a result, as shown in FIG. 6, the first metal layer 61 on the upper surface 12a of the semiconductor substrate 12 is silicided. Here, the entire first metal layer 61 on the upper surface 12a is silicided. The silicided first metal layer 61 on the upper surface 12a becomes the first electrode layer 31. If the first metal layer 61 is nickel, the first electrode layer 31 is nickel silicide, and if the first metal layer 61 is titanium, the first electrode layer 31 is titanium silicide. Furthermore, no silicide reaction occurs between the interlayer insulating film 24 (i.e., silicon oxide) and the first metal layer 61 (i.e., nickel or titanium). Therefore, the first metal layer 61 that is not silicided remains on the interlayer insulating film 24. The first metal layer 61 that is not silicided on the interlayer insulating film 24 becomes the second electrode layer 32.

If a thick first metal layer 61 is provided on the upper end of the side of the trench 14 before silicidation, the silicide layer 31 may grow thick on the side of the trench 14 as shown in FIG. 7 during the silicidation process, and the silicide layer 31 may grow in an overhanging shape on the upper part of the trench 14. For this reason, in the process of forming the first metal layer 61, the growth of the first metal layer 61 may be suppressed at the upper end of the side of the trench 14. By suppressing the growth of the first metal layer 61 at the upper end of the side of the trench 14, it is possible to prevent the silicide layer 31 from growing in an overhanging shape on the upper part of the trench 14.

After the silicidation process, as shown in FIG. 8, a barrier metal layer 34 is grown by sputtering on the upper surface of the first electrode layer 31 and the upper surface 32a of the second electrode layer 32. Since the unsilicidized second electrode layer 32 exists on the upper part of the interlayer insulating film 24, the height of the step between the upper surface of the second electrode layer 32 and the upper surface of the first electrode layer 31 is low. Therefore, the barrier metal layer 34 is prevented from being interrupted by the step between the upper surface of the second electrode layer 32 and the upper surface of the first electrode layer 31. That is, the barrier metal layer 34 is continuously distributed across the upper surface 32a of the second electrode layer 32 and the upper surface of the first electrode layer 31. Here, the barrier metal layer 34 is formed so that the thickness T1 of the laminated portion of the barrier metal layer 34 and the second electrode layer 32 is thicker than the height H1 of the step between the upper surface 12a of the semiconductor substrate 12 and the upper surface 24a of the interlayer insulating film 24. By forming the barrier metal layer 34 to such a thickness, it is possible to more reliably prevent the barrier metal layer 34 from being interrupted by steps. The barrier metal layer 34 can be formed continuously from the upper surface 32a of the second electrode layer 32 to the upper surface of the first electrode layer 31, so that the formation of the slit-shaped gap 160 shown in FIG. 10(d) can be prevented.

Next, a third electrode layer 33 made of aluminum silicide is grown on the barrier metal layer 34. This completes the upper electrode 30 as shown in FIG. 1. After that, a lower electrode 40 is formed on the lower surface 12b of the semiconductor substrate 12. Through the above steps, the semiconductor device 10 shown in FIG. 1 is manufactured.

In this manufacturing method, a slit-shaped gap is not formed in the upper part of the interlayer insulating film 24, so the third electrode layer 33 is not filled in the slit-shaped gap. This prevents high thermal stress from being applied to the interlayer insulating film 24 when the semiconductor device 10 is in use. This prevents deterioration of the interlayer insulating film 24.

In the above embodiment, as shown in FIG. 6, the entire first metal layer 61 on the upper surface 12a of the semiconductor substrate 12 is silicided in the silicidation process. However, as shown in FIG. 9, only the portion of the first metal layer 61 that contacts the upper surface 12a may be silicided. That is, the first metal layer 61 that is not silicided (hereinafter, referred to as the unreacted layer 61b) may remain on top of the silicide layer 61s obtained by silicidating the first metal layer 61. In this case, the first electrode layer 31 is composed of the silicide layer 61s and the unreacted layer 61b. In this case, the barrier metal layer 34 is formed on the unreacted layer 61b.

In the above-described embodiment, the first metal layer 61 is made of nickel or titanium. However, the first metal layer 61 may be made of any metal that can be silicided. For example, the first metal layer 61 may be made of tantalum, cobalt, molybdenum, platinum, etc.

In the above-described embodiment, the barrier metal layer 34 has a TiN layer. However, instead of the TiN layer, a TaN layer may be used as the barrier metal layer.

The third electrode layer 33 in the above embodiment is an example of the second metal layer.

Although the embodiments have been described in detail above, these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and variations of the specific examples given above. The technical elements described in this specification or drawings demonstrate technical utility either alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. Furthermore, the technology exemplified in this specification or drawings achieves multiple objectives simultaneously, and achieving one of these objectives is itself technically useful.

12: Semiconductor substrate, 14: Trench, 20: Gate insulating film, 22: Gate electrode, 24: Interlayer insulating film, 31: First electrode layer, 32: Second electrode layer, 33: Third electrode layer, 34: Barrier metal layer

Claims (4)

A method for manufacturing a semiconductor device, comprising:
preparing a wafer having a semiconductor substrate (12), a gate electrode (22), and an interlayer insulating film (24), the semiconductor substrate including silicon, a trench (14) provided in an upper surface of the semiconductor substrate, the gate electrode being disposed in the trench, the interlayer insulating film being disposed in the trench and covering an upper surface of the gate electrode, and the upper surface of the interlayer insulating film being located below the upper surface of the semiconductor substrate;
forming a first metal layer (61) on the top surface of the semiconductor substrate and on the top surface of the interlayer insulating film;
a step of reacting the first metal layer with the semiconductor substrate by heating the wafer to silicide the first metal layer, wherein the first metal layer is silicided at a portion of the first metal layer that contacts the upper surface of the semiconductor substrate and is not silicided at a portion of the first metal layer that contacts the upper surface of the interlayer insulating film;
forming a barrier metal layer (34) on the first metal layer on an upper portion of the upper surface of the semiconductor substrate and on an upper portion of the interlayer insulating film;
forming a second metal layer (33) on the barrier metal layer;
The manufacturing method comprising the steps of: The manufacturing method according to claim 1, wherein the thickness of the laminated portion of the first metal layer and the barrier metal layer in the upper part of the interlayer insulating film is greater than the height of the step between the upper surface of the interlayer insulating film and the upper surface of the semiconductor substrate. A semiconductor device comprising:
a semiconductor substrate (12) comprising silicon and having a trench (14) formed on an upper surface thereof;
a gate electrode (22) disposed within the trench;
an interlayer insulating film (24) disposed in the trench and covering an upper surface of the gate electrode, the upper surface of the interlayer insulating film being located lower than the upper surface of the semiconductor substrate;
a first electrode layer (31) covering the upper surface of the semiconductor substrate and having a silicide layer made of an alloy of a first metal and silicon in a portion in contact with the upper surface of the semiconductor substrate;
a second electrode layer (32) disposed in the trench, covering the upper surface of the interlayer insulating film, and made of the first metal, the second electrode layer having an upper surface located lower than an upper surface of the first electrode layer;
a barrier metal layer (34) covering the first electrode layer and the second electrode layer;
A third electrode layer (33) covering the barrier metal layer;
A semiconductor device having the above structure. The semiconductor device according to claim 3, wherein the thickness of the laminated portion of the second electrode layer and the barrier metal layer in the upper part of the interlayer insulating film is greater than the height of the step between the upper surface of the interlayer insulating film and the upper surface of the semiconductor substrate.

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