JP2024071834A - Wiring Board - Google Patents

Abstract

[Problem] To provide a wiring board capable of suppressing breaks and cracks in a via conductor even if the inner surface of a via hole has an inclination in the depth direction. [Solution] A wiring board 1 including a first insulating layer 2, a first conductor layer 3 formed on the first insulating layer, a second insulating layer 4 formed on the first insulating layer so as to cover the first conductor layer, a via hole 5 formed in the second insulating layer so as to expose a part of the first conductor layer, a seed layer 6 formed on an inner surface 5a of the via hole and a first surface 4a which is the opposite surface of the second insulating layer to the surface corresponding to the first insulating layer, a via conductor 7 formed on the seed layer on the inner surface of the via hole, and a second conductor layer 8 formed on the first surface, wherein the via conductor includes five or more layers of plating film. [Selected Figure] Figure 1

Description

The present invention relates to a wiring board having via conductors.

Patent Document 1 discloses an example of a wiring board having a via conductor. As shown in FIG. 3, the wiring board 51 disclosed in Patent Document 1 includes a first insulating layer 52, a first conductor layer 53 formed on the first insulating layer 52, a second insulating layer 54 formed to cover the first conductor layer 53, a via hole 55 formed in the second insulating layer 54 so as to expose a part of the first conductor layer 53, a via conductor 56 formed on the inner surface of the via hole 55, and a second conductor layer 57 formed on the upper surface of the first conductor layer 53 at the same time as the via conductor 56.

JP 2015-38909 A

In the wiring board 51 disclosed in Patent Document 1, the side of the via hole 55 is inclined in the depth direction. Therefore, if stress in the depth direction occurs in the via conductor 56 formed in a single layer, there is a risk that the via conductor 56 may break or crack.

The wiring board according to the present invention is a wiring board including a first insulating layer, a first conductor layer formed on the first insulating layer, a second insulating layer formed on the first insulating layer so as to cover the first conductor layer, a via hole formed in the second insulating layer so as to expose a part of the first conductor layer, a seed layer formed on the inner surface of the via hole and on a first surface which is the opposite surface of the second insulating layer corresponding to the first insulating layer, a via conductor formed on the seed layer on the inner surface of the via hole, and a second conductor layer formed on the first surface, and the via conductor includes five or more layers of plating film.

1 is a cross-sectional view illustrating a schematic diagram of an embodiment of a wiring board according to the present invention. 1A to 1E are cross-sectional views each showing a schematic diagram of each step for manufacturing an embodiment of a wiring board according to the present invention. FIG. 1 is a diagram showing an example of a conventional wiring board.

<About the wiring board of the present invention>
An embodiment of a wiring board according to the present invention will be described with reference to the drawings. In the example shown in Figures 1 to 3, the dimensions of each component, particularly the height dimension, are shown in dimensions different from the actual dimensions in order to make it easier to understand the features of the present invention.

Figure 1 is a cross-sectional view showing a schematic diagram of one embodiment of the wiring board according to the present invention. In Figure 1, the wiring board 1 according to the present invention includes a first insulating layer 2, a first conductor layer 3 formed on the first insulating layer 2, a second insulating layer 4 formed on the first insulating layer 2 so as to cover the first conductor layer 3, a via hole 5 formed in the second insulating layer 4 so as to expose a part of the first conductor layer 3, a seed layer 6 formed on the inner surface 5a of the via hole 5 and the first surface 4a which is the opposite surface of the second insulating layer 4 corresponding to the first insulating layer 2, a via conductor 7 formed on the seed layer 6 on the inner surface 5a of the via hole 5, and a second conductor layer 8 formed on the first surface 4a. The above configuration is the same as that of a conventional wiring board.

The wiring board 1 according to the present invention is characterized in that the via conductor 7 includes five or more layers of plating films (here, five layers of plating films 7-1 to 7-5) having approximately the same width. In the embodiment shown in FIG. 1, as a preferred embodiment, the second conductor layer 8 is formed of five layers of plating films 8-1 to 8-5 having approximately the same width, and the five layers of plating films 7-1 to 7-5 constituting the via conductor 7 are formed continuously with the five layers of plating films 8-1 to 8-5 constituting the second conductor layer 8. In addition, the plating film 7-6, which is the top layer of the via conductor 7, and the plating film 8-6, which is the top layer of the second conductor layer 8, are formed continuously, and the upper surfaces of the via conductor 7 and the second conductor layer 8 are flat. Furthermore, in the wiring board 1 according to the present invention, the second conductor layer 8 does not need to include five or more layers of plating films, and the effect can be achieved as long as the via conductor 7 is at least composed of five or more layers of plating films.

In addition, in the wiring board 1 according to the present invention, the plating films 7-1 to 7-6 are preferably electrolytic plating films. In addition, the plating films 7-1 to 7-6 preferably contain copper as a main component.

In the wiring board 1 according to the present invention, the via conductor 7 is formed of a plating film having five or more layers, so that even if the inner surface 5a of the via hole 5 has an inclination in the depth direction, breaks and cracks in the via conductor 7 can be suppressed. Here, the multilayer structure of the via conductor 7 is limited to five or more layers because if the multilayer structure has fewer than five layers, breaks and cracks in the via conductor 7 cannot be sufficiently suppressed.

<Method of Manufacturing a Wiring Board of the Present Invention>
2A to 2E are cross-sectional views each showing a schematic diagram of each step of manufacturing an embodiment of a wiring board according to the present invention. Hereinafter, an embodiment of a method for manufacturing a wiring board according to the present invention will be described with reference to FIGS.

First, as shown in FIG. 2(a), a first insulating layer 2 is prepared, and a first conductor layer 3 is formed on the first insulating layer 2 according to a predetermined circuit pattern. In many cases, multiple other conductor layers and insulating layers are alternately formed below the first insulating layer 2, but these are omitted in the figure. For the first insulating layer 2, a build-up insulating resin film containing an inorganic filler such as silica or alumina and an epoxy resin can be used.

Next, as shown in FIG. 2(b), a second insulating layer 4 is formed on the first insulating layer 2 so as to cover the first conductor layer 3. As with the first insulating layer 2, the second insulating layer 4 can be a build-up insulating resin film containing an inorganic filler such as silica or alumina and an epoxy resin.

Next, as shown in FIG. 2(c), a via hole 5 is formed in the second insulating layer 4 so that a portion of the first conductor layer 3 is exposed. The via hole 5 has an inner surface 5a that is inclined in the depth direction, and can be formed, for example, by using a mask with a carbon dioxide laser or a UV-YAG laser.

Next, as shown in FIG. 2(d), a seed layer 6 is formed on the inner surface 5a of the via hole 5 and on the first surface 4a, which is the surface of the second insulating layer 4 opposite to the surface corresponding to the first insulating layer 2. The seed layer 6 can be formed by electroless plating such as electroless copper plating or by sputtering.

2(e), a via conductor 7 is formed on the seed layer 6 on the inner surface 5a of the via hole 5, and a second conductor layer 8 is formed on the first surface 4a of the second insulating layer 4. In this embodiment, the five layers of plating films 7-1 to 7-5 and plating film 7-6, each of which has approximately the same width and which constitute the via conductor 7, are formed separately and continuously from the five layers of plating films 8-1 to 8-5 and plating film 8-6, each of which has approximately the same width and which constitute the second conductor layer 8.

Here, the five layers of plating films 7-1 to 7-5 and plating film 7-6 constituting the via conductor 7 and the five layers of plating films 8-1 to 8-5 and plating film 8-6 constituting the second conductor layer 8 are continuously formed by performing electrolytic plating treatment mainly composed of copper using, for example, a plating resist. The five layers of plating films 7-1 to 7-5 and plating film 7-6 having approximately the same width and the five layers of plating films 8-1 to 8-5 and plating film 8-6 having approximately the same width are formed, for example, by changing the current density during electrolytic plating treatment stepwise to higher or lower in five stages for each layer. Any other method can be used as long as it can form the five layers of plating films 7-1 to 7-5 and plating film 7-6 constituting the via conductor 7 and the five layers of plating films 8-1 to 8-5 and plating film 8-6 constituting the second conductor layer 8. Note that the second conductor layer 8 is not limited to a multilayer structure.

As described above, by way of example, the manufacturing method shown in Figures 2(a) to (e) can produce a wiring board 1 in which the via conductors 7 include five or more layers of plating film.

REFERENCE SIGNS LIST 1 wiring board 2 first insulating layer 3 first conductor layer 4 second insulating layer 4a first surface 5 via hole 5a inner surface 6 seed layer 7 via conductor 7-1 to 7-6 plating film 8 second conductor layer 8-1 to 8-6 plating film

Claims (5)

A first insulating layer;
a first conductor layer formed on the first insulating layer;
a second insulating layer formed on the first insulating layer so as to cover the first conductor layer;
a via hole formed in the second insulating layer so as to expose a portion of the first conductor layer;
a seed layer formed on an inner surface of the via hole and a first surface of the second insulating layer, the first surface being an opposite surface of the second insulating layer to a surface of the second insulating layer corresponding to the first insulating layer;
a via conductor formed on a seed layer on an inner surface of the via hole;
A wiring board comprising: a second conductor layer formed on the first surface,
The via conductor includes five or more layers of plating film. In the wiring board described in claim 1, the plating film is an electrolytic plating film. In the wiring board described in claim 1, the plating film contains copper as a main component. In the wiring board according to claim 1, the second conductor layer is composed of the seed layer formed on the first surface and five or more layers of plating film formed on the seed layer. In the wiring board described in claim 4, the seed layer of the second conductor layer and the seed layer on the inner surface of the via hole are formed continuously, and five or more layers of plating film of the second conductor layer and five or more layers of via conductor layers on the inner surface of the via hole are formed continuously.

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