JP2024066453A - OUTPUT BUFFER CIRCUIT, DISPLAY DRIVER AND DISPLAY DEVICE - Google Patents

Abstract

[Purpose] The present invention provides an output buffer circuit, a display driver, and a display device that have a function for adjusting current driving capability and can reduce the area when configured with multiple outputs. [Configuration] The present invention includes a first transistor that supplies a first high-voltage power supply voltage to an output terminal when it is turned on in response to the voltage of an input signal received at its gate, a second transistor that supplies a second high-voltage power supply voltage to the output terminal when it is turned on in response to the voltage of the input signal received at its gate, an output control unit that changes the gate voltage of one of the first and second transistors that is in the on state when the voltage of the input signal changes, thereby transitioning the transistor to the off state, and changes the gate voltage of the transistor in the off state at a rate of change based on the current value controlled by a bias voltage, thereby bringing the transistor to the on state, and a bias modulation unit that sets the voltage value of the bias voltage to a specified voltage value. [Selected Figure] Figure 1

Description

The present invention relates to an output buffer circuit that drives a load, and a display driver and display device that include this output buffer circuit.

A semiconductor integrated device that drives an externally connected load is provided with an output buffer that outputs a drive signal for driving the load. The output buffer includes a P-channel MOS (metal oxide semiconductor) transistor and an N-channel MOS transistor, each of which receives a binary (logical level 0, 1) input signal at its respective gate terminal and has its respective drain terminals connected to an output node. With this configuration, the output buffer outputs a binary drive signal from the output node by setting both of the above-mentioned transistors to a complementary on state by a binary input signal.

However, when the load to be driven is a large-capacity load that has a relatively large capacity, such as an LCD panel or an organic EL display panel, and requires high-voltage pulse driving, a high-drive output buffer is used as the output buffer.

In such a high-drive output buffer, the timing at which one of the two transistors switches from on to off is delayed from the timing at which the other transistor switches from off to on, causing both transistors to temporarily be on at the same time. This causes a relatively large through-current to flow between the two transistors, resulting in problems of EMI (electro magnetic interference) and increased power consumption due to the through-current. There is also the problem of EMI occurring due to current fluctuations accompanying the charging and discharging current when driving a load.

In order to solve this problem, an output buffer circuit has been proposed in which a pre-buffer section is provided in front of the buffer section consisting of the above-mentioned P-channel MOS transistors and N-channel MOS transistors (see Patent Document 1).

The pre-buffer section included in the output buffer circuit described in Patent Document 1 has a first inverter that receives an input signal and supplies an inverted signal to the gate of the P-channel MOS transistor described above, and a second inverter that receives an input signal and supplies an inverted signal to the gate of the N-channel MOS transistor described above. At this time, a current source is connected to the source of the N-channel MOS transistor of the first inverter, and a current source is connected to the source of the P-channel MOS transistor of the second inverter. In the output buffer circuit described in Patent Document 1, the currents flowing from each of the current sources of the pre-buffer section are individually adjusted to make the transition from the on state to the off state of both transistors of the buffer section faster than the transition from the off state to the on state. As a result, in the output buffer circuit, a state in which both transistors of the buffer section are simultaneously on is avoided, preventing a through current and slowing down the voltage change of the output signal.

Japanese Patent Application Laid-Open No. 6-152374

Incidentally, in the output buffer circuit described in Patent Document 1, the more the current flowing from the current source of the pre-buffer section is reduced, the longer the time it takes for both transistors in the buffer section to transition from the off state to the on state.

This makes the voltage change of the output signal more gradual, reliably suppressing shoot-through current and reducing EMI. However, this reduces the current driving capability of the output buffer circuit and significantly dulls the pulse voltage waveform of the output signal, making it impossible to drive a load at high speed.

As such, there is a trade-off between EMI reduction and current drive capacity, and the optimal adjustment value differs for each load to be driven. Therefore, there is a demand for an output buffer circuit with a built-in adjustment circuit that adjusts the current drive capacity.

In addition, in the case of a high-drive output buffer circuit, the current drive capacity adjustment circuit itself must be constructed using relatively large transistors that are compatible with high voltages. Therefore, particularly in a multi-output configuration that includes multiple output buffer circuits as described above to drive multiple loads, there is a problem in that the circuit area increases in proportion to the number of output buffer circuits.

The present invention aims to provide an output buffer circuit that has a current drive capacity adjustment function and can reduce area when configured with multiple outputs, as well as a display driver and display device that include this output buffer circuit.

The output buffer circuit according to the present invention is an output buffer circuit that outputs an output signal obtained by amplifying an input signal from an output terminal, and includes a first transistor of a first conductivity type that supplies a first high-voltage power supply voltage to the output terminal when the first transistor is turned on in response to the voltage of the input signal received at its gate, a second transistor of a second conductivity type that supplies a second high-voltage power supply voltage lower than the first high-voltage power supply voltage to the output terminal when the first transistor is turned on in response to the voltage of the input signal received at its gate, a bias unit that generates a bias voltage, and a circuit that changes the gate voltage of one of the first transistor and the second transistor that is turned on at a rate of change corresponding to the voltage change of the input signal when the voltage of the input signal changes. and an output control unit that transitions the transistor in the on state to the off state and changes the gate voltage of the transistor in the off state among the first transistor and the second transistor at a rate of change based on the current value controlled by the bias voltage to bring the transistor in the off state to the on state, and a drive setting unit that generates a setting signal for specifying the voltage value of the bias voltage and setting it to that voltage value, and the bias unit operates by receiving a first low-voltage power supply voltage having a voltage value equal to or lower than the first high-voltage power supply voltage and a second low-voltage power supply voltage having a voltage value equal to or higher than the second high-voltage power supply voltage, and includes a bias modulation unit that sets the voltage value of the bias voltage to a voltage value based on the setting signal.

The output buffer circuit according to the present invention is an output buffer circuit that outputs first to Mth output signals obtained by amplifying first to Mth input signals (M is an integer of 2 or more), and includes a bias section that generates a bias voltage, a drive setting section that generates a setting signal for specifying a voltage value of the bias voltage and setting the voltage value, and first to Mth buffer sections that individually receive the first to Mth input signals and output the first to Mth output signals via respective output terminals, and each of the first to Mth buffer sections includes a first transistor of a first conductivity type that supplies a first high-voltage power supply voltage to its output terminal when it is turned on in response to the voltage of the input signal received at its gate, a second transistor of a second conductivity type that supplies a second high-voltage power supply voltage lower than the first high-voltage power supply voltage to its output terminal when it is turned on in response to the voltage of the input signal received at its gate, and a second transistor of a second conductivity type that supplies a second high-voltage power supply voltage lower than the first high-voltage power supply voltage to its output terminal when it is turned on in response to the voltage of the input signal received at its gate, and a second transistor that is turned on when the voltage of the input signal changes, and a second transistor that is turned on when the voltage of the input signal changes. An output control unit that changes the gate voltage of the transistor at a rate of change corresponding to the voltage change of the input signal to transition the transistor in the on state to the off state, and changes the gate voltage of the transistor in the off state among the first transistor and the second transistor at a rate of change based on the current value controlled by the bias voltage to bring the transistor in the off state to the on state, and the bias unit is provided in common with each of the first to Mth buffer units, and operates by receiving a first low-voltage power supply voltage having a voltage value less than the first high-voltage power supply voltage or less than the first high-voltage power supply voltage, and a second low-voltage power supply voltage having a voltage value higher than the second high-voltage power supply voltage or greater than the second high-voltage power supply voltage, and includes a bias modulation unit that sets the voltage value of the bias voltage to a voltage value based on the setting signal, and supplies the bias voltage having a voltage value set by the bias modulation unit to each of the first to Mth buffer units.

The display driver according to the present invention is a display driver that drives a display panel including a plurality of scanning lines arranged along the horizontal direction of a screen and a plurality of data lines arranged crossing the plurality of scanning lines in response to a video signal, and has a data driver that generates a plurality of drive signals based on the video signal and supplies them to the plurality of data lines, and a scan driver that drives the plurality of scanning lines at timings according to a plurality of scan timing signals, the data driver including a scan control signal output circuit that outputs the plurality of scan timing signals, and the scan control signal output circuit is composed of the output buffer circuit with the above-mentioned multi-output configuration.

The display driver according to the present invention is a display driver that drives a passive matrix display panel including a plurality of scanning lines arranged along the horizontal direction of the screen and a plurality of data lines arranged crossing the plurality of scanning lines in response to a video signal, and includes a data driver including a first output buffer unit that outputs a plurality of driving pulse signals having a pulse width corresponding to the luminance level of each pixel shown by the video signal to the plurality of data lines, and a scan driver including a second output buffer unit that outputs a plurality of scanning pulse signals to the plurality of scanning lines, and the first output buffer unit and the second output buffer unit are made of the output buffer circuit having the above-mentioned multi-output configuration.

The display device according to the present invention is a display device having a display panel including a plurality of scanning lines arranged along the horizontal direction of the screen and a plurality of data lines arranged crossing the plurality of scanning lines, and a display driver that drives the display panel in response to a video signal, the display driver having a scanning driver that drives the plurality of scanning lines at a timing corresponding to a plurality of scanning timing signals, and a data driver including a scanning control signal output circuit that generates a plurality of driving signals based on the video signal, supplies them to the plurality of data lines, and outputs the plurality of scanning timing signals, the scanning control signal output circuit being composed of the output buffer circuit having the above-mentioned multi-output configuration.

In the output buffer circuit according to the present invention, the output control unit controls the gate voltages of the first and second transistors of the output stage based on the input signal, thereby setting the first and second transistors to the on and off states, respectively, in a complementary manner. At this time, the output control unit controls the first and second transistors as follows when the voltage of the input signal changes. That is, the gate voltage of the transistor in the on state among the first and second transistors is changed at a rate of change according to the voltage change of the input signal, thereby transitioning the transistor to the off state. Furthermore, the gate voltage of the transistor in the off state among the first and second transistors is changed at a rate of change based on the current value controlled by the bias voltage set by the setting signal, thereby adjusting the current driving capacity, thereby bringing the transistor to the on state. The bias unit that generates the bias voltage to be supplied to the output buffer unit includes a bias modulation unit that operates at a low power supply voltage equal to or lower than the power supply voltage used in the output control unit and the output stage, and variably sets the voltage value of the bias voltage in the bias modulation unit.

This makes it possible for the output buffer circuit of the present invention to avoid the first and second transistors of the output stage being turned on simultaneously when the voltage of the input signal changes. As a result, instantaneous shoot-through current is prevented from flowing between the first and second transistors, and the generation of EMI associated with this shoot-through current is suppressed. In addition, since the bias modulation section that generates the bias voltage that sets the current drive capacity of the output buffer circuit of the present invention can be configured with a low-voltage circuit, the adjustment range of the bias voltage can be increased with a small area-saving configuration with little area increase. This reduces EMI caused by fluctuations in charge/discharge current when driving a load, and enables optimal adjustment with minimal distortion of the voltage waveform of the output signal.

In addition, when multiple buffer sections each consisting of the above-mentioned output stage and output control section are provided to provide an output buffer circuit with multiple outputs, the bias section that generates the bias voltage responsible for adjusting the above-mentioned current drive capacity can be configured as a single system shared by multiple buffer sections. Therefore, even when an output buffer circuit having multiple buffer sections is provided, it is possible to reduce the area of the entire device.

Therefore, according to the present invention, it is possible to provide an output buffer circuit that has a function for adjusting the current driving capacity to optimize the reduction of distortion in the voltage waveform of the output signal and the reduction of EMI, and that can reduce the area when multiple outputs are provided.

1 is a circuit diagram showing a configuration of an output buffer circuit 100 as an example of an output buffer circuit according to the present invention. 3 is a circuit diagram showing a configuration of a bias unit 30A1 as an example of the bias unit 30A. FIG. 4 is a circuit diagram showing a configuration of a variable current source 41A1 as an example of a variable current source 41A. FIG. 4 is a circuit diagram showing a configuration of a variable current source 42A1 as an example of a variable current source 42A. FIG. FIG. 1 is a circuit diagram showing a configuration of an output buffer circuit 100A as a modified example of the output buffer circuit 100. 1 is a circuit diagram showing a configuration of a bias unit 30B1 as an example of the configuration of the bias unit 30B. FIG. FIG. 13 is a circuit diagram showing a configuration of a bias unit 30C which is a modified example of the bias unit 30B. 2 is a circuit diagram showing an example of the internal configuration of each of amplifiers 71C_P and 71C_N. FIG. 11 is a circuit diagram showing a configuration of an output buffer circuit 100B as a modification of the output buffer circuit 100. FIG. 13 is a circuit diagram showing a configuration of an output buffer circuit 100C as still another modification of the output buffer circuit 100. 11 is a time chart showing waveforms of voltages V1 and V2 generated at nodes n1 and n2, respectively, of a buffer unit 10C and an output signal So when high-voltage input signals Si1 and Si2 are received. 1 is a block diagram showing a configuration of a multi-output buffer device 200 having M output channels. 1 is a block diagram showing a configuration of a multi-output buffer device 200A having M output channels. FIG. 1 is a block diagram showing a schematic configuration of an active matrix display device 300. FIG. 1 is a block diagram showing a schematic configuration of a passive matrix display device 300A. 1 is a block diagram showing a configuration of a multi-output buffer device 200B having buffer units 10Ax and 10Ay for driving two loads X and Y, which require different current driving capabilities, respectively. 10A and 10B are diagrams illustrating a setting operation of the current driving capability of the buffer unit 10Ay. 10A and 10B are diagrams illustrating a setting operation of the current driving capability of the buffer unit 10Ay. FIG. 13 is a block diagram showing a configuration of a multi-output buffer device 200C as yet another example of a multi-output buffer device. FIG. 17 is a block diagram showing a schematic configuration of a time-division driving type display device 600 employing the multi-output buffer devices 200B and 200C shown in FIGS. 14 and 16. 6 is a diagram showing an example of the arrangement of a drive setting section 20A and control buffer sections BU1 and BU2 in a data driver 120B of the display device 600. FIG.

Figure 1 is a circuit diagram showing the configuration of an output buffer circuit 100 as an example of an output buffer circuit according to the present invention.

As shown in FIG. 1, the output buffer circuit 100 includes a buffer section 10A, a drive setting section 20, a bias section 30A, and a level shifter 90.

The level shifter 90 receives an input signal Si0L, which is a binary (logical level 0 or 1) whose voltage changes with a low voltage amplitude (power supply voltage VSS to VDD), via an input terminal TI. The level shifter 90 converts the input signal Si0L into a high voltage input signal Si0, whose amplitude is level-shifted to a high voltage range (power supply voltage VGL to VGH). The power supply voltages VSS, VDD, VGL, and VGH are expressed as follows:
VGH>VDD>VSS≧VGL
Or,
VGH≧VDD>VSS>VGL
There is a size relationship between them.

Then, the level shifter 90 supplies this high-voltage input signal Si0 to the buffer unit 10A via node Ti0.

The buffer section 10A is composed of high-voltage elements, and is composed of the following high-voltage elements that operate in the high-voltage power supply voltage range (VGL to VGH).

That is, the buffer unit 10A includes an output stage consisting of a P-channel transistor 11 and an N-channel transistor 12, and an output control unit 19A that controls the gate voltages of these transistors 11 and 12.

A power supply voltage VGH is applied to the source of transistor 11, and a power supply voltage VGL is applied to the source of transistor 12. The drains of transistors 11 and 12 are connected to an output terminal TO, and a binary signal (logic level 0 or 1) having the voltage generated at the output terminal TO is output as an output signal So.

The output control unit 19A includes inverters 13 and 14, an N-channel transistor 15, and a P-channel transistor 16.

The inverter 13 is composed of an N-channel transistor 13n and a P-channel transistor 13p, with their gates connected together to form the input terminal of the inverter 13 and connected to node Ti0, and their drains connected together to form the output terminal of the inverter 13 and connected to node n1. The source of transistor 13p is connected to the positive power supply terminal and receives the power supply voltage VGH, and the source of transistor 13n is connected to the negative power supply terminal via transistor 15 and receives the power supply voltage VGL. In other words, the inverter 13 supplies the voltage of a signal obtained by inverting the phase of the high-voltage input signal Si0 received via node Ti0 to the gate of transistor 11 via node n1.

The inverter 14 is composed of an N-channel transistor 14n and a P-channel transistor 14p, with their gates connected together to form the input terminal of the inverter 14 and connected to node Ti0, and their drains connected together to form the output terminal of the inverter 14 and connected to node n2. The source of transistor 14p is connected to the positive power supply terminal via transistor 16 and receives the power supply voltage VGH, and the source of transistor 14n is connected to the negative power supply terminal and receives the power supply voltage VGL. In other words, the inverter 14 supplies the voltage of a signal obtained by inverting the phase of the high-voltage input signal Si0 received via node Ti0 to the gate of transistor 12 via node n2.

Transistor 15 has its drain connected to the negative power supply terminal of inverter 13, receives power supply voltage VGL at its source, and receives bias voltage VBN supplied from bias unit 30A via node n3 at its gate.

Transistor 16 has its drain connected to the positive power supply terminal of inverter 14, receives power supply voltage VGH at its source, and receives bias voltage VBP supplied from bias unit 30A via node n4 at its gate.

The drive setting unit 20 has a memory unit (not shown) that indicates the voltage values of the bias voltages VBN and VBP and stores setting data for setting these voltage values. The drive setting unit 20 generates a setting signal Cs indicating the voltage value indicated in the setting data stored in the memory unit and supplies this to the bias unit 30A. The drive setting unit 20 may also receive setting data supplied from the outside, generate a setting signal Cs indicating the voltage value indicated in the setting data, and supply this to the bias unit 30A.

The bias unit 30A includes a bias modulation unit 40A, a voltage protection unit 50A, and a current-voltage conversion unit 60A.

The bias modulation unit 40A receives the power supply voltages VDD and VSS, and operates in the low power supply voltage range (VSS to VDD) within the high power supply voltage range (VGL to VGH) in the buffer unit 10A. The bias modulation unit 40A generates a pair of currents I1A and I2A having current values corresponding to the setting signal Cs, and supplies them to the withstand voltage protection unit 50A.

The withstand voltage protection unit 50A relays the currents I1A and I2A to the current-voltage conversion unit 60A, while eliminating the effects of the high-voltage power supply voltages VGH and VGL, and controls the voltage applied to the output of the bias modulation unit 40A so that it falls within the low-voltage power supply voltage range (VSS to VDD).

The current-voltage conversion unit 60A receives the power supply voltages VGH and VGL, and converts the currents I1A and I2A into bias voltages VBN and VBP, respectively, having voltage values within the high-voltage power supply voltage range (VGL to VGH). The current-voltage conversion unit 60A then supplies the bias voltage VBN to the gate of transistor 15 via node n3, and supplies the bias voltage VBP to the gate of transistor 16 via node n4.

The operation of the output buffer circuit 100 shown in FIG. 1 is described below.

First, when an input signal Si0L having a power supply voltage VSS corresponding to logic level 0 is received, the level shifter 90 generates a high-voltage input signal Si0 having a logic level 0 by level-shifting the voltage (VSS) of the input signal Si0L to the power supply voltage VGL, and supplies it to the inverters 13 and 14. As a result, the inverter 13 supplies a signal having a power supply voltage VGH corresponding to logic level 1 to the gate of the transistor 11, and the inverter 14 supplies a signal having a power supply voltage VGH corresponding to logic level 1 to the gate of the transistor 12. Therefore, at this time, the transistor 11 is in an off state, the transistor 12 is in an on state, and an output signal So having a logic level 0 and a power supply voltage VGL is output via the output terminal TO.

Next, when an input signal Si0L having a power supply voltage VDD corresponding to logic level 1 is received, the level shifter 90 generates a high-voltage input signal Si0 of logic level 1 by level-shifting the voltage (VDD) of the input signal Si0L to the power supply voltage VGH, and supplies it to the inverters 13 and 14. As a result, the inverter 13 supplies a signal having a power supply voltage VGL corresponding to logic level 0 to the gate of the transistor 11, and the inverter 14 supplies a signal having a power supply voltage VGL corresponding to logic level 0 to the gate of the transistor 12. Therefore, at this time, the transistor 11 is in an on state, the transistor 12 is in an off state, and an output signal So of logic level 1 having a power supply voltage VGH is output via the output terminal TO.

In this way, in the output buffer circuit 100, the output control unit 19A controls the gate voltages of the transistors 11 and 12 in the output stage based on the high-voltage input signal Si0, thereby setting these transistors 11 and 12 to the on or off state in a complementary manner. At this time, the output control unit 19A controls the transistors 11 and 12 in the output stage as follows when the voltage of the high-voltage input signal Si0 changes. That is, the gate voltage of the transistor 11 or 12 that is in the on state is changed at a rate of change corresponding to the voltage change of the input signal, thereby transitioning this transistor to the off state. Furthermore, the gate voltage of the transistor 11 or 12 that is in the off state is changed at a rate of change based on the current value controlled by the bias voltage (VBN, VBP) having the voltage value indicated by the setting signal Cs, thereby adjusting the current driving capacity, thereby bringing this transistor to the on state.

Specifically, when the high-voltage input signal Si0 changes from the power supply voltage VGL of logic level 0 to the power supply voltage VGH of logic level 1, the transistor 14n of the inverter 14 changes from the OFF state to the ON state by a switching operation corresponding to the voltage change of the high-voltage input signal Si0, and the gate of the transistor 12 changes quickly from the power supply voltage VGH to the power supply voltage VGL, so that the transistor 12 changes quickly from the ON state to the OFF state. Also, at this time, the transistor 13n of the inverter 13 becomes ON, and the gate of the transistor 11 changes from the power supply voltage VGH to the power supply voltage VGL at a rate of change corresponding to the current value controlled by the bias voltage VBN, and the transistor 11 changes from the OFF state to the ON state at a rate of change corresponding to that. On the other hand, when the high-voltage input signal Si0 changes from the power supply voltage VGH of logic level 1 to the power supply voltage VGL of logic level 0, the transistor 13p of the inverter 13 changes from the OFF state to the ON state by a switching operation according to the voltage change of the high-voltage input signal Si0, and the gate of the transistor 11 changes quickly from the power supply voltage VGL to the power supply voltage VGH, so that the transistor 11 changes quickly from the ON state to the OFF state. Also, at this time, the transistor 14p of the inverter 14 becomes in the ON state, and the gate of the transistor 12 changes from the power supply voltage VGL to the power supply voltage VGH at a rate of change according to the current value controlled by the bias voltage VBP, and the transistor 12 changes from the OFF state to the ON state at a rate of change according to that.

This makes it possible to prevent transistors 11 and 12 in the output stage from turning on simultaneously when the voltage of the input signal changes. As a result, instantaneous shoot-through current is prevented from flowing between transistors 11 and 12, suppressing the generation of EMI and increased power consumption associated with the shoot-through current. In addition, by controlling the rate of change of the voltage of the output signal So, the rate of change of the charge/discharge current when the load is driven can also be controlled, making it possible to reduce EMI.

In addition, when the output buffer circuit 100 is made multi-output by providing a plurality of the above-mentioned output stages (11, 12) and output control units 19A, the bias unit 30A that generates the bias voltage responsible for adjusting the above-mentioned current driving capacity can be configured with only one system shared for the multi-output. Furthermore, the bias modulation unit 40A included in the bias unit 30A that sets the voltage value of the bias voltage (VBN, VBP) to an arbitrary magnitude can be configured with low-voltage elements that operate with a power supply voltage (VDD, VSS) lower than the power supply voltage (VGH, VGL) used in the output stages (11, 12) and output control unit 19A, making it possible to reduce the number of high-voltage elements and save area. The bias modulation unit 40A configured with low-voltage elements can increase the number of adjustment steps of the bias voltage while suppressing an increase in the circuit area.

Therefore, the output buffer circuit 100 according to the present invention is provided with a means for adjusting the current drive capacity by the bias voltages VBN and VBP, which makes it possible to prevent EMI and increased power consumption due to through current while maintaining the current drive capacity required for load drive (output waveform with less distortion), and also to reduce EMI caused by charge/discharge currents associated with load drive, and also to reduce the area when multiple outputs are used.

Note that, in FIG. 1, the configuration of output buffer circuit 100 is shown as an example of the configuration of the output buffer circuit, but the configuration is not limited to this.

In short, the output buffer circuit according to the present invention may be one that includes a first and second transistor that serve as an output stage, a bias section, an output control section, and a drive setting section, as described below.

The first transistor (11) supplies a first high-voltage power supply voltage (VGH) to the output terminal (TO) when it is turned on in response to the voltage of the input signal received at its gate. The second transistor (12) supplies a second high-voltage power supply voltage (VGL) to the output terminal (TO) when it is turned on in response to the voltage of the input signal received at its gate. The bias unit (30A) generates bias voltages (VBN, VBP). When the voltage of the input signal (Si0) changes, the output control unit (19A) changes the gate voltage of the transistor in the on state among the first and second transistors at a rate of change corresponding to the voltage change of the input signal, thereby transitioning the transistor in the on state to an off state. Furthermore, the output control unit changes the gate voltage of the transistor in the off state among the first and second transistors at a rate of change based on the current value controlled by the bias voltages (VBN, VBP), thereby bringing the transistor in the off state to an on state. The drive setting unit generates a setting signal (Cs) to specify the voltage value of the bias voltage and set it to that voltage value.

The bias section (30A) includes the following bias modulation section:

The bias modulation unit (40A) operates by receiving a first low-voltage power supply voltage (VDD) having a voltage value less than or equal to a first high-voltage power supply voltage (VGH) and a second low-voltage power supply voltage (VSS) having a voltage value greater than or equal to a second high-voltage power supply voltage (VGL), and sets the voltage values of the bias voltages (VBN, VBP) to voltage values based on a setting signal (Cs).

Figure 2 is a circuit diagram showing the configuration of bias unit 30A1 as an example of bias unit 30A shown in Figure 1.

The bias unit 30A1 includes a bias modulation unit 40A1, a withstand voltage protection unit 50A1, and a current-voltage conversion unit 60A1, and generates bias voltages VBN and VBP having voltage values based on a setting signal Cs within the high-voltage power supply voltage range (VGL to VGH).

The bias modulation unit 40A1 is composed of low-voltage elements, and includes variable current sources 41A and 42A that each operate within the low-voltage power supply voltage range (VSS to VDD) and generate currents I1A and I2A having current values based on the setting signal Cs supplied from the drive setting unit 20. The variable current source 41A receives the power supply voltage VDD and outputs the current I1A, and the variable current source 42A receives the power supply voltage VSS and outputs the current I2A.

The voltage protection unit 50A1 includes a P-channel transistor 51A and an N-channel transistor 52A, which are high-voltage elements. The power supply voltage VSS is applied to the gate of the transistor 51A, and the current I1A generated by the variable current source 41A is received at the source of the transistor 51A. The power supply voltage VDD is applied to the gate of the transistor 52A, and the variable current source 42A is connected to the drain of the transistor 52A.

The current-voltage conversion unit 60A1 includes high-voltage elements, N-channel transistor 61A and P-channel transistor 62A. Transistor 61A has its gate and drain connected to the drain of transistor 51A, and a power supply voltage VGL is applied to its source. Transistor 62A has its gate and drain connected to the drain of transistor 52A, and a power supply voltage VGH is applied to its source.

Here, the voltage generated at the gate and drain of transistor 61A is output as bias voltage VBN via node n3, and the voltage generated at the gate and drain of transistor 62A is output as bias voltage VBP via node n4.

With the configuration shown in FIG. 2, the currents I1A and I2A output from the bias modulation unit 40A1 are supplied to the current-voltage conversion unit 60A1 via the transistors 51A and 52A of the voltage protection unit 50A1, respectively.

Transistor 51A of voltage protection unit 50A1 receives power supply voltage VSS at its gate, and receives current I1A generated by variable current source 41A based on power supply voltage VDD at its source, and outputs this from its drain. As a result, the source voltage of transistor 51A is held at a voltage higher than gate applied voltage VSS by the gate-source voltage difference, so transistor 51A clamps the voltage applied to variable current source 41A within the low-voltage power supply voltage range (VSS to VDD) while passing the above-mentioned current I1A to transistor 61A of current-voltage conversion unit 60A1. Note that the voltage applied to the gate of transistor 51A may be changed to a voltage deviated from power supply voltage VSS as long as variable current source 41A does not deviate from the low-voltage power supply voltage range (VSS to VDD).

The transistor 52A of the voltage protection unit 50A1 receives the power supply voltage VDD at its gate, and receives the current I2A generated by the variable current source 42A based on the power supply voltage VSS at its source, and outputs this from its drain. As a result, the source voltage of the transistor 52A is held at a voltage lower than the gate applied voltage VDD by the gate-source voltage difference, so the transistor 52A clamps the voltage applied to the variable current source 41A within the low-voltage power supply voltage range (VSS to VDD) while passing the above-mentioned current I2A to the transistor 62A of the current-voltage conversion unit 60A1. The voltage applied to the gate of the transistor 52A may be changed to a voltage deviated from the power supply voltage VDD as long as the variable current source 42A does not deviate from the low-voltage power supply voltage range (VSS to VDD).

In the current-voltage conversion unit 60A1, a diode-connected transistor 61A as shown in FIG. 2 receives a current I1A at its drain and gate, converts the current I1A into a voltage, and supplies a bias voltage VBN representing the voltage to the buffer unit 10A. Furthermore, in the current-voltage conversion unit 60A1, a diode-connected transistor 62A as shown in FIG. 2 receives a current I2A at its drain and gate, converts the current I2A into a voltage, and supplies a bias voltage VBP representing the voltage to the buffer unit 10A.

As shown in Figures 1 and 2, a first current mirror circuit may be formed by transistor 61A included in bias unit 30A1 and transistor 15 included in buffer unit 10A, and a second current mirror circuit may be formed by transistor 62A included in bias unit 30A1 and transistor 16 included in buffer unit 10A.

In addition, in the configuration shown in FIG. 2, each of transistors 61A and 62A may be configured with multiple diode-connected transistors stacked vertically, thereby increasing the current flowing through transistors 15 and 16 of buffer section 10A.

In addition, in the voltage protection unit 50A1 shown in FIG. 2, when the power supply voltages VGL and VSS are equal, the transistor 51A can be omitted, and when the power supply voltages VGH and VDD are equal, the transistor 52A can be omitted.

Figure 3A is a circuit diagram showing the configuration of variable current source 41A1 as an example of variable current source 41A shown in Figure 2.

The variable current source 41A1 is composed of the following low-voltage elements that operate within the low-voltage power supply voltage range (VSS to VDD):

That is, the variable current source 41A1 includes a plurality of constant current sources 43A, 43A_1 to 43A_k (k is an integer of 2 or more) connected in parallel between a power supply terminal to which the power supply voltage VDD is applied and a node n41A connected to the source of the transistor 51A. Furthermore, the variable current source 41A1 includes switches 44A_1 to 44A_k connected in series with each of the constant current sources 43A_1 to 43A_k, and the current supply or current cutoff to the node n41A is controlled by digital setting signals Csp1 to Cspk included in the setting signal Cs.

With the configuration shown in FIG. 3A, the variable current source 41A1 generates the current I1A as the total current of the constant current sources 43A, 43A_1 to 43A_k that are in a state where they can supply current according to the digital setting signals Ccp1 to Cspk. In other words, the variable current source 41A1 can variably set the current value of the current I1A according to the digital setting signals Ccp1 to Cspk.

Figure 3B is a circuit diagram showing the configuration of variable current source 42A1 as an example of variable current source 42A shown in Figure 2.

The variable current source 42A1 is composed of the following low-voltage elements that operate within the low-voltage power supply voltage range (VSS to VDD):

That is, the variable current source 42A1 includes a plurality of constant current sources 45A, 45A_1 to 45A_k (k is an integer of 2 or more) connected in parallel between a power supply terminal to which the power supply voltage VSS is applied and a node n42A connected to the source of the transistor 52A. The variable current source 42A1 further includes switches 46A_1 to 46A_k connected in series with each of the constant current sources 45A_1 to 45A_k, and the current supply or current cutoff to the node n42A is controlled by digital setting signals Csn1 to Csnk included in the setting signal Cs.

With the configuration shown in FIG. 3B, the variable current source 42A1 generates the current I2A as the total current of the constant current sources 45A, 45A_1 to 45A_k that are in a state where they can supply current according to the digital setting signals Ccn1 to Csnk. In other words, the variable current source 42A1 can variably set the current value of the current I2A according to the digital setting signals Ccn1 to Csnk.

Figure 4 is a circuit diagram showing the configuration of an output buffer circuit 100A, which is a modified example of the output buffer circuit 100 shown in Figure 1.

The configuration shown in FIG. 4 is the same as that shown in FIG. 1, except that bias unit 30A shown in FIG. 1 has been changed to bias unit 30B. Therefore, the configuration of only bias unit 30B will be described in detail below.

The bias unit 30B includes a bias modulation unit 40B and a voltage protection unit 50B, and supplies bias voltages VBN and VBP having voltage values corresponding to the setting signal Cs to the gates of transistors 15 and 16 of the buffer unit 10A via nodes n3 and n4.

The bias modulation unit 40B receives the power supply voltages VDD and VSS, and operates in the low power supply voltage range (VSS to VDD) within the high power supply voltage range (VGL to VGH) in the buffer unit 10A. The bias modulation unit 40B generates a pair of voltages V1B and V2B having voltage values corresponding to the setting signal Cs, and supplies them to the withstand voltage protection unit 50B.

The withstand voltage protection unit 50B uses these voltages V1B and V2B as bias voltages VBN and VBP, relaying them to the buffer unit 10A via nodes n3 and n4, respectively, while controlling the voltages V1B and V2B so that they do not deviate from the low power supply voltage range (VSS to VDD).

Figure 5 is a circuit diagram showing the configuration of bias unit 30B1 as an example of the configuration of bias unit 30B shown in Figure 4.

As shown in FIG. 5, the bias unit 30B1 includes a bias modulation unit 40B1 and a voltage protection unit 50B1, and outputs bias voltages VBN and VBP within the low power supply voltage range (VSS to VDD) for the high power supply voltage range (VGL to VGH) in which the buffer unit 10A operates.

The bias modulation unit 40B1 includes a reference voltage generation unit 41B and a D/A conversion unit 42B.

The reference voltage generating unit 41B is composed of, for example, a ladder resistor that generates multiple reference voltages by dividing the voltage between the power supply voltages VDD and VSS, and supplies the generated multiple reference voltages to the D/A conversion unit 42B.

The D/A conversion unit 42B selects two voltages from among a plurality of reference voltages based on the setting signal Cs from the drive setting unit 20, and supplies them as voltages V1B and V2B to the voltage protection unit 50B1 via nodes n3 and n4, respectively.

The voltage protection unit 50B1 includes N-channel transistors 51N and 52N, and P-channel transistors 51P and 52P.

As shown in FIG. 5, the drains of transistors 51P and 52P are commonly supplied with the power supply voltage VSS, and a predetermined control voltage Vclp is commonly applied to their gates. The source of transistor 51P is connected to node n3, which receives the above-mentioned voltage V1B, and the source of transistor 52P is connected to node n4, which receives the above-mentioned voltage V2B.

The above-mentioned control voltage Vclp is expressed as follows:
Vclp<VDD-|Vtp|
Vtp: Set to the threshold voltage of transistors 51P and 52P.

With this configuration, when the voltage of node n3 (n4) becomes higher than a predetermined voltage (Vclp + |Vtp|) near the power supply voltage VDD controlled by the control voltage Vclp, transistor 51P (52P) turns on, preventing the voltage of node n3 (n4) from exceeding the power supply voltage VDD.

As shown in FIG. 5, the drains of transistors 51N and 52N are commonly supplied with a power supply voltage VDD, and a predetermined control voltage Vcln is commonly applied to their gates. The source of transistor 51N is connected to node n3, and the source of transistor 52N is connected to node n4.

The above-mentioned control voltage Vcln is expressed as follows:
Vcln>VSS+Vtn
Vtn: Set to the threshold voltage of transistors 51N and 52N.

With this configuration, when the voltage of node n3 (n4) becomes lower than a predetermined voltage (Vcln-Vtn) near the power supply voltage VSS controlled by the control voltage Vcln, transistor 51N (52N) turns on, preventing the voltage of node n3 (n4) from becoming lower than the power supply voltage VSS.

The voltage protection unit 50B1 shares the voltages at nodes n3 and n4 with the buffer unit 10A as bias voltages VBN and VBP, respectively.

In other words, the voltage protection unit 50B1 shown in FIG. 5 operates so that the bias voltages VBN and VBP do not deviate from the low power supply voltage range (VSS to VDD) even if the bias voltages VBN and VBP fluctuate due to capacitive coupling during operation of the buffer unit 10A, for example.

In this way, when setting the drive capacity of the buffer unit 10A that operates in the high-voltage power supply voltage range (VGL to VGH), the circuit configuration of the buffer unit 10A as shown in FIG. 4 makes it possible to set the bias voltages VBN and VBP within the low-voltage power supply voltage range (VSS to VDD). As a result, both the bias modulation unit 40B1 and the withstand voltage protection unit 50B1 can be realized as low-voltage circuits that operate in the low-voltage power supply voltage range (VSS to VDD) as shown in FIG. 5, making it possible to reduce the area.

Figure 6 is a circuit diagram showing the configuration of bias unit 30C, which is a modified version of bias unit 30B shown in Figure 4.

As shown in FIG. 6, the bias section 30C is obtained by adding an amplifier section 70C to the bias modulation section 40B and the voltage protection section 50B shown in FIG. 4 or FIG. 5.

The voltage protection unit 50B shown in FIG. 6 relays the voltages V1B and V2B supplied from the bias modulation unit 40B to the amplifier unit 70C, while controlling the voltages V1B and V2B so that they do not deviate from the low-voltage power supply voltage range (VSS to VDD).

The amplifier 70C includes amplifiers 71C_N and 71C_P that operate on power supply voltages VGH and VGL. The amplifier 71C_N expands the amplitude of the voltage V1B supplied from the bias modulation unit 40B via the withstand voltage protection unit 50B to the high-voltage power supply voltage range (VGL to VGH) and outputs it as a bias voltage VBN. The amplifier 71C_P expands the amplitude of the voltage V2B supplied from the bias modulation unit 40B via the withstand voltage protection unit 50B to the high-voltage power supply voltage range (VGL to VGH) and outputs it as a bias voltage VBP.

Figure 7 is a circuit diagram showing an example of the internal configuration of amplifier 71C_P.

The amplifier 71C_P having the configuration shown in FIG. 7 receives the voltage V2B in the low power supply voltage range (VSS to VDD), expands the amplitude of the voltage V2B toward the power supply voltage VGH, and outputs the voltage V2B as the bias voltage VBP.

As shown in FIG. 7, amplifier 71C_P is an operational amplifier including a constant current source 72C, N-channel transistors 73C and 74C, P-channel transistors 75C to 77C, a load resistor 78C, and a constant current source 79.

In FIG. 7, one end of the constant current source 72 is connected to the sources of the transistors 73C and 74C that form a differential pair. The power supply voltage VGL is applied to the other end of the constant current source 72C. The voltage V2B is supplied to the gate of the transistor 73C, and the drain of the transistor 75C and the gate of the transistor 77C are connected to the source. The drain and gate of the transistor 76C and the gate of the transistor 75C are connected to the drain of the transistor 74C. The power supply voltage VGH is applied to the sources of the transistors 75C and 76C. The power supply voltage VGH is applied to the source of the transistor 77C, and one end of the load resistor 78C is connected to the drain. The gate of the transistor 74C and one end of the constant current source 79 are connected to the other end of the load resistor 78C. The power supply voltage VGL is applied to the other end of the constant current source 79. Note that VSS may be applied to the other ends of the constant current sources 72C and 79 instead of the power supply voltage VGL.

According to the configuration shown in FIG. 7, the drain of the transistor 77C is
VBP = V2B + Ic · Rc
Ic: current of constant current source 79
7 generates a bias voltage VBP having a voltage value represented by the following equation: Rc: resistance value of the load resistor That is, the amplifier 71C_P shown in FIG.

In addition, the amplifier 71C_N may be configured in a similar manner to that shown in FIG. 7 to generate a bias voltage VBN that extends the input voltage V1B toward the power supply voltage VGL.

Figure 8 is a circuit diagram showing the configuration of output buffer circuit 100B as a modified example of output buffer circuit 100 shown in Figure 1.

In addition, in the configuration shown in FIG. 8, buffer unit 10B is used instead of buffer unit 10A shown in FIG. 1, and the other configurations (20, 30A to 30C, 90) are the same as those shown in FIGS. 1 to 7.

The buffer section 10B is composed of high-voltage elements, and is composed of the following high-voltage elements that operate in the high-voltage power supply voltage range (VGL to VGH).

That is, the buffer unit 10B includes an output stage consisting of a P-channel transistor 11 and an N-channel transistor 12, and an output control unit 19B that controls the gate voltages of these transistors 11 and 12.

A power supply voltage VGH is applied to the source of the transistor 11, and a power supply voltage VGL is applied to the source of the transistor 12.
The drains of the transistors 11 and 12 are connected to the output terminal TO, and a binary (logic level 0 or 1) signal having a voltage (VGL, VGH) generated at the output terminal TO is output as an output signal So.

The output control unit 19B has a different configuration from the output control unit 19A shown in FIG. 1, but it has the same function of controlling the gate voltages of the transistors 11 and 12 in the output stage based on the high-voltage input signal Si0 and the bias voltages VBN and VBP.

As shown in FIG. 8, the output control unit 19B includes N-channel transistors 14B and 15B and P-channel transistors 13B and 16B.

A high-voltage input signal Si0 is supplied to the gates of transistors 13B and 14B. A power supply voltage VGH is applied to the source of transistor 13B, and its drain is connected to the source of transistor 16B, the drain of transistor 15B, and the gate of transistor 11 via node n1. A power supply voltage VGL is applied to the source of transistor 14B, and its drain is connected to the drain of transistor 16B, the source of transistor 15B, and the gate of transistor 12 via node n2.

The gate of transistor 15B is supplied with bias voltage VBN generated by bias unit 30A (30B, 30C), and the gate of transistor 16B is supplied with bias voltage VBP generated by bias unit 30A (30B, 30C).

Transistors 13B and 14B have a current driving capability greater than that of transistors 15B and 16B.

The operation of the buffer unit 10B will be described below. In the following, the operation will be described when the high-voltage input signal SiO changes from a logic level 0 (VGL) state to a logic level 1 (VGH) state and then changes back to a logic level 0 (VGL) state.

First, while the high-voltage input signal SiO is in a logic level 0 (VGL) state, the transistor 13B is in an on state and supplies the power supply voltage VGH to the node n1. This causes the transistor 11 to be in an off state. Also, the transistor 14B is in an off state and the node n2 is cut off from the power supply voltage VGL. As a result, the voltage of the node n1 becomes the power supply voltage VGH and the gate-source voltage of the transistor 16B exceeds the threshold voltage, so that the transistor 16B is in an on state. Therefore, the voltage (VGH) of the node n1 is supplied to the node n2 via the transistor 16B, and the voltage of the node n2 becomes the power supply voltage VGH. As a result, the gate-source voltage of the transistor 12 exceeds the threshold voltage, so that the transistor 12 is in an on state and an output signal So of logic level 0 (VGL) is output from the output terminal TO. Note that the transistor 15B is in an off state because the gate-source voltage of the transistor 15B becomes less than the threshold voltage due to the rise in the voltage of the node n2.

After that, when the voltage of the high-voltage input signal SiO starts to rise and exceeds the threshold voltage of the transistor 14B, the transistor 14B turns on and supplies the power supply voltage VGL to the node n2. As the voltage of the high-voltage input signal SiO rises, the current drive capacity of the transistor 14B increases, while the current drive capacity of the transistor 13B decreases, and the transistor 13B transitions to the off state. At this time, since the current drive capacity of the transistor 14B is higher than the current drive capacity of the transistor 16B, the voltage of the node n2 drops relatively steeply from the power supply voltage VGH to the power supply voltage VGL. This causes the transistor 12 to transition to the off state. Also, the gate-source voltage of the transistor 15B exceeds the threshold voltage, and the transistor 15B turns on. As a result, the transistor 15B supplies the voltage of the node n2 to the node n1 with a current drive capacity according to the current value controlled by the bias voltage VBN, and gradually reduces the voltage of the node n1. This also causes the gate-source voltage of transistor 16B to fall below the threshold voltage, causing transistor 16B to transition to the off state.

When the gate-source voltage of transistor 11 exceeds the threshold voltage, transistor 11 turns on and the power supply voltage VGH is supplied to the output terminal TO. As a result, the voltage of the output signal So rises gradually and transitions from logic level 0 (VGL) to logic level 1 (VGH).

After that, when the voltage of the high-voltage input signal SiO starts to decrease and exceeds the threshold voltage of the transistor 13B, the transistor 13B turns on and the power supply voltage VGH is supplied to the node n1. Also, as the voltage of the high-voltage input signal SiO decreases, the current drive capacity of the transistor 13B increases, while the current drive capacity of the transistor 14B decreases and transitions to the off state. At this time, since the current drive capacity of the transistor 13B is higher than the current drive capacity of the transistor 15B, the voltage of the node n1 rises relatively steeply from the power supply voltage VGL state to the power supply voltage VGH. As a result, the transistor 11 transitions to the off state. Also, the gate-source voltage of the transistor 16B exceeds the threshold voltage, and the transistor 16B turns on. As a result, the transistor 16B supplies the voltage (VGH) of the node n1 to the node n2 with a current drive capacity according to the current value controlled by the bias voltage VBP, and the voltage of the node n2 is gradually increased. This also causes the gate-source voltage of transistor 15B to fall below the threshold voltage, causing transistor 15B to transition to the off state.

When the gate-source voltage of transistor 12 exceeds the threshold voltage, transistor 12 turns on and the power supply voltage VGL is supplied to the output terminal TO. As a result, the voltage of the output signal So gradually decreases and transitions from logic level 1 (VGH) to logic level 0 (VGL).

As described above in detail, in the buffer unit 10B, when the output stage transistors (11, 12) are to be transitioned from an on state to an off state, the gate voltages of the output stage transistors are controlled by transistors (13B, 14B) with high current driving capacity. On the other hand, when the output stage transistors (11, 12) are to be transitioned from an off state to an on state, the gate voltages of the output stage transistors are gently changed via transistors (15B, 16B) with current driving capacity according to the current value controlled by the bias voltages (VBN, VBP).

As a result, in response to the high-voltage input signal SiO, one of the transistors 11 (12) in the output stage transitions to the off state, and then the other transistor 12 (11) transitions to the on state, preventing both from being turned on at the same time and suppressing the through current.

The number of elements constituting the output control unit 19B shown in FIG. 8 (six transistors) is smaller than the number of elements (eight transistors) of the output control unit 19A shown in FIG. 1, making it possible to further reduce the area. In addition, the input capacity of the output control unit 19B as seen from the input terminal TI is smaller than that of the output control unit 19A, making it possible to achieve high-speed response. Furthermore, the output control unit 19B shown in FIG. 8 can more reliably suppress the transient through current that occurs when the voltage of the high-voltage input signal SiO changes than the output control unit 19A shown in FIG. 1.

Figure 9A is a circuit diagram showing the configuration of output buffer circuit 100C as yet another modified example of output buffer circuit 100 shown in Figure 1.

The output buffer circuit 100C is a non-inverting buffer that receives two low-voltage input signals Si1L and Si2L, which are slightly out of phase with each other, and outputs one high-voltage output signal So. Here, the input signal Si1L is a binary signal that alternates between the power supply voltage VSS state (logic level 0) and the power supply voltage VDD state (logic level 1), and the input signal Si2L is a binary signal whose voltage rise timing is slightly earlier and whose voltage fall timing is slightly later than the input signal Si1L.

The configuration shown in FIG. 9A is the same as that shown in FIGS. 1 to 7 except that the buffer unit 10A shown in FIG. 1 is changed to the buffer unit 10C, and the one-system level shifter 90 shown in FIG. 1 is changed to two-system level shifters 91 and 92 to accommodate the input of two systems of input signals Si1L and Si2L. The other configurations (20, 30A to 30C, 90) are the same as those shown in FIGS. 1 to 7.

In addition, in the buffer section 10C shown in FIG. 9A, the other configurations (11, 12, 15, 16) are the same as those shown in FIG. 1, except that the inverters 13 and 14 shown in FIG. 1 are changed to inverters 13C and 14C.

Inverter 13C receives high-voltage input signal Si1 via node Ti1. When high-voltage input signal Si1 is at logic level 0 (VGL), it supplies power supply voltage VGH to node n1, and when high-voltage input signal Si1 is at logic level 1 (VGH), it supplies power supply voltage VGL to node n1 via transistor 15. That is, inverter 13C supplies the voltage of a phase-inverted signal to the gate of transistor 11 via node n1. Inverter 13C is identical to inverter 13 in FIG. 1 except for the input signal.

Inverter 14C receives high-voltage input signal Si2 via node Ti2. When high-voltage input signal Si2 is at logic level 0 (VGL), it supplies power supply voltage VGH to node n2 via transistor 16, and when high-voltage input signal Si2 is at logic level 1 (VGH), it supplies power supply voltage VGL to node n2. That is, inverter 14C supplies the voltage of a phase-inverted signal to the gate of transistor 12 via node n2. Inverter 14C is identical to inverter 14 in FIG. 1 except for the input signal.

The level shifter 91 receives the above-mentioned input signal Si1L via the input terminal TI1, and converts the input signal Si1L into a high-voltage input signal Si1 whose amplitude is level-shifted to the high-voltage range (VGL to VGH). The level shifter 91 supplies the high-voltage input signal Si1 to the inverter 13C via the node Ti1.

The level shifter 92 receives the above-mentioned input signal Si2L via the input terminal TI2, and converts the input signal Si2L into a high-voltage input signal Si2 whose amplitude is level-shifted to the high-voltage range (VGL to VGH). The level shifter 92 supplies the high-voltage input signal Si2 to the inverter 14C via the node Ti2.

Figure 9B is a time chart showing the waveforms of the voltages V1 and V2 generated at nodes n1 and n2, respectively, of the buffer unit 10C and the output signal So when high-voltage input signals Si1 and Si2 are received.

First, while the high-voltage input signals Si1 and Si2 are in the logic level 0 (VGL) state, the inverters 13C and 14C supply phase-inverted signals of logic level 1 (VGH) to the nodes n1 and n2, respectively. As a result, the voltage V1 at node n1 and the voltage V2 at node n2 both become the power supply voltage VGH, transistor 11 is in the OFF state, and transistor 12 is in the ON state, so that the output signal So of logic level 0 (VGL) is output from the output terminal TO.

After that, at time tr0 shown in FIG. 9B, the voltage of the high-voltage input signal Si2 transitions from logic level 0 (VGL) to logic level 1 (VGH). As a result, inverter 14C supplies power supply voltage VGL to node n2, voltage V2 at node n2 transitions to power supply voltage VGL, and transistor 12 turns off.

Then, at time tr1, which is later than time tr0, the voltage of the high-voltage input signal Si1 transitions from logic level 0 (VGL) to logic level 1 (VGH). As a result, the inverter 13C supplies the power supply voltage VGL to the node n1 via the transistor 15. At this time, the voltage V1 of the node n1 gradually drops toward the power supply voltage VGL at a rate of change corresponding to the current value controlled by the bias voltage VBN applied to the gate of the transistor 15. During this time, at time tr2 when the gate-source voltage of the transistor 11 based on the voltage V1 exceeds the threshold voltage, the transistor 11 turns on and the power supply voltage VGH is supplied to the output terminal TO. As a result, the voltage of the output signal So gradually rises and transitions from logic level 0 (VGL) to logic level 1 (VGH).

Then, at time tf0 shown in FIG. 9B, the high-voltage input signal Si1 first transitions from logic level 1 (VGH) to logic level 0 (VGL). As a result, the inverter 13C supplies the power supply voltage VGH to the node n1, the voltage V1 of the node n1 transitions to the power supply voltage VGH, and the transistor 11 turns off. Then, at time tf1, which is later than the time tf0, the high-voltage input signal Si2 transitions from logic level 1 (VGH) to logic level 0 (VGL). As a result, the inverter 14C supplies the power supply voltage VGH to the node n2 via the transistor 16. At this time, the voltage V2 of the node n2 gradually rises toward the power supply voltage VGH at a rate of change corresponding to the current value controlled by the bias voltage VBP applied to the gate of the transistor 16. During this time, at time tf2 when the gate-source voltage of transistor 12 based on voltage V2 exceeds the threshold voltage, transistor 12 turns on and power supply voltage VGL is supplied to output terminal TO. As a result, the voltage of output signal So gradually decreases and transitions from logic level 1 (VGH) to logic level 0 (VGL).

In this way, in the output buffer circuit 100C, the inverters (13C, 14C) are individually controlled using two input signals (Si1L, Si2L, Si1, Si2). In this case, as shown in FIG. 9B, by slightly shifting the phase of both input signals, a period is provided during which both transistors 11 and 12 constituting the output stage are in the off state when the voltage of the input signal changes.

Therefore, the output buffer circuit 100C shown in FIG. 9A makes it possible to completely block the shoot-through current that occurs between transistors 11 and 12 in the output stage.

In addition, by applying a configuration similar to that of FIG. 9A to the output buffer circuit 100B of FIG. 8, it is possible to completely cut off the shoot-through current occurring between transistors 11 and 12 in the output stage as shown in FIG. 9B. Specifically, this can be easily achieved by modifying the circuit so that the high-voltage input signals Si1 and Si2 of FIG. 9A are supplied to the gates of transistors 13B and 14B of the output buffer circuit 100B of FIG. 8, respectively.

Figure 10 is a block diagram showing the configuration of a multi-output buffer device 200 having M (M is an integer equal to or greater than 2) output channels.

The multi-output buffer device 200 receives binary (logical level 0 or 1) input signals Si0L_1 to Si0L_M, each of which changes voltage with a low voltage amplitude (VSS to VDD), at input terminals Ti0_1 to Ti0_M, expands and amplifies each of the signals to a high voltage amplitude (VGL to VGH), and outputs the amplified signals as output signals So_1 to So_M from output terminals T0_1 to T0_M.

The multi-output buffer device 200 is an output buffer circuit with multiple channels, which is provided with M (M is an integer of 2 or more) systems of buffer units 10A (10B) and level shifters 90 shown in FIG. 1 (FIG. 8) together with bias units 30A, 30B, or 30C and drive setting units 20 shown in FIG. 1, FIG. 4, or FIG. 6.

That is, the multi-output buffer device 200 receives the input signals Si0L_1 to Si0L_M by level shifters 90_1 to 90_M, each of which has the same configuration as the level shifter shown in FIG. 1 or FIG. 8.

The level shifters 90_1 to 90_M supply the generated M high-voltage input signals Si0 to the buffer units 10_1 to 10_M, each of which is the buffer unit 10A shown in FIG. 1 or the buffer unit 10B shown in FIG. 8.

The buffer units 10_1 to 10_M output the output signals So_1 to So_M output from each of them via output terminals T0_1 to T0_M.

The bias unit 30A (30B, 30C) supplies a bias voltage VBN based on the setting signal Cs supplied from the drive setting unit 20 to the gate of the transistor 15 (15B) of each of the buffer units 10_1 to 10_M via node n3. Furthermore, the bias unit 30A (30B, 30C) supplies a bias voltage VBP based on the setting signal Cs supplied from the drive setting unit 20 to the gate of the transistor 16 (16B) of each of the buffer units 10_1 to 10_M via node n4.

In addition, bypass capacitors may be connected to nodes n3 and n4 to suppress fluctuations in the bias voltages VBN and VBP and stabilize them.

In this way, in the multi-output buffer device 200, M systems of buffer units 10_1 to 10_M and level shifters 90_1 to 90_M, each having the same configuration as the buffer unit 10A shown in FIG. 1 or the buffer unit 10B shown in FIG. 8, are required for M output channels.

However, the drive setting unit 20 and bias unit 30A (30B, 30C) can be shared by the M buffer units 10_1 to 10_M, so only one system is required regardless of the number of output channels, making it possible to reduce the area of the entire device.

Figure 11 is a block diagram showing the configuration of a multi-output buffer device 200A, which is another configuration of a multi-output buffer device having M output channels.

The multi-output buffer device 200A is an output buffer circuit with multiple channels, which is provided with M (M is an integer of 2 or more) systems of the buffer unit 10C and level shifters 91 and 92 shown in FIG. 9A, together with the bias unit 30A, 30B or 30C and drive setting unit 20 shown in FIG. 9A.

That is, the level shifters 91_1 to 91_M, each of which has the same configuration as the level shifter 91, supply M high-voltage input signals Si1 obtained by individually level-shifting the input signals Si1L_1 to Si1L_M to the buffer units 10A_1 to 10A_M, each of which has the same configuration as the buffer unit 10C shown in FIG. 9A. The level shifters 92_1 to 92_M, each of which has the same configuration as the level shifter 92, supply M high-voltage input signals Si2 obtained by individually level-shifting the input signals Si2L_1 to Si2L_M to the buffer units 10A_1 to 10A_M.

The buffer units 10A_1 to 10A_M output the output signals So_1 to So_M output from the respective buffer units 10A_1 to 10A_M via the output terminals T0_1 to T0_M.

The bias unit 30A (30B, 30C) supplies a bias voltage VBN based on the setting signal Cs supplied from the drive setting unit 20 to the gates of the transistors 15 of each of the buffer units 10A_1 to 10A_M via node n3. Furthermore, the bias unit 30A (30B, 30C) supplies a bias voltage VBP based on the setting signal Cs supplied from the drive setting unit 20 to the gates of the transistors 16 of each of the buffer units 10A_1 to 10A_M via node n4.

In addition, bypass capacitors may be connected to nodes n3 and n4 to suppress fluctuations in the bias voltages VBN and VBP and stabilize them.

In this way, in the multi-output buffer device 200A, M systems of buffer units 10A_1 to 10A_M, level shifters 91_1 to 91_M, and level shifters 92_1 to 92_M, each having the same configuration as the buffer unit 10C shown in FIG. 9A, are required for M output channels. However, the drive setting unit 20 and bias unit 30A (30B, 30C) can be shared by the M systems of buffer units 10A_1 to 10A_M, so only one system is required regardless of the number of output channels, making it possible to reduce the area of the entire device.

Figure 12 is a block diagram showing the schematic configuration of an active matrix display device 300.

As shown in FIG. 12, the display device 300 includes a display controller 130, a data driver 120, and a display panel 150.

The display panel 150 is formed with gate lines GL1 to GLr (r is an integer of 2 or more) that are arranged along the horizontal direction of the screen, and data lines DL1 to DLk (k is an integer of 2 or more) that are arranged to intersect with each gate line. A display cell 154 that serves as a pixel is formed at each intersection of each of the gate lines GL1 to GLr and each of the data lines DL1 to DLk.

Furthermore, scanning drivers 110_1 and 110_2 formed integrally with the display panel 150 are arranged on the display panel 150. The scanning drivers 110_1 and 110_2 are constructed of thin-film transistor circuits formed integrally with pixels and wiring on an insulating substrate such as glass or plastic.

The data driver 120 receives the video data signal VDS sent from the display controller 130, generates drive signals G1 to Gk, each having a voltage value corresponding to a brightness level based on the video data signal VDS, and supplies the drive signals to the data lines DL1 to DLk. Furthermore, the data driver 120 supplies r gate timing signals GSa and r gate timing signals GSb synchronized with each horizontal synchronization signal included in the video data signal VDS to the scan drivers 110_1 and 110_2, respectively. Each of the gate timing signals GSa and GSb is a high-voltage pulse signal with an amplitude of, for example, 30 to 40 volts.

The data driver 120 is usually made of a silicon IC and is mounted on the display panel 150 by COG (chip on glass) or COF (chip on film). When the data driver 120 is made up of multiple IC chips, a video data signal VDS and various control signals corresponding to the data lines that drive each chip are supplied from the display controller 130 to each IC chip. In this case, if the screen size of the display device 300 is relatively small, the display controller 130 may be built into the data driver 120. In this case, the video data signal VDS is supplied to the data driver 120 from the system side.

The scanning driver 110_1 is connected to one end of each of the gate lines GL1 to GLr, and the scanning driver 110_2 is connected to the other end of each of the gate lines GL1 to GLr. The scanning driver 110_1 sequentially generates gate selection signals at the timing of each of the gate timing signals GSa supplied from the data driver 120, and supplies each of the gate selection signals to one end of each of the gate lines GLr to GL1. The scanning driver 110_2 sequentially generates gate selection signals at the timing of each of the gate timing signals GSb supplied from the data driver 120, and supplies each of the gate selection signals to the other end of each of the gate lines GLr to GL1.

The data driver 120 includes a gate control signal output circuit 122_1 that outputs the above-mentioned r gate timing signals GSa, and a gate control signal output circuit 122_2 that outputs r gate timing signals GSb.

At this time, the gate control signal output circuit 122_1 (122_2) includes the multi-output buffer device 200 or 200A shown in FIG. 10 or FIG. 11, and r gate timing signals GSa (GSb) are output from the multi-output buffer device 200 or 200A.

Note that, although FIG. 12 shows a configuration in which k data lines DL1 to DLk of the display panel 150 are driven by a data driver 120 having k output terminals, a multiplexer circuit including a changeover switch that switches the drive signal of one output of the data driver to multiple data lines in a time-division manner may be provided (not shown). In this case, the number of data line outputs is the number obtained by dividing the k data lines by the time division number. In addition, the data driver is provided with a multiplexer selection signal output circuit that supplies a multiplexer selection signal to the panel for sequentially selecting the changeover switches of the multiplexer circuit on the display panel. This multiplexer selection signal output circuit is a high-voltage pulse signal similar to the gate control signal output circuit, and a circuit similar to the gate control signal output circuit 122_1 (122_2) may be provided in the data driver as the multiplexer selection signal output circuit.

Therefore, by adjusting the bias voltages VBN and VBP using the setting signal Cs of the drive setting unit 20 and optimizing the voltage change rate of the output signal So output from the output buffer circuit, it is possible to suppress EMI and increased power consumption due to the through current, reduce EMI caused by the charge/discharge current associated with load driving, and obtain a gate timing signal GSa (GSb) with the required current driving capability (output waveform with less distortion) at low power consumption in a small-area configuration.

Figure 13 is a block diagram showing the schematic configuration of a passive matrix display device 300A.

As shown in FIG. 13, the display device 300A includes a display controller 130, a scan driver 110_1, a data driver 120A, and a display panel 150.

The display panel 150 is formed with scanning lines GL1 to GLr (r is an integer of 2 or more) that are arranged along the horizontal direction of the screen, and data lines DL1 to DLk (k is an integer of 2 or more) that are arranged to intersect with each scanning line. A display cell 154 that serves as a pixel is formed at each intersection of each of the scanning lines GL1 to GLr and each of the data lines DL1 to DLk.

The display controller 130 supplies the data driver 120A with a video data signal VDS, which includes horizontal and vertical synchronization signals, various control signals, and a series of pixel data pieces representing the luminance level of each pixel. In addition, the display controller 130 supplies r gate timing signals GS synchronized with each horizontal synchronization signal included in the video data signal VDS to the scan driver 110_1.

Based on the video data signal VDS, the data driver 120A generates drive pulse signals G1 to Gk, each of which has a pulse width corresponding to a brightness level, and supplies them to the data lines DL1 to DLk.

The scanning driver 110_1 is connected to one end of each of the gate lines GL1 to GLr, and sequentially generates r scanning selection pulse signals at the timing of each of the above-mentioned scanning timing signals GSa, and supplies each of them to one end of each of the scanning lines GLr to GL1.

The data driver 120 includes an output buffer section 125 that outputs the above-mentioned drive pulse signals G1 to Gk, and the scan driver 110_1 includes an output buffer section 115 that outputs the above-mentioned r gate selection pulse signals.

In this case, the output buffer unit 115 is composed of the multi-output buffer device 200 or 200A shown in FIG. 10 or FIG. 11, and r scanning selection pulse signals are output from the multi-output buffer device 200 or 200A. The output buffer unit 125 is also composed of the multi-output buffer device 200 or 200A shown in FIG. 10 or FIG. 11, and drive pulse signals G1 to Gk are output from the multi-output buffer device 200 or 200A.

By adjusting the bias voltages VBN and VBP to optimize the voltage change rate of the output signal So output from the output buffer circuit, it is possible to suppress EMI and increased power consumption due to through current, reduce EMI caused by charge/discharge currents associated with load driving, and output r scanning selection pulse signals and drive pulse signals G1 to Gk with the required current driving capability (output waveform with less distortion) with low power consumption in a space-saving configuration.

Figure 14 is a block diagram showing the configuration of a multi-output buffer device 200B having a pair of buffer units 10Ax and 10Ay that respectively drive two loads X and Y that require different current drive capabilities.

As shown in FIG. 14, the multi-output buffer device 200B includes a buffer section 10Ax that drives a load X connected to an output terminal TOx, a buffer section 10Ay that drives a load Y connected to an output terminal TOy, a bias section 30A, a drive setting section 20A, and level shifters 90x_1, 90y_1, 97y_1, and 97y_2.

In addition, in FIG. 14, the bias unit 30A is the same as the bias unit 30A shown in FIG. 1, and the buffer unit 10Ax has the same internal configuration as the buffer unit 10A shown in FIG. 1, so detailed descriptions of the two are omitted.

The level shifter 90x_1 receives an input signal Si0Lx1, which is a binary (logical level 0 or 1) whose voltage changes with a low voltage amplitude (VSS to VDD) as an input signal for driving the load X. The level shifter 90x_1 supplies a high voltage input signal, which is a level shift of the amplitude of the input signal Si0Lx1 to a high voltage amplitude (VGL to VGH), to the buffer unit 10Ax.

In response to the high-voltage input signal, the buffer unit 10Ax supplies an output signal having a waveform, for example, like the output signal So shown in FIG. 9B, to the load X via the output terminal TOx.

The drive setting unit 20A generates a setting signal Cs, for example, in the same manner as the drive setting unit 20 shown in FIG. 1, and supplies this to the bias unit 30A. Furthermore, the drive setting unit 20A supplies drive capacity control signals Pctl1 and Pctl2, each of which is, for example, 2 bits, to the level shifters 97y_1 and 97y_2, respectively, to set the drive capacity of the buffer unit 10Ay.

The level shifter 97y_1 generates a 2-bit drive capability control signal Pc1 by level-shifting the amplitude of the drive capability control signal Pctl1 to a high voltage amplitude (VGL to VGH) and supplies this to the buffer unit 10Ay.

The level shifter 97y_2 generates a 2-bit drive capability control signal Pc2 by level-shifting the amplitude of the drive capability control signal Pctl2 to a high voltage amplitude (VGL to VGH) and supplies this to the buffer unit 10Ay.

The level shifter 90y_1 receives a binary (logical level 0 or 1) input signal Si0Ly1 whose voltage changes with a low voltage amplitude (VSS to VDD) as an input signal for driving the load Y. The level shifter 90x_1 supplies a high voltage input signal obtained by level-shifting the amplitude of the input signal Si0Ly1 to a high voltage amplitude (VGL to VGH) to the buffer unit 10Ax.

In response to the high-voltage input signal, the buffer unit 10Ay supplies an output signal having a waveform similar to that of the output signal So shown in FIG. 9B to the load Y via the output terminal TOy.

The buffer unit 10Ay is composed of high-voltage elements, and is composed of the following high-voltage elements that operate within the high-voltage power supply voltage range (VGL to VGH).

That is, the buffer unit 10Ay includes an output stage consisting of a P-channel transistor 11y and an N-channel transistor 12y, and an output control unit 19Ay that controls the gate voltages of the transistors 11y and 12y. The output control unit 19Ay includes inverters 13Ay and 14Ay, a discharge speed control unit 19Ay1, and a charge speed control unit 19Ay2.

The inverter 13Ay is composed of an N-channel transistor 13yn and a P-channel transistor 13yp, and the inverter 14Ay is composed of an N-channel transistor 14yn and a P-channel transistor 14yp. Both inverters 13Ay and 14Ay receive at their gates a high-voltage input signal that has been level-shifted to the amplitude VGL to VGH of the high-voltage power supply voltage by the level shifter 90y_1. The source of the transistor 13yp of the inverter 13Ay is connected to the positive power supply terminal and receives the power supply voltage VGH, and the source of the transistor 13yn is connected to the charge speed control unit 19Ay2. The source of the transistor 14yn of the inverter 14Ay is connected to the negative power supply terminal and receives the power supply voltage VGL, and the source of the transistor 14yp is connected to the discharge speed control unit 19Ay1.

The discharge speed control unit 19Ay1 controls the discharge speed of the load Y connected to the output terminal TOy in response to the drive capability control signal Pc1. The discharge speed control unit 19Ay1 includes switch elements 84 and 85 and P-channel transistors 81 to 83.

The power supply voltage VGH is applied to the source of each of the transistors 81 to 83, and the bias voltage VBP is applied to each of the gates. The drain of the transistor 81 is connected to the source of the transistor 14p of the inverter 14, and the drains of the transistors 82 and 83 are connected to the source of the transistor 14p via the switch elements 84 and 85, respectively.

For example, when the size of the transistors 81 and 82 is 1, the size (W/L) ratio of each of the transistors 81 to 83 is as follows:
1:1:2
It is.

The switch element 84 is set to an on or off state according to the first bit of the drive capability control signal Pc1, and when in the on state, connects the drain of the transistor 82 to the source of the transistor 14yp of the inverter 14Ay.

The switch element 85 is set to an on or off state according to the second bit of the drive capability control signal Pc1, and when in the on state, connects the drain of the transistor 83 to the source of the transistor 14yp of the inverter 14Ay.

Figure 15A shows the state of switch elements 84 and 85 in response to drive capacity control signal Pc1 and the magnitude (ratio) of the current passed by discharge speed control unit 19Ay1.

The discharge speed control unit 19Ay1 can switch the magnitude of the current supplied to node n2y when transistor 12y transitions to the on state between four levels (settings 1 to 4) by combining the on and off states of switch elements 84 and 85 based on the drive capability control signal Pc1 as shown in FIG. 15A. In this case, the larger the current, the faster the discharge speed to load Y. On the other hand, the smaller the current, the slower the discharge speed to load Y.

With the above configuration, the discharge speed control unit 19Ay1 can switch the current value supplied to the node n2y upon receiving the bias voltage VBP using the drive capability control signal Pc1. This allows the buffer unit 10Ay to adjust the speed at which the load Y is discharged via the transistor 12y, thereby optimizing EMI reduction and the output waveform to the load Y.

The charging speed control unit 19Ay2 controls the charging speed of the load Y connected to the output terminal TOy in response to the drive capability control signal Pc2. The charging speed control unit 19Ay2 includes switch elements 95 and 96 and P-channel transistors 91 to 93.

The power supply voltage VGL is applied to the source of each of the transistors 91 to 93, and the bias voltage VBN is applied to each of the gates. The drain of the transistor 91 is connected to the source of the transistor 13yn of the inverter 13Ay, and the drains of the transistors 92 and 93 are connected to the source of the transistor 13yn via the switch elements 95 and 96, respectively.

For example, when the size of the transistors 91 and 92 is 1, the size (W/L) ratio of each of the transistors 91 to 93 is as follows:
1:1:2
It is.

The switch element 95 is set to an on or off state according to the first bit of the drive capability control signal Pc2, and when in the on state, connects the drain of the transistor 92 to the source of the transistor 13yn of the inverter 13Ay.

The switch element 96 is set to an on or off state according to the second bit of the drive capability control signal Pc2, and when in the on state, connects the drain of the transistor 93 to the source of the transistor 13yn of the inverter 13Ay.

Figure 15B is a diagram showing the state of switch elements 95 and 96 according to drive capacity control signal Pc2 and the magnitude (ratio) of the current passed by charging speed control unit 19Ay2 in accordance with this state.

The charging speed control unit 19Ay2 can switch the magnitude of the current drawn from node n1y when transistor 11y transitions to the on state between four levels (settings 1 to 4) by combining the on and off states of switch elements 95 and 96 based on the drive capability control signal Pc2 as shown in FIG. 15B. In this case, the larger the current, the faster the charging speed for load Y. On the other hand, the smaller the current, the slower the charging speed for load Y.

With the above configuration, the charging speed control unit 19Ay2 can switch the current value extracted from the node n1y upon receiving the bias voltage VBN using the drive capability control signal Pc2. This allows the buffer unit 10Ay to adjust the speed at which the load Y is charged via the transistor 11y, thereby optimizing EMI reduction and the output waveform to the load Y.

Therefore, in the buffer unit 10Ay equipped with the discharge speed control unit 19Ay1 and the charge speed control unit 19Ay2, by adjusting its own current drive capacity using the drive capacity control signals (Pctl1, Pctl2), it is possible to appropriately drive the load Y, which requires a different current drive capacity from the load X, while sharing the bias unit 30A.

In the example shown in FIG. 14, a pair of buffer units 10Ax and 10Ay are shared by one bias unit 30A, but multiple buffer units 10Ax and multiple buffer units 10Ay may be shared by one bias unit 30A.

Figure 16 is a block diagram showing the configuration of a multi-output buffer device 200C, which is yet another example of a multi-output buffer device that was created in consideration of the above points.

As shown in FIG. 16, the multi-output buffer device 200B includes buffer units 10x_1 to 10x_M (M is an integer of 2 or more) each having the same configuration as the buffer unit 10Ax shown in FIG. 14, and buffer units 10y_1 to 10y_F (F is an integer of 2 or more) each having the same configuration as the buffer unit 10Ay shown in FIG. 14.

Furthermore, the multi-output buffer device 200B has input terminals Ti0x_1 to Ti0x_M that individually receive the input signals Si0Lx_1 to Si0Lx_M, input terminals Ti0y_1 to Ti0y_F that individually receive the input signals Si0Ly_1 to Si0Ly_F, level shifters 90x_1 to 90x_M, and level shifters 90y_1 to 90y_F.

The level shifters 90x_1 to 90x_M generate high-voltage input signals by level-shifting the amplitudes of the input signals Si0Lx_1 to Si0Lx_M to high voltage amplitudes (VGL to VGH) individually, and supply them to the buffer units 10x_1 to 10x_M, respectively. The level shifters 90y_1 to 90y_F generate high-voltage input signals by level-shifting the amplitudes of the input signals Si0Ly_1 to Si0Ly_F individually to high voltage amplitudes (VGL to VGH), and supply them to the buffer units 10y_1 to 10y_F, respectively.

The drive setting unit 20A, level shifters 97y_1 and 97y_2, and bias unit 30A (30B, 30C) shown in FIG. 16 are the same as those described above, so their operation will not be described here.

However, in the multi-output buffer device 200B, the bias voltages VBP and VBN generated by the bias unit 30A (30B, 30C) are supplied to all of the buffer units 10x_1 to 10x_M and the buffer units 10y_1 to 10y_F. In addition, the level shifter 97y_1 supplies the generated drive capability control signal Pc1 to the buffer units 10y_1 to 10y_F, and the level shifter 97y_2 supplies the generated drive capability control signal Pc2 to the buffer units 10y_1 to 10y_F.

Figure 17 is a block diagram showing the schematic configuration of a time-division drive type display device 600 including the multi-output buffer device 200B shown in Figure 14.

The display device 600 includes a data driver 120B and a display panel 150A having gate lines GL1 to GLr (r is an integer of 2 or more) arranged along the horizontal direction of the screen and data lines DL1 to DLm (m is an integer of 2 or more) arranged to intersect with each gate line. The display device 600 employs a time-division driving method in which the data lines DL1 to DLm are grouped, for example, in groups of three, and within each group, three data lines are driven one by one in a time-division manner within one horizontal scanning period. In addition, the display panel 150A has display cells 154 that handle each pixel formed at the intersections of each of the gate lines GL1 to GLr and each of the data lines DL1 to DLm.

Furthermore, scan drivers 110_1 and 110_2 and multiplexers MX1 to MXk (k is an integer equal to or greater than 2) are arranged on the display panel 150A.

Scanning driver 110_1 is connected to one end of each of gate lines GL1 to GLr, and scanning driver 110_2 is connected to the other end of each of gate lines GL1 to GLr. Scanning driver 110_1 generates gate selection signals at the timing indicated by the gate line timing signal group GS supplied from data driver 120B, and supplies them in sequence to one end of each of gate lines GL1 to GLr. Scanning driver 110_2 generates gate selection signals at the timing indicated by the gate line timing signal group GS supplied from data driver 120B, and supplies them in sequence to the other end of each of gate lines GL1 to GLr.

Each of the multiplexers MX1 to MXk includes one input terminal that individually receives the grayscale voltage signals Ds1 to Dsk corresponding to each pixel from the data driver 120B, three output terminals that are connected to three data lines of the same group among the data lines DL1 to DLm, and switches SW1 to SW3 that individually connect or disconnect between the input terminal and each of the three output terminals. The switches SW1 to SW3 are sequentially and selectively set to the on state by the data line selection signals Sa, Sb, and Sc supplied from the data driver 120B.

The data driver 120B is made up of a semiconductor IC chip and includes a drive setting unit 20A, a power supply voltage generating unit 90, a gradation voltage output unit 125, and control buffer units BU1 and BU2. The data driver 120B is made up of, for example, a single or multiple semiconductor chips, and receives a video data signal VDS and various control signals from the outside.

Figure 18 shows an example of the layout of the drive setting unit 20A and the control buffer units BU1 and BU2 in the data driver 120B of the display device 600.

As shown in FIG. 18, the data driver 120B has a rectangular planar area with long sides aligned with the extension direction of the gate lines of the display panel 150A, with the drive setting unit 20A located in the center, and control buffer units BU1 and BU2 located at one and the other longitudinal ends of the drive setting unit 20A, respectively.

The drive setting unit 20A acquires a series of video data fragments representing the luminance level of each pixel based on the video data signal VDS and supplies them to the gradation voltage output unit 125 (not shown in FIG. 18).

The drive setting unit 20A also supplies the first to third data line switching signals, which selectively set the switches SW1 to SW3 of each of the multiplexers MX1 to MXk to the on state in sequence, and a group of control signals that are the basis of the gate line timing signal that indicates the timing for selecting a gate line, to the control buffer units BU1 and BU2.

Furthermore, the drive setting unit 20A includes a drive capacity control unit, a reference current generation unit, and an activation/deactivation control unit.

The drive capacity control units generate setting signals Cs_L and Cs_R, each including the drive capacity control signals Pctl1 and Pctl2 along with the setting signal Cs described above, and supply the setting signal Cs_L to the control buffer unit BU1 and the setting signal Cs_R to the control buffer unit BU2.

The reference current generating unit generates two reference currents Is_L and Is_R, and supplies the reference current Is_L to the control buffer unit BU1 and the reference current Is_R to the control buffer unit BU2.

The active/inactive control unit generates active/inactive control signals En_L and En_R that indicate whether the control buffer units BU1 and BU2 are individually set to an active or inactive state, and supplies the active/inactive control signal En_L to the control buffer unit BU1 and the active/inactive control signal En_R to the control buffer unit BU2. As shown in FIG. 17, when the display panel 150A is driven by one data driver 120B, the active/inactive control unit outputs the active/inactive control signals En_L and En_R that activate both the control buffer units BU1 and BU2. On the other hand, when the display panel 150A is driven by multiple data drivers 120B, the active/inactive control unit of the data driver closest to the scan driver 110_1 of the display panel 150A outputs the active/inactive control signals En_L and En_R that activate and inactivate the control buffer units BU1 and BU2, respectively. In addition, the activation/inactivation control unit of the data driver closest to the scan driver 110_2 of the display panel 150A outputs activation/inactivation control signals En_L and En_R that respectively inactivate and activate the control buffer units BU1 and BU2. Furthermore, when there are three or more data drivers driving the display panel 150A, the activation/inactivation control units of the data drivers other than those at both ends output activation/inactivation control signals En_L and En_R that inactivate both the control buffer units BU1 and BU2.

The power supply voltage generation unit 90 receives an external power supply voltage, generates various power supply voltages based on the external power supply voltage to operate each module, and supplies these to the drive setting unit 20A, the gradation voltage output unit 125, and the control buffer units BU1 and BU2.

The grayscale voltage output unit 125 generates grayscale voltage signals Ds1 to Dsk having voltage values corresponding to the luminance level of each pixel represented by the series of video data supplied from the drive setting unit 20A, and supplies each to the input terminal of each of the multiplexers MX1 to MXk.

Each of the control buffer units BU1 and BU2 includes a bias unit 30A shown in FIG. 14, a multi-output buffer 10Nx each consisting of a plurality of buffer units 10Ax shown in FIG. 14, and a multi-output buffer 10Ny each consisting of a plurality of buffer units 10Ay shown in FIG. 14.

The bias section 30A of each of the control buffer sections BU1 and BU2 supplies common bias voltages VBP and VBN to the multi-output buffers 10Nx and 10Ny to set the current drive capacity.

The multi-output buffer 10Nx of each of the control buffer units BU1 and BU2 is set to a current drive capability based on the bias voltages VBP and VBN. At this time, the multi-output buffer 10Nx of the control buffer unit BU1 generates a gate line timing signal group GS indicating the timing for selecting a gate line, and supplies it to the scan driver 110_1 as a load. The multi-output buffer 10Nx of the control buffer unit BU2 generates a gate line timing signal group GS indicating the timing for selecting a gate line, and supplies it to the scan driver 110_2 as a load.

The multi-output buffer 10Ny of each of the control buffer units BU1 and BU2 is set to a current drive capacity based on the bias voltages VBP and VBN, and the drive capacity control signals (Pctl1, Pctl2). The multi-output buffer 10Ny of the control buffer unit BU1 generates data line selection signals Sa, Sb, and Sc that sequentially select one of the three data lines connected to each of the multiplexers MX1 to MXk.

The multi-output buffer 10Ny of the control buffer unit BU1 supplies data line selection signals Sa, Sb, and Sc to the multiplexers MX1 to MXk as loads from the left end of each of the three wirings that are arranged to extend in the horizontal scanning direction of the display panel 150A as shown in FIG. 17. The multi-output buffer 10Ny of the control buffer unit BU2 supplies data line selection signals Sa, Sb, and Sc to the multiplexers MX1 to MXk as loads from the right end of each of the three wirings that are arranged to extend in the horizontal scanning direction of the display panel 150A as shown in FIG. 17.

In this way, in a time-division drive type display device such as that shown in FIG. 17, by applying the multi-output buffer device 200B shown in FIG. 14, it becomes possible to drive two load systems (scanning driver, multiplexer) that require different current drive capabilities.

10A, 10B, 10C Buffer section 11, 12, 15, 16 Transistor 13, 14 Inverter 20 Drive setting section 30A, 30B, 30C Bias section 90 to 92 Level shifter

Claims (19)

An output buffer circuit that outputs an output signal obtained by amplifying an input signal from an output terminal,
a first transistor of a first conductivity type that supplies a first high voltage power supply voltage to the output terminal when the first transistor is turned on in response to a voltage of the input signal received at its gate;
a second transistor of a second conductivity type that supplies a second high-voltage power supply voltage lower than the first high-voltage power supply voltage to the output terminal when the second transistor is turned on in response to a voltage of the input signal received at its gate;
A bias unit that generates a bias voltage;
an output control unit that, when the voltage of the input signal changes, changes a gate voltage of one of the first transistor and the second transistor that is in an on state at a rate of change corresponding to the voltage change of the input signal to transition the on-state transistor to an off-state, and changes a gate voltage of one of the first transistor and the second transistor that is in an off-state at a rate of change based on a current value controlled by the bias voltage to bring the off-state transistor to an on-state;
a drive setting unit that generates a setting signal for specifying a voltage value of the bias voltage and setting the voltage value to the specified voltage value;
The bias portion is
an output buffer circuit comprising: a bias modulation section that operates by receiving a first low-voltage power supply voltage having a voltage value equal to or lower than the first high-voltage power supply voltage and a second low-voltage power supply voltage having a voltage value equal to or higher than the second high-voltage power supply voltage, and that sets a voltage value of the bias voltage to a voltage value based on the setting signal. The output buffer circuit according to claim 1, characterized in that the bias section includes a voltage protection section that controls the voltage applied to the output of the bias modulation section to be within a low-voltage power supply voltage range from the second low-voltage power supply voltage to the first low-voltage power supply voltage by eliminating the influence of the first high-voltage power supply voltage and the second high-voltage power supply voltage. the bias modulation unit includes a current source that generates a current having a current value corresponding to the setting signal;
2. The output buffer circuit according to claim 1, wherein the bias section includes a current-voltage conversion section that converts the current into a voltage and outputs the converted voltage as the bias voltage. The output buffer circuit according to claim 1, characterized in that the bias modulation unit generates a voltage having a voltage value within the low-voltage power supply voltage range based on the setting signal and outputs this as the bias voltage. The bias modulation unit is
a reference voltage generating unit that generates a plurality of reference voltages;
4. The output buffer circuit according to claim 3, further comprising: a DA conversion section that selects a reference voltage based on the setting signal from among the plurality of reference voltages, and outputs the selected reference voltage as the bias voltage. the bias modulation unit generates a voltage having a voltage value within the low power supply voltage range based on the setting signal;
The bias portion is
2. The output buffer circuit according to claim 1, further comprising an amplifier that amplifies the voltage generated by the bias modulation unit to a voltage within a high-voltage power supply voltage range from the second high-voltage power supply voltage to the first high-voltage power supply voltage, and outputs the amplified voltage as the bias voltage. The output buffer circuit according to claim 1, characterized in that the first low-voltage power supply voltage is lower than the first high-voltage power supply voltage and the second low-voltage power supply voltage is equal to or higher than the second high-voltage power supply voltage, or the first low-voltage power supply voltage is equal to or lower than the first high-voltage power supply voltage and the second low-voltage power supply voltage is higher than the second high-voltage power supply voltage. the bias unit generates a pair of a first bias voltage and a second bias voltage as the bias voltage;
The output control unit is
a first node supplying a first voltage to a gate of the first transistor;
a second node providing a second voltage to a gate of the second transistor;
a third transistor of a first conductivity type that receives the input signal at a gate thereof, and when turned on in response to the input signal, supplies a first power supply voltage to the first node and transitions the first transistor to an off state;
a fourth transistor of a second conductivity type that receives the input signal at a gate thereof, and when turned on in response to the input signal, supplies a second power supply voltage to the second node and transitions the second transistor to an off state;
a fifth transistor of a second conductivity type that receives the first bias voltage at a gate thereof and, when activated in response to a voltage change of the input signal, changes the first voltage of the first node toward the second power supply voltage at a rate of change based on a current value controlled by the first bias voltage, thereby transitioning the first transistor to an on state;
and a sixth transistor of a first conductivity type that receives the second bias voltage at its gate and, when activated in response to a voltage change of the input signal, changes the second voltage of the second node toward the first power supply voltage at a rate of change based on a current value controlled by the second bias voltage, thereby transitioning the second transistor to an on state. the bias unit generates a pair of a first bias voltage and a second bias voltage as the bias voltage;
The output control unit is
a first inverter that receives the first high-voltage power supply voltage at a positive power supply terminal thereof and supplies a voltage of a signal obtained by inverting a phase of the input signal to a gate of the first transistor;
a third transistor of a second conductivity type, the drain of which is connected to a negative power supply terminal of the first inverter, the source of which receives the second high-voltage power supply voltage, and the gate of which receives the first bias voltage;
a second inverter that receives the second high-voltage power supply voltage at its negative power supply terminal and supplies a voltage of a signal obtained by inverting the phase of the input signal to a gate of the second transistor;
a fourth transistor of a first conductivity type having a drain connected to a positive power supply terminal of the second inverter, receiving the first high-voltage power supply voltage at a source, and receiving the second bias voltage at a gate. the bias unit generates a pair of a first bias voltage and a second bias voltage as the bias voltage;
The output control unit is
a third transistor of a first conductivity type that receives the input signal at its gate and supplies the first high voltage power supply voltage to a first node connected to the gate of the first transistor when the third transistor is turned on in response to the input signal;
a fourth transistor of a second conductivity type that receives the input signal at its gate and supplies the second high voltage power supply voltage to a second node connected to the gate of the second transistor when the fourth transistor is turned on in response to the input signal;
a fifth transistor of a second conductivity type, the fifth transistor having a gate receiving the first bias voltage, a source connected to the second node, and a drain connected to the first node;
a sixth transistor of a first conductivity type, the sixth transistor receiving the second bias voltage at its gate, having a source connected to the first node, and having a drain connected to the second node. the bias unit generates a pair of a first bias voltage and a second bias voltage as the bias voltage;
the input signals are a first input signal and a second input signal having a voltage rise timing earlier and a voltage fall timing later than the first input signal,
The output control unit is
a first inverter that receives the first high-voltage power supply voltage at a positive power supply terminal thereof and supplies a voltage of a signal obtained by inverting a phase of the first input signal to a gate of the first transistor;
a third transistor of a second conductivity type, the drain of which is connected to a negative power supply terminal of the first inverter, the source of which receives the second high-voltage power supply voltage, and the gate of which receives the first bias voltage;
a second inverter that receives the second high-voltage power supply voltage at its negative power supply terminal and supplies a voltage of a signal obtained by inverting a phase of the second input signal to a gate of the second transistor;
a fourth transistor of a first conductivity type having a drain connected to a positive power supply terminal of the second inverter, receiving the first high-voltage power supply voltage at a source, and receiving the second bias voltage at a gate. an output buffer circuit for outputting first to Mth output signals obtained by amplifying first to Mth input signals (M is an integer equal to or greater than 2),
A bias unit that generates a bias voltage;
a drive setting unit that generates a setting signal for specifying a voltage value of the bias voltage and setting the voltage value;
first to Mth buffer units each receiving the first to Mth input signals individually and outputting the first to Mth output signals via a corresponding output terminal;
Each of the first to Mth buffer units is
a first transistor of a first conductivity type that supplies a first high voltage power supply voltage to its output terminal when it is turned on in response to a voltage of the input signal received at its gate;
a second transistor of a second conductivity type that supplies a second high voltage power supply voltage lower than the first high voltage power supply voltage to its output terminal when the second transistor is turned on in response to a voltage of the input signal received at its gate;
an output control unit that, when the voltage of the input signal changes, changes a gate voltage of one of the first transistor and the second transistor that is in an on state at a rate of change corresponding to the voltage change of the input signal to transition the transistor in the on state to an off state, and changes a gate voltage of one of the first transistor and the second transistor that is in an off state at a rate of change based on a current value controlled by the bias voltage to bring the transistor in the off state to an on state,
The bias portion is
a buffer memory unit is provided in common with each of the first to Mth buffer units,
an output buffer circuit that operates by receiving a first low-voltage power supply voltage that is less than the first high-voltage power supply voltage or has a voltage value equal to or less than the first high-voltage power supply voltage, and a second low-voltage power supply voltage that is higher than the second high-voltage power supply voltage or has a voltage value equal to or greater than the second high-voltage power supply voltage, the output buffer circuit including a bias modulation section that sets a voltage value of the bias voltage to a voltage value based on the setting signal, and supplies the bias voltage having the voltage value set by the bias modulation section to each of the first to Mth buffer sections. A display driver that drives a display panel including a plurality of scanning lines arranged along a horizontal direction of a screen and a plurality of data lines arranged to cross the plurality of scanning lines in response to a video signal,
a data driver that generates a plurality of drive signals based on the video signal and supplies the drive signals to the plurality of data lines;
a scan driver that drives the plurality of scan lines at timings corresponding to a plurality of scan timing signals;
the data driver includes a scan control signal output circuit that outputs the plurality of scan timing signals;
13. A display driver, wherein said scanning control signal output circuit comprises an output buffer circuit according to claim 12. A display driver that drives a passive matrix display panel including a plurality of scanning lines arranged along a horizontal direction of a screen and a plurality of data lines arranged to cross the plurality of scanning lines in response to a video signal,
a data driver including a first output buffer unit that outputs a plurality of drive pulse signals having pulse widths corresponding to the luminance levels of the pixels represented by the video signal to a plurality of data lines;
a scan driver including a second output buffer unit that outputs a plurality of scan pulse signals to the plurality of scan lines;
13. A display driver, wherein said first output buffer section and said second output buffer section are comprised of an output buffer circuit according to claim 12. A display device having a display panel including a plurality of scanning lines arranged along a horizontal direction of a screen and a plurality of data lines arranged to cross the plurality of scanning lines, and a display driver that drives the display panel in response to a video signal,
The display driver includes:
a scan driver that drives the plurality of scan lines at timings corresponding to a plurality of scan timing signals;
a data driver including a scanning control signal output circuit that generates a plurality of driving signals based on the video signal, supplies the driving signals to the plurality of data lines, and outputs the plurality of scanning timing signals;
13. A display device, wherein said scanning control signal output circuit comprises an output buffer circuit according to claim 12. the output control section of at least one of the first to Mth buffer sections has a charge/discharge rate control section including a plurality of transistors connected in parallel to each other, receiving the bias voltage at the gates of the respective transistors and generating the current value by a composite current of currents corresponding to the bias voltages;
13. The output buffer circuit according to claim 12, wherein the charge/discharge rate control unit receives a drive capability control signal and changes the current value of the composite current by individually activating or deactivating each of the plurality of transistors in accordance with the drive capability control signal. The output control unit is
a first node for supplying a voltage corresponding to the input signal as a first voltage to a gate of the first transistor;
a second node that supplies a voltage corresponding to the input signal as a second voltage to a gate of the second transistor;
17. The output buffer circuit according to claim 16, wherein the charge/discharge rate control unit draws out the combined current corresponding to the bias voltage from the first node when the first transistor is in an on state, and supplies the combined current corresponding to the bias voltage to the second node when the second transistor is in an on state. a data driver for driving a display panel in response to a video data signal, the display panel including: first to m-th (m is an integer of 2 or more) data lines extending along a horizontal direction of a display screen and a plurality of gate lines extending along a vertical direction of the display screen; a scanning driver for receiving a gate timing signal and supplying a gate selection signal to each of the plurality of gate lines at a timing according to the gate timing signal; and (m/j) multiplexers provided for every j (j is an integer of 2 or more) of the first to m-th data lines, each having one input terminal, and for sequentially and selectively connecting each of the j data lines to the one input terminal in response to a data line selection signal,
a grayscale voltage output section that generates (m/j) grayscale voltage signals having voltage values corresponding to the luminance levels of the respective pixels based on the video data signal and supplies the grayscale voltage signals to the input terminals of the (m/j) multiplexers, respectively;
A drive setting unit that generates the drive capability control signal;
the output buffer circuit of claim 16;
the output buffer circuit outputs a predetermined number of output signals among the first to Mth output signals from the output terminal as the gate timing signal, and outputs the other output signals among the first to Mth output signals excluding the predetermined number of output signals from the output terminal as the data line selection signal;
A data driver characterized in that within a semiconductor IC chip constituting the data driver, the bias section and a plurality of the buffer sections are arranged at each of one end and the other end in the longitudinal direction of the semiconductor IC chip, and the drive setting section is arranged in a central portion within the semiconductor IC chip. a display panel including: first to m-th (m is an integer of 2 or more) data lines extending along a horizontal direction of a display screen, and a plurality of gate lines extending along a vertical direction of the display screen; a scan driver that receives a gate timing signal and supplies a gate selection signal to each of the plurality of gate lines at a timing according to the gate timing signal; and (m/j) multiplexers that are provided for every j (j is an integer of 2 or more) of the first to m-th data lines, each having one input terminal, and that sequentially and selectively connect each of the j data lines to the one input terminal according to a data line selection signal;
a data driver that drives the display panel in response to a video data signal,
The data driver includes:
a grayscale voltage output section that generates (m/j) grayscale voltage signals having voltage values corresponding to the luminance levels of the respective pixels based on the video data signal and supplies the grayscale voltage signals to the input terminals of the (m/j) multiplexers, respectively;
A drive setting unit that generates the drive capability control signal;
the output buffer circuit of claim 16;
the output buffer circuit outputs a predetermined number of the first to Mth output signals as the gate timing signal from the output terminal, and outputs the other output signals from the first to Mth output signals excluding the predetermined number of the output signals as the data line selection signal from the output terminal;
A display device characterized in that the bias section and a plurality of the buffer sections are arranged at each of one end and the other end in the longitudinal direction of the semiconductor IC chip constituting the data driver, and the drive setting section is arranged in the center of the semiconductor IC chip.

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