JP2024047542A - NITRIDE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING NITRIDE SEMICONDUCTOR DEVICE - Patent application - Google Patents

Abstract

In a nitride semiconductor device, the gate threshold voltage is increased while suppressing the effect on other device parameters.
[Solution] A nitride semiconductor device 10 includes an electron transit layer 16 made of a nitride semiconductor, an electron supply layer 18 formed on the electron transit layer 16 and made of a nitride semiconductor having a larger band gap than the electron transit layer 16, a gate layer 20 formed on the electron supply layer 18 and made of a nitride semiconductor containing acceptor-type impurities, a gate electrode 22 formed on the gate layer 20, and a source electrode 26 and a drain electrode 28 formed on the electron supply layer 18. The gate layer 20 includes an upper surface 20A in contact with the gate electrode 22. The upper surface 20A is a Ga-polar surface.
[Selected figure] Figure 2

Description

This disclosure relates to a nitride semiconductor device and a method for manufacturing a nitride semiconductor device.

Currently, high electron mobility transistors (HEMTs) using nitride semiconductors such as gallium nitride (GaN) are being commercialized. A nitride semiconductor HEMT includes, for example, an electron transit layer made of a gallium nitride (GaN) layer and an electron supply layer made of an aluminum gallium nitride (AlGaN) layer. The electron transit layer and the electron supply layer form a heterojunction, generating a two-dimensional electron gas (2DEG) that functions as a channel for the HEMT in the electron transit layer near the interface between the electron transit layer and the electron supply layer.

To achieve normally-off operation of a HEMT, it is known to provide a nitride semiconductor layer (e.g., a p-type GaN layer) containing acceptor-type impurities as a gate layer between the gate electrode and the electron transport layer. Patent Document 1 discloses such a normally-off HEMT.

JP 2017-73506 A

[overview]
In a normally-off type HEMT, a technique for controlling the gate threshold voltage while suppressing the influence on other device parameters (eg, on-resistance, maximum rated voltage, etc.) is desired.

A nitride semiconductor device according to one aspect of the present disclosure includes an electron transit layer made of a nitride semiconductor, an electron supply layer formed on the electron transit layer and made of a nitride semiconductor having a band gap larger than that of the electron transit layer, a gate layer formed on the electron supply layer and made of a nitride semiconductor containing an acceptor-type impurity, a gate electrode formed on the gate layer, and a source electrode and a drain electrode formed on the electron supply layer. The gate layer includes an upper surface in contact with the gate electrode. The upper surface is a Ga polar surface.

A method for manufacturing a nitride semiconductor device according to one aspect of the present disclosure includes forming an electron transit layer made of a nitride semiconductor, forming an electron supply layer made of a nitride semiconductor having a band gap larger than that of the electron transit layer on the electron transit layer, forming a gate layer made of a nitride semiconductor containing an acceptor-type impurity on the electron supply layer, forming a gate electrode on the gate layer, and forming a source electrode and a drain electrode on the electron supply layer. The gate layer includes an upper surface in contact with the gate electrode. The upper surface is a Ga-polar surface.

FIG. 1 is a schematic plan view of an exemplary nitride semiconductor device according to the first embodiment. FIG. 2 is a schematic cross-sectional view of the nitride semiconductor device taken along line F2-F2 in FIG. 3(a) and 3(b) are schematic diagrams showing the crystal structures of Ga-polar GaN and N-polar GaN, respectively. 4A to 4C are schematic cross-sectional views showing exemplary manufacturing steps for the nitride semiconductor device shown in FIG. FIG. 5 is a schematic cross-sectional view showing a manufacturing step subsequent to the step shown in FIG. FIG. 6 is a schematic cross-sectional view showing a manufacturing step subsequent to the step shown in FIG. FIG. 7 is a schematic cross-sectional view showing a manufacturing step subsequent to the step shown in FIG. FIG. 8 is a schematic cross-sectional view showing a manufacturing step subsequent to the step shown in FIG. FIG. 9 is a schematic cross-sectional view showing a manufacturing step subsequent to the step shown in FIG. FIG. 10 is a schematic cross-sectional view showing a manufacturing step subsequent to the step shown in FIG. FIG. 11 is a schematic cross-sectional view of an exemplary nitride semiconductor device according to a modified example. FIG. 12 is a schematic plan view of an exemplary nitride semiconductor device according to the second embodiment. FIG. 13 is a schematic cross-sectional view of the nitride semiconductor device taken along line F13-F13 in FIG. FIG. 14 is a schematic cross-sectional view showing an enlarged portion of FIG. FIG. 15 is a schematic cross-sectional view showing a portion relating to two gate layers and two gate electrodes in the nitride semiconductor device of FIG. FIG. 16 is a schematic cross-sectional view showing a nitride semiconductor device of a comparative example. 17A to 17C are schematic cross-sectional views showing exemplary manufacturing steps for the nitride semiconductor device of FIG. FIG. 18 is a schematic cross-sectional view showing a manufacturing process subsequent to FIG. FIG. 19 is a schematic cross-sectional view showing a manufacturing process subsequent to FIG. FIG. 20 is a schematic cross-sectional view showing a manufacturing process subsequent to FIG. FIG. 21 is a schematic cross-sectional view showing a manufacturing process subsequent to FIG. FIG. 22 is a schematic cross-sectional view showing a manufacturing process subsequent to FIG. FIG. 23 is a schematic cross-sectional view showing a manufacturing process subsequent to FIG. FIG. 24 is a schematic cross-sectional view showing a manufacturing process subsequent to FIG. FIG. 25 is a schematic cross-sectional view showing a manufacturing process subsequent to FIG. FIG. 26 is a schematic cross-sectional view showing a manufacturing process subsequent to FIG. FIG. 27 is a schematic cross-sectional view showing a manufacturing process subsequent to FIG. FIG. 28 is a schematic cross-sectional view showing a manufacturing process following FIG. FIG. 29 is a schematic cross-sectional view of an exemplary nitride semiconductor device according to the third embodiment. 30A to 30C are schematic cross-sectional views showing exemplary manufacturing steps for the nitride semiconductor device of FIG. FIG. 31 is a schematic cross-sectional view showing a manufacturing process subsequent to FIG. FIG. 32 is a schematic cross-sectional view of a nitride semiconductor device according to a modified example.

Detailed Description
Hereinafter, some embodiments of the nitride semiconductor device of the present disclosure will be described with reference to the accompanying drawings. Note that for simplicity and clarity of description, components shown in the drawings are not necessarily drawn to scale. Also, hatching lines may be omitted in cross-sectional views to facilitate understanding. The accompanying drawings are merely illustrative of embodiments of the present disclosure and should not be considered as limiting the present disclosure.

The following detailed description includes devices, systems, and methods embodying exemplary embodiments of the present disclosure. The detailed description is merely illustrative in nature and is not intended to limit the embodiments of the present disclosure or the application and uses of such embodiments.

First Embodiment
(Schematic structure of nitride semiconductor device)
FIG. 1 is a schematic plan view of an exemplary nitride semiconductor device 10 according to the first embodiment. FIG. 2 is a schematic cross-sectional view of the nitride semiconductor device 10 taken along line F2-F2 in FIG. 1. As shown in FIG. 2, the nitride semiconductor device 10 may include a semiconductor substrate 12 and a buffer layer 14 formed on the semiconductor substrate 12. The Z-axis direction of the mutually orthogonal XYZ axes shown in FIG. 1 and FIG. 2 is a direction orthogonal to the surface of the semiconductor substrate 12. Note that the term "planar view" used in this specification refers to viewing the nitride semiconductor device 10 from above along the Z-axis direction, unless otherwise expressly stated. The nitride semiconductor device 10 further includes an electron transit layer 16 and an electron supply layer 18 formed on the electron transit layer 16.

The semiconductor substrate 12 may be formed of silicon (Si), silicon carbide (SiC), gallium nitride (GaN), sapphire, or other substrate materials. In one example, the semiconductor substrate 12 may be a Si substrate. The thickness of the semiconductor substrate 12 may be, for example, 200 μm or more and 1500 μm or less.

The buffer layer 14 may include one or more nitride semiconductor layers. The electron transit layer 16 may be formed on the buffer layer 14. The buffer layer 14 may be made of any material that can suppress warping of the semiconductor substrate 12 caused by mismatching of the thermal expansion coefficient between the semiconductor substrate 12 and the electron transit layer 16, or the occurrence of cracks in the nitride semiconductor device 10. For example, the buffer layer 14 may include at least one of an aluminum nitride (AlN) layer, an aluminum gallium nitride (AlGaN) layer, and a graded AlGaN layer having a different aluminum (Al) composition. For example, the buffer layer 14 may be made of a single AlN layer, a single AlGaN layer, a layer having an AlGaN/GaN superlattice structure, a layer having an AlN/AlGaN superlattice structure, or a layer having an AlN/GaN superlattice structure.

In one example, the buffer layer 14 may include a first buffer layer which is an AlN layer formed on the semiconductor substrate 12, and a second buffer layer which is an AlGaN layer formed on the AlN layer. The first buffer layer may be an AlN layer having a thickness of, for example, 200 nm, while the second buffer layer may be formed by stacking graded AlGaN layers having a thickness of, for example, 300 nm multiple times. In order to suppress leakage current in the buffer layer 14, impurities may be introduced into a part of the buffer layer 14 to make the buffer layer 14 semi-insulating. In this case, the impurity may be, for example, carbon (C) or iron (Fe), and the concentration of the impurity may be, for example, 4×10 ¹⁶ cm ⁻³ or more.

The electron transit layer 16 is made of a nitride semiconductor. The electron transit layer 16 may be, for example, a GaN layer. The thickness of the electron transit layer 16 may be, for example, 0.5 μm or more and 2 μm or less. In order to suppress leakage current in the electron transit layer 16, impurities may be introduced into a part of the electron transit layer 16 to make the electron transit layer 16 semi-insulating except for the surface layer region. In this case, the impurity may be, for example, C. The impurity concentration in the electron transit layer 16 may be, for example, 4×10 ¹⁶ cm ⁻³ or more. That is, the electron transit layer 16 may include a plurality of GaN layers having different impurity concentrations, for example, a C-doped GaN layer and a non-doped GaN layer. In this case, the C-doped GaN layer may be formed on the buffer layer 14. The C-doped GaN layer may have a thickness of 0.3 μm or more and 2 μm or less. The C concentration in the C-doped GaN layer may be 5×10 ¹⁷ cm ⁻³ or more and 9×10 ¹⁹ cm ⁻³ or less. The non-doped GaN layer may be formed on the C-doped GaN layer and have a thickness of 0.05 μm or more and 0.4 μm or less. The non-doped GaN layer is in contact with the electron supply layer 18. In one example, the electron transit layer 16 may include a C-doped GaN layer having a thickness of 0.4 μm and a non-doped GaN layer having a thickness of 0.4 μm. The C concentration in the C-doped GaN layer may be about 2×10 ¹⁹ cm ⁻³ .

The electron supply layer 18 is made of a nitride semiconductor having a larger band gap than the electron transit layer 16. The electron supply layer 18 may be, for example, an AlGaN layer. Since the band gap increases as the Al composition increases, the electron supply layer 18, which is an AlGaN layer, has a larger band gap than the electron transit layer 16, which is a GaN layer. In one example, the electron supply layer 18 is made of Al _x Ga _1-x N, where x is 0.1<x<0.4, and more preferably 0.1<x<0.3. The electron supply layer 18 may have a thickness of 5 nm or more and 20 nm or less. In one example, the electron supply layer 18 may have a thickness of 8 nm or more.

The electron transit layer 16 and the electron supply layer 18 are made of nitride semiconductors having different lattice constants. Therefore, the nitride semiconductor (e.g., GaN) constituting the electron transit layer 16 and the nitride semiconductor (e.g., AlGaN) constituting the electron supply layer 18 form a heterojunction of a lattice mismatch system. Due to spontaneous polarization of the electron transit layer 16 and the electron supply layer 18 and piezoelectric polarization caused by crystal distortion near the heterojunction interface, the energy level of the conduction band of the electron transit layer 16 near the heterojunction interface is lower than the Fermi level. As a result, two-dimensional electron gas (2DEG) spreads in the electron transit layer 16 at a position close to the heterojunction interface between the electron transit layer 16 and the electron supply layer 18 (for example, within a range of about several nm from the interface). In addition, by increasing at least one of the Al composition and thickness of the electron supply layer 18, the sheet carrier density of the 2DEG generated in the electron transit layer 16 can be increased.

(Gate layer and gate electrode)
The nitride semiconductor device 10 further includes a gate layer 20 formed on the electron supply layer 18, and a gate electrode 22 formed on the gate layer 20. The gate layer 20 may be formed on a portion of the electron supply layer 18.

The gate layer 20 is made of a nitride semiconductor containing an acceptor-type impurity. In this embodiment, the gate layer 20 may be a gallium nitride layer (p-type GaN layer) doped with an acceptor-type impurity. The acceptor-type impurity may include at least one of zinc (Zn), magnesium (Mg), and carbon (C). The maximum concentration of the acceptor-type impurity in the gate layer 20 may be 7×10 ¹⁸ cm ⁻³ or more and 1×10 ²⁰ cm ⁻³ or less. In one example, the gate layer 20 may be GaN containing at least one of Mg and Zn as an impurity. Further details of the gate layer 20 will be described later.

The gate electrode 22 may be composed of one or more metal layers. In one example, the gate electrode 22 may be composed of a titanium nitride (TiN) layer. In another example, the gate electrode 22 may be composed of a first metal layer made of Ti and a second metal layer made of TiN provided on the first metal layer. The gate electrode 22 can form a Schottky junction with the gate layer 20. The gate electrode 22 can be formed in an area smaller than the gate layer 20 in a plan view. The thickness of the gate electrode 22 may be, for example, 50 nm or more and 200 nm or less.

The nitride semiconductor device 10 may further include a passivation layer 24 covering the electron supply layer 18, the gate layer 20, and the gate electrode 22. The passivation layer 24 has a first opening 24A and a second opening 24B spaced apart in the X-axis direction. The gate layer 20 is located between the first opening 24A and the second opening 24B. More specifically, the gate layer 20 may be located between the first opening 24A and the second opening 24B, and closer to the first opening 24A than the second opening 24B. The passivation layer 24 may be formed of at least one of silicon nitride (SiN), silicon dioxide (SiO ₂ ), silicon oxynitride (SiON), aluminum oxide (Al ₂ O ₃ ), AlN, and aluminum oxynitride (AlON). The thickness of the passivation layer 24 may be, for example, 80 nm or more and 150 nm or less.

(Source and drain electrodes)
The nitride semiconductor device 10 further includes a source electrode 26 in contact with the electron supply layer 18 through the first opening 24A, and a drain electrode 28 in contact with the electron supply layer 18 through the second opening 24B. The source electrode 26 and the drain electrode 28 can be formed of one or more metal layers (e.g., any combination of a Ti layer, a TiN layer, an Al layer, an AlSiCu layer, an AlCu layer, etc.).

At least a portion of the source electrode 26 is filled in the first opening 24A, and therefore can make ohmic contact with the 2DEG directly below the electron supply layer 18 through the first opening 24A. Similarly, at least a portion of the drain electrode 28 is filled in the second opening 24B, and therefore can make ohmic contact with the 2DEG directly below the electron supply layer 18 through the second opening 24B.

(field plate electrode)
The nitride semiconductor device 10 may optionally further include a field plate electrode 30 formed on the passivation layer 24 and extending at least partially into a region between the gate layer 20 and the drain electrode 28 in a plan view. In the example shown in FIG. 2, the field plate electrode 30 is formed integrally with the source electrode 26. Of the electrodes formed integrally, the source electrode 26 may include at least a portion embedded in the first opening 24A of the passivation layer 24, and the field plate electrode 30 may include the remaining portion. Note that the field plate electrode 30 may only be electrically connected to the source electrode 26 and may not necessarily be continuous with the source electrode 26.

The field plate electrode 30 is spaced apart from the drain electrode 28. The field plate electrode 30 may include an end 30A located between the drain electrode 28 (second opening 24B) and the gate layer 20 in a plan view.

The field plate electrode 30 can reduce electric field concentration near the end of the gate electrode 22 when a drain voltage is applied to the drain electrode 28 in a zero bias state where no gate voltage is applied to the gate electrode 22.

(Plane layout of nitride semiconductor device)
Next, an example of a planar layout of the nitride semiconductor device 10 will be described with reference to Fig. 1. In Fig. 1, the gate electrode 22, the source electrode 26, the drain electrode 28, and the field plate electrode 30 are depicted by dashed lines. In addition, for the passivation layer 24, a first opening 24A and a second opening 24B are depicted by solid lines, and the other portions are shown transparently.

As shown in FIG. 1, the gate layer 20 may be formed to surround the drain electrode 28 in a plan view. The gate layer 20 may include a body portion 60 extending in the Y-axis direction and a connection portion 62 connecting two adjacent body portions 60. The body portion 60 of the gate layer 20 is disposed between the first opening 24A and the second opening 24B of the passivation layer 24.

The gate electrode 22 is arranged so as to overlap the gate layer 20 in a planar view. Thus, like the gate layer 20, the gate electrode 22 may be formed so as to surround the drain electrode 28 in a planar view. The gate electrode 22 may include a main body portion 64 extending in the Y-axis direction and a connection portion 66 that connects two adjacent main body portions 64. The gate electrode 22 may have an area smaller than that of the gate layer 20 in a planar view.

The nitride semiconductor device 10 may include a gate wiring 68, a source wiring 70, and a drain wiring 72. In FIG. 1, the gate wiring 68, the source wiring 70, and the drain wiring 72 are depicted by dashed lines. The gate wiring 68, the source wiring 70, and the drain wiring 72 are located above the source electrode 26 and the drain electrode 28 in the Z-axis direction. The gate wiring 68 may extend in the X-axis direction and be disposed above the connection portion 66 of the gate electrode 22. The source wiring 70 and the drain wiring 72 may extend in the X-axis direction and be disposed so as to intersect with the source electrode 26 and the drain electrode 28 in a plan view, respectively. In one example, the gate electrode 22 may be electrically connected to the gate wiring 68 through a via 74 disposed on the connection portion 66. The source electrode 26 may be electrically connected to the source wiring 70 through a via 76. The drain electrode 28 may be electrically connected to the drain wiring 72 through a via 78.

The planar layout of the nitride semiconductor device 10 is not limited to the example shown in Fig. 1. Any other planar layout may be applied to the nitride semiconductor device 10.
(Details of the gate layer)
2, the gate layer 20 may include a first GaN layer 32 in contact with the gate electrode 22 and a second GaN layer 34 in contact with the electron supply layer 18. The first GaN layer 32 is made of Ga-polar GaN. The second GaN layer 34 is made of N-polar GaN.

In GaN crystals with a wurtzite structure, Ga atoms and N atoms are arranged slightly offset from each other in the c-axis direction extending in the [0001] direction, resulting in an asymmetric crystal structure. This asymmetry causes polarization, and as a result, the c-plane ((0001) plane) of the GaN crystal is a polar plane. GaN obtained by crystal growth proceeding so that Ga atoms are located at the top surface is called Ga-polar GaN, and the top surface of Ga-polar GaN is called a Ga-polar plane. On the other hand, GaN obtained by crystal growth proceeding so that N atoms are located at the top surface is called N-polar GaN, and the top surface of N-polar GaN is called an N-polar plane.

Figures 3(a) and 3(b) are schematic diagrams showing the crystal structures of Ga-polar GaN and N-polar GaN, respectively. The arrows in Figure 3 indicate the growth direction of the GaN crystal. As shown in Figure 3(a), in Ga-polar GaN, the Ga atoms are located above the N atoms in the growth direction. As shown in Figure 3(b), in N-polar GaN, the N atoms are located above the Ga atoms in the growth direction. Such arrangements of Ga atoms and N atoms can be identified by observing the GaN crystal with, for example, a spherical aberration corrected scanning transmission electron microscope.

Referring again to FIG. 2, the gate layer 20 includes an upper surface 20A in contact with the gate electrode 22 and a bottom surface 20B in contact with the electron supply layer 18. Since the gate layer 20 grows on the electron supply layer 18, the direction from the bottom surface 20B toward the upper surface 20A of the gate layer 20 (the Z-axis direction in FIG. 2) is the growth direction of the gate layer 20.

The top surface 20A of the gate layer 20 corresponds to the top surface of the first GaN layer 32, which is Ga-polar GaN. Therefore, the top surface 20A of the gate layer 20 is a Ga-polar surface. The gate electrode 22 contacts the top surface 20A of the gate layer 20, which is a Ga-polar surface. The top surface 20A of the gate layer 20 forms a Schottky junction with the gate electrode 22. On the other hand, the bottom surface 20B of the gate layer 20 corresponds to the bottom surface of the second GaN layer 34, which is N-polar GaN. Therefore, the bottom surface 20B of the gate layer 20 is a Ga-polar surface. The electron supply layer 18 contacts the bottom surface 20B of the gate layer 20, which is a Ga-polar surface.

In the gate layer 20, the polarity of the GaN crystal is inverted at the interface between the first GaN layer 32 and the second GaN layer 34. The interface between the first GaN layer 32 and the second GaN layer 34 does not necessarily have to be flat. An intermediate layer containing GaN of different polarities may be present between the first GaN layer 32 and the second GaN layer 34.

The first GaN layer 32 may be thinner than the second GaN layer 34. In one example, the gate layer 20 may have a thickness of 100 nm or more and less than 150 nm, and the first GaN layer 32 may have a thickness of 5 nm or more and less than 30 nm.

In one example, the first GaN layer 32 may contain a higher concentration of hydrogen than the second GaN layer 34. This may be due to a difference between the carrier gas used to grow the first GaN layer 32 and the carrier gas used to grow the second GaN layer 34, which will be described later.

The second GaN layer 34 may include a ridge portion 36 covered by the first GaN layer 32, and a first extension portion 38 and a second extension portion 40 that are thinner than the ridge portion 36. The ridge portion 36 includes an upper surface 34A of the second GaN layer 34. The first GaN layer 32 may be formed on the upper surface 34A of the second GaN layer 34. The ridge portion 36, the first extension portion 38, and the second extension portion 40 are all in contact with the electron supply layer 18. The first extension portion 38 and the second extension portion 40 extend outward from the ridge portion 36 in a planar view. In this disclosure, each of the first extension portion 38 and the second extension portion 40 is also simply referred to as an "extension portion." In another example, the gate layer 20 may include at least one of the first extension portion 38 and the second extension portion 40. By including at least one of the first extension portion 38 and the second extension portion 40 in the gate layer 20, localized electric field concentration in the gate layer 20 can be suppressed. Note that the first extension portion 38 and the second extension portion 40 are omitted in FIG. 1.

The first extension 38 extends from the ridge portion 36 toward the first opening 24A. A passivation layer 24 is disposed between the source electrode 26 embedded in the first opening 24A and the first extension 38.

The second extension 40 extends from the ridge portion 36 toward the second opening 24B. A passivation layer 24 is disposed between the drain electrode 28 embedded in the second opening 24B and the second extension 40.

The ridge portion 36 is between the first extension portion 38 and the second extension portion 40, and is formed integrally with the first extension portion 38 and the second extension portion 40. Due to the presence of the first extension portion 38 and the second extension portion 40, the bottom surface 20B of the gate layer 20 has a larger area than the top surface 20A. In the example shown in FIG. 2, the second extension portion 40 may extend longer toward the outside of the ridge portion 36 in a planar view than the first extension portion 38. That is, the second extension portion 40 may have a dimension in the X-axis direction larger than that of the first extension portion 38. The first extension portion 38 may have a dimension in the X-axis direction of, for example, 0.2 μm or more and 0.3 μm or less. On the other hand, the second extension portion 40 may have a dimension in the X-axis direction of, for example, 0.2 μm or more and 0.6 μm or less.

The ridge portion 36 corresponds to a relatively thick portion of the second GaN layer 34. The ridge portion 36 may have a thickness of, for example, 80 nm or more and 150 nm or less. In one example, the ridge portion 36 may have a thickness greater than 110 nm.

Each of the first extension portion 38 and the second extension portion 40 has a thickness that is smaller than the thickness of the ridge portion 36. In one example, each of the first extension portion 38 and the second extension portion 40 may have a thickness that is less than half the thickness of the ridge portion 36.

The first extension portion 38 may include a first step portion 42 having a substantially constant thickness, and a first intermediate portion 44 connecting the first step portion 42 to the ridge portion 36. In this specification, "substantially constant thickness" refers to the thickness being within the range of manufacturing variation (e.g., 20%). In one example, the thickness of the first step portion 42 may be 5 nm or more and 25 nm or less. The thickness of the first intermediate portion 44 may be greater than or equal to the thickness of the first step portion 42 and less than the thickness of the ridge portion 36.

Similarly, the second extension portion 40 may include a second step portion 46 having a substantially constant thickness, and a second intermediate portion 48 connecting the second step portion 46 to the ridge portion 36. In one example, the thickness of the second step portion 46 may be 5 nm or more and 25 nm or less. The thickness of the second intermediate portion 48 may be greater than or equal to the thickness of the second step portion 46 and less than the thickness of the ridge portion 36. The second step portion 46 may have the same thickness as the first step portion 42.

The first extension 38 is made of N-polar GaN. Therefore, the first extension 38 may include an upper surface 38A, at least a portion of which is an N-polar surface. More specifically, the portion of the upper surface 38A of the first extension 38 that is included in the first step portion 42 may be an N-polar surface.

The second extension portion 40 is made of N-polar GaN. Therefore, the second extension portion 40 may include an upper surface 40A, at least a portion of which is an N-polar surface. More specifically, the portion of the upper surface 40A of the second extension portion 40 that is included in the second step portion 46 may be an N-polar surface.

(Method of Manufacturing a Nitride Semiconductor Device)
Next, an example of a method for manufacturing the nitride semiconductor device 10 shown in Fig. 2 will be described. Fig. 4 to Fig. 10 are schematic cross-sectional views showing exemplary manufacturing steps for the nitride semiconductor device 10. For ease of understanding, in Fig. 4 to Fig. 10, the same components as those in Fig. 2 are denoted by the same reference numerals.

The method for manufacturing the nitride semiconductor device 10 includes forming an electron transit layer 16 made of a nitride semiconductor, and forming an electron supply layer 18 made of a nitride semiconductor having a larger band gap than the electron transit layer 16 on the electron transit layer 16.

As shown in FIG. 4, a buffer layer 14 may be formed on a semiconductor substrate 12, which may be, for example, a Si substrate, and then an electron transit layer 16 may be formed on the buffer layer 14. The buffer layer 14, the electron transit layer 16, and the electron supply layer 18 may be epitaxially grown using a metal organic chemical vapor deposition (MOCVD) method.

Although detailed illustration is omitted, in one example, the buffer layer 14 may be a multi-layer buffer layer. The multi-layer buffer layer may include an AlN layer (first buffer layer) formed on the semiconductor substrate 12 and a graded AlGaN layer (second buffer layer) formed on the AlN layer. The graded AlGaN layer may be formed, for example, by stacking three AlGaN layers with Al compositions of 75%, 50%, and 25%, in that order, from the side closest to the AlN layer.

The electron transit layer 16 formed on the buffer layer 14 may be a GaN layer. The electron supply layer 18 formed on the electron transit layer 16 may be an AlGaN layer. Therefore, the electron supply layer 18 is composed of a nitride semiconductor having a larger band gap than the electron transit layer 16.

The method for manufacturing the nitride semiconductor device 10 further includes forming a gate layer 20 made of a nitride semiconductor containing acceptor-type impurities on the electron supply layer 18, forming a gate electrode 22 on the gate layer 20, and forming a source electrode 26 and a drain electrode 28 on the electron supply layer 18.

FIG. 5 is a schematic cross-sectional view showing a manufacturing process following the process shown in FIG. 4. As shown in FIG. 5, a first nitride semiconductor layer 50 is formed on the electron supply layer 18, and then a second nitride semiconductor layer 52 is formed on the first nitride semiconductor layer 50. The first nitride semiconductor layer 50 and the second nitride semiconductor layer 52 can be epitaxially grown using the MOCVD method. The first nitride semiconductor layer 50 and the second nitride semiconductor layer 52 may be composed of a nitride semiconductor containing an acceptor-type impurity. In one example, the first nitride semiconductor layer 50 and the second nitride semiconductor layer 52 containing an acceptor-type impurity can be formed by doping with magnesium during the growth of the first nitride semiconductor layer 50 and the second nitride semiconductor layer 52. The amount of magnesium doped into the first nitride semiconductor layer 50 and the second nitride semiconductor layer 52 can be adjusted, for example, by controlling the flow rate of a doping gas (e.g., biscyclopentadienyl magnesium (Cp ₂ Mg)) introduced into the growth chamber, the growth temperature, and the like. In one example, the first nitride semiconductor layer 50 and the second nitride semiconductor layer 52 may contain magnesium as an impurity at a concentration of not less than 1×10 ¹⁸ cm ⁻³ and less than 1×10 ²⁰ cm ⁻³ .

The first nitride semiconductor layer 50 and the second nitride semiconductor layer 52 may both be formed of GaN. By controlling the carrier gas used in the growth of GaN, the first nitride semiconductor layer 50 and the second nitride semiconductor layer 52 with different polarities can be formed. Specifically, the first nitride semiconductor layer 50 is N-polarity GaN grown using nitrogen (N ₂ ) as a carrier gas, and the second nitride semiconductor layer 52 is Ga-polarity GaN grown using hydrogen (H ₂ ) as a carrier gas. The first GaN layer 32 shown in FIG. 2 is formed from a part of the second nitride semiconductor layer 52, while the second GaN layer 34 is formed from a part of the first nitride semiconductor layer 50.

When GaN crystal growth is started on the electron supply layer 18, N ₂ is used as a carrier gas. While N ₂ is used as a carrier gas, GaN crystal growth proceeds so that N atoms are located on the top surface. Next, by switching the carrier gas from N ₂ to H ₂ , GaN crystal growth proceeds so that Ga atoms are located on the top surface. This allows the first nitride semiconductor layer 50, which is N-polarity GaN, to be formed on the electron supply layer 18, and then the second nitride semiconductor layer 52, which is Ga-polarity GaN, to be formed on the first nitride semiconductor layer 50. In one example, the second nitride semiconductor layer 52 may be formed to be thinner than the first nitride semiconductor layer 50. The thickness uniformity of the first nitride semiconductor layer 50, which is N-polarity GaN, is better than that of the second nitride semiconductor layer 52, which is Ga-polarity GaN.

Figure 6 is a schematic cross-sectional view showing a manufacturing process following the process shown in Figure 5. As shown in Figure 6, a gate electrode 22 is formed on the second nitride semiconductor layer 52. The gate electrode 22 can be formed by forming a metal layer (not shown) on the second nitride semiconductor layer 52 and then selectively removing the metal layer by lithography and etching.

The gate electrode 22 is formed on the second nitride semiconductor layer 52, which is Ga-polar GaN. The second nitride semiconductor layer 52, which is Ga-polar GaN, includes an upper surface 52A, which is a Ga-polar surface. Therefore, the gate electrode 22 is in contact with the upper surface 52A, which is a Ga-polar surface, of the second nitride semiconductor layer 52.

7 is a schematic cross-sectional view showing a manufacturing process following the process shown in FIG. 6. As shown in FIG. 7, a mask 54 is formed to cover the upper and side surfaces of the gate electrode 22 and the second nitride semiconductor layer 52 in the region around the gate electrode 22, and then the first nitride semiconductor layer 50 and the second nitride semiconductor layer 52 are etched using the mask 54. As a result, the first nitride semiconductor layer 50 and the second nitride semiconductor layer 52 located under the mask 54 remain even after etching, and the ridge portion 36 of the second GaN layer 34 and the first GaN layer 32 on the ridge portion 36 described with reference to FIG. 2 are formed. The second nitride semiconductor layer 52 not covered by the mask 54 is removed by etching. The thickness of the first nitride semiconductor layer 50 in the region not covered by the mask 54 may be reduced by etching to half or less of the thickness of the ridge portion 36. The mask 54 is removed after etching.

8 is a schematic cross-sectional view showing a manufacturing process following the process shown in FIG. 7. As shown in FIG. 8, a mask 56 is formed to cover the upper and side surfaces of the gate electrode 22, the ridge portion 36, and the first nitride semiconductor layer 50 in the region around the ridge portion 36, and then the first nitride semiconductor layer 50 is etched using the mask 56. As a result, the first nitride semiconductor layer 50 located under the mask 56 remains after etching, and the second GaN layer 34 including the ridge portion 36, the first extension portion 38, and the second extension portion 40 is formed. The mask 56 is removed after etching. The etching process shown in FIG. 7 and FIG. 8 can obtain the gate layer 20 including the first GaN layer 32 and the second GaN layer 34. The shape of the gate layer 20 can change depending on the etching conditions. The first extension portion 38 may include a first step portion 42 having a substantially constant thickness and a first intermediate portion 44 connecting the first step portion 42 to the ridge portion 36. The second extension portion 40 may include a second step portion 46 having a substantially constant thickness and a second intermediate portion 48 that connects the second step portion 46 to the ridge portion 36.

FIG. 9 is a schematic cross-sectional view showing a manufacturing process subsequent to the process shown in FIG. 8. As shown in FIG. 9, the method for manufacturing the nitride semiconductor device 10 further includes forming a passivation layer 24 so as to cover the entire exposed surfaces of the electron supply layer 18, the gate layer 20, and the gate electrode 22. In one example, the passivation layer 24 may be a SiN layer formed by a low-pressure chemical vapor deposition (LPCVD) method.

The passivation layer 24 covers a portion of the upper surface 20A of the gate layer 20. The upper surface 20A of the gate layer 20 is a Ga-polar surface. The passivation layer 24 also covers the upper surface 38A of the first extension 38 and the upper surface 40A of the second extension 40. The first extension 38 and the second extension 40 are part of the second GaN layer 34 made of N-polar GaN. Thus, the first extension 38 includes an upper surface 38A at least partially of which is an N-polar surface, and similarly, the second extension 40 includes an upper surface 40A at least partially of which is an N-polar surface. In this way, the surface of the gate layer 20 covered by the passivation layer 24 includes both a Ga-polar surface and an N-polar surface.

10 is a schematic cross-sectional view showing a manufacturing process following the process shown in FIG. 9. As shown in FIG. 10, a first opening 24A and a second opening 24B are formed in the passivation layer 24, and then a metal layer 58 is formed to cover the passivation layer 24. In this process, a first opening 24A and a second opening 24B are formed to penetrate the passivation layer 24 and expose the electron supply layer 18. The first opening 24A and the second opening 24B are formed so that the gate layer 20 is located between the first opening 24A and the second opening 24B. The gate layer 20 may be located closer to the first opening 24A than the second opening 24B. The metal layer 58 is formed to fill the first opening 24A and the second opening 24B and to contact the electron supply layer 18 through the first opening 24A and the second opening 24B. In one example, the metal layer 58 may include at least one of a Ti layer, a TiN layer, an Al layer, an AlSiCu layer, and an AlCu layer.

Then, the metal layer 58 is selectively removed by lithography and etching to form the source electrode 26, the drain electrode 28, and the field plate electrode 30 shown in FIG. 2. As a result, the nitride semiconductor device 10 shown in FIG. 2 can be obtained.

In this manner, forming the gate layer 20 includes forming a first nitride semiconductor layer 50 which is N-polarity GaN grown on the electron supply layer 18 using _N2 as a carrier gas, and forming a second nitride semiconductor layer 52 which is Ga-polarity GaN grown on the first nitride semiconductor layer 50 using _H2 as a carrier gas.

(Functions of the nitride semiconductor device)
The operation of the nitride semiconductor device 10 of this embodiment will be described below. When a voltage exceeding the gate threshold voltage is applied to the gate electrode 22 of the nitride semiconductor device 10, a channel by 2DEG is formed in the electron transit layer 16, and conduction occurs between the source and the drain. On the other hand, at zero bias, 2DEG is not formed in at least a part of the region of the electron transit layer 16 located under the gate layer 20. This is because the gate layer 20 contains acceptor-type impurities, which raises the energy levels of the electron transit layer 16 and the electron supply layer 18, resulting in depletion of the 2DEG. This realizes a normally-off operation of the nitride semiconductor device 10.

The gate threshold voltage of the nitride semiconductor device 10 depends on the Schottky barrier formed between the gate electrode 22 and the gate layer 20, in addition to the energy barrier formed by the electron supply layer 18. One method for increasing the gate threshold voltage of the nitride semiconductor device 10 is to increase the Schottky barrier height between the gate electrode 22 and the gate layer 20. The Schottky barrier height between the gate electrode 22 and the gate layer 20 is affected by the state of the upper surface 20A of the gate layer 20 in contact with the gate electrode 22. When a metal layer and a GaN layer are joined together, the Schottky barrier height between the metal layer and the GaN layer is greater when the surface of the GaN layer in contact with the metal layer is a Ga polar surface than when the surface is an N polar surface.

In this regard, in the nitride semiconductor device 10 of this embodiment, the upper surface 20A of the gate layer 20 in contact with the gate electrode 22 is a Ga polar surface. Therefore, the Schottky barrier height between the gate electrode 22 and the gate layer 20 can be increased. In addition, the effect of making the upper surface 20A of the gate layer 20 a Ga polar surface on device parameters other than the gate threshold voltage (e.g., on-resistance, maximum rated voltage, etc.) is relatively small. Therefore, according to the nitride semiconductor device 10 of this embodiment, the gate threshold voltage can be increased while suppressing the effect on other device parameters.

The nitride semiconductor device 10 of this embodiment has the following advantages.
(1-1) The gate layer 20 includes an upper surface 20A in contact with the gate electrode 22, and the upper surface 20A is a Ga polar surface. This makes it possible to increase the Schottky barrier height between the gate electrode 22 and the gate layer 20, thereby making it possible to increase the gate threshold voltage while suppressing the effects on other device parameters.

(1-2) The gate layer 20 may include a first GaN layer 32 in contact with the gate electrode 22 and a second GaN layer 34 in contact with the electron supply layer 18. The first GaN layer 32 is made of Ga-polar GaN, and the second GaN layer 34 is made of N-polar GaN. The gate layer 20 includes the second GaN layer 34 made of N-polar GaN, which has better thickness uniformity than the first GaN layer 32 made of Ga-polar GaN. Therefore, the thickness uniformity of the gate layer 20 can be improved compared to when the gate layer 20 is made of only Ga-polar GaN.

(1-3) The second GaN layer 34 may be thicker than the first GaN layer 32. The gate layer 20 contains a greater proportion of the second GaN layer 34 made of N-polarity GaN, which has better thickness uniformity than the first GaN layer 32 made of Ga-polarity GaN. Therefore, the thickness uniformity of the gate layer 20 can be further improved.

(1-4) The gate layer 20 may have a thickness of 100 nm or more and less than 150 nm, and the first GaN layer 32 may have a thickness of 5 nm or more and less than 30 nm. This allows the gate threshold voltage to be increased while maintaining the desired uniformity in the thickness of the gate layer 20.

(1-5) The second GaN layer 34 may include a ridge portion 36 that is in contact with the electron supply layer 18 and is covered by the first GaN layer 32, and an extension portion (first extension portion 38 and/or second extension portion 40) that is in contact with the electron supply layer 18 and extends outward from the ridge portion 36 in a planar view. The first extension portion 38 and the second extension portion 40 are thinner than the ridge portion 36. By including the first extension portion 38 and/or the second extension portion 40 that are thinner than the ridge portion 36 in the second GaN layer 34, local electric field concentration in the gate layer 20 can be suppressed. Therefore, the gate reliability of the nitride semiconductor device 10 can be improved.

<Example of changing the gate layer>
Fig. 11 is a schematic cross-sectional view of an exemplary nitride semiconductor device 100 for explaining a modification of the gate layer. In Fig. 11, the same components as those in the nitride semiconductor device 10 shown in Fig. 2 are denoted by the same reference numerals. Further, detailed description of the same components as those in the nitride semiconductor device 10 will be omitted.

As shown in FIG. 11, the nitride semiconductor device 100 includes a gate layer 102 formed on an electron supply layer 18. The gate layer 102 includes an upper surface 102A in contact with the gate electrode 22 and a bottom surface 102B in contact with the electron supply layer 18. Since the gate layer 102 grows on the electron supply layer 18, the direction from the bottom surface 102B toward the upper surface 102A of the gate layer 102 (the Z-axis direction in FIG. 11) is the growth direction of the gate layer 102.

The gate layer 102 is made of Ga-polar GaN. Therefore, the top surface 102A of the gate layer 102 is a Ga-polar surface. The gate electrode 22 is in contact with the top surface 102A of the gate layer 102, which is a Ga-polar surface. The top surface 102A of the gate layer 102 forms a Schottky junction with the gate electrode 22. On the other hand, the bottom surface 102B of the gate layer 102 is an N-polar surface. The electron supply layer 18 is in contact with the bottom surface 102B of the gate layer 102, which is an N-polar surface.

In the nitride semiconductor device 100, the upper surface 102A of the gate layer 102 in contact with the gate electrode 22 is a Ga polar surface, so the Schottky barrier height between the gate electrode 22 and the gate layer 102 can be increased. In addition, the effect of making the upper surface 102A of the gate layer 102 a Ga polar surface on device parameters other than the gate threshold voltage is relatively small. Therefore, the gate threshold voltage can be increased while suppressing the effect on other device parameters.

The gate layer 102 may include a ridge portion 104 including the upper surface 102A of the gate layer 102, and a first extension portion 106 and a second extension portion 108 that are thinner than the ridge portion 104. The gate electrode 22 is formed on the ridge portion 104. The ridge portion 104, the first extension portion 106, and the second extension portion 108 are all in contact with the electron supply layer 18. The first extension portion 106 and the second extension portion 108 extend outward from the ridge portion 104 in a planar view. In this disclosure, each of the first extension portion 106 and the second extension portion 108 is also simply referred to as an "extension portion." In another example, the gate layer 102 may include at least one of the first extension portion 106 and the second extension portion 108. By including at least one of the first extension portion 106 and the second extension portion 108 in the gate layer 102, localized electric field concentration in the gate layer 102 can be suppressed. Therefore, the gate reliability of the nitride semiconductor device 100 can be improved.

The first extension 106 extends from the ridge portion 104 toward the first opening 24A. A passivation layer 24 is disposed between the first extension 106 and the source electrode 26 embedded in the first opening 24A.

The second extension 108 extends from the ridge portion 104 toward the second opening 24B. A passivation layer 24 is disposed between the drain electrode 28 embedded in the second opening 24B and the second extension 108.

The ridge portion 104 is between the first extension portion 106 and the second extension portion 108, and is formed integrally with the first extension portion 106 and the second extension portion 108. Due to the presence of the first extension portion 106 and the second extension portion 108, the bottom surface 102B of the gate layer 102 has a larger area than the top surface 102A. In the example shown in FIG. 11, the second extension portion 108 may extend longer toward the outside of the ridge portion 104 in a planar view than the first extension portion 106. That is, the second extension portion 108 may have a dimension in the X-axis direction that is larger than that of the first extension portion 106. The first extension portion 106 may have a dimension in the X-axis direction of, for example, 0.2 μm or more and 0.3 μm or less. On the other hand, the second extension portion 108 may have a dimension in the X-axis direction of, for example, 0.2 μm or more and 0.6 μm or less.

The ridge portion 104 corresponds to a relatively thick portion of the gate layer 102. The ridge portion 104 may have a thickness of, for example, 80 nm or more and 150 nm or less. In one example, the ridge portion 104 may have a thickness greater than 110 nm.

Each of the first extension portion 106 and the second extension portion 108 has a thickness that is smaller than the thickness of the ridge portion 104. In one example, each of the first extension portion 106 and the second extension portion 108 may have a thickness that is less than half the thickness of the ridge portion 104.

The first extension portion 106 may include a first step portion 110 having a substantially constant thickness, and a first intermediate portion 112 connecting the first step portion 110 to the ridge portion 104. In one example, the thickness of the first step portion 110 may be 5 nm or more and 25 nm or less. The thickness of the first intermediate portion 112 may be greater than or equal to the thickness of the first step portion 110 and less than the thickness of the ridge portion 104.

Similarly, the second extension portion 108 may include a second step portion 114 having a substantially constant thickness, and a second intermediate portion 116 connecting the second step portion 114 to the ridge portion 104. In one example, the thickness of the second step portion 114 may be 5 nm or more and 25 nm or less. The thickness of the second intermediate portion 116 may be greater than or equal to the thickness of the second step portion 114 and less than the thickness of the ridge portion 104. The second step portion 114 may have the same thickness as the first step portion 110.

The first extension 106 is made of Ga-polar GaN. Therefore, the first extension 106 may include an upper surface 106A, at least a portion of which is a Ga-polar surface. More specifically, the portion of the upper surface 106A of the first extension 106 that is included in the first step portion 110 may be a Ga-polar surface.

The second extension portion 108 is composed of Ga-polar GaN. Therefore, the second extension portion 108 may include an upper surface 108A, at least a portion of which is a Ga-polar surface. More specifically, the portion of the upper surface 108A of the second extension portion 108 that is included in the second step portion 114 may be a Ga-polar surface.

The method for manufacturing the nitride semiconductor device 100 may be similar to the method for manufacturing the nitride semiconductor device 10, except that in the manufacturing process shown in FIG. 5, the first nitride semiconductor layer 50 is not formed, and the second nitride semiconductor layer 52 is formed directly on the electron supply layer 18. The method for manufacturing the nitride semiconductor device 100 does not require control of the carrier gas to invert the polarity of the GaN layer, and therefore the complexity of the manufacturing process can be reduced.

<Other Modifications of the First Embodiment>
The above-described embodiment and modified examples can be implemented with the following modifications.
In the GaN crystal growth for forming the gate layer 20, instead of switching the carrier gas from _N2 to _H2 , the ratio of _H2 in the carrier gas may be controlled to be gradually increased relative to _N2 . In this case, an intermediate layer containing GaN of different polarities may be present between the first GaN layer 32 and the second GaN layer 34.

In the example shown in FIG. 2, the second GaN layer 34 may not include the first extension portion 38 and the second extension portion 40. That is, the second GaN layer 34 may be formed to have a substantially uniform thickness. In that case, the second GaN layer 34 may have the same width in the X-axis direction as the first GaN layer 32.

- In the example shown in FIG. 11, the gate layer 102 may not include the first extension portion 106 and the second extension portion 108. In other words, the gate layer 102 may be formed to have a substantially uniform thickness.

Second Embodiment
In a nitride semiconductor device, for example, when a positive voltage is applied to a gate electrode, an electric field may locally concentrate in a portion of the electron supply layer near an end of the gate layer. Such local electric field concentration may cause a decrease in the breakdown voltage of the nitride semiconductor device. According to the nitride semiconductor device of the second and third embodiments described below, such electric field concentration can be alleviated.

(Cross-sectional structure of nitride semiconductor device)
Fig. 12 is a schematic plan view of an illustrative nitride semiconductor device 210A according to the second embodiment. Fig. 13 is a schematic cross-sectional view of the nitride semiconductor device 210A taken along line F13-F13 in Fig. 12. Fig. 14 is a schematic cross-sectional view showing an enlarged portion of Fig. 13. Note that Figs. 13 and 14 show the configuration related to one gate layer 222 and gate electrode 224 included in the nitride semiconductor device 210A.

The term "planar view" used in this embodiment refers to viewing the nitride semiconductor device 210A in the Z-axis direction of the mutually orthogonal XYZ axes shown in FIG. 13. For convenience, in the nitride semiconductor device 210A shown in FIG. 13, the +Z direction is defined as up, the -Z direction as down, the +X direction as right, and the -X direction as left. Unless otherwise explicitly stated, "planar view" refers to viewing the nitride semiconductor device 210A from above along the Z-axis.

The nitride semiconductor device 210A can be configured as a high electron mobility transistor (HEMT) using a nitride semiconductor.
13, the nitride semiconductor device 210A includes a substrate 212, a buffer layer 214 formed on the substrate 212, an electron transit layer 216 formed on the buffer layer 214, and an electron supply layer 218 formed on the electron transit layer 216. The nitride semiconductor device 210A further includes a gate layer 222 formed on the electron supply layer 218, and a gate electrode 224 formed on the gate layer 222.

The substrate 212 may be, for example, a silicon (Si) substrate. The thickness of the substrate 212 may be, for example, 200 μm or more and 1500 μm or less. The substrate 212 includes an upper surface 212S. Instead of a Si substrate, the substrate 212 may be a silicon carbide (SiC) substrate, a gallium nitride (GaN) substrate, a sapphire substrate, or the like. In the following description, unless otherwise explicitly stated, the thickness refers to the dimension along the Z direction in FIG. 13 and FIG. 14.

The buffer layer 214 may be made of any material capable of suppressing the occurrence of wafer warpage or cracks due to mismatch in thermal expansion coefficient between the substrate 212 and the electron transit layer 216. The buffer layer 214 may also include one or more nitride semiconductor layers. The buffer layer 214 may include, for example, at least one of an aluminum nitride (AlN) layer, an aluminum gallium nitride (AlGaN) layer, and a graded AlGaN layer having different aluminum (Al) compositions. For example, the buffer layer 214 may be made of a single film of AlN, a single film of AlGaN, a film having an AlGaN/GaN superlattice structure, a film having an AlN/AlGaN superlattice structure, or a film having an AlN/GaN superlattice structure.

In one example, the buffer layer 214 may include a first buffer layer which is an AlN layer formed on the substrate 212, and a second buffer layer which is an AlGaN layer formed on the AlN layer (first buffer layer). The first buffer layer may be an AlN layer having a thickness of, for example, 200 nm, and the second buffer layer may be a graded AlGaN layer having a thickness of, for example, 300 nm. In order to suppress leakage current in the buffer layer 214, impurities may be introduced into a portion of the buffer layer 214 to make the buffer layer 214 semi-insulating except for the surface region. In this case, the impurity is, for example, carbon (C) or iron (Fe). The impurity concentration may be, for example, 4×10 ¹⁶ cm ⁻³ or more.

The electron travel layer 216 is formed on the buffer layer 214 formed on the substrate 212, and therefore can be said to be formed above the substrate 212 or on the substrate 212. The electron travel layer 216 may be, for example, a GaN layer. The thickness of the electron travel layer 216 may be, for example, 0.5 μm or more and 2 μm or less. The electron travel layer 216 of the second embodiment includes a first semiconductor layer 216A formed on the buffer layer 214 and a second semiconductor layer 216B formed on the first semiconductor layer 216A. The first semiconductor layer 216A can be said to be formed above the substrate 212 or on the substrate 212. The first semiconductor layer 216A and the second semiconductor layer 216B are GaN layers with different impurity concentrations.

In one example, the first semiconductor layer 216A is a C-doped GaN layer containing carbon (C) as an impurity, and the second semiconductor layer 216B is a non-doped GaN layer. The first semiconductor layer 216A may be 0.5 μm or more and 2 μm or less. The C concentration in the first semiconductor layer 216A may be 5×10 ¹⁷ cm ⁻³ or more and 9×10 ¹⁹ cm ⁻³ or less. The second semiconductor layer 216B may be 0.05 μm or more and 0.4 μm or less. The second semiconductor layer 216B is in contact with the electron supply layer 218. One or more nitride semiconductor layers may be included between the buffer layer 214 and the first semiconductor layer 216A. In one example, the electron travel layer 216 includes a first semiconductor layer 216A having a thickness of 0.4 μm and a second semiconductor layer 216B having a thickness of 0.4 μm. The C concentration in the first semiconductor layer 216A may be about 2×10 ¹⁹ cm ⁻³ .

The electron supply layer 218 is made of a nitride semiconductor having a larger band gap than the electron transit layer 216. The electron supply layer 218 may be, for example, an AlGaN layer. In a nitride semiconductor, the higher the Al composition, the larger the band gap. Therefore, the electron supply layer 218, which is an AlGaN layer, has a larger band gap than the electron transit layer 216, which is a GaN layer. In one example, the electron supply layer 218 is made of Al _x Ga _1-x N. That is, the electron supply layer 218 can be said to be an Al _x Ga _1-x N layer. x is 0<x<0.4, and more preferably 0.1<x<0.3. The electron supply layer 218 can have a thickness of, for example, 5 nm or more and 20 nm or less.

The electron transit layer 216 and the electron supply layer 218 have different lattice constants in the bulk region. Therefore, the electron transit layer 216 and the electron supply layer 218 form a lattice-mismatched heterojunction. Due to spontaneous polarization of the electron transit layer 216 and the electron supply layer 218 and piezoelectric polarization caused by compressive stress applied to the heterojunction of the electron transit layer 216, the energy level of the conduction band of the electron transit layer 216 near the heterojunction interface between the electron transit layer 216 and the electron supply layer 218 becomes lower than the Fermi level. As a result, a two-dimensional electron gas (2DEG) 220 spreads in the electron transit layer 216 near the heterojunction interface between the electron transit layer 216 and the electron supply layer 218 (for example, at a distance of about several nm from the interface).

The gate layer 222 is formed on the electron supply layer 218. The gate layer 222 is formed to extend in the Y direction. The nitride semiconductor device 210A includes a plurality of gate layers 222 arranged in the X direction (see FIG. 15). The gate layer 222 has a band gap smaller than that of the electron supply layer 218 and is made of a nitride semiconductor containing an acceptor-type impurity. The gate layer 222 may be made of any material having a band gap smaller than that of the electron supply layer 218, which is, for example, an AlGaN layer. In one example, the gate layer 222 is a GaN layer (p-type GaN layer) doped with an acceptor-type impurity. The acceptor-type impurity may include at least one of magnesium (Mg), zinc (Zn), and C. The maximum concentration of the acceptor-type impurity in the gate layer 222 may be, for example, 1×10 ¹⁸ cm ⁻³ or more and 1×10 ²⁰ cm ⁻³ or less. The gate layer 222 may be, for example, 50 nm to 200 nm thick.

The gate electrode 224 is disposed on the entire upper surface 222S of the gate layer 222. The gate electrode 224 is formed on the upper surface 222S of the gate layer 222. The gate electrode 224 forms a Schottky junction with the gate layer 222. The gate electrode 224 may be composed of one or more metal layers. In one example, the gate electrode 224 is composed of a titanium nitride (TiN) layer. In another example, the gate electrode 224 may be composed of a first metal layer made of Ti and a second metal layer made of TiN provided on the first metal layer. The gate electrode 224 may have a thickness of, for example, 50 nm to 200 nm.

The nitride semiconductor device 210A further includes a passivation layer 226. The passivation layer 226 covers the electron supply layer 218, the gate layer 222, and the gate electrode 224. The passivation layer 226 may be made of a material including any one of silicon dioxide (SiO ₂ ), silicon nitride (SiN), silicon oxynitride (SiON), alumina (Al ₂ O ₃ ), AlN, and aluminum oxynitride (AlON). In one example, the passivation layer 226 is formed of a material including SiO ₂ .

The passivation layer 226 includes a flat upper surface 226S. The passivation layer 226 includes a source opening 2261 and a drain opening 2262. The source opening 2261 penetrates the passivation layer 226 from the upper surface 226S to the upper surface of the electron supply layer 218. The source opening 2261 exposes the upper surface of the electron supply layer 218 as a source connection region 2181. The drain opening 2262 penetrates the passivation layer 226 from the upper surface 226S to the upper surface of the electron supply layer 218. The drain opening 2262 exposes the upper surface of the electron supply layer 218 as a drain connection region 2182. The gate layer 222 is located between the source opening 2261 and the drain opening 2262.

The nitride semiconductor device 210 A further includes a source electrode 232 and a drain electrode 234 .
The source electrode 232 is in contact with a source connection region 2181 of the electron supply layer 218 through a source opening 2261 of the passivation layer 226. The source electrode 232 is in ohmic contact with the 2DEG 220 directly below the electron supply layer 218. The drain electrode 234 is in contact with a drain connection region 2182 of the electron supply layer 218 through a drain opening 2262 of the passivation layer 226. The drain electrode 234 is in ohmic contact with the 2DEG 220 directly below the electron supply layer 218.

The source electrode 232 and the drain electrode 234 are formed of one or more metal layers using at least one of, for example, a Ti layer, a TiN layer, an Al layer, an AlSiCu layer, and an AlCu layer. For example, the source electrode 232 and the drain electrode 234 are formed of the same material.

A portion of the source electrode 232 is filled in the source opening 2261 of the passivation layer 226. A portion of the drain electrode 234 is filled in the drain opening 2262 of the passivation layer 226. The source electrode 232 includes a filling region filled in the source opening 2261 and an upper region formed integrally with the filling region and positioned around the source opening 2261 in a plan view.

The nitride semiconductor device 210A may include a source field plate portion 236 that is continuous with the source electrode 232. The source field plate portion 236 is formed integrally with the upper region of the source electrode 232, and is provided on the upper surface 226S of the passivation layer 226 so as to cover the entire gate layer 222 in a plan view. The source field plate portion 236 may be configured as part of the source electrode 232.

The source field plate portion 236 has an end 2361 near the drain electrode 234. This end 2361 is located between the drain electrode 234 and the gate electrode 224 in a plan view. When a high voltage is applied between the source and drain with the gate-source voltage at 0V, the source field plate portion 236 extends the depletion layer toward the 2DEG 220 directly below the source field plate portion 236, thereby playing a role in mitigating electric field concentration near the end of the gate electrode 224 and near the end of the gate layer 222.

(Plane layout of nitride semiconductor device)
Next, an example of a planar layout of the nitride semiconductor device 210A will be described with reference to Fig. 12. In Fig. 12, the gate electrode 224, the source electrode 232, the drain electrode 234, and the source field plate portion 236 are drawn with dashed lines. In addition, for the passivation layer 226, the source opening 2261 and the drain opening 2262 are drawn with solid lines, and the other portions are shown transparently.

12, the gate layer 222 may be formed to surround the drain electrode 234 in a plan view. The gate layer 222 may include a body portion 80 extending in the Y-axis direction and a connection portion 82 connecting two adjacent body portions 80. The body portion 80 of the gate layer 222 is disposed between the source opening 2261 and the drain opening 2262 of the passivation layer 226.

The gate electrode 224 is disposed so as to overlap the gate layer 222 in a planar view. Thus, like the gate layer 222, the gate electrode 224 may be formed so as to surround the drain electrode 234 in a planar view. The gate electrode 224 may include a main body portion 84 extending in the Y-axis direction and a connection portion 86 that connects two adjacent main body portions 84. The gate electrode 224 may have an area smaller than that of the gate layer 222 in a planar view.

The nitride semiconductor device 210A may include a gate wiring 88, a source wiring 90, and a drain wiring 92. In FIG. 12, the gate wiring 88, the source wiring 90, and the drain wiring 92 are depicted by dashed lines. The gate wiring 88, the source wiring 90, and the drain wiring 92 are located above the source electrode 232 and the drain electrode 234 in the Z-axis direction. The gate wiring 88 may extend in the X-axis direction and be disposed above the connection portion 86 of the gate electrode 224. The source wiring 90 and the drain wiring 92 may extend in the X-axis direction and be disposed so as to intersect with the source electrode 232 and the drain electrode 234 in a plan view, respectively. In one example, the gate electrode 224 may be electrically connected to the gate wiring 88 through a via 94 disposed on the connection portion 86. The source electrode 232 may be electrically connected to the source wiring 90 through a via 96. The drain electrode 234 may be electrically connected to the drain wiring 92 through a via 98.

The planar layout of the nitride semiconductor device 210A is not limited to the example shown in Fig. 12. Any other planar layout may be applied to the nitride semiconductor device 210A.
(Exemplary Structure of Gate Layer and Gate Electrode)
As shown in Fig. 14, the gate layer 222 has, for example, a trapezoidal shape in cross section. The gate layer 222 includes an upper surface 222S and a lower surface 222R facing the opposite side to the upper surface 222S. The lower surface 222R of the gate layer 222 contacts the upper surface 218S of the electron supply layer 218. Here, the Z direction corresponds to the thickness direction of the gate layer 222. Fig. 14 shows a cross-sectional structure of the gate layer 222 cut by a plane along the thickness direction and width direction of the gate layer 222. The thickness of the gate layer 222 is the distance from the upper surface 222S to the lower surface 222R of the gate layer 222. The thickness of the gate layer 222 can be determined in consideration of various parameters such as the gate breakdown voltage.

The lower surface 222R of the gate layer 222 has a larger area than the upper surface 222S of the gate layer 222. In other words, the gate layer 222 has a shape in which the width W12 of the upper surface 222S in the X direction is smaller than the width W11 of the lower surface 222R in the X direction. The gate length is determined by the width W11 of the lower surface 222R of the gate layer 222. The width W11 of the lower surface 222R may be, for example, 0.2 μm or more and 0.5 μm or less. Preferably, the width W11 of the lower surface 222R may be, for example, 0.3 μm.

The gate layer 222 includes a source-side gate surface 2221 disposed closer to the source electrode 232, and a drain-side gate surface 2222 disposed on the opposite side of the source-side gate surface 2221 closer to the drain electrode 234. The source-side gate surface 2221 faces the source electrode 232 shown in FIG. 13. The drain-side gate surface 2222 faces the drain electrode 234 shown in FIG. 13.

As shown in FIG. 14, the source side gate surface 2221 and the drain side gate surface 2222 are inclined surfaces that have a predetermined angle with respect to the direction in which the source electrode 232 and the drain electrode 234 on the upper surface 218S of the electron supply layer 218 are aligned, that is, the X direction, relative to the upper surface 218S of the electron supply layer 218.

The inclination angle θ11 of the source side gate surface 2221 refers to the acute angle between the upper surface 218S of the electron supply layer 218 and the source side gate surface 2221. The inclination angle θ11 of the source side gate surface 2221 is, for example, 80° or more and 90° or less.

The inclination angle θ12 of the drain side gate surface 2222 refers to the acute angle between the upper surface 218S of the electron supply layer 218 and the drain side gate surface 2222. The inclination angle θ12 of the drain side gate surface 2222 is, for example, 60° or more and 80° or less.

In the gate layer 222 of the second embodiment, the inclination angle θ12 of the drain side gate surface 2222 facing the drain electrode 234 is smaller than the inclination angle θ11 of the source side gate surface 2221 facing the source electrode 232. In the gate layer 222, the shape of the source electrode 232 side and the shape of the drain electrode 234 side are different in the X direction. In other words, the gate layer 222 of the second embodiment has an asymmetric shape in the X direction.

The gate electrode 224 is formed on a portion of the upper surface 222S of the gate layer 222. The gate electrode 224 is, for example, trapezoidal in cross section. The gate electrode 224 includes an upper surface 224S and a lower surface 224R facing the opposite side to the upper surface 224S. The lower surface 224R of the gate electrode 224 is in contact with the upper surface 222S of the gate layer 222.

The lower surface 224R of the gate electrode 224 has a larger area than the upper surface 224S of the gate electrode 224. In other words, the gate electrode 224 has a shape in which the width W22 of the upper surface 224S in the X direction is smaller than the width W21 of the lower surface 224R in the X direction.

The gate electrode 224 includes a source side electrode surface 2241 disposed closer to the source electrode 232, and a drain side electrode surface 2242, which is the surface opposite the source side electrode surface 2241 and disposed closer to the drain electrode 234. The source side electrode surface 2241 is the surface facing the source electrode 232 shown in FIG. 13. The drain side electrode surface 2242 is the surface facing the drain electrode 234 shown in FIG. 13.

The source side electrode surface 2241 and the drain side electrode surface 2242 are inclined surfaces that have a predetermined angle with respect to the direction in which the source electrode 232 and the drain electrode 234 are aligned, i.e., the X direction, with respect to the upper surface 222S of the gate layer 222.

The inclination angle θ21 of the source side electrode surface 2241 refers to the acute angle among the angles formed between the upper surface 222S of the gate layer 222 and the source side electrode surface 2241. The inclination angle θ21 of the source side electrode surface 2241 is, for example, 80° or more and 90° or less. The inclination angle θ21 of the source side electrode surface 2241 is, for example, equal to the inclination angle θ11 of the source side gate surface 2221. Note that the inclination angle θ21 of the source side electrode surface 2241 may be smaller than the inclination angle θ11 of the source side gate surface 2221, or may be larger than the inclination angle θ11 of the source side gate surface 2221.

The inclination angle θ22 of the drain side electrode surface 2242 refers to an acute angle among the angles formed between the upper surface 222S of the gate layer 222 and the drain side electrode surface 2242. The inclination angle θ22 of the drain side electrode surface 2242 is, for example, 60° or more and 80° or less. The inclination angle θ22 of the drain side electrode surface 2242 is, for example, equal to the inclination angle θ12 of the drain side gate surface 2222. Note that the inclination angle θ22 of the drain side electrode surface 2242 may be smaller than the inclination angle θ12 of the drain side gate surface 2222, or may be larger than the inclination angle θ12 of the drain side gate surface 2222.

In the gate electrode 224 of the second embodiment, the inclination angle θ22 of the drain side electrode surface 2242 facing the drain electrode 234 is smaller than the inclination angle θ21 of the source side electrode surface 2241 facing the source electrode 232. In the gate electrode 224, the shape of the source electrode 232 side and the shape of the drain electrode 234 side are different in the X direction. In other words, the gate electrode 224 of the second embodiment has an asymmetric shape in the X direction.

The gate electrode 224 of the second embodiment is formed on a part of the upper surface 222S of the gate layer 222. The width W21 of the lower surface 224R of the gate electrode 224 is shorter than the width W12 of the upper surface 222S of the gate layer 222. Therefore, the upper surface 222S of the gate layer 222 includes a region that is not in contact with the lower surface 224R of the gate electrode 224, that is, a gate side space (hereinafter referred to as a side space) region that is exposed from the lower surface 224R of the gate electrode 224 and extends outside the gate electrode 224. In the example of FIG. 14, the upper surface 222S of the gate layer 222 includes a first side space portion 222S1 and a second side space portion 222S2 as two side space regions extending outside both side walls of the gate electrode 224 in the X direction. The first side space portion 222S1 is a region located closer to the source electrode 232. The second side space portion 222S2 is a region located closer to the drain electrode 234.

Figure 15 shows the configuration of two gate layers 222 and a gate electrode 224 arranged in the X direction of a nitride semiconductor device 210A. Note that the passivation layer 226 and the source field plate portion 236 shown in Figure 13 are omitted in Figure 15.

15, the nitride semiconductor device 210A includes two gate layers 222 and two gate electrodes 224, and two drain electrodes 234. In order to distinguish between the two gate layers 222, one gate layer 222 will be described as the first gate layer 222A, and the other gate layer 222 will be described as the second gate layer 222B. Similarly, for the two gate electrodes 224, the gate electrode 224 on the first gate layer 222A will be described as the first gate electrode 224A, and the gate electrode 224 on the second gate layer 222B will be described as the second gate electrode 224B. In addition, for the two drain electrodes 234, the drain electrode 234 sandwiching the source electrode 232 and the first gate layer 222A will be described as the first drain electrode 234A, and the drain electrode 234 sandwiching the source electrode 232 and the second gate layer 222B will be described as the second drain electrode 234B.

The first gate layer 222A and the second gate layer 222B are disposed on either side of the source electrode 232. The first gate electrode 224A is formed on the first gate layer 222A. The second gate electrode 224B is formed on the second gate layer 222B. The first drain electrode 234A is disposed so as to sandwich the source electrode 232 and the first gate layer 222A. The second drain electrode 234B is disposed so as to sandwich the source electrode 232 and the second gate layer 222B.

The first gate layer 222A and the second gate layer 222B are disposed at positions symmetrical to each other with respect to the source electrode 232. In other words, the distance L1A from the center of the source electrode 232 to the first gate layer 222A is equal to the distance L1B from the center of the source electrode 232 to the second gate layer 222B. Here, if the difference between the distance L1A to the first gate layer 222A and the distance L1B to the second gate layer 222B is, for example, within 10% of the distance L1A to the first gate layer 222A, it can be said that the distance L1A to the first gate layer 222A and the distance L1B to the second gate layer 222B are equal to each other.

The first gate layer 222A and the second gate layer 222B are formed in a shape symmetrical to each other with respect to the source electrode 232. The first gate layer 222A includes a source side gate surface 2221A on the side of the source electrode 232 and a drain side gate surface 2222B on the side of the first drain electrode 234A. The second gate layer 222B includes a source side gate surface 2221B on the side of the source electrode 232 and a drain side gate surface 2222B on the side of the second drain electrode 234B. The inclination angle of the source side gate surface 2221A of the first gate layer 222A is equal to the inclination angle of the source side gate surface 2221B of the second gate layer 222B. The inclination angle of the drain side gate surface 2222A of the first gate layer 222A is equal to the inclination angle of the drain side gate surface 2222B of the second gate layer 222B. Here, if the difference between the two tilt angles is within 10% of one of the tilt angles, the two tilt angles can be said to be equal to each other.

The first gate electrode 224A and the second gate electrode 224B are formed in a shape symmetrical to each other with respect to the source electrode 232. The first gate electrode 224A includes a source side electrode surface 2241A on the source electrode 232 side and a drain side electrode surface 2242A on the first drain electrode 234A side. The second gate electrode 224B includes a source side electrode surface 2241B on the source electrode 232 side and a drain side electrode surface 2242B on the second drain electrode 234B side. The inclination angle of the source side electrode surface 2241A of the first gate electrode 224A is equal to the inclination angle of the source side electrode surface 2241B of the second gate electrode 224B. The inclination angle of the drain side electrode surface 2242A of the first gate electrode 224A is equal to the inclination angle of the drain side electrode surface 2242B of the second gate electrode 224B.

The width W11A of the first gate layer 222A is equal to the width W11B of the second gate layer 222B. Here, if the difference between the width W11A of the first gate layer 222A and the width W11B of the second gate layer 222B is, for example, within 10% of the width W11A of the first gate layer 222A, then the width W11A of the first gate layer 222A and the width W11B of the second gate layer 222B can be said to be equal to each other.

The width W21A of the first gate electrode 224A is equal to the width W21B of the second gate electrode 224B. Here, if the difference between the width W21A of the first gate electrode 224A and the width W21B of the second gate electrode 224B is, for example, within 10% of the width W21A of the first gate electrode 224A, it can be said that the width W21A of the first gate electrode 224A and the width W21B of the second gate electrode 224B are equal to each other.

The first drain electrode 234A and the second drain electrode 234B are disposed at positions symmetrical to each other with respect to the source electrode 232. In other words, the distance L2A from the center of the source electrode 232 to the first drain electrode 234A is equal to the distance L2B from the center of the source electrode 232 to the second drain electrode 234B. Here, if the difference between the distance L2A to the first drain electrode 234A and the distance L2B to the second drain electrode 234B is, for example, within 10% of the distance L2A to the first drain electrode 234A, it can be said that the distance L2A to the first drain electrode 234A and the distance L2B to the second drain electrode 234B are equal to each other.

In FIG. 15, the nitride semiconductor device 210A is shown as including one source electrode 232, two gate layers 222A and 222B, two gate electrodes 224A and 224B, and two drain electrodes 234A and 234B. In reality, the nitride semiconductor device 210A includes multiple source electrodes 232, gate layers 222 and gate electrodes 224, and drain electrodes 234, by repeating the structure of FIG. 15.

(Action)
(Comparative Example)
Fig. 16 is a schematic cross-sectional view showing an enlarged portion of a nitride semiconductor device 210X as a comparative example to the nitride semiconductor device 210A of the second embodiment. The structure of Fig. 16 is shown as an example for comparison with the structure of Fig. 13. Note that in the nitride semiconductor device 210X as the comparative example, components similar to those in the nitride semiconductor device 210A of the second embodiment are denoted by the same reference numerals.

In the comparative nitride semiconductor device 210X, the gate layer 222X is formed in a rectangular shape in cross section. That is, the source side gate surface 2221X and the drain side gate surface 2222X of the gate layer 222X are formed perpendicular to the upper surface 218S of the electron supply layer 218. The width (length in the X direction) of the upper surface 222SX of the gate layer 222X is equal to the width of the lower surface 222RX of the gate layer 222X. The gate electrode 224X is formed on a part of the upper surface 222S of the gate layer 222X. The gate electrode 224X is formed in a rectangular shape in cross section. That is, the source side electrode surface 2241X and the drain side electrode surface 2242X of the gate electrode 224X are formed perpendicular to the upper surface 222S of the gate layer 222X. The width of the upper surface 224SX of the gate electrode 224X is equal to the width of the lower surface 224RX of the gate electrode 224X.

In the nitride semiconductor device 210X of this comparative example, when a high voltage is applied between the drain and source, an electric field concentration occurs near the end of the gate electrode 224X in the drain-source region. Such electric field concentration can cause dielectric breakdown of the electron supply layer 218, etc., and can be a factor in reducing the drain-source breakdown voltage. In addition, in the nitride semiconductor device 210X of this comparative example, when a positive voltage is applied to the gate electrode 224X, an electric field is locally concentrated in a portion of the gate layer 222X near the end of the gate electrode 224X. Such local electric field concentration can cause crystal defects and ultimately crystal breakdown in the gate layer 222X, and can be a factor in reducing the gate breakdown voltage.

(Nitride Semiconductor Device of Second Embodiment)
13 and 14, the gate layer 222 includes a drain-side gate surface 2222 inclined at an inclination angle θ12 with respect to an upper surface 218S of the electron supply layer 218. The gate layer 222 including the inclined drain-side gate surface 2222 in this manner can reduce electric field concentration at an end of the gate layer 222 on the drain electrode 234 side. Therefore, the nitride semiconductor device 210A can suppress dielectric breakdown of the electron supply layer 218, etc., and suppress a decrease in the drain-source breakdown voltage.

The gate electrode 224 also includes a drain-side electrode surface 2242 that is inclined at an inclination angle θ22 with respect to the upper surface 222S of the gate layer 222. The gate electrode 224 that includes such an inclined drain-side electrode surface can reduce electric field concentration in the portion of the gate layer 222 near the end of the gate electrode 224 when a positive voltage is applied to the gate electrode 224. Therefore, this nitride semiconductor device 210A can suppress crystal defects and crystal destruction in the gate layer 222, and can suppress a decrease in the gate breakdown voltage.

The gate layer 222 includes a source-side gate surface 2221 on the side of the source electrode 232 and a drain-side gate surface 2222 on the side of the drain electrode 234. The inclination angle θ11 of the source-side gate surface 2221 is larger than the inclination angle θ12 of the drain-side gate surface 2222. Therefore, the width W11 of the gate layer 222, i.e., the gate length, can be made shorter than when the source-side gate surface 2221 is formed at the same inclination angle as the drain-side gate surface 2222.

(Method of Manufacturing the Nitride Semiconductor Device of the Second Embodiment)
Next, an example of a method for manufacturing the nitride semiconductor device 210A shown in FIGS. 13 and 15 will be described.

Figures 17 to 28 are schematic cross-sectional views showing exemplary manufacturing steps of the nitride semiconductor device 210A. As shown in Figure 15, the nitride semiconductor device 210A of the second embodiment has two gate layers 222 and two gate electrodes 224 that are symmetrical with respect to the source electrode 232. Therefore, Figures 17 to 28 show cross-sectional shapes related to the manufacturing steps based on the state shown in Figure 15. Also, for ease of understanding, the same reference numerals are used in Figures 16 to 27 for components similar to those in Figure 13.

As shown in FIG. 17, the method for manufacturing the nitride semiconductor device 210A includes sequentially forming a buffer layer 214, a first nitride semiconductor layer 216, a second nitride semiconductor layer 218, and a third nitride semiconductor layer 222 on a substrate 212, which is, for example, a Si substrate. The buffer layer 214, the first nitride semiconductor layer 216, the second nitride semiconductor layer 218, and the third nitride semiconductor layer 222 can be epitaxially grown using a metal organic chemical vapor deposition (MOCVD) method.

Although detailed illustration is omitted, in one example, the buffer layer 214 may be a multi-layer buffer layer. In the multi-layer buffer layer, an AlN layer (first buffer layer) is formed on the substrate 212, and then a graded AlGaN layer (second buffer layer) is formed on the AlN layer. The graded AlGaN layer can be formed, for example, by stacking three AlGaN layers with Al compositions of 75%, 50%, and 25% in that order from the side closest to the AlN layer.

The first nitride semiconductor layer 216 is formed on the buffer layer 214. That is, the first nitride semiconductor layer 216 is formed on the substrate 212 with the buffer layer 214 interposed therebetween. The first nitride semiconductor layer 216 may be a GaN layer. The first nitride semiconductor layer 216 constitutes the electron transit layer 216 in FIGS. 13 to 15.

Then, a second nitride semiconductor layer 218 is formed on the first nitride semiconductor layer 216. The second nitride semiconductor layer 218 may be an AlGaN layer. Therefore, the second nitride semiconductor layer 218 has a larger band gap than the first nitride semiconductor layer 216. The second nitride semiconductor layer 218 constitutes the electron supply layer 218 in FIGS. 13 to 15.

Then, a third nitride semiconductor layer 222 is formed on the second nitride semiconductor layer 218. The third nitride semiconductor layer 222 may be a GaN layer containing an acceptor-type impurity (a p-type GaN layer). The acceptor-type impurity may be, for example, magnesium. The third nitride semiconductor layer 222 constitutes the gate layer 222 in FIGS. 13 to 15.

The buffer layer 214, the first nitride semiconductor layer 216, the second nitride semiconductor layer 218, and the third nitride semiconductor layer 222 are composed of nitride semiconductors with relatively similar lattice constants. Therefore, the buffer layer 214, the first nitride semiconductor layer 216, the second nitride semiconductor layer 218, and the third nitride semiconductor layer 222 can be epitaxially grown continuously.

As shown in FIG. 18, the method for manufacturing the nitride semiconductor device 210A further includes forming a metal layer 224 on the third nitride semiconductor layer 222. The metal layer 224 constitutes the gate electrode 224 shown in FIGS. 13 to 15. The metal layer 224 may be, for example, a TiN layer. The TiN layer is formed by a sputtering method.

The method for manufacturing the nitride semiconductor device 210A further includes forming a first mask 262. The first mask 262 is formed so as to cover a portion of the metal layer 224 corresponding to the region between the first gate electrode 224A and the second gate electrode 224B shown in FIG. 15. As the first mask 262, for example, a SiO ₂ film is formed on the third nitride semiconductor layer 222. The first mask 262 is obtained by forming a first mask layer 261 that covers the upper surface 224S of the metal layer 224 and patterning the first mask layer 261. In FIG. 18, the first mask layer 261 is indicated by a dashed line.

As shown in FIG. 19, the method for manufacturing the nitride semiconductor device 210A further includes forming a second mask layer 264 covering the metal layer 224 and the first mask 262. The second mask layer 264 is for forming a second mask for self-alignment. The second mask layer 264 may be, for example, a SiN layer. The second mask layer 264 is formed to a thickness corresponding to the widths W21 and W22 of the gate electrode 224 shown in FIG. 14.

20, the method for manufacturing the nitride semiconductor device 210A further includes forming second masks 264A and 264B. The second masks 264A and 264B are obtained by etching back the second mask layer 264 shown in FIG. 19 until the surfaces of the metal layer 224 and the first mask 262 are exposed. The second masks 264A and 264B can be formed, for example, as side walls of the first mask 262. The second masks 264A and 264B are formed, for example, with a trapezoidal cross section. The second masks 264A and 264B are formed such that the side surface 2642 opposite the first mask 262 is inclined with respect to the upper surface 224S of the metal layer 224.

21, the method for manufacturing the nitride semiconductor device 210A further includes removing the first mask 262. By removing the first mask 262, two second masks 264A and 264B are formed on the metal layer 224.

As shown in FIG. 22, the method for manufacturing the nitride semiconductor device 210A further includes forming a gate electrode 224. The gate electrode 224 includes a first gate electrode 224A and a second gate electrode 224B. The first gate electrode 224A and the second gate electrode 224B are formed by patterning the metal layer 224 (see FIG. 21) exposed from the two second masks 264A and 264B.

At this time, the first gate electrode 224A is formed into a shape corresponding to the second masks 264A and 264B. As shown in FIG. 22, the first gate electrode 224A is formed into a trapezoidal shape in cross section. The first gate electrode 224A includes a source side electrode surface 2241A facing the second gate electrode 224B side, and a drain side electrode surface 2242A facing the opposite side to the second gate electrode 224B. The source side electrode surface 2241A has an inclination angle θ11 as shown in FIG. 14. The drain side electrode surface 2242A has an inclination angle θ12 as shown in FIG. 14.

Similarly, the second gate electrode 224B is formed in a shape corresponding to the second masks 264A and 264B. As shown in FIG. 22, the second gate electrode 224B is formed in a trapezoidal shape in cross section. The second gate electrode 224B includes a source side electrode surface 2241B facing the first gate electrode 224A side, and a drain side electrode surface 2242B facing the opposite side to the second gate electrode 224B. The source side electrode surface 2241B has an inclination angle θ21 as shown in FIG. 14. The drain side electrode surface 2242B has an inclination angle θ22 as shown in FIG. 14.

23, the method for manufacturing the nitride semiconductor device 210A further includes forming a third mask layer 266. The third mask layer 266 is, for example, a SiN layer. The third mask layer 266 can be formed, for example, by a plasma-enhanced chemical vapor deposition (PECVD) method. The third mask layer 266 is formed so as to cover the upper surface 222S of the third nitride semiconductor layer 222, the side surfaces of the first gate electrode 224A and the second gate electrode 224B, and the upper and side surfaces of the second masks 264A and 264B.

24, the method for manufacturing the nitride semiconductor device 210A further includes forming third masks 2661 and 2662 that cover the source side electrode surfaces 2241A and 2241B and the drain side electrode surface 2242, which are the side surfaces of the first gate electrode 224A and the second gate electrode 224B, and the side surfaces 2641 and 2642 of the second masks 264A and 264B. The third masks 2661 and 2662 are obtained by etching back the third mask layer 266 shown in FIG. 23 until the upper surface of the third nitride semiconductor layer 222 is exposed.

25, the method for manufacturing the nitride semiconductor device 210A further includes forming a first gate layer 222A and a second gate layer 222B. The first gate layer 222A and the second gate layer 222B are obtained by etching the third nitride semiconductor layer 222 exposed from the second masks 264A, 264B and the third masks 2661, 2662.

At this time, the first gate layer 222A is formed into a shape corresponding to the third masks 2661, 2662 that cover the first gate electrode 224A. As shown in FIG. 25, the first gate layer 222A is formed into a trapezoidal shape in cross section. The first gate layer 222A includes a source side gate surface 2221A facing the second gate layer 222B side, and a drain side gate surface 2222A facing the opposite side to the second gate layer 222B. The source side gate surface 2221A has an inclination angle θ11 as shown in FIG. 14. The drain side gate surface 2222A has an inclination angle θ12 as shown in FIG. 14.

Similarly, the second gate layer 222B is formed in a shape corresponding to the third masks 2661, 2662 covering the second gate electrode 224B. As shown in FIG. 25, the second gate layer 222B is formed in a trapezoidal shape in cross section. The second gate layer 222B includes a source side gate surface 2221B facing the first gate layer 222A side, and a drain side gate surface 2222B facing the opposite side to the first gate layer 222A. The source side gate surface 2221B has an inclination angle θ11 as shown in FIG. 14. The drain side gate surface 2222B has an inclination angle θ12 as shown in FIG. 14.

As shown in FIG. 26, the method for manufacturing the nitride semiconductor device 210A further includes removing the second masks 264A, 264B and the third masks 2661, 2662.
27, the method for manufacturing the nitride semiconductor device 210A further includes forming a passivation layer 226 that covers the entire exposed surfaces of the electron supply layer 218, the first and second gate layers 222A, 222B, and the first and second gate electrodes 224A, 224B. The passivation layer 226 may be, for example, a SiN layer. The passivation layer 226 may be formed by, for example, a low-pressure chemical vapor deposition (LPCVD) method.

28, the method for manufacturing the nitride semiconductor device 210A further includes forming a source opening 2261 and a drain opening 2262 in the passivation layer 226. The source opening 2261 and the drain opening 2262 can be formed by selectively removing the passivation layer 226 by lithography and etching.

The method for manufacturing the nitride semiconductor device 210A further includes forming the source electrode 232, the drain electrodes 234A, 234B, and the source field plate portion 236. The source electrode 232, the drain electrodes 234A, 234B, and the source field plate portion 236 are obtained by forming a metal layer that fills the source opening 2261 and the drain opening 2262 and covers the passivation layer 226, and selectively removing the metal layer by lithography and etching. The metal layer may include at least one of a Ti layer, a TiN layer, an Al layer, an AlSiCu layer, and an AlCu layer. This results in the nitride semiconductor device 210A shown in Figures 13 to 15.

In the method for manufacturing the nitride semiconductor device 210A of the second embodiment, the first gate electrode 224A and the second gate electrode 224B are formed using two second masks 264A and 264B formed as sidewalls on both sides of the first mask 262. In this case, the width of the second masks 264A and 264B (the length in the X direction in FIG. 21) can be made shorter than in a method in which two second masks are formed without using the first mask 262.

The second masks 264A and 264B can be formed by forming a mask layer that covers the metal layer 224 shown in FIG. 18, forming a resist film that covers the mask layer, and etching the mask layer using a pattern formed on the resist film by photolithography as a mask. In this case, the width of the second masks 264A and 264B depends on the performance of the exposure machine that exposes the resist film that forms the pattern. For example, with an exposure machine that uses i-line, the minimum width is about 0.7 μm.

On the other hand, the width of the side walls formed on both sides of the first mask 262, that is, the width of the second masks 264A and 264B, is determined by the film thickness of the second mask layer 264 (see FIG. 19) that covers the first mask 262. Therefore, the width of the second masks 264A and 264B can be adjusted by adjusting the film thickness of the second mask layer 264. The gate layer 222 is also formed by the third masks 2661 and 2662 that cover the gate electrode 224. Therefore, the width of the gate layer 222 is determined by the film thickness of the third masks 2661 and 2662 that cover the gate electrode 224, that is, the film thickness of the third mask layer 266. In this way, the gate layer 222 and the gate electrode 224 can be formed without being affected by the constraints of the exposure machine, etc. Therefore, the gate layer 222 and the gate electrode 224 can be formed with a width narrower than the line width determined by the performance of the exposure machine. By reducing the width of the gate layer 222, the on-resistance of the nitride semiconductor device 210A can be reduced.

As described above, according to this embodiment, the following effects are achieved.
(2-1) The nitride semiconductor device 210A includes an electron transit layer 216, an electron supply layer 218, a gate layer 222, a gate electrode 224, a source electrode 232, and a drain electrode 234. The electron transit layer 216 is made of a nitride semiconductor. The electron supply layer 218 is formed on the electron transit layer 216 and made of a nitride semiconductor having a smaller band gap than the electron transit layer 216. The gate layer 222 is formed on the electron supply layer 218 and made of a nitride semiconductor having a smaller band gap than the electron supply layer 218. The gate electrode 224 is formed on the gate layer 222. The source electrode 232 and the drain electrode 234 are disposed on both sides of the gate layer 222 in the X direction and are in contact with the electron supply layer 218.

The gate layer 222 includes a source-side gate surface 2221 disposed closer to the source electrode 232 on both sides in the X direction, and a drain-side gate surface 2222 opposite the source-side gate surface 2221. The drain-side gate surface 2222 has an inclination angle θ12 smaller than the inclination angle θ11 of the source-side gate surface 2221 when viewed from a direction perpendicular to both the thickness direction of the gate layer 222 and the X direction.

The gate layer 222 including the inclined drain-side gate surface 2222 in this manner can reduce electric field concentration at the end of the gate layer 222 on the drain electrode 234 side. As a result, the nitride semiconductor device 210A can suppress dielectric breakdown of the electron supply layer 218, etc., and suppress a decrease in the drain-source breakdown voltage.

(2-2) The gate electrode 224 includes a drain side electrode surface 2242 that is inclined at an inclination angle θ22 with respect to the upper surface 222S of the gate layer 222. The gate electrode 224 including the inclined drain side electrode surface 2242 in this manner can reduce electric field concentration in the portion of the gate layer 222 near the end of the gate electrode 224 when a positive voltage is applied to the gate electrode 224. Therefore, this nitride semiconductor device 210A can suppress crystal defects and crystal destruction in the gate layer 222, and can suppress a decrease in the gate breakdown voltage.

(2-3) The gate layer 222 includes a source-side gate surface 2221 on the side of the source electrode 232 and a drain-side gate surface 2222 on the side of the drain electrode 234. The inclination angle θ11 of the source-side gate surface 2221 is larger than the inclination angle θ12 of the drain-side gate surface 2222. Therefore, the width W11 of the gate layer 222, i.e., the gate length, can be made shorter than when the source-side gate surface 2221 is formed at the same inclination angle as the drain-side gate surface 2222.

(2-4) In the manufacturing method of the nitride semiconductor device 210A of the second embodiment, the first gate electrode 224A and the second gate electrode 224B are formed using two second masks 264A, 264B formed as sidewalls on both sides of the first mask 262. In this case, the width of the second masks 264A, 264B can be made shorter than in a method of forming two second masks without using the first mask 262. This allows the width of the gate layer 222 and the gate electrode 224 to be made smaller than in a case where the two second masks 264A, 264B are each formed by photolithography.

Third Embodiment
(Cross-sectional structure of nitride semiconductor device)
Fig. 29 is a schematic cross-sectional view of an exemplary nitride semiconductor device 210B according to the third embodiment. Fig. 14 is a schematic cross-sectional view showing an enlarged portion of Fig. 13. Fig. 29 shows a state corresponding to Fig. 13 showing the nitride semiconductor device 210A of the second embodiment. In Fig. 29, the same components as those in the nitride semiconductor device 210A of the second embodiment are denoted by the same reference numerals. Further, detailed description of the same components as those in the second embodiment will be omitted.

The nitride semiconductor device 210B of the third embodiment includes a gate layer 282 and a gate electrode 284. The gate layer 282 includes an upper surface 282S, a lower surface 282R facing the opposite side to the upper surface 282S, a source side gate surface 2821 facing the source electrode 232, and a drain side gate surface 2822 facing the drain electrode 234. The gate electrode 284 includes an upper surface 284S, a lower surface 284R facing the opposite side to the upper surface 284S, a source side electrode surface 2841 facing the source electrode 232, and a drain side electrode surface 2842 facing the drain electrode 234.

The inclination angle of the source side gate surface 2821 is the same as the inclination angle θ11 of the source side gate surface 2221 of the second embodiment shown in FIG. 14. The inclination angle of the drain side gate surface 2822 is the same as the inclination angle θ12 of the drain side gate surface 2222 of the second embodiment shown in FIG. 14. In other words, the drain side gate surface 2822 has an inclination angle smaller than the inclination angle of the source side gate surface 2821.

The inclination angle of the source side electrode surface 2841 is the same as the inclination angle θ21 of the source side electrode surface 2241 of the second embodiment shown in FIG. 14. The inclination angle of the drain side electrode surface 2842 is the same as the inclination angle θ22 of the drain side electrode surface 2242 of the second embodiment shown in FIG. 14. In other words, the drain side electrode surface 2842 has an inclination angle smaller than the inclination angle of the source side electrode surface 2841.

In the third embodiment, the gate layer 282 has a source side gate surface 2821 that is flush with the source side electrode surface 2841 of the gate electrode 284. In addition, the gate layer 282 has a drain side gate surface 2822 that is flush with the drain side electrode surface 2842 of the gate electrode 284.

The nitride semiconductor device 210B including the gate layer 282 and gate electrode 284 thus formed can reduce electric field concentration, similar to the nitride semiconductor device 210A of the second embodiment.

(Method of Manufacturing the Nitride Semiconductor Device of the Third Embodiment)
Next, an example of a method for manufacturing the nitride semiconductor device 210B shown in FIG. 29 will be described.

The method for manufacturing the nitride semiconductor device 210B of the third embodiment differs from the method for manufacturing the nitride semiconductor device 210A of the second embodiment in the steps of forming the gate layer 282 and the gate electrode 284. These steps will be described in detail.

30, the method for manufacturing the nitride semiconductor device 210B includes sequentially forming a buffer layer 214, a first nitride semiconductor layer 216, a second nitride semiconductor layer 218, and a third nitride semiconductor layer 282 on a substrate 212, which is, for example, a Si substrate. The third nitride semiconductor layer 282 includes the same material as the third nitride semiconductor layer 222 of the second embodiment. The third nitride semiconductor layer 282 constitutes the gate layer 282 of FIG. 29. The method for manufacturing the nitride semiconductor device 210A further includes forming a metal layer 284 on the third nitride semiconductor layer 282. The metal layer 284 constitutes the gate electrode 284 shown in FIG. 29. The metal layer 284 may be, for example, a TiN layer.

The method for manufacturing the nitride semiconductor device 210B further includes forming two second masks 264A, 264B on the upper surface of the metal layer 284. These second masks 264A, 264B are the same as those in the process shown in FIG. 21 in the method for manufacturing the nitride semiconductor device 210A of the second embodiment. In other words, FIG. 30 is shown as a manufacturing process following FIG. 20 of the second embodiment.

31, the method for manufacturing the nitride semiconductor device 210B includes forming the gate electrodes 284A, 284B and the gate layers 282A, 282B. The gate electrodes 284A, 284B include source side electrode surfaces 2841A, 2841B and drain side electrode surfaces 2842A, 2842B. The gate layers 282A, 282B include source side gate surfaces 2821A, 2821B and drain side gate surfaces 2822A, 2822B. The first gate electrode 284A and the second gate electrode 284B are obtained by etching the metal layer 284 (see FIG. 30) exposed from the second masks 264A, 264B. Next, the third nitride semiconductor layer 282 (see FIG. 30) exposed from the second masks 264A, 264B, the first gate electrode 284A, and the second gate electrode 284B is etched to obtain the first gate layer 282A and the second gate layer 282B.

Then, the passivation layer 226, the source electrode 232, and the drain electrode 234 (see FIG. 29) are formed in the same manner as in the manufacturing method of the nitride semiconductor device 210A of the second embodiment shown in FIG. 27 and FIG. 28. This results in the nitride semiconductor device 210B shown in FIG. 29.

(effect)
As described above, according to the third embodiment, the following effects are achieved.
(3-1) The nitride semiconductor device 210B of the third embodiment includes a gate layer 282 and a gate electrode 284. The drain-side gate surface 2822 of the gate layer 282 has an inclination angle smaller than the inclination angle of the source-side gate surface 2821. Therefore, similar to the nitride semiconductor device 210A of the second embodiment, the nitride semiconductor device 210B of the third embodiment can reduce electric field concentration at the end of the gate layer 282 on the drain electrode 234 side. Therefore, the nitride semiconductor device 210B can suppress dielectric breakdown of the electron supply layer 218, etc., and suppress a decrease in the drain-source breakdown voltage.

(3-2) The drain side electrode surface 2842 of the gate electrode 284 has an inclination angle smaller than the inclination angle of the source side electrode surface 2841. Therefore, the gate electrode 284 including the drain side electrode surface 2842 can reduce electric field concentration in the portion of the gate layer 282 near the end of the gate electrode 284 when a positive voltage is applied to the gate electrode 284. Therefore, this nitride semiconductor device 210B can suppress crystal defects and crystal destruction in the gate layer 222, and can suppress a decrease in the gate breakdown voltage.

(3-3) In the nitride semiconductor device 210B of the third embodiment, the source side gate surface 2821 of the gate layer 282 and the source side electrode surface 2841 of the gate electrode 284 are flush with each other. In addition, in the nitride semiconductor device 210B, the drain side gate surface 2822 of the gate layer 282 and the drain side electrode surface 2842 of the gate electrode 284 are flush with each other. Therefore, the gate layer 282 of the third embodiment does not include the first side space portion 222S1 and the second side space portion 222S2 of the gate layer 222 of the second embodiment. For example, if the width of the gate electrode 284 is the same as the width of the gate electrode 224 of the second embodiment, the width of the gate layer 282 of the third embodiment is smaller than the width of the gate layer 222 of the second embodiment. Therefore, the nitride semiconductor device 210B of the third embodiment can have a shorter gate length than the nitride semiconductor device 210A of the second embodiment.

(3-4) In the method for manufacturing the nitride semiconductor device 210B of the third embodiment, the gate layer 282 is formed by etching the gate electrode 284 and then the third nitride semiconductor layer 282 exposed from the gate electrode 284. Therefore, the number of steps is smaller than that of the nitride semiconductor device 210A of the second embodiment. This makes it possible to shorten the time required for manufacturing the nitride semiconductor device 210B of the third embodiment.

<Modifications of the second and third embodiments>
The above embodiment can be modified, for example, as follows. The above embodiment and the following modified examples can be combined with each other as long as no technical contradiction occurs. In the following modified examples, the same reference numerals as in the above embodiment are used for the parts common to the above embodiment, and the description thereof will be omitted.

The shapes of the gate layers 222 and 282 in the above embodiment may be changed as appropriate.
32, the gate layer 292 may have a step structure. In one example, the gate layer 292 includes a ridge portion 293, and a source side step portion 294 and a drain side step portion 295 extending in opposite directions from both sides of the ridge portion 293. The step structure of the gate layer 292 is formed by the ridge portion 293, the source side step portion 294, and the drain side step portion 295.

The ridge portion 293 corresponds to a relatively thick portion of the gate layer 292. The ridge portion 293 includes an upper surface 293S and a lower surface 293R facing the opposite side to the upper surface 293S. The gate electrode 224 contacts the entire upper surface 293S of the ridge portion 293. The ridge portion 293 may have a trapezoidal shape in a cross section along the XZ plane in FIG. 32. The ridge portion 293 may have a thickness of, for example, 100 nm or more and 200 nm or less. The thickness of the ridge portion 293 refers to the distance from the upper surface of the ridge portion 293 to the lower surface (the lower surface of the gate layer 292 that contacts the electron supply layer 218). The thickness of the ridge portion 293 (gate layer 292) may be determined taking into account various parameters such as the gate breakdown voltage.

The ridge portion 293 has the same shape as the gate layer 222 of the second embodiment shown in, for example, FIG. 13 and FIG. 14. The ridge portion 293 includes a source side gate surface 2931 on the source electrode 232 side and a drain side gate surface 2932 on the drain electrode 234 side opposite to the source side gate surface 2931. The source side gate surface 2931 is inclined with respect to the upper surface 218S of the electron supply layer 218. The inclination angle of the source side gate surface 2931 is the same as the inclination angle θ11 of the source side gate surface 2221 of the second embodiment shown in FIG. 14. The drain side gate surface 2932 is inclined with respect to the upper surface 218S of the electron supply layer 218. The inclination angle of the drain side gate surface 2932 is the same as the inclination angle θ12 of the drain side gate surface 2222 of the second embodiment shown in FIG. 14. The ridge portion 293 may have the same shape as the gate layer 282 of the third embodiment shown in FIG. 29.

The source side step 294 extends from the source side gate surface 2931 of the ridge portion 293 toward the source opening 2261 of the passivation layer 226. The drain side step 295 extends from the drain side gate surface 2932 of the ridge portion 293 toward the drain opening 2262 of the passivation layer 226. In the example of FIG. 32, the drain side step 295 extends longer from the ridge portion 293 than the source side step 294. However, the source side step 294 and the drain side step 295 may be the same length. The thickness of the source side step 294 and the thickness of the drain side step 295 are equal to each other. Here, if the difference between the thickness of the source side step 294 and the thickness of the drain side step 295 is, for example, within 10% of the thickness of the source side step 294, it can be said that the thickness of the source side step 294 and the thickness of the drain side step 295 are equal to each other.

As with the nitride semiconductor device 210A of the second embodiment, the nitride semiconductor device 210C of this modified example can reduce electric field concentration in the gate layer 292. This can also suppress a decrease in the gate breakdown voltage.

The source field plate portion 236 is formed integrally with the upper region of the source electrode 232, and is provided on the passivation layer 226 so as to cover the entire gate layer 222 in plan view (in the example of FIG. 13, the ridge portion 293, the source side step portion 294, and the drain side step portion 295).

The nitride semiconductor device 210C of this modified example can reduce the density of holes accumulated at the interface between the gate layer 222 and the electron supply layer 218 by using the source side step portion 294 and the drain side step portion 295. Therefore, band bending of the electron supply layer 218 caused by hole accumulation can be suppressed, and an increase in gate leakage current can be suppressed.

In each of the above embodiments, the source field plate portion 236 may be omitted.
In the second embodiment, the gate layer 222 may have a shape that does not include either the first side space portion 222S1 or the second side space portion 222S2. For example, the source side gate surface 2221 of the gate layer 222 and the source side electrode surface 2241 of the gate electrode 224 may be flush with each other. Also, the drain side gate surface 2222 of the gate layer 222 and the drain side electrode surface 2242 of the gate electrode 224 may be flush with each other. In these cases, the width of the gate layer 222 may be narrowed, and the width of the gate electrode 224 may be widened.

One or more of the various examples described in this specification may be combined to the extent that they are not technically inconsistent.
In this specification, "at least one of A and B" should be understood to mean "A only, or B only, or both A and B."

The term "on" as used in this disclosure includes the meanings "on" and "above" unless the context clearly indicates otherwise. Thus, the expression "a first layer is formed on a second layer" is intended to mean that in some embodiments, the first layer may be placed directly on the second layer in contact with the second layer, while in other embodiments, the first layer may be placed above the second layer without contacting the second layer. That is, the term "on" does not exclude a structure in which another layer is formed between the first layer and the second layer. For example, a structure in which the electron supply layer 18 is formed on the electron transit layer 16 may include a structure in which an intermediate layer is located between the electron supply layer 18 and the electron transit layer 16 to stably form a 2DEG.

The terms "first", "second", "third", etc. in this disclosure are used merely to distinguish objects and do not rank the objects.
The directional terms used in this disclosure, such as "vertical,""horizontal,""upper,""lower,""top,""bottom,""front,""rear,""longitudinal,""lateral,""left,""right,""front,""rear," and the like, depend on the particular orientation of the device being described and illustrated. Various alternative orientations can be envisioned in this disclosure, and therefore these directional terms should not be construed in a narrow sense.

For example, the Z-axis direction used in this disclosure does not necessarily have to be vertical, nor does it have to completely coincide with the vertical direction. Therefore, various structures according to this disclosure (e.g., the structure shown in FIG. 2) are not limited to the "up" and "down" in the Z-axis direction described in this specification being "up" and "down" in the vertical direction. For example, the X-axis direction may be vertical, or the Y-axis direction may be vertical.

[Additional Notes]
The technical ideas that can be understood from the present disclosure are described below. Note that, for the purpose of aiding understanding, not for the purpose of limitation, the components described in the appendices are given the reference numbers of the corresponding components in the embodiments. The reference numbers are shown as examples for the purpose of aiding understanding, and the components described in each appendix should not be limited to the components indicated by the reference numbers.

(Appendix A1)
An electron transit layer (16) made of a nitride semiconductor;
an electron supply layer (18) formed on the electron transit layer (16) and made of a nitride semiconductor having a band gap larger than that of the electron transit layer (16);
A gate layer (20; 102) formed on the electron supply layer (18) and made of a nitride semiconductor containing an acceptor-type impurity;
a gate electrode (22) formed on the gate layer (20; 102);
a source electrode (26) and a drain electrode (28) formed on the electron supply layer (18);
The nitride semiconductor device (10; 100), wherein the gate layer (20; 102) includes an upper surface (20A; 102A) in contact with the gate electrode (22), and the upper surface (20A; 102A) is a Ga polar surface.

(Appendix A2)
The gate layer (20)
a first GaN layer (32) in contact with the gate electrode (22);
and a second GaN layer (34) in contact with the electron supply layer (18), wherein the first GaN layer (32) is made of Ga-polar GaN and the second GaN layer (34) is made of N-polar GaN.

(Appendix A3)
The nitride semiconductor device according to Appendix A2, wherein the second GaN layer (34) is thicker than the first GaN layer (32).

(Appendix A4)
The nitride semiconductor device according to Appendix A2 or Appendix A3, wherein the gate layer (20) has a thickness of 100 nm or more and less than 150 nm, and the first GaN layer (32) has a thickness of 5 nm or more and less than 30 nm.

(Appendix A5)
The second GaN layer (34) is
a ridge portion (36) in contact with the electron supply layer (18) and covered with the first GaN layer (32);
and an extension portion (38; 40) that is in contact with the electron supply layer (18) and extends outward beyond the ridge portion (36) in a planar view, the extension portion (38; 40) being thinner than the ridge portion (36).

(Appendix A6)
The nitride semiconductor device according to Appendix A5, wherein the extension portion (38; 40) includes an upper surface (38A, 40A) at least a portion of which is an N-polar surface.

(Appendix A7)
The nitride semiconductor device according to claim A1, wherein the gate layer (102) is made of Ga-polar GaN.

(Appendix A8)
The gate layer (102)
a ridge portion (104) in contact with the electron supply layer (18) and including the upper surface (102A) of the gate layer (102);
an extension portion (106; 108) that is in contact with the electron supply layer (18) and extends outward from the ridge portion (104) in a plan view and is thinner than the ridge portion (104).

(Appendix A9)
The nitride semiconductor device according to any one of Appendix A1 to Appendix A8, wherein the upper surface (20A; 102A) of the gate layer (20; 102) forms a Schottky junction with the gate electrode (22).

(Appendix A10)
a passivation layer (24) covering the electron supply layer (18), the gate layer, and the gate electrode (22) and having a first opening (24A) and a second opening (24B);
The source electrode (26) is in contact with the electron supply layer (18) through the first opening (24A),
The drain electrode (28) is in contact with the electron supply layer (18) through the second opening (24B),
The nitride semiconductor device according to any one of Appendix A1 to Appendix A9, wherein the gate layer (20; 102) is located between the first opening (24A) and the second opening (24B).

(Appendix A11)
The electron transport layer (16) is made of GaN,
The electron supply layer (18) is composed of Al _x Ga _1-x N, where 0.1<x<0.3.
The nitride semiconductor device according to any one of Appendix A1 to Appendix A10.

(Appendix A12)
The nitride semiconductor device according to Appendix A2, wherein the first GaN layer (32) contains hydrogen at a higher concentration than the second GaN layer (34).

(Appendix A13)
The nitride semiconductor device according to any one of Appendix A1 to Appendix A12, further comprising a semiconductor substrate (12) and a buffer layer (14) formed on the semiconductor substrate (12), and the electron transit layer (16) is formed on the buffer layer (14).

(Appendix A14)
a passivation layer (24) covering the electron supply layer (18), the gate layer, and the gate electrode (22) and having a first opening (24A) and a second opening (24B);
The source electrode (26) is in contact with the electron supply layer (18) through the first opening (24A),
The drain electrode (28) is in contact with the electron supply layer (18) through the second opening (24B),
The gate layer (102)
a ridge portion (104) in contact with the electron supply layer (18) and including the upper surface (102A) of the gate layer (102);
a first extension portion (106) in contact with the electron supply layer (18) and extending from the ridge portion (104) toward the first opening (24A);
and a second extension portion (108) that is in contact with the electron supply layer (18) and extends from the ridge portion (104) toward the second opening (24B), wherein the first extension portion (106) and the second extension portion (108) are thinner than the ridge portion (104).

(Appendix A15)
forming an electron transit layer (16) made of a nitride semiconductor;
forming an electron supply layer (18) made of a nitride semiconductor having a band gap larger than that of the electron transport layer (16) on the electron transport layer (16);
forming a gate layer (20) made of a nitride semiconductor containing an acceptor-type impurity on the electron supply layer (18);
forming a gate electrode (22) on the gate layer (20);
forming a source electrode (26) and a drain electrode (28) on the electron supply layer (18);
The method for manufacturing a nitride semiconductor device (10), wherein the gate layer (20) includes an upper surface (20A) in contact with the gate electrode (22), and the upper surface (20A) is a Ga polar surface.

(Appendix A16)
Forming the gate layer (20) comprises:
forming a first nitride semiconductor layer (50) on the electron supply layer (18), the first nitride semiconductor layer (50) being N-polar GaN grown using _N2 as a carrier gas;
forming a second nitride semiconductor layer (52) on the first nitride semiconductor layer (50), the second nitride semiconductor layer (52) being Ga-polar GaN grown using _H2 as a carrier gas.

(Appendix A17)
The gate layer (20)
a first GaN layer (32) in contact with the gate electrode (22);
and a second GaN layer (34) in contact with the electron supply layer (18), wherein the first GaN layer (32) is made of Ga-polarity GaN, and the second GaN layer (34) is made of N-polarity GaN.

(Appendix A18)
The method for manufacturing a nitride semiconductor device according to Appendix A17, wherein the second GaN layer (34) is thicker than the first GaN layer (32).

(Appendix A19)
The method for manufacturing a nitride semiconductor device according to Appendix A17 or Appendix A18, wherein the gate layer (20) has a thickness of 100 nm or more and less than 150 nm, and the first GaN layer (32) has a thickness of 5 nm or more and less than 30 nm.

(Appendix A20)
The method for manufacturing a nitride semiconductor device according to any one of Appendix A15 to Appendix A19, wherein the upper surface (20A) of the gate layer (20) forms a Schottky junction with the gate electrode (22).

(Appendix B1)
An electron transit layer (216) made of a nitride semiconductor;
an electron supply layer (218) formed on the electron transit layer (216) and made of a nitride semiconductor having a band gap larger than that of the electron transit layer (216);
a gate layer (222) formed on the electron supply layer (218) and made of a nitride semiconductor having a band gap smaller than that of the electron supply layer (218);
a gate electrode (224) formed on the gate layer (222);
a source electrode (232) and a drain electrode (234) disposed on both sides of the gate layer (222) in a predetermined direction and in contact with the electron transit layer (216);
Including,
The gate layer (222)
A source-side gate surface (2221) disposed closer to the source electrode (232) on both side surfaces in the predetermined direction;
a drain-side gate surface (2222) which is a surface opposite to the source-side gate surface (2221) and has a smaller inclination angle (θ12) than the source-side gate surface (2221) when viewed from a direction perpendicular to both the thickness direction of the gate layer (222) and the predetermined direction;
A nitride semiconductor device comprising:

(Appendix B2)
The nitride semiconductor device according to Appendix B1, wherein an inclination angle of the source side gate surface (2221) is 80° or more and 90° or less, and an inclination angle of the drain side gate surface (2222) is 60° or more and 80° or less.

(Appendix B3)
The nitride semiconductor device according to claim Bl or B2, wherein a length of a lower surface of the gate layer (222) in contact with the electron supply layer (218) is 0.2 μm or more and 0.5 μm or less.

(Appendix B4)
The gate electrode (224) has both side surfaces in the predetermined direction, and includes a source side electrode surface (2241) closer to the source electrode (232) and a drain side electrode surface (2242) closer to the drain electrode (234),
The inclination angle (θ22) of the drain side electrode surface (2242) is smaller than the inclination angle (θ21) of the source side electrode surface (2241);
The nitride semiconductor device according to any one of Appendix B1 to Appendix B3.

(Appendix B5)
The nitride semiconductor device according to Appendix B4, wherein an inclination angle (θ22) of the drain side electrode surface (2242) is equal to or smaller than an inclination angle (θ12) of the drain side gate surface (2222).

(Appendix B6)
The nitride semiconductor device according to Appendix B4, wherein an inclination angle (θ22) of the drain side electrode surface (2242) is equal to or greater than an inclination angle (θ12) of the drain side gate surface (2222).

(Appendix B7)
The nitride semiconductor device according to any one of Appendix B4 to Appendix B6, wherein an inclination angle (θ21) of the source side electrode surface (2241) is equal to or smaller than an inclination angle (θ11) of the source side gate surface (2221).

(Appendix B8)
The nitride semiconductor device according to any one of Appendix B4 to Appendix B6, wherein an inclination angle (θ21) of the source side electrode surface (2241) is equal to or greater than an inclination angle (θ11) of the source side gate surface (2221).

(Appendix B9)
The nitride semiconductor device according to any one of Appendix B4 to Appendix B8, wherein, in a planar view, the drain side electrode surface (2242) is located closer to the source electrode (232) than the drain side gate surface (2222).

(Appendix B10)
The nitride semiconductor device according to any one of Appendix B4 to Appendix B9, wherein the drain side electrode surface (2242) and the drain side gate surface (2222) are flush with each other.

(Appendix B11)
The nitride semiconductor device according to any one of Appendix B7 to Appendix B10, wherein, in a planar view, the source side electrode surface (2241) is located closer to the drain electrode (234) than the source side gate surface (2221).

(Appendix B12)
The nitride semiconductor device according to any one of Appendix B7 to Appendix B11, wherein the source side electrode surface (2241) and the source side gate surface (2221) are flush with each other.

(Appendix B13)
The gate layer (222) includes a first gate layer (222) and a second gate layer (222) arranged on both sides of the source electrode (232) in the predetermined direction,
The gate electrode (224) includes a first gate electrode (224) formed on the first gate layer (222) and a second gate electrode (224) formed on the second gate layer (222).
The nitride semiconductor device according to any one of Appendix B1 to Appendix B12.

(Appendix B14)
The gate layer (222) includes a drain side step portion provided so as to continue from the drain side gate surface (2222) toward the drain electrode (234), and a source side step portion provided so as to continue from the source side gate surface (2221) toward the source electrode (232).
The nitride semiconductor device according to any one of Appendix B1 to Appendix B13.

(Appendix B15)
a gate layer (222) on the electron supply layer (218), a gate electrode (224) on the gate layer (222), and a source electrode (232) and a drain electrode (234) disposed on both sides of the gate layer (222) in a predetermined direction and in contact with the electron transit layer (216), the gate layer (222) including a first gate layer (222) and a second gate layer (222) disposed on both sides of the source electrode (232) in the predetermined direction, the gate electrode (224) including a first gate electrode (224) formed on the first gate layer (222) and a second gate electrode (224) formed on the second gate layer (222),
forming, on a substrate, in this order, a first nitride semiconductor layer (216) constituting the electron transit layer (216), a second nitride semiconductor layer (218) constituting the electron supply layer (218), and a third nitride semiconductor layer (222) constituting the gate layer (222);
forming a metal layer (224) constituting the gate electrode (224) and a first mask layer (261) in this order on the third nitride semiconductor layer (222);
patterning the first mask layer (261) to form a first mask (262) partially covering the metal layer (224);
forming a second mask layer (264) covering the metal layer (224) and the first mask (262);
Etching back the second mask layer (264) to form second masks (264A, 264B) covering both side surfaces of the first mask;
removing the first mask (262);
Etching the metal layer using the second mask (264A, 264B) to form the first gate electrode (224A) and the second gate electrode (224B);
Etching the third nitride semiconductor layer (33) using the first gate electrode (224A) and the second gate electrode (224B) to form the first gate layer (222A) and the second gate layer (222B);
A method for manufacturing a nitride semiconductor device comprising the steps of:

(Appendix B16)
removing the second mask after forming the first gate electrode (224) and the second gate electrode (224);
forming a third mask layer (266) covering the first gate electrode (224), the second gate electrode (224), and the third nitride semiconductor layer (222);
Etching back the third mask layer (266) to form a third mask (2661, 2662) covering both side surfaces of the first gate electrode (224) and both side surfaces of the second gate electrode (224);
Including,
forming the first gate layer (222A) and the second gate layer (222B) by etching the third nitride semiconductor layer (222) using the first gate electrode (224), the second gate electrode (224), and the third mask (2661, 2662);
A method for manufacturing a nitride semiconductor device according to Appendix B15.

The above description is merely illustrative. Those skilled in the art may recognize that many more possible combinations and permutations are possible other than the components and methods (manufacturing processes) enumerated for purposes of describing the technology of the present disclosure. The present disclosure is intended to encompass all alternatives, modifications, and variations that are within the scope of the present disclosure, including the claims.

REFERENCE SIGNS LIST 10,100...Nitride semiconductor device 12...Semiconductor substrate 14...Buffer layer 16...Electron transit layer 18...Electron supply layer 20,102...Gate layer 20A,102A...Top surface 20B,102B...Bottom surface 22...Gate electrode 24...Passivation layer 24A...First opening 24B...Second opening 26...Source electrode 28...Drain electrode 30...Field plate electrode 32...First GaN layer 34...Second GaN layer 36,104...Ridge portion 38,106...First extension portion 40,108...Second extension portion 42,110...First step portion 44,112...First intermediate portion 46,114...Second step portion 48,116...Second intermediate portion 50...First nitride semiconductor layer 52...Second nitride semiconductor layer 54, 56... Mask 58... Metal layer 60, 64, 80, 84... Main body portion 62, 66, 82, 86... Connection portion 68, 88... Gate wiring 70, 90... Source wiring 72, 92... Drain wiring 74, 76, 78, 94, 96, 98... Vias 210A, 210B, 210C... Nitride semiconductor device 212... Substrate 212S... Upper surface 214... Buffer layer 216... Electron transit layer (first nitride semiconductor layer)
216A: First semiconductor layer 216B: Second semiconductor layer 218: Electron supply layer (second nitride semiconductor layer)
218S: upper surface 2181: source connection region 2182: drain connection region 220: two-dimensional electron gas 222: gate layer (third nitride semiconductor layer)
222A: First gate layer 222B: Second gate layer 222R: Lower surface 222S: Upper surface 2221, 2221A, 2221B: Source side gate surface 2222, 2222A, 2222B: Drain side gate surface 222S1: First side space portion 222S2: Second side space portion 224: Gate electrode (metal layer)
224A...first gate electrode 224B...second gate electrode 224R...lower surface 224S...upper surface 2241, 2241A, 2241B...source side electrode surface 2242, 2242A, 2242B...drain side electrode surface 226...passivation layer 226S...upper surface 2261...source opening 2262...drain opening 232...source electrode 234...drain electrode 234A...first drain electrode 234B...second drain electrode 236...source field plate portion 2361...end 261...first mask layer 262...first mask 264...second mask layer 264A...second mask 264B...second mask 2641...side surface 2642...side surface 266...third mask layer 2661, 2662...third mask 282...Third nitride semiconductor layer 282...Gate layer 282A...First gate layer 282B...Second gate layer 2821, 2821A, 2821B...Source side gate surface 2822, 2822A, 2822B...Drain side gate surface 284...Gate electrode (metal layer)
284A...First gate electrode 284B...Second gate electrode 2841, 2841A, 2841B...Source side electrode surface 2842, 2842A, 2842B...Drain side electrode surface 292...Gate layer 293...Ridge portion 293S...Upper surface 2931...Source side gate surface 2932...Drain side gate surface 294...Source side step portion 295...Drain side step portion θ11, θ12...Tilt angle θ21, θ22...Tilt angle L1A, L1B...Distance L2A, L2B...Distance W11, W11A, W11B...Width W12...Width W21, W21A, W21B...Width W22...Width

Claims (15)

an electron transit layer made of a nitride semiconductor;
an electron supply layer formed on the electron transit layer and made of a nitride semiconductor having a band gap larger than that of the electron transit layer;
a gate layer formed on the electron supply layer and made of a nitride semiconductor containing an acceptor-type impurity;
a gate electrode formed on the gate layer;
a source electrode and a drain electrode formed on the electron supply layer;
the gate layer includes an upper surface in contact with the gate electrode, the upper surface being a Ga polar surface. The gate layer is
a first GaN layer in contact with the gate electrode;
2. The nitride semiconductor device according to claim 1, further comprising: a second GaN layer in contact with said electron supply layer, said first GaN layer being made of Ga-polarity GaN, and said second GaN layer being made of N-polarity GaN. The nitride semiconductor device of claim 2, wherein the second GaN layer is thicker than the first GaN layer. The nitride semiconductor device of claim 2, wherein the gate layer has a thickness of 100 nm or more and less than 150 nm, and the first GaN layer has a thickness of 5 nm or more and less than 30 nm. The second GaN layer is
a ridge portion in contact with the electron supply layer and covered with the first GaN layer;
The nitride semiconductor device according to claim 2 , further comprising: an extension portion in contact with said electron supply layer and extending outward beyond said ridge portion in a plan view, said extension portion being thinner than said ridge portion. The nitride semiconductor device according to claim 5, wherein the extension portion includes an upper surface, at least a portion of which is an N-polar surface. The nitride semiconductor device of claim 1, wherein the gate layer is made of Ga-polar GaN. The gate layer is
a ridge portion in contact with the electron supply layer and including the upper surface of the gate layer;
The nitride semiconductor device according to claim 7 , further comprising: an extension portion that is in contact with said electron supply layer, that extends outward from said ridge portion in a plan view, and that is thinner than said ridge portion. The nitride semiconductor device according to any one of claims 1 to 8, wherein the upper surface of the gate layer forms a Schottky junction with the gate electrode. a passivation layer covering the electron supply layer, the gate layer, and the gate electrode and having a first opening and a second opening;
the source electrode is in contact with the electron supply layer through the first opening,
the drain electrode is in contact with the electron supply layer through the second opening,
9. The nitride semiconductor device according to claim 1, wherein said gate layer is located between said first opening and said second opening. the electron transport layer is made of GaN;
The electron supply layer is made of Al _x Ga _1-x N, where 0.1<x<0.3.
The nitride semiconductor device according to any one of claims 1 to 8. The nitride semiconductor device according to claim 2, wherein the first GaN layer contains hydrogen at a higher concentration than the second GaN layer. The nitride semiconductor device according to any one of claims 1 to 8, further comprising a semiconductor substrate and a buffer layer formed on the semiconductor substrate, and the electron transit layer is formed on the buffer layer. forming an electron transit layer made of a nitride semiconductor;
forming an electron supply layer on the electron transit layer, the electron supply layer being made of a nitride semiconductor having a band gap larger than that of the electron transit layer;
forming a gate layer made of a nitride semiconductor containing an acceptor-type impurity on the electron supply layer;
forming a gate electrode on the gate layer;
forming a source electrode and a drain electrode on the electron supply layer;
the gate layer includes an upper surface in contact with the gate electrode, the upper surface being a Ga polar surface. forming the gate layer
forming a first nitride semiconductor layer, which is N-polar GaN grown using _N2 as a carrier gas, on the electron supply layer;
15. The method of claim 14, further comprising: forming a second nitride semiconductor layer on the first nitride semiconductor layer, the second nitride semiconductor layer being Ga-polar GaN grown using _H2 as a carrier gas.

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