JP2024046581A - Light receiving element and light detection device - Google Patents

Abstract

[Problem] To provide a light receiving element and a light detection device capable of reducing dark current. [Solution] The light receiving element has a substrate having a first main surface, a light receiving layer provided on the first main surface, a contact layer provided on the light receiving layer, and a groove separating the contact layer for each pixel, the light receiving layer has a first semiconductor layer provided on the first main surface and a second semiconductor layer provided on the first semiconductor layer, the first semiconductor layer has a type II quantum well layer including an InGaAs layer and a GaAsSb layer, the second semiconductor layer has an AlxGayIn1-x-yAs layer (0≦x<1, 0≦y<1, 0<x+y<1), the bottom surface of the groove is in the second semiconductor layer, and the light receiving layer has an n-type region in a portion exposed to the bottom surface. [Selected Figure] Figure 1

Description

The present disclosure relates to a light receiving element and a light detection device.

A photodetector that detects infrared rays and has a type II quantum well layer in the light receiving layer is disclosed. In the photodetector, a groove for separating pixels is formed, and a mesa is provided for each pixel.

Japanese Patent Application Publication No. 2001-144278 Japanese Patent Application Publication No. 2013-175686 Japanese Patent Application Publication No. 2015-149422

With conventional light receiving elements, it is difficult to further reduce dark current.

The present disclosure aims to provide a light receiving element and a photodetecting device that can reduce dark current.

The light-receiving element of the present disclosure comprises a substrate having a first major surface, an absorption layer provided on the first major surface, a contact layer provided on the absorption layer, and grooves separating the contact layer for each pixel, the absorption layer having a first semiconductor layer provided on the first major surface and a second semiconductor layer provided on the first semiconductor layer, the first semiconductor layer having a type II quantum well layer including an InGaAs layer and a GaAsSb layer, the second semiconductor layer having an Al _x Ga _y In _1-x-y As layer (0≦x<1, 0≦y<1, 0<x+y<1), a bottom surface of the groove is in the second semiconductor layer, and the absorption layer has an n-type region in a portion exposed to the bottom surface.

According to the present disclosure, dark current can be reduced.

FIG. 1 is a cross-sectional view showing a light receiving element according to the first embodiment. FIG. 2 is a cross-sectional view (part 1) illustrating the method for manufacturing the light-receiving element according to the first embodiment. FIG. 3 is a cross-sectional view (part 2) showing the method for manufacturing the light receiving element according to the first embodiment. FIG. 4 is a cross-sectional view (part 3) showing the method for manufacturing the light-receiving element according to the first embodiment. FIG. 5 is a cross-sectional view (part 4) showing the method for manufacturing the light-receiving element according to the first embodiment. 6A to 6C are cross-sectional views (part 5) illustrating the method for manufacturing the light-receiving element according to the first embodiment. FIG. 7 is a cross-sectional view (Part 6) showing the method for manufacturing the light receiving element according to the first embodiment. FIG. 8 is a cross-sectional view (part 7) showing the method for manufacturing the light-receiving element according to the first embodiment. FIG. 9 is a cross-sectional view (part 8) showing the method for manufacturing the light-receiving element according to the first embodiment. FIG. 10 is a cross-sectional view showing an example of a detailed structure of a mesa. FIG. 11 is a cross-sectional view showing the simulated sample. FIG. 12 is a diagram showing the relationship between n-type carrier concentration and dark current. FIG. 13 is a diagram showing the measurement results of the concentration profile of hydrogen atoms. FIG. 14 is a diagram showing the measurement results of dark current. FIG. 15 is a cross-sectional view showing a light detection device according to the second embodiment. FIG. 16 is a cross-sectional view showing a light receiving element according to the third embodiment. FIG. 17 is a cross-sectional view showing a light receiving element according to the fourth embodiment. FIG. 18 is a cross-sectional view showing a light receiving element according to the fifth embodiment. FIG. 19 is a cross-sectional view showing a light receiving element according to the sixth embodiment. FIG. 20 is a diagram showing the relationship between dimensional parameters and dark current density. FIG. 21 is a diagram showing a measurement system used for measuring quantum efficiency. FIG. 22 is a diagram showing the relationship between wavelength and quantum efficiency.

[Description of embodiments of the present disclosure]
First, embodiments of the present disclosure will be listed and described.

[1] A light-receiving element according to one aspect of the present disclosure includes a substrate having a first main surface, an absorption layer provided on the first main surface, a contact layer provided on the absorption layer, and grooves separating the contact layer for each pixel, the absorption layer includes a first semiconductor layer provided on the first main surface and a second semiconductor layer provided on the first semiconductor layer, the first semiconductor layer includes a type II quantum well layer including an InGaAs layer and a GaAsSb layer, the second semiconductor layer includes an Al _x Ga _y In _1-x-y As layer (0≦x<1, 0≦y<1, 0<x+y<1), a bottom surface of the groove is within the second semiconductor layer, and the absorption layer includes an n-type region in a portion exposed to the bottom surface.

As will be described later, by having the n-type region in the portion of the light-receiving layer exposed at the bottom of the groove, crystal leakage can be suppressed and dark current can be reduced. Further, the first semiconductor layer has high sensitivity in a wavelength range of, for example, 1.0 μm or more and 2.5 μm or less.

[2] In [1], the concentration of n-type carriers in the n-type region may be 5×10 ¹⁷ cm ⁻³ or more. In this case, it is easy to reduce dark current.

[3] In [1] or [2], the thickness of the n-type region may be 0.05 μm or more. In this case, it is easy to reduce dark current.

[4] In any of [1] to [3], the distance between the n-type region and the contact layer may be 1.0 μm or more in a plan view perpendicular to the first main surface. In this case, it is easy to reduce dark current.

[5] In any one of [1] to [4], the substrate may be an n-type InP substrate. In this case, crystal growth of the first semiconductor layer, second semiconductor layer, and contact layer is facilitated. Further, a voltage can be applied to the light-receiving layer between the substrate and the contact layer.

[6] In any of [1] to [5], the n-type region may contain hydrogen as an n-type impurity. When hydrogen is used, n-type carriers can be obtained without performing activation annealing.

[7] In any of [1] to [6], the substrate may have a second main surface opposite to the first main surface and an anti-reflection film provided on the second main surface. As described below, even if a temperature load is applied to the light-receiving layer when the anti-reflection film is formed, the presence of the n-type region suppresses an increase in crystal leakage.

[8] In any one of [1] to [7], the second semiconductor layer may have a Ga _y In _1-y As layer (0<y<1). In this case, the second semiconductor layer has high sensitivity in a wavelength range of, for example, 1.0 μm or more and 1.6 μm or less.

[9] In [8], the second semiconductor layer may have an Al _x In _1-x As layer (0<x<1) provided on the Ga _y In _1-y As layer, and the bottom surface of the groove may be in the Al _x In _1-x As layer. In this case, the band gap of the Al _x In _1-x As layer is larger than the band gap of the Ga _y In _1-y As layer, so that surface leakage is easily suppressed.

[10] In [8], the second semiconductor layer may include an InP layer provided on the Ga _y In _1-y As layer, and the bottom surface of the groove may be within the InP layer. . In this case, the band gap of the InP layer is larger than the band gap of the Ga _y In _1-y As layer, and P contained in the InP layer is difficult to oxidize, so surface leakage can be further suppressed.

[11] In any one of [1] to [7], the second semiconductor layer may have an Al _x In _1-x As layer (0<x<1). In this case, the band gap of the Al _x In _1-x As layer is larger than the band gap of the Ga _y In _1-y As layer, so that surface leakage is easily suppressed.

[12] A light-receiving element according to another aspect of the present disclosure includes an n-type InP substrate having a first main surface and a second main surface opposite to the first main surface, an absorption layer provided on the first main surface, a contact layer provided on the absorption layer, grooves separating the contact layer for each pixel, and an antireflection film provided on the second main surface, the absorption layer includes a first semiconductor layer provided on the first main surface and a second semiconductor layer provided on the first semiconductor layer, the first semiconductor layer includes a type II quantum well layer including an InGaAs layer and a GaAsSb layer, the second semiconductor layer includes an Al _x Ga _y In _1-x-y As layer (0≦x<1, 0≦y<1, 0<x+y<1), a bottom surface of the groove is in the second semiconductor layer, the absorption layer contains hydrogen in a portion exposed to the bottom surface, and an n-type carrier concentration is 5×10 ¹⁷ cm The semiconductor device has an n-type region having an n-type conductivity of ^-3 or more, the thickness of the n-type region being 0.1 μm or more, and the distance between the n-type region and the contact layer being 1.0 μm or more in a plan view perpendicular to the first main surface. In this case, it is particularly easy to reduce dark current.

[13] A photodetection device according to still another aspect of the present disclosure includes the light receiving element according to any one of [1] to [12], and a circuit board connected to the light receiving element. When the photodetector includes the above-mentioned light receiving element, dark current is reduced and a good S/N ratio can be obtained.

[Details of the embodiment of the present disclosure]
Hereinafter, the embodiments of the present disclosure will be described in detail, but the present disclosure is not limited thereto. In this specification and drawings, components having substantially the same functional configurations may be denoted by the same reference numerals to avoid redundant description.

First, the background to the invention will be described. The inventors of the present application conducted extensive research to clarify the path of dark current in a conventional light receiving element having a type II quantum well layer in the light receiving layer. As a result, it was found that the crystal leakage was suppressed before the anti-reflection film was formed on the substrate, whereas the crystal leakage increased after the anti-reflection film was formed. However, when a single-layer light receiving layer of indium gallium arsenide (InGaAs) was used instead of the type II quantum well layer, such an increase in crystal leakage did not occur.

The inventors of the present application believe that when a Type II quantum well layer is used, the temperature load during the formation of the anti-reflection film causes an increase in crystal leakage. We conducted further careful consideration. As a result, it was found that although no impurity was intentionally introduced into the light-receiving layer, the amount of hydrogen (H), which is an unavoidable n-type impurity, was changed. In other words, it was found that the amount of hydrogen was reduced after the antireflection film was applied compared to before. Note that between the formation of the mesa and the formation of the anti-reflection film, a silicon oxide (SiO ₂ ) film is formed to cover the mesa and the pixel isolation groove, and during the formation of the SiO ₂ film, hydrogen is absorbed into the light-receiving layer. May be mixed into the surface layer. It has also been revealed that by intentionally providing a region with a high concentration of n-type carriers in the light-receiving layer, crystal leakage can be suppressed to a low level even after the antireflection film is formed, and dark current can be suppressed. The mechanism by which crystal leakage is suppressed by the presence of a region with a high concentration of n-type carriers is not clear, but the presence of n-type carriers changes the band structure of the path where crystal leakage occurs, suppressing charge tunneling. This is thought to be due to the

First Embodiment
A first embodiment will be described. The first embodiment relates to a light receiving element. Fig. 1 is a cross-sectional view showing a light receiving element according to the first embodiment.

In the light receiving element 100 according to the first embodiment, for example, 256×320 pixels are formed at a pitch of 30 μm. The pixel pitch may be, for example, 50 μm or 90 μm. For example, the light receiving element 100 may have 512×640 pixels or 32×128 pixels.

As shown in FIG. 1, the light receiving element 100 includes a substrate 10, a light receiving layer 20, a p-type contact layer 25, a passivation film 31, an antireflection film 32, a p electrode 40, and a first n-electrode 51. , a second n-electrode 52, a wiring 53, an indium (In) bump 61, and an In bump 62.

The substrate 10 is, for example, an n-type indium phosphide (InP) substrate. The substrate 10 contains, for example, sulfur (S) at a concentration of about 5×10 ¹⁸ cm ⁻³ . The substrate 10 has a first main surface 10a and a second main surface 10b opposite to the first main surface 10a. The thickness of the substrate 10 is, for example, about 300 μm. An n-type buffer layer may be provided on the first main surface 10a. The buffer layer is, for example, an InP layer with a thickness of about 0.5 μm. The buffer layer contains, for example, silicon (Si) at a concentration of about 1×10 ¹⁸ cm ⁻³ . The light-receiving layer 20 and the p-type contact layer 25 are stacked on the first main surface 10a. The antireflection film 32 is provided on the second main surface 10b.

The light receiving layer 20 has a first semiconductor layer 21 and a second semiconductor layer 22. The first semiconductor layer 21 is provided on the substrate 10, and the second semiconductor layer 22 is provided on the first semiconductor layer 21. The first semiconductor layer 21 is, for example, a type II quantum well layer in which indium gallium arsenide (InGaAs) and gallium arsenic antimonide (GaAsSb) are alternately stacked. For example, the thickness of the InGaAs layer is 2 nm or more and 6 nm or less, and the thickness of the GaAsSb layer is 2 nm or more and 6 nm or less. The number of pairs of the InGaAs layer and the GaAsSb layer is, for example, 100 or more and 350 or less. For example, the composition of the InGaAs layer included in the first semiconductor layer 21 is In _0.53 Ga _0.47 As, and the composition of the GaAsSb layer is GaAs _0.51 Sb _0.49 . In _0.53 Ga _0.47 As and GaAs _0.51 Sb _0.49 are lattice-matched to InP. The second semiconductor layer 22 is, for example, an InGaAs layer. The thickness of the second semiconductor layer 22 is, for example, about 1 μm. For example, the composition of the InGaAs layer included in the second semiconductor layer 22 is In _0.53 Ga _0.47 As. Even if the composition of the InGaAs layer included in the second semiconductor layer 22 is In _1-y Ga _y As (0.454≦y≦0.499), the lattice distortion between the second semiconductor layer 22 and InP can be suppressed to be particularly small.

The p-type contact layer 25 is, for example, a p-type InGaAs layer. The p-type contact layer 25 contains, for example, zinc (Zn) at a concentration of about 1×10 ¹⁹ cm ⁻³ . The thickness of the p-type contact layer 25 is, for example, 0.2 μm. Although no impurity is intentionally implanted into the second semiconductor layer 22, the second semiconductor layer 22 has a weak n-type conductivity type due to the unavoidable mixing of impurities. Therefore, a pn junction exists between the second semiconductor layer 22 and the p-type contact layer 25.

A first groove 71 for separating pixels and a second groove 72 for exposing the substrate 10 are formed in the p-type contact layer 25 and the second semiconductor layer 22.

The first groove 71 is formed in part of the p-type contact layer 25 and the second semiconductor layer 22, and the second semiconductor layer 22 is exposed at the bottom of the first groove 71. That is, the bottom surface of the first groove 71 is located in the second semiconductor layer 22. A mesa 70 is formed for each pixel by the first groove 71, and the pixels are separated. The depth of the first groove 71 is about 0.5 μm, and the width is about 5 μm. The planar shape of the mesa 70 is, for example, a square with a side length of 20 μm. The second groove 72 is formed in the p-type contact layer 25, the second semiconductor layer 22, the first semiconductor layer 21, and a part of the substrate 10, and the substrate 10 is exposed at the bottom of the second groove 72. . The second groove 72 separates the pixel region 11 and the electrode connection region 12 from each other. Mesa 70 is formed in pixel region 11 . A mesa 73 is formed in the electrode connection region 12 .

Passivation film 31 covers p-type contact layer 25, light-receiving layer 20, and substrate 10. The passivation film 31 is, for example, a silicon oxide (SiO ₂ ) film. The thickness of the passivation film 31 is, for example, about 0.3 μm. An opening 31 a that exposes the p-type contact layer 25 of the mesa 70 and an opening 31 b that exposes the substrate 10 between the pixel region 11 and the electrode connection region 12 are formed in the passivation film 31 .

A p-electrode 40 is formed on the p-type contact layer 25 in each mesa 70. The p-electrode 40 contacts the p-type contact layer 25 through the opening 31a. The p-electrode 40 is made of a metal laminate film in which, for example, a titanium (Ti) layer, a platinum (Pt) layer, and a gold (Au) layer are laminated in this order.

A first n-electrode 51 is formed on the substrate 10 between the pixel region 11 and the electrode connection region 12. The first n-electrode 51 contacts the substrate 10 through the opening 31b. A second n-electrode 52 is formed on the p-type contact layer 25 on the mesa 73 . The first n-electrode 51 and the second n-electrode 52 are made of a metal laminated film in which, for example, a Ti layer, a Pt layer, and an Au layer are laminated in this order.

The wiring 53 connects the first n-electrode 51 and the second n-electrode 52. The wiring 53 is formed on the passivation film 31. The wiring 53 is constituted by a metal laminated film in which, for example, a nickel (Ni) layer and an Au layer are laminated in this order.

An In bump 61 is provided on the p-electrode 40. In each pixel in the pixel region 11, a p-electrode 40 having a circular planar shape is formed on the upper surface of the mesa 70, and an In bump 61 having a circular planar shape is formed on the p-electrode 40. .

In the electrode connection region 12, an In bump 62 is provided on the second n-electrode 52. The In bump 62 has a circular planar shape and is formed on the second n-electrode 52.

The p-electrode 40 and the second n-electrode 52 are connected to electrodes provided on the readout circuit board 300 (see FIG. 15) via In bumps 61 and 62, respectively. The height of the In bumps 61 and 62 is, for example, about 10 μm.

The light receiving layer 20 has an n-type region 24 having an n-type conductivity type in a portion exposed to the bottom surface of the first groove 71. The upper surface of the n-type region 24 is at least a part of the bottom surface of the first groove 71. The n-type region 24 is formed in a ring shape so as to surround the mesa 70 in a plan view. The n-type region 24 contains an n-type impurity, for example, a type carrier. The n-type impurity is, for example, hydrogen (H). The n-type region 24 may be present only in the second semiconductor layer 22, or may be present in both the first semiconductor layer 21 and the second semiconductor layer 22. The thickness of the n-type region 24 is, for example, 0.05 μm or more. In a plan view, the n-type region 24 is separated from the mesa 70. Note that the n-type region 24 is formed, for example, by ion implantation into the light receiving layer 20, and no intentional implantation of impurities is performed in other regions of the light receiving layer 20, but impurities may be inevitably mixed into the surface layer portion of the light receiving layer 20 when the passivation film 31 is formed, etc. The depth of the impurities that are inevitably mixed in is at most about 0.1 μm. The concentration of n-type carriers in the regions of the absorption layer 20 other than the n-type region 24 is, for example, less than 1×10 ¹⁵ cm ⁻³ .

The antireflection film 32 is, for example, a silicon oxynitride (SiON) film. For example, the refractive index of the antireflection film 32 is about 1.8, and the film thickness is about 148 nm.

Next, a method for manufacturing the light receiving element 100 according to the first embodiment will be described. 2 to 9 are cross-sectional views showing a method of manufacturing the light receiving element according to the first embodiment.

First, as shown in FIG. 2, the first semiconductor layer 21, the second semiconductor layer 22, and the p-type contact layer 25 are formed in this order by epitaxial growth on the first major surface 10a of the substrate 10. Metal organic vapor phase epitaxy (MOVPE) is used for the epitaxial growth of the compound semiconductor layers. The thickness of the substrate 10 is, for example, about 350 μm. Before the formation of the first semiconductor layer 21, an n-type buffer layer may be formed on the first major surface 10a of the substrate 10.

Next, as shown in FIG. 3, a first groove 71 for pixel separation is formed. Specifically, a silicon nitride (SiN) film (not shown) having a thickness of 0.5 μm is formed on the p-type contact layer 25 by plasma chemical vapor deposition (CVD) method, a photoresist is applied on the formed SiN film, and a resist pattern (not shown) is formed by performing exposure and development using an exposure device. This resist pattern has an opening in the area where the first groove 71 is formed, and the SiN film in the opening of the resist pattern is removed by wet etching using buffered hydrofluoric acid to form a mask with the SiN film. After that, the resist pattern (not shown) is removed by an organic solvent or the like. After that, the p-type contact layer 25 and a part of the second semiconductor layer 22 in the area where the SiN film has been removed are removed by dry etching such as reactive ion etching (RIE). In this RIE, for example, a mixed gas of silicon tetrachloride (SiCl ₄ ) gas and argon (Ar) gas is used. In this manner, a first groove 71 for isolating pixels is formed. Along with the formation of the first groove 71, a mesa 70 is formed, and each pixel is separated. In this process, the compound semiconductor layer in the region where a second groove 72 (described later) is formed is also removed in the same manner. Thereafter, the SiN film (not shown) is removed with buffered hydrofluoric acid.

Next, as shown in FIG. 4, a second groove 72 is formed along the outer periphery of the substrate 10. Specifically, a SiN film (not shown) with a thickness of 0.5 μm is formed on the p-type contact layer 25 etc. by plasma CVD method, and a photoresist is applied on the formed SiN film. Then, a resist pattern (not shown) is formed by performing exposure and development using an exposure device. This resist pattern has an opening in the region where the second groove 72 is formed, and by removing the SiN film in the opening of the resist pattern by wet etching using buffered hydrofluoric acid, the SiN film is removed. to form a mask. Thereafter, the resist pattern (not shown) is removed using an organic solvent or the like, and then the second semiconductor layer 22, the first semiconductor layer 21, and a part of the substrate 10 in the area where the SiN film has been removed are subjected to dry etching such as RIE. By removing, the surface of the substrate 10 is exposed. Thereafter, the SiN film (not shown) is removed using buffered hydrofluoric acid. In this way, the second groove 72 is formed, and a mesa 73 is formed outside the second groove 72 when viewed from the mesa 70.

Dry etching causes damage to the compound semiconductor layer. For this reason, after forming the second groove 72, dry etching is performed to remove the damaged portion. For this dry etching, a mixed solution with a mass ratio of sulfuric acid:hydrogen peroxide:water=1:1:60 is used, for example.

5, a _SiO2 film 81 having a thickness of 0.3 μm is formed so as to cover the p-type contact layer 25, the absorption layer 20, and the substrate 10. Next, a photoresist is applied onto the _SiO2 film 81, and a resist pattern 82 is formed by performing exposure and development using an exposure device. The thickness of the resist pattern 82 is, for example, about 3 μm. The resist pattern 82 has an opening 83 in the region where the n-type region 24 is to be formed.

Next, using the resist pattern 82 as a selective ion implantation mask, hydrogen ions are implanted to form the n-type region 24 in the absorption layer 20. For example, the dose of hydrogen ions is 3×10 ¹⁵ cm ^-2 and the acceleration voltage is 46 keV. The SiO ₂ film 81 suppresses surface roughness of the p-type contact layer 25, the second semiconductor layer 22, and the substrate 10 during ion implantation.

Next, as shown in FIG. 6, the resist pattern 82 and the SiO ₂ film 81 are removed. Next, the passivation film 31 is formed. Specifically, a SiO ₂ film (not shown) is formed on the entire surface by plasma CVD, a photoresist is applied on the formed SiO ₂ film, and a resist pattern (not shown) is formed by performing exposure and development using an exposure device. The SiO ₂ film is formed at a substrate temperature of, for example, 150° C. This resist pattern has openings in the region where the p-electrode 40 is formed and the region where the first n-electrode 51 is formed, and the SiO ₂ film in the openings of the resist pattern is removed by dry etching such as RIE. As a result, the passivation film 31 is formed, which has an opening 31a that exposes the surface of the p-type contact layer 25 of the mesa 70 and an opening 31b that exposes the surface of the substrate 10.

Next, as shown in FIG. 7, a p-electrode 40 is formed on the p-type contact layer 25, a first n-electrode 51 is formed on the substrate 10, and a passivation film 31 is formed on the mesa 73. A second n-electrode 52 is formed. The p-electrode 40, the first n-electrode 51, and the second n-electrode 52 are formed by a lift-off method. Specifically, a resist pattern (not shown) having openings in a region where the p-electrode 40 is formed, a region where the first n-electrode 51 is formed, and a region where the second n-electrode 52 is formed is formed, A metal laminated film in which a Ti layer, a Pt layer, and an Au layer are sequentially laminated is formed by electron beam (EB) evaporation, and then immersed in an organic solvent or the like. As a result, the metal laminated film on the resist pattern is removed together with the resist pattern, and the p-electrode 40, the first n-electrode 51, and the second n-electrode 52 are formed from the remaining metal laminated film.

Further, a wiring 53 connecting the first n-electrode 51 and the second n-electrode 52 is formed by a lift-off method. Specifically, a resist pattern (not shown) having an opening in the region where the wiring 53 is to be formed is formed, a metal laminated film in which a Ni layer and an Au layer are sequentially laminated by EB evaporation is formed, and then an organic layer is formed. Immerse it in a solvent, etc. As a result, the metal laminated film on the resist pattern is removed together with the resist pattern, and the wiring 53 is formed from the remaining metal laminated film.

Next, as shown in FIG. 8, the second main surface 10b of the substrate 10 is polished to a mirror surface. Next, an antireflection film 32 is formed on the second main surface 10b. The antireflection film 32 is formed by plasma CVD. The antireflection film 32 is formed at a substrate temperature of, for example, 200°C. The time required to form the antireflection film 32 is, for example, about 40 minutes.

Next, as shown in FIG. 9, an In bump 61 is formed on the p-electrode 40, and an In bump 62 is formed on the second n-electrode 52. The In bumps 61 and 62 are formed by a lift-off method. After this, the light receiving element 100 is formed by dividing it into chips.

In this way, the light receiving element 100 according to the first embodiment can be manufactured.

In the light receiving element 100 according to the first embodiment, the portion of the light receiving layer 20 exposed at the bottom surface of the first groove 71 has an n-type region 24 with n-type conductivity. Therefore, even if the n-type impurities inevitably contained in the light receiving layer 20 are reduced during the formation of the anti-reflection film 32, sufficient n-type impurities are present in the light receiving layer 20, and crystal leakage can be suppressed. Therefore, according to the first embodiment, dark current can be reduced.

In addition, the first semiconductor layer 21 has high sensitivity in the wavelength range of, for example, 1.0 μm or more and 2.5 μm or less, and the second semiconductor layer 22 has high sensitivity in the wavelength range of, for example, 1.0 μm or more and 1.6 μm or less.

By using an n-type InP substrate as the substrate 10, it is easy to grow the crystals of the first semiconductor layer 21, the second semiconductor layer 22, and the p-type contact layer 25. In addition, a voltage can be applied to the light receiving layer 20 between the substrate 10 and the p-type contact layer 25.

Note that the concentration of n-type carriers in the n-type region 24 may be 5×10 ¹⁷ cm ⁻³ or higher, 1×10 ¹⁸ cm ⁻³ or higher, or 1×10 ¹⁹ cm ⁻³ or higher. It may be. If the concentration of n-type carriers is too low, it may be difficult to obtain the effect of suppressing dark current. For example, when the concentration of n-type carriers is 5×10 ¹⁷ cm ⁻³ or more, the dark current can be easily suppressed to 5 pA or less. The concentration of n-type carriers can be measured, for example, by CV measurement.

The thickness of the n-type region 24 may be 0.05 μm or more, 0.1 μm or more, or 0.4 μm or more. If the n-type region 24 is too thin, it may be difficult to obtain the effect of suppressing dark current. The thickness of the n-type region 24 herein refers to the thickness of the region where the concentration of n-type carriers is 1×10 ¹⁵ cm ⁻³ or more.

In a plan view perpendicular to the first main surface 10a, the distance L1 between the n-type region 24 and the p-type contact layer 25 may be 1.0 μm or more, or 1.2 μm or more, It may be 1.5 μm or more. If the distance L1 between the n-type region 24 and the p-type contact layer 25 is too short, it may be difficult to obtain the effect of suppressing dark current. Note that, as shown in FIG. 10, the side surface of the mesa 70 may be a curved surface. FIG. 10 is a cross-sectional view showing an example of a detailed structure of the mesa 70.

Here, we will explain the various tests that the inventors conducted.

(First test)
In the first test, the relationship between the concentration of n-type carriers and the dark current was investigated. In the first test, a plurality of samples with different concentrations of n-type carriers in the absorption layer 20 were prepared by changing the forming conditions of the SiO ₂ film that becomes the passivation film 31 and by the presence or absence of heat treatment after the formation of the mesa 70. The heat treatment temperature was 200° C. and the time was 4 minutes. However, the n-type region 24 was not formed. Then, for each sample, the dark current was measured when a voltage of −1.2 V was applied between the p-electrode 40 and the second n-electrode 52 at a temperature of 213 K. The concentration of n-type carriers was not measured directly for each sample, but was measured by preparing a simulated sample shown in FIG. 11 under the same forming conditions of the SiO ₂ film as each sample and with or without heat treatment, and performing a CV measurement of the simulated sample. The simulated sample has a substrate 510 equivalent to the substrate 10, an InGaAs layer 520 on the substrate 10, a passivation film 531 on the InGaAs layer 520, and an electrode 540 on the passivation film 531. The n-type carrier concentration is the n-type carrier concentration in a region 521 from the interface between the InGaAs layer 520 and the passivation film 531 to 0.1 μm. The results are shown in FIG. 12. FIG. 11 is a cross-sectional view showing the simulated sample. FIG. 12 is a diagram showing the relationship between the n-type carrier concentration and dark current.

As shown in FIG. 12, the lower the concentration of n-type carriers, the larger the dark current. In the first test, the dark current was 5 pA when the n-type carrier concentration was 5×10 ¹⁷ cm ⁻³ or more.

(Second exam)
In the second test, a sample was prepared according to the first embodiment, and the concentration profile of hydrogen atoms in the n-type region 24 and the dark current were measured before and after the formation of the antireflection film 32. went. The thickness of the second semiconductor layer 22 is 0.8 μm, the thickness of the p-type contact layer 25 is 0.2 μm, the thickness of the n-type region 24 is 0.5 μm, and the thickness of the passivation film 31 is 0.8 μm. It was set to 3 μm. When forming the n-type region 24, the dose was 3×10 ¹⁵ cm ⁻² and the acceleration voltage was 46 keV. The concentration profile of hydrogen atoms was measured by secondary ion mass spectrometry (SIMS). Dark current was measured at a temperature of 213K. These results are shown in FIGS. 13 and 14. FIG. 13 is a diagram showing the measurement results of the concentration profile of hydrogen atoms. FIG. 14 is a diagram showing the measurement results of dark current.

As shown in FIG. 13, the concentration profile of hydrogen atoms changed before and after the formation of the anti-reflection film 32, but hydrogen atoms were still present in high concentration in the n-type region 24 even after the formation of the anti-reflection film 32. Also, as shown in FIG. 14, the magnitude of the dark current hardly changed before and after the formation of the anti-reflection film 32.

The results of the first and second tests confirm that the first embodiment suppresses dark current.

The impurity used to form the n-type region 24 is not limited to hydrogen. For example, sulfur (S) or silicon (Si) may be used. However, when hydrogen is used, n-type carriers can be obtained without performing activation annealing, but when sulfur or silicon is used, n-type carriers cannot be obtained without performing activation annealing. Since performing activation annealing may increase surface leakage, for example, the impurity used to form the n-type region 24 is hydrogen.

Second Embodiment
Next, a second embodiment will be described. The second embodiment relates to a light detection device including the light receiving element 100 according to the first embodiment. Fig. 15 is a cross-sectional view showing the light detection device according to the second embodiment.

The photodetector 200 according to the second embodiment has a light receiving element 100 and a read out integrated circuit (ROIC) 300. The read out circuit 300 has a wiring board 320, a pixel electrode 340, and a common electrode 350. The pixel electrode 340 and the common electrode 350 are arranged on one side of the wiring board 320. The read out circuit 300 includes a circuit, such as a multiplexer, that reads out a signal output from the light receiving element 100. The read out circuit 300 is an example of a circuit board.

The photodetecting device 200 further includes a connecting member 240 that connects the p-electrode 40 and the pixel electrode 340, and a connecting member 250 that connects the second n-electrode 52 and the common electrode 350. The connection member 240 includes the In bump 61 and the In bump that was provided on the pixel electrode 340 of the readout circuit board 300 before bonding. The connection member 250 includes the In bump 62 and the In bump that was provided on the common electrode 350 of the readout circuit board 300 before bonding.

According to the second embodiment, the dark current in the light receiving element 100 is suppressed, and an excellent S/N ratio is obtained.

(Third embodiment)
Next, a third embodiment will be described. The third embodiment differs from the first embodiment mainly in the configuration of the light-receiving layer. FIG. 16 is a sectional view showing a light receiving element according to the third embodiment.

The light receiving element 600 according to the third embodiment has a light receiving layer 620 instead of the light receiving layer 20. The light receiving layer 620 has a first semiconductor layer 21 and a second semiconductor layer 622. The second semiconductor layer 622 is, for example, an AlInAs layer. The thickness of the second semiconductor layer 622 is, for example, about 1 μm. For example, the composition of the AlInAs layer included in the second semiconductor layer 622 is Al _0.47 In _0.53 As. Even if the composition of the AlInAs layer included in the second semiconductor layer 622 is Al _x In _1-x As (0.464≦x≦0.509), the lattice distortion between the second semiconductor layer 622 and InP can be suppressed to be particularly small.

The first groove 71 is formed in a part of the p-type contact layer 25 and the second semiconductor layer 622, and the second semiconductor layer 622, for example an AlInAs layer, is exposed at the bottom surface of the first groove 71. That is, the bottom surface of the first groove 71 is in the second semiconductor layer 622. The n-type region 24 may be present only in the second semiconductor layer 622, or may be present in both the first semiconductor layer 21 and the second semiconductor layer 622.

Although no impurity is intentionally implanted into the second semiconductor layer 622, the second semiconductor layer 622 has weak n-type conductivity due to unavoidable mixing of impurities. Therefore, a pn junction exists between the second semiconductor layer 622 and the p-type contact layer 25.

The other configurations of the third embodiment are the same as those of the first embodiment.

In the light receiving element 600 according to the third embodiment, the light receiving layer 620 has an n-type region 24 with n-type conductivity in the portion exposed to the bottom surface of the first groove 71, and the upper surface of the n-type region 24 is at least a part of the bottom surface of the first groove 71. Therefore, even if the n-type impurities inevitably contained in the light receiving layer 620 are reduced during the formation of the anti-reflection film 32, there is sufficient n-type impurity in the light receiving layer 620, and crystal leakage can be suppressed. Therefore, the dark current can be reduced according to the third embodiment.

Furthermore, in the third embodiment, the second semiconductor layer 622 includes an AlInAs layer, and the band gap of AlInAs is larger than that of InGaAs. For example, when comparing compositions that are lattice matched to InP, the band gap of In _0.53 Ga _0.47 As is 0.73 eV, while the band gap of Al _0.47 In _0.53 As is 1.42 eV. It is. Therefore, according to the third embodiment, surface leakage can be suppressed more than in the first embodiment. The smaller the pixel, the higher the proportion of surface leakage in the dark current. Therefore, the effect of the third embodiment becomes more pronounced as the pixel becomes smaller.

(Fourth embodiment)
Next, a fourth embodiment will be described. The fourth embodiment differs from the first embodiment mainly in the configuration of the light-receiving layer. FIG. 17 is a cross-sectional view showing a light receiving element according to the fourth embodiment.

The light receiving element 700 according to the fourth embodiment has a light receiving layer 720 instead of the light receiving layer 620. The light receiving layer 720 has a first semiconductor layer 21 and a second semiconductor layer 722. The second semiconductor layer 722 has, for example, an InGaAs layer 722A and an AlInAs layer 722B. The AlInAs layer 722B is provided on the InGaAs layer 722A. The thicknesses of the InGaAs layer 722A and the AlInAs layer 722B are, for example, about 1 μm each. For example, the composition of the InGaAs layer 722A is In _0.53 Ga _0.47 As, and the composition of the AlInAs layer 722B is Al _0.47 In _0.53 As. Even if the composition of the InGaAs layer 722A is _{In1-yGayAs (} 0.454≦y≦0.499), the lattice distortion between the InGaAs layer 722A and InP can be suppressed to be particularly small. Even if the composition of the AlInAs layer 722B is _{AlxIn1 -xAs} (0.464≦x≦0.509), the lattice distortion between the AlInAs layer 722B and InP can be suppressed to be particularly small.

The first groove 71 is formed in the p-type contact layer 25 and part of the AlInAs layer 722B, and the AlInAs layer 722B is exposed at the bottom surface of the first groove 71. That is, the bottom surface of the first groove 71 is in the AlInAs layer 722B. The top surface of the n-type region 24 is at least a part of the bottom surface of the first groove 71. The n-type region 24 may be only in the AlInAs layer 722B, or may be in the InGaAs layer 722A and the AlInAs layer 722B, or may be in the first semiconductor layer 21 and the second semiconductor layer 722.

Although no impurities are intentionally implanted into the AlInAs layer 722B, the AlInAs layer 722B has a weak n-type conductivity due to the unavoidable inclusion of impurities. Therefore, a pn junction exists between the AlInAs layer 722B and the p-type contact layer 25.

The other configurations of the fourth embodiment are the same as those of the first embodiment.

In the light-receiving element 700 according to the fourth embodiment, the light-receiving layer 720 has an n-type region 24 having an n-type conductivity in a portion exposed to the bottom surface of the first groove 71, and the upper surface of the n-type region 24 is This is at least a portion of the bottom surface of the first groove 71 . Therefore, even if the n-type impurity inevitably included in the light-receiving layer 720 is reduced during the formation of the antireflection film 32, a sufficient amount of n-type impurity exists in the light-receiving layer 720, and crystal leakage can be suppressed. Therefore, the fourth embodiment can also reduce dark current.

Furthermore, in the fourth embodiment, the second semiconductor layer 622 has an AlInAs layer 722B, so that, like the third embodiment, surface leakage can be suppressed more than in the first embodiment.

AlInAs layer 722B has high sensitivity in the wavelength range of, for example, 0.9 μm or less, but does not absorb light in the wavelength range of 1.0 μm or more and 1.6 μm or less. Therefore, in the third embodiment, the sensitivity in the wavelength range of 1.0 μm or more and 1.6 μm or less may be lower than in the first embodiment. On the other hand, in the fourth embodiment, the second semiconductor layer 622 has not only the AlInAs layer 722B but also the InGaAs layer 722A, so that the same level of sensitivity as in the first embodiment can be obtained in the wavelength range of 1.0 μm or more and 1.6 μm or less.

Fifth Embodiment
Next, a fifth embodiment will be described. The fifth embodiment differs from the fourth embodiment mainly in the configuration of the light receiving layer. Fig. 18 is a cross-sectional view showing a light receiving element according to the fifth embodiment.

In the light receiving element 701 according to the fifth embodiment, the light receiving layer 720 has a p-type AlInAs layer 722C in addition to the InGaAs layer 722A and the AlInAs layer 722B. The p-type AlInAs layer 722C is provided on the AlInAs layer 722B. The p-type AlInAs layer 722C contains, for example, Zn at a concentration of about 1×10 ¹⁹ cm ⁻³ . The thickness of the p-type AlInAs layer 722C is, for example, about 0.1 μm. The composition of the p-type AlInAs layer 722C is Al _0.47 In _0.53 As. Even if the composition of the p-type AlInAs layer 722C is Al _x In _1-x As (0.464≦x≦0.509), the lattice distortion between the p-type AlInAs layer 722C and InP can be suppressed to be particularly small. In the fifth embodiment, a pn junction exists between the AlInAs layer 722B and the p-type AlInAs layer 722C.

The first groove 71 is formed in part of the p-type contact layer 25, the p-type AlInAs layer 722C, and the AlInAs layer 722B, and the AlInAs layer 722B is exposed at the bottom of the first groove 71. That is, as in the fourth embodiment, the bottom surface of the first groove 71 is in the AlInAs layer 722B. The upper surface of the n-type region 24 is at least a portion of the bottom surface of the first groove 71.

The other configurations of the fifth embodiment are the same as those of the fourth embodiment.

The fifth embodiment also provides the same effects as the fourth embodiment.

In the third embodiment, a p-type AlInAs layer corresponding to the p-type AlInAs layer 722C may be provided between the second semiconductor layer 622 and the p-type contact layer 25.

(Sixth embodiment)
Next, a sixth embodiment will be described. The sixth embodiment differs from the fifth embodiment mainly in the configuration of the light-receiving layer. FIG. 19 is a sectional view showing a light receiving element according to the sixth embodiment.

The light receiving element 800 according to the sixth embodiment includes a light receiving layer 820 instead of the light receiving layer 720. The light-receiving layer 820 includes a first semiconductor layer 21 and a second semiconductor layer 822. The second semiconductor layer 822 includes, for example, an InGaAs layer 722A, an InP layer 822B, and a p-type InP layer 822C. InP layer 822B is provided on InGaAs layer 722A. The p-type InP layer 822C is provided on the InP layer 822B. The thickness of the InP layer 822B is, for example, about 1 μm. The p-type InP layer 822C contains, for example, Zn at a concentration of about 1×10 ¹⁸ cm ⁻³ . The thickness of the p-type InP layer 822C is, for example, about 0.1 μm.

The first groove 71 is formed in part of the p-type contact layer 25, the p-type InP layer 822C, and the InP layer 822B, and the InP layer 822B is exposed at the bottom of the first groove 71. That is, the bottom surface of the first groove 71 is in the InP layer 822B. The upper surface of the n-type region 24 is at least a portion of the bottom surface of the first groove 71. The n-type region 24 may be present only in the InP layer 822B, may be present in the InGaAs layer 722A and the InP layer 822B, or may be present in the first semiconductor layer 21 and the second semiconductor layer 822.

Although no impurity is intentionally implanted into the InP layer 822B, the InP layer 822B has weak n-type conductivity due to the unavoidable mixing of impurities. Therefore, a pn junction exists between the InP layer 822B and the p-type InP layer 822C.

The other configurations of the sixth embodiment are the same as those of the fifth embodiment.

In the light-receiving element 800 according to the sixth embodiment, the light-receiving layer 820 has an n-type region 24 with n-type conductivity in a portion exposed to the bottom surface of the first groove 71, and the upper surface of the n-type region 24 is at least a part of the bottom surface of the first groove 71. Therefore, even if the n-type impurities inevitably contained in the light-receiving layer 820 are reduced during the formation of the anti-reflection film 32, there is sufficient n-type impurity in the light-receiving layer 820, and crystal leakage can be suppressed. Therefore, the sixth embodiment can also reduce dark current.

Further, in the sixth embodiment, the second semiconductor layer 822 includes an InP layer 822B, and the band gap of InP is larger than the band gap of InGaAs. For example, when comparing compositions that are lattice matched to InP, the band gap of In _0.53 Ga _0.47 As is 0.73 eV, while the band gap of InP is 1.35 eV. Therefore, according to the sixth embodiment, surface leakage can be suppressed more than in the first embodiment.

Furthermore, although the bandgap of InP is smaller than that of AlInAs, P contained in InP is more difficult to oxidize than As contained in AlInAs. Therefore, surface leakage can be suppressed more than in the fifth embodiment.

The third embodiment, the fourth embodiment, the fifth embodiment, and the sixth embodiment can be used in a photodetection device like the second embodiment, like the first embodiment. That is, the photodetecting device 200 according to the second embodiment may include a light receiving element 600, 700, 701, or 800 instead of the light receiving element 100.

In the present disclosure, the second semiconductor layer is not limited to an InGaAs layer or an AlInAs layer, and may include an Al _x Ga _y In _1-x-y As layer (0≦x<1, 0≦y<1, 0<x+y<1).

Next, we will explain other tests conducted by the inventors.

(Third exam)
In the third test, the relationship between the dimensions of the mesa 70 and the dark current density was investigated. In the third test, a plurality of samples imitating the first embodiment, third embodiment, fifth embodiment, or sixth embodiment were prepared. Furthermore, four types of samples having different mesa 70 dimensions were prepared for each of the first embodiment, the third embodiment, the fifth embodiment, and the sixth embodiment. Specifically, the mesa 70 having a square planar shape with each side length of 20 μm, 40 μm, 80 μm, or 160 μm is used in each of the first, third, fifth, and sixth embodiments. It was created in The dark current Id was then measured for each sample. The results are shown in FIG. In the graph shown in FIG. 20, the horizontal axis is the dimensional parameter (P/A) obtained by dividing the perimeter P of the mesa 70 in plan view by the area A, and the vertical axis is the density of dark current Id (Id /A). FIG. 20 is a diagram showing the relationship between dimensional parameters and dark current density.

In the graph shown in FIG. 20, the slope reflects surface leakage. In the third embodiment and the fifth embodiment, the slopes of the graphs are the same, the slopes of the graphs in the third embodiment and the fifth embodiment are smaller than those in the first embodiment, and the slopes of the graphs in the sixth embodiment are smaller than those in the first embodiment. , the slope of the graph is smaller than that of the third embodiment and the fifth embodiment. This result shows that the surface leakage is the same in the third embodiment and the fifth embodiment, and the surface leakage is suppressed in the third embodiment and the fifth embodiment more than in the first embodiment. The sixth embodiment shows that surface leakage is more suppressed than the third and fifth embodiments.

(4th exam)
In the fourth test, samples imitating the first embodiment or the third embodiment were prepared, and the relationship between wavelength and quantum efficiency was investigated.

Here, a method for measuring quantum efficiency will be explained. FIG. 21 is a diagram showing a measurement system used for measuring quantum efficiency. As shown in FIG. 21, the measurement system includes a halogen lamp 90, an integrating sphere 91, a mirror 92, a chopper 93, a low-pass filter 94, a spectrometer 95, a dewar 96, a preamplifier 97, and a lock-in It has an amplifier 98 and a computer 99. The halogen lamp 90 emits light having a wavelength of 350 nm or more and 3500 nm or less. Integrating sphere 91 collects the light beam emitted from halogen lamp 90 and emits it toward mirror 92 . Mirror 92 reflects the light emitted from integrating sphere 91 toward spectroscope 95 . The chopper 93 is arranged between the mirror 92 and the spectrometer 95, and the low-pass filter 94 is arranged between the chopper 93 and the spectrometer 95. The sample 9 is attached to a dewar 96 and is cooled by the dewar 96. The spectrometer 95 separates the light that has passed through the chopper 93 and the low-pass filter 94 and irradiates it onto the sample 9 . Preamplifier 97 amplifies the output signal from sample 9. The lock-in amplifier 98, together with the chopper 93, measures the current with noise contained in the output signal from the preamplifier 97 reduced. The computer 99 analyzes the output signal (current value) from the lock-in amplifier 98 and calculates the quantum efficiency.

When measuring the quantum efficiency, the sample 9 was cooled to a temperature of -60° C. by a Dewar 96, and a voltage of -2V was applied to the sample 9. In addition, the amount of incident light was measured using a calibration sample, and the relationship between the wavelength and the amount of incident light was obtained. The computer 99 collected data on wavelengths and current values, and calculated the quantum efficiency for each wavelength. The results are shown in FIG. 22. FIG. 22 is a diagram showing the relationship between wavelength and quantum efficiency.

As shown in FIG. 22, in the third embodiment, the quantum efficiency is lower than that of the first embodiment in the wavelength band of 1.0 μm or more and 1.6 μm or less. This is because the AlInAs layer included in the second semiconductor layer 622 does not have sensitivity in the wavelength range of 1.0 μm or more and 1.6 μm or less. On the other hand, in the fourth, fifth, and sixth embodiments, it is considered that the same quantum efficiency as the first embodiment can be obtained.

Although the embodiments have been described in detail above, they are not limited to specific embodiments, and various modifications and changes can be made within the scope of the claims.

9: Sample 10: Substrate 10a: First main surface 10b: Second main surface 11: Pixel region 12: Electrode connection region 20, 620, 720, 820: Light receiving layer 21: First semiconductor layer 22, 622, 722, 822: Second semiconductor layer 24: N-type region 25: P-type contact layer 31: Passivation films 31a, 31b: Opening 32: Anti-reflection film 40: P-electrode 51: First n-electrode 52: Second n-electrode 53: Wiring 61, 62: In bump 70, 73: Mesa 71: First groove 72: Second groove 81: SiO ₂ film 82: resist pattern 83: opening 90: halogen lamp 91: integrating sphere 92: mirror 93: chopper 94: low pass filter 95: spectrometer 96: dewar 97: preamplifier 98: lock-in amplifier 99: computer 100, 600, 700, 701, 800: light receiving element 200: photodetector 240, 250: connection member 300: readout circuit board 320: wiring board 340: pixel electrode 350: common electrode 510: substrate 520: InGaAs layer 521: region 531: passivation film 540: electrode 722A: InGaAs layer 722B: AlInAs layer 722C: p-type AlInAs layer 822B: InP layer 822C: p-type InP layer L1: distance

Claims (13)

a substrate having a first main surface;
a light-receiving layer provided on the first main surface;
a contact layer provided on the light-receiving layer;
a groove that separates the contact layer for each pixel;
has
The light-receiving layer is
a first semiconductor layer provided on the first main surface;
a second semiconductor layer provided on the first semiconductor layer;
has
The first semiconductor layer has a type II quantum well layer including an InGaAs layer and a GaAsSb layer,
The second semiconductor layer has an Al _x Ga _y In _1-xy As layer (0≦x<1, 0≦y<1, 0<x+y<1),
a bottom surface of the trench is within the second semiconductor layer;
The light receiving layer is a light receiving element, wherein the light receiving layer has an n-type region in a portion exposed to the bottom surface. The light-receiving element according to claim 1, wherein the concentration of n-type carriers in the n-type region is 5×10 ¹⁷ cm ⁻³ or more. The light receiving element according to claim 1 or 2, wherein the thickness of the n-type region is 0.05 μm or more. The light receiving element according to claim 1 or 2, wherein the distance between the n-type region and the contact layer is 1.0 μm or more in a plan view perpendicular to the first main surface. The light receiving element according to claim 1 or 2, wherein the substrate is an n-type InP substrate. 3. The light receiving element according to claim 1, wherein the n-type region contains hydrogen as an n-type impurity. The substrate has a second main surface opposite to the first main surface,
The light receiving element according to claim 1 or 2, further comprising an antireflection film provided on the second main surface. 3. The light receiving element according to claim 1, wherein the second semiconductor layer includes an InGaAs layer. the second semiconductor layer has an AlInAs layer provided on the InGaAs layer,
9. The photodiode according to claim 8, wherein the bottom surface of the groove is located within the AlInAs layer. the second semiconductor layer has an InP layer provided on the InGaAs layer,
9. The photodiode according to claim 8, wherein the bottom surface of the groove is located within the InP layer. The light receiving element according to claim 1 or 2, wherein the second semiconductor layer includes an AlInAs layer. an n-type InP substrate having a first major surface and a second major surface opposite to the first major surface;
a light receiving layer provided on the first main surface;
a contact layer provided on the absorption layer;
A groove separating the contact layer for each pixel;
an anti-reflection film provided on the second main surface;
having
The light receiving layer is
a first semiconductor layer provided on the first major surface;
a second semiconductor layer provided on the first semiconductor layer;
having
the first semiconductor layer has a type II quantum well layer including an InGaAs layer and a GaAsSb layer;
the second semiconductor layer has an Al _x Ga _y In _1-x-y As layer (0≦x<1, 0≦y<1, 0<x+y<1);
a bottom surface of the groove is in the second semiconductor layer;
the absorption layer has an n-type region that contains hydrogen and has an n-type carrier concentration of 5×10 ¹⁷ cm ⁻³ or more in a portion exposed to the bottom surface,
The thickness of the n-type region is 0.1 μm or more,
a distance between the n-type region and the contact layer is 1.0 μm or more in a plan view perpendicular to the first main surface. A light receiving element according to claim 1, claim 2 or claim 12;
A circuit board connected to the light receiving element;
A light detection device comprising:

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