JP2024020852A - Semiconductor optical device array - Google Patents

Abstract

The present invention provides a semiconductor optical device array having good optical characteristics. The present invention includes a semiconductor substrate 1, a mask layer 2 disposed on a main surface of the semiconductor substrate and having an opening, and a group III nitride layer extending from the semiconductor substrate in the thickness direction through the opening. A semiconductor optical device array 10 having a nanocolumn 3 which is a columnar crystal of a semiconductor, a light emitting layer 4 disposed at the tip of the nanocolumn, and a covering semiconductor layer 5 covering the light emitting layer and containing a semiconductor, The semiconductor optical device array has a pixel including a plurality of the nanocolumns, and in the pixel, the size of the nanocolumns increases stepwise or continuously from the center toward the outer periphery, or the size of the nanocolumns increases stepwise or continuously. decreases to [Selection diagram] Figure 3

Description

The present disclosure relates to semiconductor optical device arrays.

In recent years, group III nitride semiconductors such as gallium nitride (GaN) have attracted attention as semiconductor materials useful for light-emitting devices such as light-emitting diodes and laser diodes. Light emitting devices are made by depositing group III nitride semiconductors on a substrate using crystal growth techniques such as metal organic chemical vapor deposition (MOCVD) and molecular beam epitaxy (MBE). It is manufactured by forming a layered structure.

For example, Patent Document 1 discloses a semiconductor optical device array that includes fine columnar crystals containing a Group III nitride semiconductor grown from a semiconductor substrate through openings arranged in a mask pattern. One purpose of this technique is to control the position and shape of fine columnar crystals formed on a substrate with high precision.

International Publication No. 2010/023921

A semiconductor optical device array is used, for example, as a light emitting device. From the viewpoint of improving the performance of light emitting devices, it is desired to improve the optical characteristics of semiconductor optical device arrays. The present disclosure has been made in view of the above circumstances, and its main purpose is to provide a semiconductor optical device array having good optical characteristics.

In the present disclosure, a semiconductor substrate, a mask layer disposed on a main surface of the semiconductor substrate and having an opening, a group III nitride semiconductor extending from the semiconductor substrate in the thickness direction through the opening, A semiconductor optical device array comprising: a nanocolumn that is a columnar crystal; a light emitting layer disposed at the tip of the nanocolumn; and a covering semiconductor layer covering the light emitting layer and containing a semiconductor, the semiconductor optical device array comprising: has a pixel including a plurality of the nanocolumns, and in the pixel, the size of the nanocolumns increases stepwise or continuously, or decreases stepwise or continuously from the center to the outer periphery. An optical device array is provided.

The semiconductor optical device array according to the present disclosure has the advantage of having good optical characteristics.

1 is a schematic cross-sectional view illustrating a semiconductor optical device array according to the present disclosure. FIG. 2 is a schematic plan view illustrating a mask layer and nanocolumns in the present disclosure. FIG. 2 is a schematic plan view illustrating a pixel in the present disclosure. FIG. 2 is a schematic plan view illustrating a pixel in the present disclosure. FIG. 2 is an explanatory diagram illustrating a pixel in the present disclosure. FIG. 2 is an explanatory diagram illustrating a pixel in the present disclosure. FIG. 2 is a schematic cross-sectional view illustrating a nanocolumn in the present disclosure. FIG. 2 is a schematic plan view illustrating a pixel in the present disclosure. FIG. 1 is a schematic perspective view illustrating a semiconductor optical device array according to the present disclosure. FIG. 1 is a schematic perspective view illustrating a method for manufacturing a semiconductor optical device array according to the present disclosure. 3 is an explanatory diagram illustrating pixels used in Comparative Example 1 and Examples 1 and 2. FIG. 3 shows emission spectra of pixels obtained in Comparative Example 1 and Examples 1 and 2. FIG. 4 is an explanatory diagram illustrating pixels used in Comparative Example 2 and Examples 3 and 4. It is the emission spectrum of the pixel obtained in Comparative Example 2 and Examples 3 and 4.

Hereinafter, the semiconductor optical device array according to the present disclosure will be described in detail. In each figure shown below, the size and shape of each part are appropriately exaggerated for easy understanding. Furthermore, in each figure, hatching or symbols may be omitted for convenience. In addition, in the present disclosure, "another member is arranged on the surface (principal surface) of one member" refers to a case where another member is arranged so as to be in contact with the surface (principal surface) of one member. , and cases in which another member is placed above the surface (principal surface) of one member via another member.

FIG. 1 is a schematic cross-sectional view illustrating a semiconductor optical device array according to the present disclosure. A semiconductor optical device array 10 shown in FIG. 1 includes a semiconductor substrate 1, a mask layer 2, a nanocolumn 3, a light emitting layer 4, and a covering semiconductor layer 5. Semiconductor substrate 1 has base substrate 1a and semiconductor layer 1b. The mask layer 2 is arranged on the main surface m of the semiconductor substrate 1 (semiconductor layer 1b) and has an opening 2x. The nanocolumn 3 extends in the thickness direction _DT from the semiconductor substrate 1 (semiconductor layer 1b) through the opening 2x of the mask layer 2, and is a columnar crystal of a group III nitride semiconductor. The light emitting layer 4 is arranged at the tip of the nanocolumn 3. The covering semiconductor layer 5 covers at least a portion of the light emitting layer 4 and includes a semiconductor.

FIG. 2 is a schematic plan view illustrating a mask layer and nanocolumns in the present disclosure. As shown in FIG. 2(a), the mask layer 2 has patterned openings 2x. A group III nitride semiconductor crystal is epitaxially grown through the opening 2x. As a result, nanocolumns 3 as shown in FIGS. 1 and 2(b) are obtained.

A semiconductor optical device array in the present disclosure has a pixel including a plurality of nanocolumns. Specifically, one pixel is configured by arranging a plurality of nanocolumns in a pattern. Each nanocolumn is usually provided with the above-mentioned light-emitting layer and covering semiconductor layer. 3 and 4 are schematic plan views illustrating pixels in the present disclosure, respectively. As shown in FIGS. 3 and 4, the pixel P includes a plurality of nanocolumns 3. In the pixel P shown in FIG. 3, the size of the nanocolumn 3 increases continuously from the center C toward the outer periphery X. On the other hand, in the pixel P shown in FIG. 4, the size of the nanocolumn 3 decreases continuously from the center C toward the outer periphery X.

According to the present disclosure, in a pixel including a plurality of nanocolumns, the size of the nanocolumns increases in a stepwise or continuous manner or decreases in a stepwise or continuous manner from the center toward the outer periphery, thereby achieving good optical performance. This results in a semiconductor optical device array having characteristics. Here, as described in Patent Document 1, the light emission characteristics of light emitted from the light emitting layer change depending on the size of the nanocolumn. Specifically, the peak wavelength of light emitted from the light-emitting layer shifts toward longer wavelengths as the nanocolumn size increases, and shifts toward shorter wavelengths as the nanocolumn size decreases.

Therefore, it is assumed that a pixel including a plurality of nanocolumns with non-uniform sizes is inferior in monochromaticity than a pixel including a plurality of nanocolumns with a uniform size. However, when the size of the nanocolumn was changed from the center of the pixel toward the outer periphery of the pixel, no decrease in monochromaticity was observed at least near the center of the pixel. Even more surprisingly, when the size of the nanocolumns was changed from the center of the pixel toward the outer periphery of the pixel, an improvement in the emission intensity was confirmed at least near the center of the pixel. The reason for this is not completely clear, but it is because the nanocolumns placed near the outer periphery of the pixel function like lenses or reflectors, improving light extraction efficiency near the center of the pixel. It is assumed that there is.

1. Pixel A pixel in this disclosure includes multiple nanocolumns. Details of the nanocolumn will be explained in "2. Nanocolumn" below. Further, in the present disclosure, the size of the nanocolumn increases stepwise or continuously, or decreases stepwise or continuously from the center of the pixel toward the outer periphery of the pixel.

In the present disclosure, the center of a pixel refers to the center of gravity of a planar view of the pixel along the thickness direction. On the other hand, the outer periphery of a pixel refers to the outer periphery of the pixel in a planar view along the thickness direction. Moreover, "the size of a nanocolumn" refers to the size of a columnar part of a nanocolumn (a columnar part 3a illustrated in FIG. 7, which will be described later). The size of the columnar section is defined as the distance between the intersection points of straight lines that pass through the center of gravity (center) of the columnar section in plan view along the thickness direction and intersect the columnar section at two points. The length of the longest straight line.

The size of the nanocolumn at the center of the pixel is, for example, 10 nm or more and 1000 nm or less. "Nanocolumn at the center of the pixel" means the nanocolumn if there is a nanocolumn at the center of the pixel when the pixel is viewed in plan along the thickness direction, and if there is no nanocolumn at the center of the pixel, it means , refers to the nanocolumn closest to the center of the pixel. The size of the nanocolumn may be, for example, 700 nm or less, 650 nm or less, or 600 nm or less. By setting the size of the nanocolumn to 700 nm or less, it becomes easier to suppress the occurrence of threading dislocations.

In the present disclosure, the size of the nanocolumn may increase stepwise or continuously from the center of the pixel toward the outer periphery of the pixel. This case will be explained using FIG. 5. In the pixel P shown in FIG. 5A, the size of the nanocolumn 3 increases continuously from the center C toward the outer periphery X. Furthermore, in the pixel P shown in FIG. 5A, the size of the nanocolumn 3 changes concentrically from the center C toward the outer periphery X. As shown in FIG. 5(b), the size of the nanocolumn may increase linearly from the center C toward the outer circumference X. On the other hand, although not particularly illustrated, the size of the nanocolumn may increase in a curved manner (eg, n-th order function) from the center C toward the outer periphery X.

FIG. 5(c) shows the nanocolumn 3 near the center of the pixel, and FIG. 5(d) shows the nanocolumn 3 near the outer periphery of the pixel. Let the size of the nanocolumn at the center of the pixel be _S1 , and the size of the nanocolumn at the outer periphery of the pixel be _S2 . The "nanocolumn at the center of the pixel" is as described above. On the other hand, "nanocolumns on the outer periphery of a pixel" refers to nanocolumns forming the outer periphery of a pixel when the pixel is viewed from above in the thickness direction.

_S1 is, for example, 10 nm or more, may be 20 nm or more, or may be 30 nm or more. On the other hand, S ₁ is, for example, 300 nm or less, may be 200 nm or less, or may be 100 nm or less. Further, S ₂ is not particularly limited as long as it is larger than S ₁ , but is, for example, 20 nm or more, may be 50 nm or more, or may be 100 nm or more. On the other hand, _S2 is, for example, 1000 nm or less, may be 500 nm or less, or may be 300 nm or less. Further, the ratio of S ₂ to S ₁ (S ₂ /S ₁ ) is, for example, 1.5 or more and 6.0 or less, and may be 2.0 or more and 4.0 or less.

Further, in the present disclosure, the size of the nanocolumn may increase stepwise from the center of the pixel toward the outer periphery of the pixel. In this case, the size of the nanocolumn may increase in two or more steps, five or more steps, or ten or more steps from the center of the pixel toward the outer periphery of the pixel.

On the other hand, in the present disclosure, the size of the nanocolumn may decrease stepwise or continuously from the center of the pixel toward the outer periphery of the pixel. This case will be explained using FIG. 6. In the pixel P shown in FIG. 6A, the size of the nanocolumn 3 decreases continuously from the center C toward the outer periphery X. Furthermore, in the pixel P shown in FIG. 6A, the size of the nanocolumn 3 changes concentrically from the center C toward the outer periphery X. As shown in FIG. 6(b), the size of the nanocolumn may decrease linearly from the center C toward the outer periphery X. On the other hand, although not particularly illustrated, the size of the nanocolumn may decrease in a curved manner (for example, as an n-th order function) from the center C toward the outer periphery X.

FIG. 6(c) shows the nanocolumn 3 near the center of the pixel, and FIG. 6(d) shows the nanocolumn 3 near the outer periphery of the pixel. Let the size of the nanocolumn at the center of the pixel be _S3 , and the size of the nanocolumn at the outer periphery of the pixel be _S4 . The "nanocolumn at the center of the pixel" and the "nanocolumn at the periphery of the pixel" are as described above.

_S3 is, for example, 100 nm or more, may be 150 nm or more, or may be 200 nm or more. On the other hand, _S3 is, for example, 1000 nm or less, may be 500 nm or less, or may be 400 nm or less. Further, S ₄ is not particularly limited as long as it is smaller than S ₃ , but is, for example, 10 nm or more, may be 100 nm or more, or may be 150 nm or more. On the other hand, _S4 is, for example, 300 nm or less, and may be 250 nm or less. Further, the ratio of S ₄ to S ₃ (S ₄ /S ₃ ) is, for example, 0.4 or more and 0.8 or less, and may be 0.45 or more and 0.6 or less.

Further, in the present disclosure, the size of the nanocolumn may decrease stepwise from the center of the pixel toward the outer periphery of the pixel. In this case, the size of the nanocolumn may decrease in two or more steps, five or more steps, or ten or more steps from the center of the pixel toward the outer periphery of the pixel.

In the direction from the center of the pixel to the outer periphery of the pixel, the difference in size between adjacent nanocolumns is, for example, 5 nm or less, may be 3 nm or less, or may be 1 nm or less. When the distance from the center of the pixel to the outer periphery of the pixel is L, the difference in size between adjacent nanocolumns may be within the above range in a region from the center of the pixel to 1/2L. Similarly, in the region from the center of the pixel to 3/4L, the difference in size between adjacent nanocolumns may be within the above range. Note that when the size of the nanocolumn changes continuously from the center of the pixel toward the outer periphery of the pixel, the difference in size between adjacent nanocolumns is usually larger than zero.

The arrangement of the nanocolumns is not particularly limited, but may be arranged, for example, in a triangular lattice shape or in a square lattice shape. In FIG. 2 described above, the openings 2x of the mask layer 2 are arranged in a triangular lattice shape, and the nanocolumns 3 growing from the openings 2x are also arranged in a triangular lattice shape. Further, as shown in FIG. 5(c), the distance between the centers of adjacent nanocolumns is called a pitch. The pitch is, for example, 200 nm or more, and may be 300 nm or more. On the other hand, the pitch is, for example, 600 nm or less, and may be 500 nm or less. Further, adjacent nanocolumns are usually arranged so as not to come into contact with each other. It is preferable that the gap between adjacent nanocolumns is, for example, 1 nm or more. The pitch of nanocolumns in a pixel may be the same or different. The same pitch means that the difference between the maximum and minimum pitches of nanocolumns in a pixel is 5 nm or less. On the other hand, the phrase "the pitches are different" means that the difference between the maximum value and the minimum value of the nanocolumn pitch in a pixel is greater than 5 nm.

The planar view shape of the pixel in the present disclosure is not particularly limited, but includes polygons such as a triangular shape, a quadrangular shape (for example, a square shape, a rectangular shape, and a rhombic shape), and a hexagonal shape. The size of the pixel is, for example, 10 μm or more, and may be 50 μm or more. On the other hand, the size of the pixel is, for example, 500 μm or less, and may be 100 μm or less. In the present disclosure, "pixel size" refers to a straight line that passes through the center of gravity (center) of a planar view of a pixel in the thickness direction and intersects the pixel at two points, between the intersection points. The length of the straight line with the longest distance.

2. Nanocolumn The nanocolumn in the present disclosure extends in the thickness direction from the semiconductor substrate through the opening of the mask layer, and is a columnar crystal of a group III nitride semiconductor. The nanocolumn may be composed of a single crystal of a Group III nitride semiconductor. It is preferable that there are few crystal defects in the nanocolumns.

Group III nitride semiconductors contain Group III elements and N elements. A typical example of a Group III nitride semiconductor is gallium nitride (GaN). Further, another example of a group III nitride semiconductor is represented by the general formula: Al _x Ga _y In _1-x-y N (0≦x≦1, 0≦y≦1, 0≦x+y≦1). Materials that can be used include: x may be greater than 0. x may be smaller than 1. y may be greater than 0. y may be smaller than 1. x+y may be greater than 0 and less than 1. The group III nitride semiconductor represented by the above general formula preferably has a band gap of 0.63 eV or more and 6.2 eV or less at room temperature. Further, another example of the Group III nitride semiconductor is boron nitride. Furthermore, from the viewpoint of manufacturing stability, the Group III nitride semiconductor is preferably a material having a hexagonal crystal structure.

The nanocolumn may have a columnar part and a facet structure located on the tip side of the columnar part (on the opposite side to the semiconductor substrate). The facet structure refers to a polyhedral structure whose side surfaces are facet surfaces located obliquely with respect to a direction perpendicular to the thickness direction. The shape of the columnar portion is not particularly limited, and examples thereof include a cylindrical shape, a quadrangular prism shape, and a hexagonal prism shape.

For example, when a nanocolumn is formed by growing a Group III nitride semiconductor with a wurtzite crystal structure in the direction of the c-plane (=(0001) plane, polar plane), the planar shape of the nanocolumn is as shown in Figure 2(b). ), it has a hexagonal shape. FIGS. 7A and 7B are schematic cross-sectional views showing the cross section of the nanocolumn taken along the central axis. Each of the nanocolumns 3 shown in FIGS. 7(a) and 7(b) has a columnar portion 3a and a facet structure portion 3b located on the tip side of the columnar portion 3a (on the opposite side to the semiconductor substrate). .

The facet structure 3b shown in FIG. 7A has a facet surface 31 (a semipolar surface of a wurtzite crystal structure), and the shape is a hexagonal pyramid. Examples of semipolar planes include (10-1-1) plane, (10-1-3) plane, (11-22) plane, (11-24) plane, and (10-12) plane. On the other hand, the facet structure portion 3b shown in FIG. 7(b) has a facet surface 31 (semipolar surface of wurtzite crystal structure), and further has a flat surface 32 (wurtzite crystal structure) parallel to the direction perpendicular to the thickness direction. It has a polar surface (ore type crystal structure). Depending on the crystal growth conditions, for example, a facet structure shown in FIG. 7(a) or FIG. 7(b) is formed.

When the size of the nanocolumn is small, a facet structure having a hexagonal pyramid shape as shown in FIG. 7(a) is likely to be formed, and when the size of the nanocolumn is large, a facet structure as shown in FIG. 7(b) is likely to be formed. . Although it depends on the crystal growth conditions, when the size of the nanocolumn is about 300 nm or more, a flat surface (polar surface) as shown in FIG. 7(b) tends to appear. Further, as the size of the nanocolumn increases beyond about 300 nm, the area of the flat surface (polar surface) tends to increase.

Although the height of the nanocolumn is not particularly limited, it is, for example, 200 nm or more, and may be 500 nm or more. On the other hand, the height of the nanocolumn is, for example, 5 μm or less. The height of the nanocolumn refers to the distance (distance in the thickness direction) from the surface of the mask layer 2 opposite to the semiconductor substrate to the tip of the nanocolumn.

3. Light Emitting Layer The light emitting layer in the present disclosure is placed at the tip of the nanocolumn. That is, the light-emitting layer is arranged on the surface opposite to the semiconductor substrate. The light emitting layer is preferably provided so as to cover the facet structure of the nanocolumn.

The light emitting layer preferably has a multiple quantum well (MQW) structure or a single quantum well (SQW) structure. A quantum well structure is a structure including a quantum well layer and barrier layers sandwiching the quantum well layer. The bandgap of the barrier layer is typically larger than that of the quantum well layer. Examples of the light emitting layer include InGaN, GaN, AlGaN, AlInGaN, InGaAsN, and InN. More specifically, the light emitting layer is, for example, InGaN/GaN (barrier layer: InGaN, well layer: GaN), In _x Ga _1-x N/In _y Ga _1-y N (0≦x≦1, 0≦ y≦1), GaN/AlGaN (barrier layer: AlGaN, well layer: GaN), and Al _x Ga _1-x N/Al _y Ga _1-y N (0≦x≦1, 0≦y≦1) can be mentioned.

The peak wavelength of light emitted from the emissive layer depends on the size of the nanocolumns just before the emissive layer is formed. Specifically, the peak wavelength of light emitted from the light-emitting layer shifts toward longer wavelengths as the nanocolumn size increases, and shifts toward shorter wavelengths as the nanocolumn size decreases. That is, the peak wavelength of light emitted from the light emitting layer can be controlled based on the size of the nanocolumns. The size of the nanocolumns can be controlled based on the size of the openings in the mask layer.

The peak wavelength of light emitted from the light emitting layer depends on the surface area of the facet structure of the nanocolumns. Specifically, the peak wavelength of light emitted from the light emitting layer shifts toward longer wavelengths as the surface area of the facet structure increases, and shifts toward shorter wavelengths as the surface area of the facet structure decreases. That is, the peak wavelength of light emitted from the light emitting layer can be controlled based on the surface area of the facet structure of the nanocolumn.

4. Covering Semiconductor Layer The covering semiconductor layer in the present disclosure is a layer that covers the light emitting layer and contains a semiconductor. The covering semiconductor layer preferably contains semiconductor crystals, and more preferably contains group III nitride semiconductor crystals. The covering semiconductor layer may be made of a single crystal group III nitride semiconductor. It is preferable that the covering semiconductor layer has few crystal defects. Regarding the Group III nitride semiconductor, the content is the same as that described in "2. Nano Column" above, so the description here will be omitted.

The covering semiconductor layer 5 only needs to cover at least a portion of the light emitting layer 4 . Above all, it is preferable that the covering semiconductor layer 5 covers the light emitting layer 4 so as to cover the entire circumference of the light emitting layer 4 in a plan view along the thickness direction. This is because better optical characteristics can be obtained. Further, as shown in FIG. 1, the covering semiconductor layer 5 may completely cover the light emitting layer 4. That is, the covering semiconductor layer 5 may cover the light emitting layer 4 so that the light emitting layer 4 has no exposed portion to the external space. By suppressing the formation of non-radiative recombination levels due to exposed parts, high internal quantum efficiency is achieved.

Further, the conductivity type of the nanocolumn and the conductivity type of the covering semiconductor layer are usually in an opposite relationship. When the conductivity type of the nanocolumn is n-type, the conductivity type of the covering semiconductor layer is usually p-type. In this case, the light emitting layer emits light due to the combination of electrons supplied from the nanocolumns and holes supplied from the covering semiconductor layer. On the other hand, when the conductivity type of the nanocolumn is p-type, the conductivity type of the covering semiconductor layer is usually n-type.

5. Semiconductor Substrate A semiconductor substrate in the present disclosure supports nanocolumns. Further, the semiconductor substrate includes, for example, a base substrate and a semiconductor layer. Examples of the base substrate include a sapphire substrate, a silicon substrate, and a SiC substrate.

The semiconductor layer preferably contains a group III nitride semiconductor as the semiconductor. The semiconductor layer may be made of a single crystal group III nitride semiconductor. It is preferable that the semiconductor layer has few crystal defects. Regarding Group III nitride semiconductors, the contents are the same as those described in "2. Nano Column" above. The Group III nitride semiconductor in the semiconductor layer and the Group III nitride semiconductor in the nanocolumn may have the same composition.

As shown in FIG. 1, the semiconductor layer 1b may have a recess 1x at a position that at least overlaps with the opening 2x of the mask layer 2 in a plan view along the thickness direction _DT . The depth of the recess 1x is not particularly limited, but is, for example, 1 nm or more and 250 nm or less.

A buffer layer may be arranged between the base substrate and the semiconductor layer. By providing the buffer layer, the crystal quality (for example, the flatness of the layer surface) of the semiconductor layer is improved. Examples of the buffer layer include Group III nitride semiconductors such as gallium nitride and aluminum nitride. Further, the semiconductor substrate does not need to have a base substrate. That is, the semiconductor substrate may be a self-supporting semiconductor layer (for example, a GaN substrate).

6. Mask Layer The mask layer in the present disclosure has an opening. Examples of the shape of the opening in plan view include a square shape, a circular shape, and a polygonal shape. The shape of the opening in plan view is preferably axially symmetrical. By adjusting the opening pattern, the density of the nanocolumns can be controlled. Similarly, by adjusting the size of the openings, the size of the nanocolumns can be controlled. The pattern and size of the openings are adjusted to obtain the nanocolumns described above.

The mask layer is preferably a metal mask layer containing metal. Examples of the metal elements contained in the metal mask layer include titanium (Ti), tantalum (Ta), iron (Fe), nickel (Ni), platinum (Pt), gold (Au), cobalt (Co), and tungsten ( W) and molybdenum (Mo). The metal mask layer may contain only one type of metal element, or may contain two or more types of metal elements. Preferably, the metal mask layer contains at least Ti. The metal mask layer may be a layer having an oxide on its surface, or may be a metal oxide layer. The thickness of the mask layer is not particularly limited, but is, for example, 2 nm or more and 100 nm or less.

7. Semiconductor Optical Device Array In the semiconductor optical device array according to the present disclosure, all of the pixels may be light-emitting regions, or some of the pixels may be light-emitting regions. For example, a part of the pixel P shown in FIG. 8 is the light emitting region α. It is preferable that the light emitting region α includes the center C of the pixel P. Further, the shape of the light emitting region in plan view includes, for example, a square shape, a circular shape, and a polygonal shape. The shape of the light emitting region in plan view may be axially symmetrical. Further, the shape of the light emitting region in plan view may or may not be similar to that of the pixels.

The size of the light emitting region is, for example, 5 μm or more, and may be 50 μm or more. On the other hand, the size of the light emitting region is, for example, 300 μm or less, and may be 100 μm or less. In the present disclosure, the "size of the light-emitting region" refers to a straight line that passes through the center of gravity (center) of a planar view of the light-emitting region in the thickness direction and intersects the light-emitting region at two points. , is the length of the straight line with the longest distance between intersection points.

When part of a pixel is a light emitting region, the area ratio of the light emitting region to the pixel is, for example, 5% or more, and may be 10% or more. On the other hand, the area ratio is, for example, 80% or less, and may be 60% or less. Further, as a method for forming the light emitting region, for example, a method of adjusting the shape of an electrode electrically connected to the covering semiconductor layer can be mentioned.

The emission spectrum in the emission region may have a peak wavelength at a position of, for example, 430 nm or more and less than 500 nm. In this case, blue light emission is obtained. Note that the peak wavelength refers to the wavelength at which the highest emission intensity is obtained in the emission spectrum. Further, the emission spectrum in the emission region may have a peak wavelength at a position of, for example, 500 nm or more and less than 580 nm. In this case, green light emission is obtained. Further, the emission spectrum in the emission region may have a peak wavelength at a position of, for example, 580 nm or more and less than 780 nm. In this case, red light emission is obtained.

In the emission spectrum in the emission region, the number of peaks observed in the visible light region of 380 nm or more and 780 nm or less is preferably 2 or less, and more preferably 1. In addition, when the number of peaks observed in the visible light region from 380 nm to 780 nm is 2 or more, the highest emission intensity is preferably at least twice the second highest emission intensity, and preferably 4 times or more. It is more preferable that there be.

Further, a light emitting region in which the size of all nanocolumns in the light emitting region is changed to the size of the nanocolumn at the center of the pixel is defined as a light emitting region for comparison. In this case, the emission intensity at the peak wavelength in the light-emitting region is preferably higher than the emission intensity at the peak wavelength in the comparative light-emitting region.

The semiconductor optical device array in the present disclosure preferably has a plurality of pixels. For example, as shown in FIG. 9, the semiconductor optical device array preferably has a plurality of pixels (P ₁ , P ₂ , P ₃ ). The emission properties of the nanocolumns in this disclosure vary depending on their size. Therefore, for example, by adjusting the size of the nanocolumn, pixels P ₁ , P ₂ , and P ₃ can be made to emit light with the wavelengths of the three primary colors of R (red), G (green), and B (blue), respectively. It can be a pixel.

The use of the semiconductor optical device array in the present disclosure is not particularly limited. Applications of semiconductor optical device arrays include, for example, light emitting devices such as light emitting diodes and laser diodes.

The method of manufacturing a semiconductor optical device array in the present disclosure is not particularly limited. FIG. 10 is a schematic perspective view illustrating a method for manufacturing a semiconductor optical device array according to the present disclosure. In the method for manufacturing a semiconductor optical device array shown in FIG. 10, first, a base substrate 1a is prepared (FIG. 10(a)). Next, a buffer layer (not shown) containing a group III nitride semiconductor is formed on the base substrate 1a at a low temperature by MOCVD or MBE, and a group III nitride semiconductor is formed on the buffer layer at a high temperature. A semiconductor layer 1b is formed by growing a crystal of (FIG. 10(b)). Thereby, a semiconductor substrate 1 having a base substrate 1a and a semiconductor layer 1b is obtained.

Thereafter, a mask layer 2 containing titanium (Ti) is formed on the main surface of the semiconductor layer 1b by vacuum evaporation (FIG. 10(c)). Next, a resist layer 6 is formed on the mask layer 2, and electron beam drawing and development are performed to form an opening 6x (FIG. 10(d)). At this time, the drawing pattern of the opening 6x is set so as to obtain the above-mentioned pixels. Next, the mask layer 2 exposed from the opening 6x is removed by etching to form an opening 2x (FIG. 10(e)). At this time, when not only the mask layer 2 but also the semiconductor layer 1b is etched, a recess 1x as shown in FIG. 1 is formed.

Thereafter, a group III nitride semiconductor crystal is grown from the semiconductor layer 1b through the opening 2x by MOCVD or MBE. As a result, nanocolumns 3 are formed (FIG. 10(f)). At this time, the light emitting layer 4 and the covering semiconductor layer 5 may be formed continuously. For example, when forming nanocolumns using the MBE method, a raw material gas containing active nitrogen generated by high-frequency plasma excitation and a group III metal is introduced onto the semiconductor layer to grow crystals of group III nitride semiconductors. let The crystal growth temperature is, for example, 350°C or higher and 1200°C or lower. For example, when growing a GaN crystal, the crystal growth temperature is preferably 400°C or more and 1000°C or less. Further, when a group III nitride semiconductor crystal grows, it may grow not only in the thickness direction but also in a direction perpendicular to the thickness direction (in-plane direction). In that case, as shown in FIG. 1, the size of the nanocolumn 3 is usually larger than the size of the opening 2x and the size of the recess 1x. In this way, a semiconductor optical device array 10 is obtained as shown in FIG. 10(f). Thereafter, as shown in FIG. 10(g), electrodes 11 may be placed on the covering semiconductor layer 5 and the mask layer 2, respectively.

The present disclosure is not limited to the above embodiments. The above-mentioned embodiments are illustrative, and any configuration that has substantially the same technical idea as the claims of the present disclosure and provides similar effects is the present invention. within the technical scope of the disclosure.

[Comparative example 1]
GaN was grown on the (0001) plane of a sapphire substrate (underlying substrate) by MOCVD to form a GaN layer (semiconductor layer, thickness: approximately 3.5 μm). Next, a titanium thin film (mask layer, thickness: about 5 nm) was formed on the GaN layer by vacuum evaporation. Next, a resist layer was formed on the titanium thin film, electron beam lithography was performed, and development was performed to form a resist pattern having openings. Next, the mask layer exposed through the openings of the resist pattern was removed by etching to form patterned openings in the mask layer. Next, the resist pattern was peeled off.

Thereafter, by RF MBE, GaN columnar crystals were grown from the semiconductor substrate through the openings of the mask layer under a temperature condition of 900° C. to form nanocolumns (height: 2.5 μm). As a result, a pixel shown in FIG. 11(a) and shown below was obtained.
・Plane view shape of pixel: hexagonal shape ・Pixel size: 150μm
・Pitch between centers of adjacent nanocolumns: 350nm
・Size of nanocolumn at the center of pixel: 60nm
・Size of nanocolumn at outer periphery of pixel: 60nm

Subsequently, a light emitting layer having a multiple quantum well structure including an InGaN film (thickness: 1 nm) was formed at the tip of the nanocolumn. Subsequently, GaN crystal was grown on the light emitting layer to form a covering semiconductor layer (thickness: 10 nm). As a result, a semiconductor optical device array was obtained.

In addition, at the stage where nanocolumns were formed by performing the same operations as above, the nanocolumns were observed using a scanning electron microscope (SEM). The results are shown in FIG. 11(b) and FIG. 11(c). As shown in FIGS. 11(b) and 11(c), the size of the nanocolumn at the center of the pixel and the size of the nanocolumn at the outer periphery of the pixel were the same.

[Example 1]
A semiconductor optical device array was obtained in the same manner as in Comparative Example 1, except for forming the pixels shown in FIG. 11(d) and below.
・Pixel shape in plan view: Hexagonal ・Pixel size (maximum length between opposing corners): 150 μm
・Pitch between centers of adjacent nanocolumns: 350nm
・Size of nanocolumn at the center of pixel: 60nm
・Size of nanocolumn at outer periphery of pixel: 100nm

The results of SEM observation of the nanocolumn are shown in FIGS. 11(e) and 11(f). As shown in FIGS. 11(e) and 11(f), in the pixel, the size of the nanocolumn continuously increased from the center toward the outer periphery.

[Example 2]
A semiconductor optical device array was obtained in the same manner as in Comparative Example 1 except that the pixels shown in FIG. 11(g) and shown below were formed.
・Pixel shape in plan view: Hexagonal ・Pixel size (maximum length between opposing corners): 150 μm
・Pitch between centers of adjacent nanocolumns: 350nm
・Size of nanocolumn at the center of pixel: 60nm
・Size of nanocolumn at outer periphery of pixel: 350nm

The results of SEM observation of the nanocolumn are shown in FIG. 11(h) and FIG. 11(i). As shown in FIG. 11(h) and FIG. 11(i), in the pixel, the size of the nanocolumn continuously increased from the center toward the outer periphery.

[evaluation]
The same operations as in Comparative Example 1 and Examples 1 and 2 were performed to form a light-emitting layer, and then the light-emitting layer was irradiated with a laser and the luminescence intensity was measured. The measurement area was a 30 μm diameter area including the center of the pixel, as shown by the black circles in FIGS. 11(a), (d), and (g). The results are shown in FIG. As shown in FIG. 12, in Examples 1 and 2, higher luminescence intensity was obtained than in Comparative Example 1. More specifically, it was confirmed that by increasing the size of the nanocolumns around the measurement area, high emission intensity could be obtained without increasing the size of the nanocolumns in the measurement area.

Further, in Example 1, the size of the nanocolumn at the center of the measurement area was 50 nm, and the size of the nanocolumn at the outer periphery of the measurement area was 60 nm. When comparing the area of nanocolumns occupying the measurement region, Example 1 was 1.21 times larger than Comparative Example 1. In Example 2, the size of the nanocolumn at the center of the measurement area was 50 nm, and the size of the nanocolumn at the outer periphery of the measurement area was 100 nm. Comparing the area of nanocolumns occupying the measurement region, Example 2 was 2.25 times larger than Comparative Example 1. These rates of increase are smaller than the amount of increase in the emission intensity shown in FIG. 12, so it was confirmed that in Examples 1 and 2, the emission intensity was improved due to factors other than the increase in area.

Further, when the half width of the peak shown in FIG. 12 was measured, it was 82 nm in Comparative Example 1, 47.6 nm in Example 1, and 55.4 nm in Example 2. In Examples 1 and 2, since the size of the nanocolumn was changed even within the measurement region, an increase in the half-width (decreased monochromaticity) was expected; however, surprisingly, the half-width decreased (the monochromaticity It was confirmed that

[Comparative example 2]
A semiconductor optical device array was obtained in the same manner as in Comparative Example 1 except that the pixels shown in FIG. 13(a) and below were formed.
・Pixel shape in plan view: Hexagonal ・Pixel size (maximum length between opposing corners): 150 μm
・Pitch between centers of adjacent nanocolumns: 450nm
・Size of nanocolumn at the center of pixel: 200nm
・Size of nanocolumn at outer periphery of pixel: 200nm

The results of SEM observation of the nanocolumn are shown in FIGS. 13(b) and 13(c). As shown in FIG. 13(b) and FIG. 13(c), the size of the nanocolumn at the center of the pixel and the size of the nanocolumn at the outer periphery of the pixel were the same.

[Example 3]
A semiconductor optical device array was obtained in the same manner as Comparative Example 1 except that the pixels shown in FIG. 13(d) and below were formed.
・Pixel shape in plan view: Hexagonal ・Pixel size (maximum length between opposing corners): 150 μm
・Pitch between centers of adjacent nanocolumns: 450nm
・Size of nanocolumn at the center of pixel: 200nm
・Size of nanocolumn at outer periphery of pixel: 150nm

The results of SEM observation of the nanocolumn are shown in FIGS. 13(e) and 13(f). As shown in FIGS. 13(e) and 13(f), in the pixel, the size of the nanocolumn decreased continuously from the center toward the outer periphery.

[Example 4]
A semiconductor optical device array was obtained in the same manner as Comparative Example 1 except that the pixels shown in FIG. 13(g) and below were formed.
・Pixel shape in plan view: Hexagonal ・Pixel size (maximum length between opposing corners): 150 μm
・Pitch between centers of adjacent nanocolumns: 450nm
・Size of nanocolumn at the center of pixel: 200nm
・Size of nanocolumn at outer periphery of pixel: 100nm

The results of SEM observation of the nanocolumn are shown in FIG. 13(h) and FIG. 13(i). As shown in FIG. 13(h) and FIG. 13(i), in the pixel, the size of the nanocolumn decreased continuously from the center toward the outer periphery.

[evaluation]
The same operations as in Comparative Example 2 and Examples 3 and 4 were performed to form a light-emitting layer, and then the light-emitting layer was irradiated with a laser, and the luminescence intensity was measured in the same manner as above. The results are shown in FIG. As shown in FIG. 14, in Examples 3 and 4, higher luminescence intensity was obtained than in Comparative Example 2. Further, when the half width of the peak shown in FIG. 14 was measured, it was 61.2 nm in Comparative Example 2, 57.5 nm in Example 3, and 53.9 nm in Example 4.

As described above, the present disclosure provides, for example, the following inventions.

[1]
a semiconductor substrate;
a mask layer disposed on the main surface of the semiconductor substrate and having an opening;
a nanocolumn extending in the thickness direction from the semiconductor substrate through the opening and being a columnar crystal of a group III nitride semiconductor;
a light-emitting layer placed at the tip of the nanocolumn;
A covering semiconductor layer that covers the light emitting layer and includes a semiconductor;
A semiconductor optical device array having
The semiconductor optical device array has a pixel including a plurality of the nanocolumns,
In the pixel, the size of the nanocolumns increases stepwise or continuously, or decreases stepwise or continuously from the center to the outer periphery.

[2]
The semiconductor optical device array according to [1], wherein the nanocolumn at the center of the pixel has a size of 10 nm or more and 1000 nm or less.

[3]
The semiconductor optical device array according to [1] or [2], wherein in the pixel, the size of the nanocolumn increases stepwise or continuously from the center toward the outer periphery.

[4]
When the size of the nanocolumn at the center of the pixel is S ₁ [nm], and the size of the nanocolumn at the outer periphery of the pixel is S ₂ [nm], the ratio of S ₂ to S ₁ (S ₂ /S ₁ ) is 1.5 or more and 6.0 or less, the semiconductor optical device array according to [3].

[5]
The semiconductor optical device array according to [1] or [2], wherein in the pixel, the size of the nanocolumn decreases stepwise or continuously from the center toward the outer periphery.

[6]
When the size of the nanocolumn at the center of the pixel is S ₃ [nm], and the size of the nanocolumn at the outer periphery of the pixel is S ₄ [nm], the ratio of S ₄ to S ₃ (S ₄ /S ₃ ) is 0.4 or more and 0.8 or less, the semiconductor optical device array according to [5].

[7]
The semiconductor optical device array according to any one of [1] to [6], wherein a difference in size between adjacent nanocolumns in a direction from the center toward the outer periphery is 5 nm or less.

[8]
The semiconductor optical device array according to any one of [1] to [7], wherein the nanocolumn is a columnar crystal of GaN.

[9]
The semiconductor optical device array according to any one of [1] to [8], wherein the light emitting layer contains InGaN.

[10]
The semiconductor optical device array according to any one of [1] to [9], wherein a part of the pixel is a light emitting region, and the light emitting region includes the center.

DESCRIPTION OF SYMBOLS 1... Semiconductor substrate 1a... Base substrate 1b... Semiconductor layer 2... Mask layer 3... Nanocolumn 4... Light emitting layer 5... Covering semiconductor layer 10... Semiconductor optical device array

Claims (10)

a semiconductor substrate;
a mask layer disposed on the main surface of the semiconductor substrate and having an opening;
a nanocolumn extending in the thickness direction from the semiconductor substrate through the opening and being a columnar crystal of a group III nitride semiconductor;
a light-emitting layer disposed at the tip of the nanocolumn;
a covering semiconductor layer covering the light emitting layer and containing a semiconductor;
A semiconductor optical device array having
The semiconductor optical device array has a pixel including a plurality of the nanocolumns,
In the semiconductor optical device array, in the pixel, the size of the nanocolumns increases stepwise or continuously, or decreases stepwise or continuously from the center toward the outer periphery. The semiconductor optical device array according to claim 1, wherein the size of the nanocolumn at the center of the pixel is 10 nm or more and 1000 nm or less. 3. The semiconductor optical device array according to claim 1, wherein in the pixel, the size of the nanocolumn increases stepwise or continuously from the center toward the outer periphery. When the size of the nanocolumn at the center of the pixel is S ₁ [nm] and the size of the nanocolumn at the outer periphery of the pixel is S ₂ [nm], the ratio of S ₂ to S ₁ (S 4. The semiconductor optical device array according to claim 3, wherein ₂ / _S1 ) is 1.5 or more and 6.0 or less. 3. The semiconductor optical device array according to claim 1, wherein in the pixel, the size of the nanocolumn decreases stepwise or continuously from the center toward the outer periphery. When the size of the nanocolumn at the center of the pixel is S ₃ [nm] and the size of the nanocolumn at the outer periphery of the pixel is S ₄ [nm], the ratio of the S ₄ to the S ₃ (S 6. The semiconductor optical device array according to claim 5, wherein ₄ / _S3 ) is 0.4 or more and 0.8 or less. 3. The semiconductor optical device array according to claim 1, wherein a difference in size between adjacent nanocolumns in a direction from the center toward the outer periphery is 5 nm or less. 3. The semiconductor optical device array according to claim 1, wherein the nanocolumn is a columnar crystal of GaN. The semiconductor optical device array according to claim 1 or 2, wherein the light emitting layer contains InGaN. 3. The semiconductor optical device array according to claim 1, wherein a part of the pixel is a light emitting region, and the light emitting region includes the center.