JP2024015771A - semiconductor equipment - Google Patents

Abstract

The present invention provides a semiconductor device that achieves suppression of leakage current during operation in a high-temperature environment. A semiconductor device 10 includes a substrate 100, a semiconductor stacked structure 200, a source electrode 600S, a gate electrode 600G, a drain electrode 600D, and a gate insulating film 700, in which the semiconductor stacked structure includes a first semiconductor layer 300 made of a first nitride semiconductor; a second semiconductor layer 400 made of a second nitride semiconductor formed on the first semiconductor layer and having a larger band gap than the first nitride semiconductor; ,including. When a reverse bias of 100 V is applied between the gate electrode and the drain electrode, the gate leakage current value at an operating temperature of 400 K is 2×10 −5 A/mm or less. [Selection diagram] Figure 1

Description

The present invention relates to a semiconductor device.

Nitride semiconductors have characteristics such as high saturated electron velocity and wide bandgap. For this reason, various studies have been conducted on applying nitride semiconductors to high voltage and high output semiconductor devices by utilizing these characteristics.
In recent years, GaN-based high electron mobility transistors (HEMTs) (hereinafter sometimes referred to as "GaN-HEMTs") have been actively developed for high frequency device applications from tens of GHz to hundreds of GHz. . For example, an AlGaN/GaN-HEMT using Al _x Ga _1-x N (0<x<1) as an electron supply layer has Al _x Ga _1-x N (0<x<1) due to spontaneous polarization and piezo polarization. A two-dimensional electron gas (hereinafter sometimes referred to as "2DEG") is generated at the /GaN hetero interface, and a sheet carrier concentration of about 1×10 ¹³ cm ⁻² or more can be obtained without doping anything. Thereby, high frequency operation is realized (Patent Documents 1 and 2).

International Publication No. 2014/108946 Patent No. 5390768

An unintended current flowing between electrodes when a semiconductor device is off is called leakage current. In particular, the leakage current between the source electrode and the drain electrode is called a drain leakage current, and the leakage current between the source electrode and the gate electrode is called a gate leakage current. A large leakage current flowing through a semiconductor device is not only disadvantageous in terms of energy efficiency, but also poses a major problem in terms of safety. Therefore, suppressing leakage current is an important issue.

On the other hand, the need to use HEMT devices in high-temperature environments is increasing year by year. For example, in the space environment, high frequencies are required for communication, but the environmental temperature is extremely high. Taking the moon as an example, the surface temperature during the day reaches over 100 degrees Celsius. Therefore, there is an urgent need to develop HEMT devices that can withstand high-temperature operation.

Even if there is no problem with gate leakage current and drain leakage current when operating at room temperature, when the operating temperature is raised, both leakage currents increase. This is thought to be caused by a layer doped in the carrier compensation layer, such as a GaN:Fe layer or an AlN buffer layer, as a leak source in conventional HEMT devices, but the details are not yet clear.
As described above, a semiconductor device that achieves suppression of leakage current during operation in a high-temperature environment has not been obtained so far.

Therefore, an object of the present invention is to provide a semiconductor device that achieves suppression of leakage current during operation in a high-temperature environment.

The inventors of the present invention have conducted intensive studies to solve the above problems, and have discovered that the above problems can be solved with a semiconductor device whose gate leakage current value or drain leakage current value during high-temperature operation is below a certain value, and have completed the present invention. I ended up doing it.

That is, the gist of the present invention is as follows.
[1] A semiconductor device comprising a substrate, a semiconductor stacked structure, a source electrode, a gate electrode, and a drain electrode,
The semiconductor stacked structure includes a first semiconductor layer made of a first nitride semiconductor formed on the substrate, and a first semiconductor layer formed on the first semiconductor layer and having a band gap smaller than that of the first nitride semiconductor. a second semiconductor layer made of a large second nitride semiconductor;
A semiconductor device having a gate leakage current value of 2×10 ⁻⁵ A/mm or less at an operating temperature of 400 K when a reverse bias of 100 V is applied between the gate electrode and the drain electrode.
[2] In the above [1], the gate leakage current value at an operating temperature of 500 K is less than 1×10 ⁻⁴ A/mm when a reverse bias of 100 V is applied between the gate electrode and the drain electrode. The semiconductor device described.

[3] A semiconductor device comprising a substrate, a semiconductor stacked structure, a source electrode, a gate electrode, and a drain electrode,
The semiconductor stacked structure includes a first semiconductor layer made of a first nitride semiconductor formed on the substrate, and a first semiconductor layer formed on the first semiconductor layer and having a band gap smaller than that of the first nitride semiconductor. a second semiconductor layer made of a large second nitride semiconductor;
A semiconductor device having a gate leakage current value of 1×10 ⁻⁵ A/mm or less at an operating temperature of 400 K when a reverse bias of 20 V is applied between the gate electrode and the drain electrode.
[4] In [3] above, the gate leakage current value at an operating temperature of 500 K is 4×10 ⁻⁵ A/mm or less when a reverse bias of 20 V is applied between the gate electrode and the drain electrode. The semiconductor device described.
[5] The above [3], wherein the gate leakage current value at an operating temperature of 600 K is less than 1×10 ⁻⁴ A/mm when a reverse bias of 20 V is applied between the gate electrode and the drain electrode. The semiconductor device according to [4].

[6] A semiconductor device comprising a substrate, a semiconductor stacked structure, a source electrode, a gate electrode, and a drain electrode,
The semiconductor stacked structure includes a first semiconductor layer made of a first nitride semiconductor formed on the substrate, and a first semiconductor layer formed on the first semiconductor layer and having a band gap smaller than that of the first nitride semiconductor. a second semiconductor layer made of a large second nitride semiconductor;
When a reverse bias of 10 V is applied between the gate electrode and the source electrode and a forward bias of 100 V is applied between the source electrode and the drain electrode, the drain leak current value at an operating temperature of 400 K is 5. A semiconductor device having a power consumption of less than ×10 ⁻⁵ A/mm.
[7] Drain leak current at an operating temperature of 500 K when a reverse bias of 10 V is applied between the gate electrode and the source electrode and a forward bias of 100 V is applied between the source electrode and the drain electrode. The semiconductor device according to [6] above, wherein the semiconductor device has a value of less than 5×10 ⁻⁴ A/mm.
[8] Drain leak current at an operating temperature of 600 K when a reverse bias of 10 V is applied between the gate electrode and the source electrode and a forward bias of 100 V is applied between the source electrode and the drain electrode. The semiconductor device according to [6] or [7], wherein the semiconductor device has a value of less than 1×10 ⁻³ A/mm.

[9] A semiconductor device comprising a substrate, a semiconductor stacked structure, a source electrode, a gate electrode, and a drain electrode,
The semiconductor stacked structure includes a first semiconductor layer made of a first nitride semiconductor formed on the substrate, and a first semiconductor layer formed on the first semiconductor layer and having a band gap smaller than that of the first nitride semiconductor. a second semiconductor layer made of a large second nitride semiconductor;
When a reverse bias of 10 V is applied between the gate electrode and the source electrode and a forward bias of 20 V is applied between the source electrode and the drain electrode, the drain leak current value at an operating temperature of 400 K is 3. A semiconductor device having a power consumption of less than ×10 ⁻⁵ A/mm.
[10] Drain leak current at an operating temperature of 500 K when a reverse bias of 10 V is applied between the gate electrode and the source electrode and a forward bias of 20 V is applied between the source electrode and the drain electrode. The semiconductor device according to the above [9], wherein the semiconductor device has a value of 1.5×10 ⁻⁴ A/mm or less.
[11] Drain leak current at an operating temperature of 600 K when a reverse bias of 10 V is applied between the gate electrode and the source electrode and a forward bias of 20 V is applied between the source electrode and the drain electrode. The semiconductor device according to [9] or [10], wherein the semiconductor device has a value of less than 1×10 ⁻³ A/mm.

[12] The first nitride semiconductor includes GaN,
The semiconductor device according to any one of [1] to [11], wherein the second nitride semiconductor contains Al _x Ga _1-x N (0<x<1).
[13] The semiconductor device according to any one of [1] to [12], wherein the substrate is a GaN substrate.
[14] The semiconductor device according to [13], wherein the GaN substrate has a resistivity of 1×10 ⁷ Ωcm or more at 400K.
[15] The semiconductor device according to [13] or [14], wherein the GaN substrate has a resistivity of 1×10 ⁶ Ωcm or more at 500K.
[16] The semiconductor device according to any one of [13] to [15], wherein the GaN substrate has a resistivity of 1×10 ⁵ Ωcm or more at 600K.
[17] The semiconductor device according to any one of [13] to [16], wherein the GaN substrate is a C-doped GaN substrate.

In the semiconductor device according to this embodiment, leakage current is effectively suppressed during operation in a high-temperature environment. Therefore, it is very suitable for application in environments where high-speed operation under high-temperature conditions is required.

FIG. 1 is a schematic cross-sectional view showing an example of a semiconductor device according to this embodiment. FIG. 2 is a graph showing the measurement results of the resistivity of the GaN substrates used in Example 1 and Comparative Example 1. FIG. 3 is a graph showing the results of two-terminal measurements on the semiconductor device according to Example 1. FIG. 4 is a graph showing the results of three-terminal measurements on the semiconductor device according to Example 1. FIG. 5 is a graph showing the results of two-terminal measurements on the semiconductor device according to Comparative Example 1. FIG. 6 is a graph showing the results of three-terminal measurements on the semiconductor device according to Comparative Example 1.

The present invention will be described in detail below, but the present invention is not limited to the following embodiments, and can be implemented with various modifications within the scope of the gist.
In this specification, the crystal axis parallel to the [0001] axis is called the c-axis, the crystal axis parallel to the <10-10> axis is called the m-axis, and the crystal axis parallel to the <11-20> axis is called the a-axis. A crystal plane perpendicular to the c-axis is called a c-plane.
The hexagonal Miller index (hkil) is sometimes expressed as (hkl) with three digits because there is a relationship h+k=-i. For example, (0004) is expressed in three digits as (004).
In this specification, when referring to a crystal axis, a crystal plane, a crystal orientation, etc., unless otherwise specified, each refers to a crystal axis, a crystal plane, a crystal orientation, etc. in a substrate or a semiconductor layer.
In this specification, both the carbon (C) concentration and the Fe concentration at a specific position are values determined by respective detection amounts using secondary ion mass spectrometry (SIMS).
In this specification, when the expression "~" is used, it is used as an expression including numerical values or physical property values before and after it. That is, "A to B" means greater than or equal to A and less than or equal to B.
In this specification, the gate electrode and the semiconductor are Schottky junctions. Therefore, applying a voltage so that the gate electrode becomes a positive electrode is defined as "forward bias," and applying a voltage so that the gate electrode becomes a negative electrode is defined as "reverse bias." According to general notation in academic circles, "forward bias" is defined as applying a voltage between the source electrode and the drain electrode so that the drain electrode becomes a positive electrode.

[Semiconductor device]
The semiconductor device according to the first embodiment includes a substrate, a semiconductor stacked structure, a source electrode, a gate electrode, and a drain electrode. The semiconductor stacked structure includes a first semiconductor layer made of a first nitride semiconductor formed on a substrate, and a second semiconductor layer formed on the first semiconductor layer and having a larger band gap than the first nitride semiconductor. a second semiconductor layer made of a nitride semiconductor.
The semiconductor device has a gate leakage current value of 2×10 ⁻⁵ A/mm or less at an operating temperature of 400 K when a reverse bias of 100 V is applied between the gate electrode and the drain electrode.

The fact that the gate leakage current value at an operating temperature of 400 K when applying a reverse bias of 100 V between the gate electrode and the drain electrode is 2×10 ⁻⁵ A/mm or less means that when the semiconductor device is in the off state, This means that gate leakage current in a high-temperature environment is effectively suppressed. This can prevent a large gate leakage current from flowing and causing the device to malfunction when the semiconductor device is operated in a high-temperature environment.
Note that the term "high temperature environment" as used herein refers to an environment of 50°C or higher, and may be, for example, 100°C or higher, or 150°C or higher. Further, the upper limit is not particularly limited, but is usually 500°C or less.

When a reverse bias of 100V is applied between the gate electrode and the drain electrode, the gate leakage current value at an operating temperature of 400K should be 2×10 ^-5 A/mm or less, but there is a risk of device failure due to gate leakage current. From the viewpoint of reducing the current, it is preferably 1.5×10 ⁻⁵ A/mm or less, more preferably 1×10 ⁻⁵ A/mm or less. The smaller the gate leakage current value is, the more preferable it is, but it is usually 1.0×10 ⁻⁸ A/mm or more.

Further, it is desirable that gate leakage current of a semiconductor device be suppressed even under a higher temperature operating environment. From this point of view, it is preferable that the gate leakage current value at an operating temperature of 500 K when a reverse bias of 100 V is applied between the gate electrode and the drain electrode is less than 1 x 10 ^-4 A/mm, and 8 x 10 ^- It is preferably ⁵ A/mm or less, more preferably 5×10 ⁻⁵ A/mm or less, even more preferably 3×10 ⁻⁵ A/mm or less. When the gate leakage current at an operating temperature of 500K is within the above range, the risk of failure of the device due to the gate leakage current can be further reduced. The smaller the gate leakage current value is, the more preferable it is, but it is usually 1.0×10 ⁻⁸ A/mm or more.

The semiconductor device according to the second embodiment includes a substrate, a semiconductor stacked structure, a source electrode, a gate electrode, and a drain electrode. The semiconductor stacked structure includes a first semiconductor layer made of a first nitride semiconductor formed on a substrate, and a second semiconductor layer formed on the first semiconductor layer and having a larger band gap than the first nitride semiconductor. a second semiconductor layer made of a nitride semiconductor.
The semiconductor device has a gate leakage current value of 1×10 ⁻⁵ A/mm or less at an operating temperature of 400 K when a reverse bias of 20 V is applied between the gate electrode and the drain electrode.

The fact that the gate leakage current value at an operating temperature of 400 K when applying a reverse bias of 20 V between the gate electrode and the drain electrode is 1×10 ⁻⁵ A/mm or less means that when the semiconductor device is in the off state, This means that gate leakage current in a high-temperature environment is effectively suppressed. This can prevent a large gate leakage current from flowing and causing the device to malfunction when the semiconductor device is operated in a high-temperature environment.

When applying a reverse bias of 20V between the gate electrode and the drain electrode, the gate leakage current value at an operating temperature of 400K should be 1×10 ^-5 A/mm or less, but there is a risk of device failure due to gate leakage current. From the viewpoint of reducing the current, it is preferably 8×10 ⁻⁶ A/mm or less, more preferably 5×10 ⁻⁶ A/mm or less, even more preferably 2×10 ⁻⁶ A/mm or less, and 1×10 ⁻⁶ A/mm or less is particularly preferable, and 5×10 ⁻⁷ A/mm or less is most preferable. The smaller the gate leakage current value is, the more preferable it is, but it is usually 1.0×10 ⁻⁸ A/mm or more.

Further, it is desirable that gate leakage current of a semiconductor device be suppressed even under a higher temperature operating environment. From this point of view, it is preferable that the gate leakage current value at an operating temperature of 500 K when a reverse bias of 20 V is applied between the gate electrode and the drain electrode is 4×10 ⁻⁵ A/mm or less, and 2×10 ⁻⁵ A/mm or less. It is preferably ⁵ A/mm or less, more preferably 1×10 ⁻⁵ A/mm or less, further preferably 8×10 ⁻⁶ A/mm or less, particularly preferably 5×10 ⁻⁶ A/mm or less. When the gate leakage current at an operating temperature of 500K is within the above range, the risk of failure of the device due to the gate leakage current can be further reduced. The smaller the gate leakage current value is, the more preferable it is, but it is usually 1.0×10 ⁻⁸ A/mm or more.

From a similar point of view, it is desirable that gate leakage current of a semiconductor device be suppressed even under a higher temperature operating environment. From this point of view, it is preferable that the gate leakage current value at an operating temperature of 600 K is less than 1×10 −4 A/mm when a reverse bias of 20 V is applied between the gate electrode and the drain electrode, and 9×10 ⁻⁴ A/mm ^. It is preferably ⁵ A/mm or less, more preferably 8×10 ⁻⁵ A/mm or less. When the gate leakage current at an operating temperature of 600K is within the above range, the risk of failure of the device due to the gate leakage current can be further reduced. The smaller the gate leakage current value is, the more preferable it is, but it is usually 1.0×10 ⁻⁸ A/mm or more.

A semiconductor device according to a third embodiment includes a substrate, a semiconductor stacked structure, a source electrode, a gate electrode, and a drain electrode. The semiconductor stacked structure includes a first semiconductor layer made of a first nitride semiconductor formed on a substrate, and a second semiconductor layer formed on the first semiconductor layer and having a larger band gap than the first nitride semiconductor. a second semiconductor layer made of a nitride semiconductor.
The semiconductor device has a drain leak current value of 5×10 ⁻⁵ at an operating temperature of 400 K when a reverse bias of 10 V is applied between the gate electrode and the source electrode and a forward bias of 100 V is applied between the source electrode and the drain electrode. less than A/mm.

The drain leakage current value at an operating temperature of 400K is less than 5×10 ^-5 A/mm when a reverse bias of 10V is applied between the gate electrode and the source electrode and a forward bias of 100V is applied between the source and drain electrodes. This means that drain leakage current in a high-temperature environment is effectively suppressed when the semiconductor device is in an off state. This can prevent a large drain leakage current from flowing and causing the device to malfunction when the semiconductor device is operated in a high-temperature environment.

When a reverse bias of 10 V is applied between the gate electrode and the source electrode, and a forward bias of 100 V is applied between the source electrode and the drain electrode, the drain leakage current value at an operating temperature of 400 K is 5 × 10 ^-5 A/mm. It may be less than 4×10 ⁻⁵ A/mm, more preferably 3×10 ⁻⁵ A/mm or less, and 2×10 ^-5 A/mm or less is more preferable. The smaller the drain leakage current value is, the more preferable it is, but it is usually 1.0×10 ⁻⁸ A/mm or more.

Further, it is desirable that drain leakage current of the semiconductor device be suppressed even under a higher temperature operating environment. From this point of view, when a reverse bias of 10 V is applied between the gate electrode and the source electrode, and a forward bias of 100 V is applied between the source electrode and the drain electrode, the drain leakage current value at an operating temperature of 500 K is 5 × 10 ^- It is preferably less than ⁴ A/mm, preferably less than 2×10 ⁻⁴ A/mm, more preferably less than 1×10 ⁻⁴ A/mm, even more preferably less than 8×10 ⁻⁵ A/mm, and even more preferably less than 6 It is even more preferably at most ×10 ⁻⁵ A/mm, particularly preferably at most 4×10 ⁻⁵ A/mm. When the drain leakage current at an operating temperature of 500K is within the above range, the risk of failure of the device due to the drain leakage current can be further reduced. The smaller the drain leakage current value is, the more preferable it is, but it is usually 1.0×10 ⁻⁸ A/mm or more.

From a similar point of view, it is desirable that drain leakage current of a semiconductor device be suppressed even under a higher temperature operating environment. From this point of view, when a reverse bias of 10 V is applied between the gate electrode and the source electrode, and a forward bias of 100 V is applied between the source electrode and the drain electrode, the drain leakage current value at an operating temperature of 600 K is 1×10 ⁻ It is preferably less than ³ A/mm, preferably 9×10 ⁻⁴ A/mm or less, and more preferably 8×10 ⁻⁴ A/mm or less. When the drain leak current at an operating temperature of 600 K is within the above range, the risk of failure of the device due to drain leak current can be further reduced. The smaller the drain leakage current value is, the more preferable it is, but it is usually 1.0×10 ⁻⁸ A/mm or more.

The semiconductor device according to the fourth embodiment includes a substrate, a semiconductor stacked structure, a source electrode, a gate electrode, and a drain electrode. The semiconductor stacked structure includes a first semiconductor layer made of a first nitride semiconductor formed on a substrate, and a second semiconductor layer formed on the first semiconductor layer and having a larger band gap than the first nitride semiconductor. a second semiconductor layer made of a nitride semiconductor.
The semiconductor device has a drain leakage current value of 3×10 ⁻⁵ at an operating temperature of 400 K when a reverse bias of 10 V is applied between the gate electrode and the source electrode, and a forward bias of 20 V is applied between the source electrode and the drain electrode. less than A/mm.

The drain leakage current value at an operating temperature of 400 K is less than 3×10 ^-5 A/mm when a reverse bias of 10 V is applied between the gate electrode and the source electrode and a forward bias of 20 V is applied between the source electrode and the drain electrode. This means that drain leakage current in a high-temperature environment is effectively suppressed when the semiconductor device is in an off state. This can prevent a large drain leakage current from flowing and causing the device to malfunction when the semiconductor device is operated in a high-temperature environment.

When a reverse bias of 10 V is applied between the gate electrode and the source electrode, and a forward bias of 20 V is applied between the source electrode and the drain electrode, the drain leakage current value at an operating temperature of 400 K is 3 × 10 ^-5 A/mm. It may be less than 1×10 ⁻⁵ A/mm, more preferably 8×10 ⁻⁶ A/mm or less, and 6×10 ^-6 A/mm or less is more preferable, 3×10 ⁻⁶ A/mm or less is even more preferable, and 1×10 ⁻⁶ A/mm or less is particularly preferable. The smaller the drain leakage current value is, the more preferable it is, but it is usually 1.0×10 ⁻⁸ A/mm or more.

Further, it is desirable that drain leakage current of the semiconductor device be suppressed even under a higher temperature operating environment. From this point of view, when a reverse bias of 10 V is applied between the gate electrode and the source electrode, and a forward bias of 20 V is applied between the source electrode and the drain electrode, the drain leakage current value at an operating temperature of 500 K is 1.5× It is preferably 10 ⁻⁴ A/mm or less, 1×10 ⁻⁴ A/mm or less, more preferably 8×10 ⁻⁵ A/mm or less, even more preferably 5×10 ⁻⁵ A/mm or less. , 3×10 ⁻⁵ A/mm or less is particularly preferable. When the drain leakage current at an operating temperature of 500K is within the above range, the risk of failure of the device due to the drain leakage current can be further reduced. The smaller the drain leakage current value is, the more preferable it is, but it is usually 1.0×10 ⁻⁸ A/mm or more.

From a similar point of view, it is desirable that drain leakage current of a semiconductor device be suppressed even under a higher temperature operating environment. From this point of view, when a reverse bias of 10 V is applied between the gate electrode and the source electrode, and a forward bias of 20 V is applied between the source electrode and the drain electrode, the drain leak current value at an operating temperature of 600 K is 1×10 ⁻ It is preferably less than ³ A/mm, preferably 8×10 ⁻⁴ A/mm or less, more preferably 5×10 ⁻⁴ A/mm or less, particularly preferably 3×10 ⁻⁴ A/mm or less. When the drain leak current at an operating temperature of 600 K is within the above range, the risk of failure of the device due to drain leak current can be further reduced. The smaller the drain leakage current value is, the more preferable it is, but it is usually 1.0×10 ⁻⁸ A/mm or more.

-Structure FIG. 1 is a schematic cross-sectional view showing an example of a semiconductor device according to this embodiment. In the semiconductor device 10, a semiconductor stacked structure 200 is formed on a substrate 100. The semiconductor stacked structure 200 includes a first semiconductor layer 300 and a second semiconductor layer 400 in this order, and optionally also includes a cap layer 500.
A source electrode 600S, a drain electrode 600D, and a gate electrode 600G are formed on the semiconductor stacked structure 200. A gate insulating film 700 is optionally formed between the source electrode 600S and the gate electrode 600G, and between the drain electrode 600D and the gate electrode 600G.
The first semiconductor layer 300 is a layer made of a first nitride semiconductor, and is made of, for example, a C-containing GaN layer 301 and an i-GaN layer 302. The C-containing GaN layer 301 is preferably formed on the substrate 100, and the i-GaN layer 302 is preferably formed on the C-containing GaN layer 301.
The second semiconductor layer 400 is a layer made of a second nitride semiconductor, and is preferably formed, for example, on the i-GaN layer 302 that constitutes the first semiconductor layer 300.
When the semiconductor stacked structure 200 includes a cap layer 500, the cap layer 500 is preferably formed on the second semiconductor layer 400. A source electrode 600S, a drain electrode 600D, and a gate electrode 600G are each formed on the cap layer 500.

-Substrate In any of the first to fourth embodiments of the present invention (these may be collectively referred to as "this embodiment"), the semiconductor device includes a substrate.
The substrate is not particularly limited, and may be, for example, a silicon substrate, a sapphire substrate, a SiC substrate, or a GaN substrate. Among these, it is preferable that the substrate be a GaN substrate from the viewpoint that a layer made of a nitride semiconductor epitaxially grown on the substrate has high crystal quality and excellent device performance.

When the substrate is a GaN substrate, it is more preferable that the resistivity at 400K is 1×10 ⁷ Ωcm or more.
The present inventors have found that when the resistivity of the GaN substrate at 400K is 1×10 ⁷ Ωcm or more, drain leakage current during high-temperature operation of a semiconductor device is significantly suppressed. The reason for this is not yet clear, but I think it is as follows.
That is, in the HEMT structure, the spread of the depletion layer inhibits drain leakage current, but in a high-temperature environment, it is thought that the resistivity of the substrate decreases, causing drain leakage current to flow through the substrate. Based on this knowledge, by using a GaN substrate used in semiconductor devices that has high resistivity even in high-temperature environments, it will be possible to effectively suppress drain leakage current during high-temperature operation of semiconductor devices. Conceivable.

Furthermore, it has been found that when the resistivity of the GaN substrate at 400K is 1×10 ⁷ Ωcm or more, gate leakage current during high-temperature operation of the semiconductor device is also significantly suppressed.
The cause of gate leakage current is said to be a surface current between the source electrode and the gate electrode, a defect in the channel layer, etc., but the detailed mechanism is unknown. The mechanism by which the gate leakage current occurs in this embodiment is also unknown, but since changes in the resistivity of the substrate are linked to changes in the gate leakage current, the resistivity of the substrate affects the potential near the channel layer. It is thought that the gate leakage current changes due to a change in the depletion layer distribution as a result.

From the above viewpoint, the resistivity of the GaN substrate at 400K is preferably 1×10 ⁷ Ωcm or more, more preferably 1×10 ¹⁰ Ωcm or more, even more preferably 5×10 ¹⁰ Ωcm or more, and even more preferably 1×10 ¹¹ Ωcm or more. Particularly preferred. The higher the resistivity at 400K, the better, so the upper limit is not particularly limited.

From the same viewpoint, the resistivity of the GaN substrate at 500K is preferably 1×10 ⁶ Ωcm or more, more preferably 1×10 ⁷ Ωcm or more, and even more preferably 1×10 ⁸ Ωcm or more. The higher the resistivity at 500K, the better, so the upper limit is not particularly limited.

From the same viewpoint, it is also preferable that the resistivity of the GaN substrate at 600K is 1×10 ⁵ Ωcm or more, more preferably 1×10 ⁶ Ωcm or more, and particularly preferably 1×10 ⁷ Ωcm or more. The higher the resistivity at 600K, the better, so the upper limit is not particularly limited.

The substrate is also preferably a carbon (C) doped substrate, ie a GaN substrate with a C-doped layer. In this case, the thickness of the C-doped layer in the c-axis direction does not need to match the thickness of the GaN substrate in the c-axis direction.

For example, while the overall thickness of the GaN substrate is 400 μm, it is sufficient that the thickness of the C-doped layer is 100 μm in the surface layer of the GaN substrate. Of course, the thickness of the C-doped layer is not limited to the above, and does not exclude cases where it is thicker or thinner than that, and the entire thickness direction of the GaN substrate is composed of a C-doped layer. You can.

The C concentration in the C-doped layer of the GaN substrate is preferably 1.0×10 ¹⁶ atoms/cm ³ or more and 1.0×10 ²⁰ atoms/cm ³ or less. Since C, which is a compensating impurity, contributes to high resistance, it is preferable that the C concentration is 1.0×10 ¹⁶ atoms/cm ³ or more from the viewpoint of increasing the resistance of the GaN crystal, and 1.0×10 ²⁰ Atoms/cm ³ or less is preferable from the viewpoint of maintaining good crystal quality of the GaN crystal.

The C concentration in the C-doped layer of the GaN substrate is determined in stages as follows: the upper limit is 6.0×10 ¹⁹ atoms/cm ³ or less, 5.0×10 ¹⁹ atoms/cm ³ or less, and 3.0×10 ¹⁹ atoms /cm ³ or less, 1.0×10 ¹⁹ atoms/cm ³ or less, 5.0×10 ¹⁸ atoms/cm ³ or less, and the lower limit is 1.0×10 ¹⁶ atoms/cm ³ or more, 3. 0×10 ¹⁶ atoms/cm ³ or more, 5.0×10 ¹⁶ atoms/cm ³ or more, 1.0×10 ¹⁷ atoms/cm ³ or more, 3.0×10 ¹⁷ atoms/cm ³ or more, 5.0× It is preferable that it is 10 ¹⁷ atoms/cm ³ or more. The combination of the preferable upper and lower limits of the above C concentration is arbitrary.

- Semiconductor stacked structure The semiconductor device according to this embodiment includes a first semiconductor layer made of a first nitride semiconductor formed on a substrate, and a first semiconductor layer formed on the first semiconductor layer and made of a first nitride semiconductor. and a second semiconductor layer made of a second nitride semiconductor having a large bandgap.

...First Semiconductor Layer The first semiconductor layer is a nitride semiconductor crystal layer formed on the substrate and made of a first nitride semiconductor. A suitable example of the first nitride semiconductor is GaN.
When the first nitride semiconductor is GaN, the first semiconductor layer preferably includes a C-containing GaN layer containing carbon (C) and an i-GaN layer. The first semiconductor layer may be composed of one layer or two or more layers, and may further include a crystal phase composed of GaN other than the C-containing GaN layer and the i-GaN layer.

... C-containing GaN layer The first semiconductor layer preferably includes a C-containing GaN layer having a carbon (C) concentration of 1×10 ¹⁶ atoms/cm ³ or more. The C-containing GaN layer is a crystal layer made of GaN epitaxially grown, and is a layer containing carbon (C) as an impurity.
The presence of the C-containing GaN layer inhibits the migration of compensating impurities between different regions defined by the C-containing GaN layer.
This is because, for example, when the substrate is doped with C, the C in the substrate moves as a compensation impurity through thermal diffusion in the HEMT structure and may reach the 2DEG region. When a compensating impurity such as C diffuses into the 2DEG, the movement of electrons in the 2DEG may be inhibited, and the performance as a semiconductor device may deteriorate. On the other hand, when the C-containing GaN layer is present, it inhibits the movement of compensating impurities, and therefore it is possible to suppress the performance deterioration of the semiconductor device.

The C concentration in the C-containing GaN layer is preferably 1×10 ¹⁶ atoms/cm ³ or more, and from the viewpoint of more effectively inhibiting the movement of compensation impurities, it is more preferably 5×10 ¹⁶ atoms/cm ^{3 or more, and 1×10 16 atoms/cm 3} or more. More preferably, it is ¹⁷ atoms/cm ³ or more. Further, from the viewpoint of preventing defects such as threading dislocations, the C concentration in the C-containing GaN layer is preferably less than 1×10 ¹⁹ atoms/cm ³ , more preferably less than 1×10 ¹⁸ atoms/cm ³ , and more preferably less than 5×10 18 atoms/cm 3 . More preferably, it is less than ¹⁷ atoms/cm ³ .

From the viewpoint of normal device fabrication, the thickness of the C-containing GaN layer in the c-axis direction is preferably 50 nm or more, more preferably 100 nm or more, and even more preferably 200 nm or more. Further, from the viewpoint of reducing leakage current, the thickness of the C-containing GaN layer is preferably 900 nm or less, more preferably 600 nm or less, and even more preferably 500 nm or less.

From the viewpoint of normal device fabrication, the thickness of the C-containing GaN layer in the c-axis direction is preferably 5% or more, more preferably 10% or more, and even more preferably 20% or more of the total film thickness of the first semiconductor layer. Moreover, from the same viewpoint, the above-mentioned thickness is preferably 90% or less of the total film thickness of the first semiconductor layer, more preferably 80% or less, and even more preferably 70% or less. Note that the total film thickness of the first semiconductor layer is the total film thickness in the c-axis direction including, if the first semiconductor layer includes an i-GaN layer, which will be described later, in addition to the C-containing GaN layer. Refers to thickness.

...i-GaN layer In this embodiment, when the first semiconductor layer includes the above-mentioned C-containing GaN layer, the first semiconductor layer has the i-GaN layer in the [0001] axis direction from the C-containing GaN layer. It is preferable. More preferably, the i-GaN layer is placed directly on the C-containing GaN layer.
Having an i-GaN layer in the [0001] axis direction than the C-containing GaN layer means that the i-GaN layer exists in the +c-axis direction, that is, in the direction of the Ga polar plane of the crystal, than the C-containing GaN layer. .

The i-GaN layer is a crystalline layer made of GaN epitaxially grown without intentional doping with impurities, and is distinguished from the C-containing GaN layer by the C concentration. That is, the C concentration of the i-GaN layer is less than 1×10 ¹⁶ atoms/cm ³ . The i-GaN layer functions as a so-called channel layer.

The thickness of the first semiconductor layer in the c-axis direction is ideally as thin as possible in order to reduce drain leakage current during HEMT operation. The thickness of the i-GaN layer in the first semiconductor layer in the c-axis direction is preferably 50 nm or more, more preferably 100 nm or more, and even more preferably 200 nm or more, from the viewpoint of normal device fabrication. Further, from the viewpoint of reducing leakage current, the thickness of the i-GaN layer is preferably 900 nm or less, more preferably 600 nm or less, and even more preferably 500 nm or less.
Preferably, the top surface of the i-GaN layer in the first semiconductor layer coincides with the top surface of the first semiconductor layer.

...Second Semiconductor Layer The second semiconductor layer is formed on the first semiconductor layer, and is made of a second nitride semiconductor having a larger band gap than the first nitride semiconductor. The second nitride semiconductor is not particularly limited as long as its band gap is larger than that of the first nitride semiconductor. For example, if the first nitride semiconductor is GaN, the second nitride semiconductor The semiconductor is preferably Al _x Ga _1-x N (0<x<1) or AlInGaN. The second semiconductor layer may consist of one layer, or may consist of two or more layers.

A two-dimensional electron gas (2DEG) is formed at the heterojunction interface between the first semiconductor layer and the second semiconductor layer. Specifically, when the first semiconductor layer includes the above-mentioned i-GaN layer, 2DEG is generated in the region sandwiched between the i-GaN layer and the second semiconductor layer. The second semiconductor layer functions as a so-called barrier layer or an electron supply layer.

A typical example is a GaN (first semiconductor layer)/Al _x Ga _1-x N (0<x<1) (second semiconductor layer) heterostructure formed on a GaN substrate with the (0001) plane as the main surface. In this case, 2DEG is generated at the hetero interface due to spontaneous polarization and piezoelectric polarization, and a sheet carrier concentration of about 1×10 ¹³ cm ⁻² or more can be obtained without doping anything, thereby achieving high frequency operation.

The thickness of the second semiconductor layer in the c-axis direction is preferably 1 nm or more, more preferably 5 nm or more, and even more preferably 10 nm or more, from the viewpoint of normal device fabrication. Further, from the viewpoint of reducing leakage current, the thickness of the second semiconductor layer is preferably 50 nm or less, more preferably 40 nm or less, and even more preferably 30 nm or less. Note that when the second semiconductor layer is composed of two or more layers of second nitride semiconductor, the above thickness is the total thickness of the second semiconductor layer.

... Cap layer Although the semiconductor stacked structure includes a first semiconductor layer and a second semiconductor layer, a cap layer may be further formed on the second semiconductor layer. The cap layer is preferably made of a nitride semiconductor different from the second nitride semiconductor, for example, when the second nitride semiconductor is Al _x Ga _1-x N (0<x<1) or AlInGaN, Preferably, the cap layer is made of GaN. The cap layer may consist of one layer, or may consist of two or more layers.

From the viewpoint of normal device fabrication, the thickness of the cap layer in the c-axis direction is preferably 0.1 nm or more, more preferably 0.5 nm or more, and even more preferably 1 nm or more. Further, from the viewpoint of reducing leakage current, the thickness of the cap layer is preferably 10 nm or less, more preferably 8 nm or less, and even more preferably 5 nm or less. Note that when the cap layer is composed of two or more layers, the above thickness is the total thickness of the cap layer.

- Electrode The semiconductor device according to this embodiment includes a source electrode, a gate electrode, and a drain electrode. Preferably, a source electrode, a gate electrode, and a drain electrode are formed above the semiconductor stacked structure.

The source electrode is, for example, a metal electrode, and specifically includes a laminated structure containing titanium (Ti) and aluminum (Al), a laminated structure containing molybdenum (Mo) and aluminum (Al), and the like.

The drain electrode is, for example, a metal electrode, and specifically includes a laminated structure containing titanium (Ti) and aluminum (Al), a laminated structure containing molybdenum (Mo) and aluminum (Al), and the like.

It is preferable that the source electrode and the drain electrode and the semiconductor stacked structure are each connected to each other in an ohmic contact. The distance between the source electrode and the drain electrode is, for example, 5 μm or more and 30 μm or less.

The gate electrode is, for example, a metal electrode, and specifically includes a stacked structure containing nickel (Ni) and gold (Au), a stacked structure containing platinum (Pt) and gold (Au), and the like. The gate length is, for example, 1 μm or more and 15 μm or less.
Preferably, the gate electrode is formed between the source electrode and the drain electrode. The distance between the gate electrode and the source electrode is, for example, 1 μm or more and 15 μm or less. The distance between the gate electrode and the drain electrode is, for example, 1 μm or more and 15 μm or less.

A gate insulating film may be provided between the gate electrode and the semiconductor stacked structure. That is, the gate electrode may be formed above the semiconductor stacked structure with the gate insulating film interposed therebetween.
Furthermore, a gate insulating film may be provided between the gate electrode and the source electrode, and between the gate electrode and the drain electrode.

The gate insulating film is, for example, an oxide or an oxynitride. The gate insulating film is, for example, silicon oxide, aluminum oxide, silicon nitride, silicon oxynitride, or aluminum oxynitride.

In an example of a preferred embodiment, a source electrode, a gate electrode, and a drain electrode are formed on the cap layer, and more preferably, a gate electrode is formed between the source electrode and the gate electrode, and between the gate electrode and the drain electrode, respectively. It has an insulating film.
In another preferred embodiment, a source electrode and a drain electrode are formed on the second semiconductor layer, and a gate electrode is formed on the cap layer.
In another preferred embodiment, a source electrode and a drain electrode are formed on the cap layer, and a gate electrode is formed on the gate insulating film.

・Applications The semiconductor device according to this embodiment is suitable for communication in high-temperature environments such as deserts and outer space because it is possible to suppress leakage current when high-speed operation is required in high-temperature environments. It can be used for.

[Method for manufacturing semiconductor device]
Although the method for manufacturing the semiconductor device according to this embodiment is not particularly limited, one embodiment will be described below. Further, preferred embodiments of the semiconductor device obtained by this manufacturing method are the same as the preferred embodiments described in the above-mentioned [Semiconductor Device].
The method for manufacturing a semiconductor device according to the above embodiment includes at least the steps of preparing a substrate, then forming a semiconductor stacked structure on the substrate, and forming an electrode above the semiconductor stacked structure.

・Method of preparing a substrate The substrate used in the semiconductor device according to the present embodiment is not particularly limited as described in [Semiconductor device] above, but is preferably a GaN substrate, and has a resistivity of 1×10 at 400K. A GaN substrate having a resistance of ⁷ Ωcm or more is more preferable. Alternatively, it may be a GaN substrate having a C-doped layer.

The above-mentioned substrate may be manufactured by a known method and used, or a commercially available product may be obtained and used. When manufacturing a GaN substrate, the step of preparing the substrate described above is a step of manufacturing the GaN substrate.
A GaN substrate with a resistivity of 1×10 ⁷ Ωcm or more at 400 K is grown as a bulk GaN crystal while doping a compensating impurity such as C onto the seed using the HVPE (Hydride Vapor Phase Epitaxy) method. It can be obtained by growing and processing such as slicing, grinding, polishing, etc.
A C-doped GaN substrate can be obtained, for example, by growing a C-doped bulk GaN crystal on a seed using the HVPE method and performing processing such as slicing, grinding, polishing, etc.

・Method for forming a semiconductor stacked structure A semiconductor stacked structure includes a first semiconductor layer made of a first nitride semiconductor formed on a substrate, and a first semiconductor layer formed on the first semiconductor layer. Also includes a second semiconductor layer made of a second nitride semiconductor with a large band gap. Therefore, a method for forming a semiconductor stacked structure includes a step of forming a first semiconductor layer on a substrate, and a step of forming a second semiconductor layer on the first semiconductor layer.

The method for forming the first semiconductor layer on the substrate is not particularly limited, and various known methods can be employed, but a preferred example is MOCVD (metal organic chemical vapor deposition). ) method and molecular beam epitaxy (MBE) method.
Below, a method for forming the first semiconductor layer made of GaN will be specifically described.

When using the MOCVD method, the raw material gas is not particularly limited as long as it contains a Ga source and a N source for forming GaN, and any known gas can be used.

When doping the first semiconductor layer with C to form a C-containing GaN layer, the thickness in the c-axis direction (height in the thickness direction) of the C-containing GaN layer with a C concentration of 1×10 ¹⁶ atoms/cm ³ or more is As described in "Semiconductor stacked structure\...first semiconductor layer\...C-containing GaN layer" in the above [Semiconductor device], the thickness is 50 nm or more from the viewpoint of normal device fabrication. In addition, from the viewpoint of reducing leakage current, the thickness is preferably 900 nm or less.

The concentration of C in the C-containing GaN layer may be 1×10 ¹⁶ atoms/cm ³ or more, but such a concentration may be 5×10 ¹⁶ atoms/cm ³ or more, 1×10 ¹⁷ atoms/cm ³ or more, etc. There may be.

The concentration of C in the C-containing GaN layer is preferably less than 1×10 ¹⁹ atoms/cm ³ , less than 1×10 ¹⁸ atoms/cm 3 , or less than 5×10 atoms/cm ³ to avoid significant deterioration of crystal quality due to excessive doping. It may be less than ¹⁷ atoms/cm ³ .

For doping with C, a conventionally known method can be used. For example, it is preferable to use MOCVD method or MBE method.

When using the MOCVD method, a hydrocarbon gas such as CH ₄ (methane) can be used as a raw material gas, but from the viewpoint of simplification, a raw material gas that also contains a Ga source and a N source for forming GaN is used. It is preferable to use From this viewpoint, it is preferable to use trimethyl gallium (TMG) or triethyl gallium (TEG) as the raw material gas for C, and TMG is more preferable. Further, it is more preferable to use a mixed gas of TMG and ammonia (NH ₃ ) or a mixed gas of TEG and NH ₃ .

When using a mixed gas of trimethyl gallium (TMG) and ammonia (NH ₃ ), the TMG supply rate is preferably 100 μmol/min or more, more preferably 200 μmol/min or more, from the viewpoint of reducing the concentration of impurities such as Si. Further, from the viewpoint of film thickness controllability, the TMG supply rate is preferably 500 μmol/min or less, more preferably 300 μmol/min or less.
Further, the ratio of the supply rate expressed by TMG:NH ₃ is preferably 1:100 to 1:4000, preferably 1:500 to 1:4000 or 1:100 to 1:2000 from the viewpoint of controllability of C concentration. is more preferable, and even more preferably 1:500 to 1:2000.

As described above, the i-GaN layer may be formed after forming the C-containing GaN layer as the first semiconductor layer.
The method for forming the i-GaN layer is the same as the method for forming the C-containing GaN layer, except that it is performed without intentional doping of impurities, and preferred examples include the MOCVD method and the MBE method. This can be mentioned.

When using the MOCVD method to form the i-GaN layer, a hydrocarbon gas such as CH ₄ (methane) can be used as the raw material gas, but from the viewpoint of simplification, the Ga source for forming GaN is It is preferable to use a raw material gas that also contains a nitrogen source.

When using a mixed gas of trimethyl gallium (TMG) and ammonia (NH ₃ ), the TMG supply rate is preferably 50 μmol/min or more, more preferably 100 μmol/min or more, from the viewpoint of reducing the concentration of impurities such as Si. Further, from the viewpoint of film thickness controllability, the TMG supply rate is preferably 250 μmol/min or less, more preferably 150 μmol/min or less.
In addition, the ratio of the supply rate expressed by TMG:NH ₃ is preferably 1:400 to 1:16000, more preferably 1:400 to 1:1800 or 1:2000 to 1:16000, from the viewpoint of reducing C concentration. Preferably, 1:2000 to 1:8000 is more preferable.

The thickness of the i-GaN layer in the first semiconductor layer in the c-axis direction is as described in "Semiconductor stacked structure\...first semiconductor layer\...i-GaN layer" in [Semiconductor layer device] above. The thickness is preferably 50 nm or more from the viewpoint of normal device fabrication, and is preferably 900 nm or less from the viewpoint of reducing leakage current.

- Formation method of second semiconductor layer After forming the above-mentioned first semiconductor layer, a second semiconductor layer is formed on the first semiconductor layer. The second nitride semiconductor constituting the second semiconductor layer is not particularly limited as long as its band gap is larger than the band gap of the first nitride semiconductor, but for example, the first nitride semiconductor is GaN. In this case, the second nitride semiconductor is preferably Al _x Ga _1-x N (0<x<1) or AlInGaN. 2DEG is generated in a region sandwiched between the first semiconductor layer and the second semiconductor layer.

The method for forming the second semiconductor layer is not particularly limited, and any conventionally known method may be used, but preferred examples include MOCVD and MBE.
The preferable thickness in the c-axis direction of the second semiconductor layer on the first semiconductor layer is the same as that described in "Semiconductor stacked structure\...Second semiconductor layer" in the above [Semiconductor layer device].

When the above second semiconductor layer is formed, a conventionally known layer such as a cap layer can be formed by a conventionally known method if necessary.

-Method for forming electrodes The method for forming electrodes includes a step of forming a source electrode, a gate electrode, and a drain electrode above the semiconductor stacked structure.
The method for forming the electrode is not particularly limited, and any conventionally known method may be used, but a preferred example is the use of photolithography.

The source electrode is, for example, a metal electrode, and specifically includes a laminated structure containing titanium (Ti) and aluminum (Al), a laminated structure containing molybdenum (Mo) and aluminum (Al), and the like.
The drain electrode is, for example, a metal electrode, and specifically includes a laminated structure containing titanium (Ti) and aluminum (Al), a laminated structure containing molybdenum (Mo) and aluminum (Al), and the like.
It is preferable that the source electrode and the drain electrode and the semiconductor stacked structure are each connected to each other in an ohmic contact.

The gate electrode is, for example, a metal electrode, and specifically includes a stacked structure containing nickel (Ni) and gold (Au), a stacked structure containing platinum (Pt) and gold (Au), and the like.
Preferably, the gate electrode is formed between the source electrode and the drain electrode. Further, a gate insulating film may be provided between the gate electrode and the semiconductor stacked structure. That is, the gate electrode may be formed above the semiconductor stacked structure with the gate insulating film interposed therebetween. Furthermore, a gate insulating film may be provided between the gate electrode and the source electrode, and between the gate electrode and the drain electrode.

The gate insulating film is, for example, an oxide or an oxynitride. The gate insulating film is, for example, silicon oxide, aluminum oxide, silicon nitride, silicon oxynitride, or aluminum oxynitride.
The method for forming the gate insulating film is not particularly limited, and any conventionally known method may be used, but a preferred example is a PECVD (plasma-enhanced chemical vapor deposition) method.

The present invention will be specifically described below with reference to Examples, but the present invention is not limited thereto.

[Example 1]
A semiconductor stacked structure was deposited by MOCVD on a c-plane GaN substrate having a C-doped layer obtained by HVPE to obtain a HEMT-structured GaN epitaxial substrate. The thickness of the entire c-plane GaN substrate in the c-axis direction was 400 μm, of which the C-doped layer was present with a thickness of about 100 μm on the Ga polar surface side. The C concentration of the C-doped layer was 3×10 ¹⁸ atoms/cm ³ .
The resistivity of the c-plane GaN substrate with a C-doped layer at 400K is 2.3×10 ¹¹ Ωcm, the resistivity at 500K is 4.2×10 ⁸ Ωcm, and the resistivity at 600K is 1.2×10 ⁷ Ωcm. Ta. Note that the resistivity was measured by the method described below.

Specifically, to form the first semiconductor layer, a c-plane GaN substrate is set in an MOCVD apparatus, heated to 1090°C in a hydrogen/nitrogen mixed gas atmosphere and atmospheric pressure, and trimethylgallium (TMG) and NH ₃ gases were supplied. The gas supply rates were 410 μmol/min for TMG and 5 slm for NH ₃ gas. By growing the crystal for 2.7 minutes under these conditions, a C-containing GaN layer having a C concentration of 1×10 ¹⁷ atoms/cm ³ was formed in the first semiconductor layer. The thickness of the C-containing GaN layer was 300 nm.
Next, on the obtained C-containing GaN layer, an i-GaN layer of 200 nm was grown by changing the supply rate and growth time of TMG and NH ₃ gas, that is, the gas supply amount.

To form the second semiconductor layer, an Al _x Ga _1-x N (0<x<1) layer with a thickness of 18 nm was formed on the i-GaN layer formed above.
Next, a GaN cap layer was grown to a thickness of 2 nm to form a semiconductor stacked structure.
Through the above steps, a HEMT-structured GaN epitaxial substrate having a substrate and a semiconductor layer stacked structure was obtained.

Electrodes were formed on the GaN epitaxial substrate obtained above by photolithography.
Mo (7 nm)/Al (75 nm)/Mo (50 nm)/Au (120 nm) was deposited on the source electrode and drain electrode, and Ni (36 nm)/Au (370 nm) was deposited on the gate electrode using an electron beam. Note that the values in parentheses indicate the respective thicknesses. The gate length, the distance between the gate electrode and the source electrode, and the distance between the gate electrode and the drain electrode were set to 2 μm, 2 μm, and 5 μm, respectively.
SiNx with a thickness of 60 nm was formed as a gate insulating film between the gate electrode and the source electrode and between the gate electrode and the drain electrode by PECVD.
Through the above steps, a semiconductor device with a HEMT structure (also referred to as a HEMT element) was obtained.

[Comparative example 1]
A semiconductor device (HEMT element) having a HEMT structure was obtained in the same manner as in Example 1 except that Fe was used instead of C as a compensation impurity and a c-plane GaN substrate having an Fe-doped layer was used. The Fe-doped layer was present on the Ga polar surface side with a thickness of about 100 μm, and the Fe concentration of the Fe-doped layer was 3×10 ¹⁸ atoms/cm ³ .
The resistivity of the c-plane GaN substrate with an Fe-doped layer at 400K is 3.2×10 ⁶ Ωcm, the resistivity at 500K is 1.2×10 ⁵ Ωcm, and the resistivity at 600K is 1.5×10 ⁴ Ωcm. Ta. Note that the resistivity was measured by the method described below.

[Measurement of resistivity of substrate]
30 nm of Ti and 100 nm of Au were successively vacuum-deposited on the surface of a c-plane GaN substrate, and hole measurements were performed. In the Hall measurement, resistivity (specific resistance) was measured using a four-terminal Van der Pauw method while changing the measurement temperature.
The measurement results of the specific resistance of Example 1 are shown by "●" in FIG. 2, and the measurement results of the specific resistance of Comparative Example 1 are shown by "▲" in FIG. 2, respectively. Note that the carrier type determined by each Hall measurement in all temperature ranges was p-type.

[Evaluation of semiconductor devices]
- Two-terminal measurement In the HEMT structure semiconductor device, a reverse bias was applied between the gate electrode and the drain electrode, and the two-terminal reverse breakdown voltage characteristics were evaluated. The HEMT element was closely attached to the temperature variable stage by vacuum suction. The temperature variable stage temperature was changed to 300K, 400K, 500K, or 600K, and the two-terminal reverse breakdown voltage characteristics were evaluated at each temperature. The results of Example 1 are shown in FIG. 3, and the results of Comparative Example 1 are shown in FIG. 5, respectively. Vgd is the bias value between the gate electrode and the drain electrode, and -Ig is the gate leakage current.
In the measurement, 1×10 ⁻⁴ A/mm was used as the cutoff current. The cutoff current is a threshold value for determining the quality of leakage current, and a value of 1×10 ⁻⁴ A/mm or more indicates leakage. From the results shown in FIGS. 3 and 5, the values of -Ig at Vgd of 100V are shown in Table 1, and the values of -Ig at Vgd of 20V are shown in Table 2, respectively. In Tables 1 and 2, "leak" means that the gate leak current value was 1×10 ⁻⁴ A/mm or more.

・3-terminal measurement In a semiconductor device with a HEMT structure, a reverse bias of 10 V is applied between the gate electrode and the source electrode, and a forward bias is applied between the source electrode and the drain electrode to measure the 3-terminal breakdown voltage characteristics. evaluated. The HEMT element was closely attached to the temperature variable stage by vacuum suction. The temperature variable stage temperature was changed to 300K, 400K, 500K, or 600K, and the three-terminal breakdown voltage characteristics at each temperature were evaluated. The results of Example 1 are shown in FIG. 4, and the results of Comparative Example 1 are shown in FIG. 6, respectively. Vds represents a bias value between the source electrode and drain electrode, and Id represents a drain leakage current.
In the measurement, 1×10 ⁻³ A/mm was used as the cutoff current. The cutoff current is a threshold value for determining the quality of leakage current, and a value of 1×10 ⁻³ A/mm or more indicates leakage. From the results shown in FIGS. 4 and 6, Table 3 shows the Id values when Vds is 100V, and Table 4 shows the Id values when Vds is 20V. In Tables 3 and 4, "leak" means that the drain leak current value was 1×10 ⁻³ A/mm or more.

From the results in Table 1, when Vgd is 100 V and the operating temperature is 400 K, the gate leakage current value of the HEMT element of Comparative Example 1 exceeds 2 × 10 ^-5 A/mm, whereas the HEMT element of Example 1 The gate leakage current value of the device was 2×10 ⁻⁵ A/mm or less, which was considerably smaller than that of Comparative Example 1. Furthermore, at operating temperatures of 500K and 600K, the gate leakage current value of the HEMT element of Comparative Example 1 exceeded the cutoff current value and was determined to be a leak, whereas the HEMT element of Example 1 had an operating temperature of 500K. In this case, the gate leakage current value was a small value of less than 1×10 ⁻⁴ A/mm.

From the results in Table 2, when Vgd is 20V and the operating temperature is 400K, the gate leakage current value of the HEMT element of Comparative Example 1 exceeds 1×10 ^-5 A/mm, whereas that of Example 1 The HEMT element had a gate leakage current value of 1×10 ⁻⁵ A/mm or less. Furthermore, at an operating temperature of 500K, the gate leakage current value of the HEMT element of Comparative Example 1 exceeded 4 × 10 ^-5 A/mm, whereas the gate leakage current value of the HEMT element of Example 1 exceeded 4 × 10 -5 A/mm. It became 10 ⁻⁵ A/mm or less. At both operating temperatures of 400K and 500K, the gate leakage current value in the HEMT element of Example 1 was considerably larger than that of Comparative Example 1. Furthermore, at an operating temperature of 600K, the gate leakage current value of the HEMT element of Comparative Example 1 exceeded the cutoff current value and was determined to be a leak, whereas the HEMT element of Example 1 had a gate leakage current value of 1×10 ^-4 The value was small, less than A/mm.

From the results in Table 3, when Vds is 100 V and the operating temperature is 400 K, the drain leakage current value of the HEMT element of Comparative Example 1 was 5 × 10 ^-5 A/mm, while that of the HEMT element of Example 1. The drain leak current value was less than 5×10 ⁻⁵ A/mm, which was smaller than that of Comparative Example 1. Furthermore, at an operating temperature of 500 K, the HEMT device of Comparative Example 1 had a drain leakage current value of more than 5×10 ⁻⁴ A/mm, whereas the HEMT device of Example 1 had a drain leakage current value of more than 5×10 −4 A/mm. It was less than 10 ⁻⁴ A/mm, which was a considerably smaller value than Comparative Example 1. Furthermore, at an operating temperature of 600 K, the drain leak current value of the HEMT element of Comparative Example 1 exceeded the cutoff current value and was determined to be a leak, whereas the HEMT element of Example 1 had a drain leak current value of The value was small, less than 1×10 ⁻³ A/mm.

From the results in Table 4, when Vds is 20V and the operating temperature is 400K, the drain leakage current value of Comparative Example 1 is 3×10 ^{-5 A/mm, whereas the HEMT element of Example 1 has a drain leakage current value of 3×10 −5} A/mm. The current value was less than 3×10 ⁻⁵ A/mm, which was smaller than that of Comparative Example 1. Furthermore, at an operating temperature of 500 K, the drain leak current value of the HEMT element of Comparative Example 1 exceeded 1.5 × 10 ^-4 A/mm, whereas the drain leak current value of the HEMT element of Example 1 exceeded 1.5 × 10 -4 A/mm. It was less than 1.5×10 ⁻⁴ A/mm, which was a considerably smaller value than Comparative Example 1. Furthermore, at an operating temperature of 600 K, the drain leak current value of the HEMT element of Comparative Example 1 exceeded the cutoff current value and was determined to be a leak, whereas the HEMT element of Example 1 had a drain leak current value of The value was small, less than 1×10 ⁻³ A/mm.

Claims (17)

A semiconductor device comprising a substrate, a semiconductor stacked structure, a source electrode, a gate electrode, and a drain electrode,
The semiconductor stacked structure includes a first semiconductor layer made of a first nitride semiconductor formed on the substrate, and a first semiconductor layer formed on the first semiconductor layer and having a band gap smaller than that of the first nitride semiconductor. a second semiconductor layer made of a large second nitride semiconductor;
A semiconductor device having a gate leakage current value of 2×10 ⁻⁵ A/mm or less at an operating temperature of 400 K when a reverse bias of 100 V is applied between the gate electrode and the drain electrode. 2. The semiconductor device according to claim 1, wherein a gate leakage current value at an operating temperature of 500 K is less than 1×10 ⁻⁴ A/mm when a reverse bias of 100 V is applied between the gate electrode and the drain electrode. . A semiconductor device comprising a substrate, a semiconductor stacked structure, a source electrode, a gate electrode, and a drain electrode,
The semiconductor stacked structure includes a first semiconductor layer made of a first nitride semiconductor formed on the substrate, and a first semiconductor layer formed on the first semiconductor layer and having a band gap smaller than that of the first nitride semiconductor. a second semiconductor layer made of a large second nitride semiconductor;
A semiconductor device having a gate leakage current value of 1×10 ⁻⁵ A/mm or less at an operating temperature of 400 K when a reverse bias of 20 V is applied between the gate electrode and the drain electrode. 4. The semiconductor device according to claim 3, wherein a gate leakage current value at an operating temperature of 500 K is 4×10 ⁻⁵ A/mm or less when a reverse bias of 20 V is applied between the gate electrode and the drain electrode. . 5. The method according to claim 3, wherein a gate leakage current value at an operating temperature of 600 K is less than 1×10 ⁻⁴ A/mm when a reverse bias of 20 V is applied between the gate electrode and the drain electrode. Semiconductor equipment. A semiconductor device comprising a substrate, a semiconductor stacked structure, a source electrode, a gate electrode, and a drain electrode,
The semiconductor stacked structure includes a first semiconductor layer made of a first nitride semiconductor formed on the substrate, and a first semiconductor layer formed on the first semiconductor layer and having a band gap smaller than that of the first nitride semiconductor. a second semiconductor layer made of a large second nitride semiconductor;
When a reverse bias of 10 V is applied between the gate electrode and the source electrode and a forward bias of 100 V is applied between the source electrode and the drain electrode, the drain leak current value at an operating temperature of 400 K is 5. A semiconductor device having a power consumption of less than ×10 ⁻⁵ A/mm. When a reverse bias of 10 V is applied between the gate electrode and the source electrode and a forward bias of 100 V is applied between the source electrode and the drain electrode, the drain leak current value at an operating temperature of 500 K is 5. 7. The semiconductor device according to claim 6, wherein the semiconductor device has an electric current of less than ×10 ⁻⁴ A/mm. When a reverse bias of 10 V is applied between the gate electrode and the source electrode and a forward bias of 100 V is applied between the source electrode and the drain electrode, the drain leak current value at an operating temperature of 600 K is 1. The semiconductor device according to claim 6 or 7, wherein the semiconductor device has an electric current of less than ×10 ⁻³ A/mm. A semiconductor device comprising a substrate, a semiconductor stacked structure, a source electrode, a gate electrode, and a drain electrode,
The semiconductor stacked structure includes a first semiconductor layer made of a first nitride semiconductor formed on the substrate, and a first semiconductor layer formed on the first semiconductor layer and having a band gap smaller than that of the first nitride semiconductor. a second semiconductor layer made of a large second nitride semiconductor;
When a reverse bias of 10 V is applied between the gate electrode and the source electrode and a forward bias of 20 V is applied between the source electrode and the drain electrode, the drain leak current value at an operating temperature of 400 K is 3. A semiconductor device having a power consumption of less than ×10 ⁻⁵ A/mm. When a reverse bias of 10 V is applied between the gate electrode and the source electrode and a forward bias of 20 V is applied between the source electrode and the drain electrode, the drain leak current value at an operating temperature of 500 K is 1. 10. The semiconductor device according to claim 9, wherein the semiconductor device has an electric current of .5×10 ⁻⁴ A/mm or less. When a reverse bias of 10 V is applied between the gate electrode and the source electrode and a forward bias of 20 V is applied between the source electrode and the drain electrode, the drain leak current value at an operating temperature of 600 K is 1. The semiconductor device according to claim 9 or 10, wherein the semiconductor device has a conductivity of less than ×10 ⁻³ A/mm. The first nitride semiconductor includes GaN,
10. The semiconductor device according to claim 1, wherein the second nitride semiconductor includes Al _x Ga _1-x N (0<x<1). The semiconductor device according to claim 1, wherein the substrate is a GaN substrate. 14. The semiconductor device according to claim 13, wherein the resistivity of the GaN substrate at 400K is 1×10 ⁷ Ωcm or more. 14. The semiconductor device according to claim 13, wherein the GaN substrate has a resistivity of 1×10 ⁶ Ωcm or more at 500K. 14. The semiconductor device according to claim 13, wherein the GaN substrate has a resistivity of 1×10 ⁵ Ωcm or more at 600K. 14. The semiconductor device according to claim 13, wherein the GaN substrate is a C-doped GaN substrate.

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