JP2024008506A - signal conversion circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress reduction in the degree of freedom of design.

SOLUTION: Disclosed is a signal conversion circuit for converting a first signal and a second signal constituting a differential signal into a single-ended third signal, which includes; a transformer in which a first signal is inputted to one end of a primary winding, a second signal is inputted to the other end of the primary winding, a third signal having the same polarity as that of the first signal is outputted from one end of a secondary winding, and the other end of the secondary winding is electrically connected to a reference potential; a first capacitor electrically connected between one end of the primary winding and the reference potential; and a negative capacitance electrically connected between the other end of the primary winding and one end of the secondary winding.

SELECTED DRAWING: Figure 2

COPYRIGHT: (C)2024,JPO&INPIT

Description

The present invention relates to a signal conversion circuit that converts a differential signal into a single-ended signal.

When using a transformer to convert a differential signal output from a power amplifier etc. into a single-ended signal, the differential signal may be input to the Asymmetry occurs in the input impedance at both ends of the primary winding.

As a related technique, in FIG. 6 of Patent Document 1 below and its explanation, when converting a single-ended signal into a differential signal, due to the parasitic capacitance between the primary winding and the secondary winding, It has been shown that asymmetry occurs in the primary winding.

In FIG. 7 of Patent Document 1 and its explanation, in order to solve the above-mentioned asymmetry, the center tap of the primary winding is grounded, a signal is input to one end of the primary winding, and the primary winding It is described that the other end is floating.

Patent No. 2938082

As described above, Patent Document 1 describes a transformer configuration technique that reduces the influence of parasitic capacitance. However, in the technique described in Patent Document 1, it is necessary to design the transformer including parasitic capacitance. Therefore, the technique described in Patent Document 1 has a problem in that the degree of freedom in design is reduced, such as not being able to obtain a sufficiently large conversion ratio of impedance.

The present invention has been made in view of the above, and an object of the present invention is to suppress a decrease in the degree of freedom of design.

A signal conversion circuit according to one aspect of the present invention is a signal conversion circuit that converts a first signal and a second signal forming a differential signal into a single-ended third signal, and includes a first signal connected to one end of a primary winding. A signal is input, a second signal is input to the other end of the primary winding, a third signal with the same polarity as the first signal is output from one end of the secondary winding, and the other end of the secondary winding is the reference signal. a transformer electrically connected to a potential; a first capacitor electrically connected between one end of the primary winding and a reference potential; and the other end of the primary winding and one end of the secondary winding. and a negative capacitance electrically connected between the negative capacitor and the negative capacitor.

According to the present invention, it is possible to suppress a decrease in the degree of freedom in design.

FIG. 1 is a diagram showing the configuration of a signal conversion circuit of a comparative example. FIG. 2 is a diagram illustrating the principle of the signal conversion circuit of the present disclosure. FIG. 3 is a diagram showing the configuration of the signal conversion circuit according to the first embodiment. FIG. 4 is a schematic plan view of a signal conversion circuit according to the second embodiment. FIG. 5 is a diagram showing the configuration of a signal conversion circuit according to the third embodiment. FIG. 6 is a diagram showing the configuration of the negative capacitance circuit of the signal conversion circuit according to the third embodiment. FIG. 7 is a diagram showing the configuration of a negative capacitance circuit according to the fourth embodiment. FIG. 8 is a diagram showing the configuration of a negative capacitance circuit according to the fifth embodiment.

Embodiments of the signal conversion circuit of the present invention will be described in detail below with reference to the drawings. Note that the present invention is not limited to this embodiment. It goes without saying that each embodiment is an example, and that parts of the configurations shown in different embodiments can be replaced or combined.

<Principle of the present disclosure and comparative examples>
The principle of the present disclosure will be described below, but in order to facilitate understanding of the principle of the present disclosure, a comparative example will be described first.

(Comparative example)
FIG. 1 is a diagram showing the configuration of a signal conversion circuit of a comparative example.

The signal conversion circuit 201 converts a first input signal 21 and a second input signal 22 forming a differential signal into a single-ended output signal 23.

Amplifier 31 includes a transistor 41 . The transistor 41 outputs the first input signal 21 of the first polarity from its collector or drain to the first input terminal IN+ of the signal conversion circuit 201. The first polarity is exemplified by positive polarity, but the present disclosure is not limited thereto.

Amplifier 32 includes a transistor 42 . The transistor 42 outputs the second input signal 22 of the second polarity from its collector or drain to the second input terminal IN- of the signal conversion circuit 201. The second polarity is exemplified by negative polarity, but the present disclosure is not limited thereto.

It is assumed that the first input signal 21 and the second input signal 22 have the same amplitude and opposite phases (180 degree phase difference).

Signal conversion circuit 201 includes transformer 10 . The transformer 10 includes a first winding 11 and a second winding 12. The first winding 11 and the second winding 12 are electromagnetically coupled.

One end 11a of the first winding 11 is electrically connected to the first input terminal IN+. The other end 11b of the first winding 11 is electrically connected to the second input terminal IN-.

The center tap 11c of the first winding 11 is electrically connected to the high potential side end of the DC power supply 51. A low potential side end of the DC power supply 51 is electrically connected to a reference potential. The reference potential is exemplified by a ground potential, but the present disclosure is not limited thereto.

Although the DC power supply 51 applies a bias voltage to the collectors or drains of the transistors 41 and 42 via the first winding 11, the present disclosure is not limited thereto. A bias voltage may be applied to the collectors or drains of the transistors 41 and 42, respectively, not through the first winding 11 but through a choke coil (not shown).

One end 12a of the second winding 12 is electrically connected to the output terminal OUT of the signal conversion circuit 201. The other end 12b of the second winding 12 is electrically connected to a reference potential.

A single-ended output signal 23 is output from the output terminal OUT. The polarity of the output signal is the first polarity. The amplitude of the output signal 23 is relatively large compared to the first input signal 21 and the second input signal 22.

The transformer 10 is configured by winding a first winding 11 and a second winding 12 together. Therefore, a parasitic capacitance _CP1 is generated between one end 11a of the first winding 11 and one end 12a of the second winding 12. A parasitic capacitance _CP2 is generated between the other end 11b of the first winding 11 and the other end 12b of the second winding 12.

The voltage waveforms at one end 12a and the other end 12b of the second winding 12 are different. Therefore, asymmetry in operation appears between the first input terminal IN+ side and the second input terminal IN- side.

That is, the side of the first input terminal IN+ is influenced by the output signal 23 via the parasitic capacitance _CP1 . On the other hand, on the side of the second input terminal IN-, a parasitic capacitor _CP2 is added as a load, but the parasitic capacitor _CP2 is connected to the reference potential and is not affected by the output signal 23.

This causes the input impedance of the first input terminal IN+ to be different from the input impedance of the second input terminal IN-. In other words, the load impedance of transistor 41 and the load impedance of transistor 42 are different.

Therefore, the first input signal 21 and the second input signal 22 may have different amplitudes or a phase difference of 180°. Alternatively, the signal waveform of the first input signal 21 or the second input signal 22 may be disturbed.

(Principle of this disclosure)
FIG. 2 is a diagram illustrating the principle of the signal conversion circuit of the present disclosure.

Compared to the signal conversion circuit 201 (see FIG. 1), the signal conversion circuit 1 includes a capacitance C _a and a negative capacitance -C _b . Here, C _a >0 and -C _b <0. Note that although negative capacitance is described using the symbol of capacitance in FIG. 1, it is only shown as a capacitance for convenience, and is not actually constituted by a capacitive element. For example, as will be described later, there are circuits made of synthesized transistors, and circuits constructed using materials such as hafnium dioxide.

One end of the capacitor _Ca is electrically connected to the amplifier 31 and the first input terminal IN+. The other end of the capacitor _Ca is electrically connected to a reference potential.

One end of the negative capacitance _-Cb is electrically connected to the second input terminal IN- and the other end 11b of the first winding 11. The other end of the negative capacitor _-Cb is electrically connected to one end 12a of the second winding 12 and the output terminal OUT.

Here, the angular frequency of the first input signal 21, the second input signal 22, and the output signal 23 is ω, the voltage of the first input signal 21 is V ₁ , the voltage of the second input signal 22 is −V ₁ , Let the voltage of the output signal 23 be aV ₁ . a is a positive number.

The voltage across the parasitic capacitance C _P1 is V ₁ (1-a). Therefore, the current _I11 flowing through the parasitic capacitance C _P1 is expressed by the following equation (1).
I ₁₁ =V ₁ (1-a)ωC _P1 ...(1)

The voltage across the parasitic capacitance C _P2 is −V ₁ . Therefore, the current _I22 flowing through the parasitic capacitance _CP2 is expressed by the following equation (2).
I ₂₂ =-V ₁ ωC _P2 ...(2)

The present disclosure takes the following two measures to eliminate asymmetry.

As a first measure, one end of the capacitor _Ca is electrically connected to the first input terminal IN+. The other end of the capacitor _Ca is electrically connected to a reference potential.

The value of the capacitance C _a is set to be approximately the same as the value of the parasitic capacitance C _P2 (for example, this also includes the case where the value of the capacitance C _a has a difference within ±30% compared to the value of the capacitance C _p2 ).

The voltage across capacitance C _a is V ₁ . Therefore, the current I ₁₂ flowing through the capacitor _Ca is expressed by the following equation (3).
I ₁₂ =V ₁ ωC _a
=V ₁ ωC _P2 ...(3)

Referring to equations (2) and (3), the polarity of current I ₁₂ is reversed compared to current I ₂₂ , and current I ₁₂ and current I ₂₂ are symmetrical.

As a second measure, a negative capacitor -C _b having a negative capacitance is electrically connected between the second input terminal IN- and the output terminal OUT.

The voltage across the capacitor -C _b is -V ₁ (1+a). Therefore, the current I ₂₁ flowing through the capacitor -C _b is expressed by the following equation (4).
I ₂₁ =V ₁ (1+a)ωC _b ...(4)

The value of negative capacitance -C _b is set so that the following equation (5) holds true.
C _b = ((a-1)/(a+1)) C _P1 ...(5)

By substituting equation (5) into equation (4), the following equation (6) is obtained.
I ₂₁ =V ₁ (1+a)ωC _b
=V ₁ (1+a)ω((a-1)/(a+1))C _P1
=V ₁ (a-1)ωC _P1
=-V ₁ (1-a)ωC _P1 ...(6)

Referring to equations (1) and (6), the polarity of current I ₂₁ is reversed compared to current I ₁₁ , and current I ₂₁ and current I ₁₁ are symmetrical.

As described above, the present disclosure can eliminate the asymmetry caused by the parasitic capacitance C _P1 and the parasitic capacitance C _P2 by adding the capacitance C _a and the negative capacitance −C _b . As a result, the present disclosure can maintain the symmetry of the input impedances of the first input terminal IN+ and the second input terminal IN-, and can maintain the symmetry of the load impedances of the amplifiers 31 and 32.

<First embodiment>
FIG. 3 is a diagram showing the configuration of the signal conversion circuit according to the first embodiment.

Compared to the signal conversion circuit 1 (see FIG. 2), the signal conversion circuit 1A includes an inductor L _a as an example of negative capacitance -C _b .

In the signal conversion circuit 1A, the asymmetry is eliminated by using an inductor L _a that can easily realize negative capacitance -C _b .

Comparing the impedances of negative capacitance -C _b and inductor L _a , the following equation (7) is obtained.
jωL _a =j/(ωC _b )...(7)

That is, by setting the value of the inductor L _a as shown in the following equation (8), the asymmetry can be eliminated at each angular frequency ω.
L _a =1/(ω ² C _b )...(8)

Although the signal conversion circuit 1A has frequency dependence, it is possible to eliminate the asymmetry of the load impedances of the amplifiers 31 and 32 without using the negative capacitance -C _b .

<Second embodiment>
Among the constituent elements of the second embodiment, the same constituent elements as those of the first embodiment are given the same reference numerals, and a description thereof will be omitted.

FIG. 4 is a schematic plan view of a signal conversion circuit according to the second embodiment.

The second embodiment is a specific example in which the signal conversion circuit 1A (see FIG. 3) is arranged on a plane when applied to an output matching circuit of a power amplifier.

The signal conversion circuit 1A is formed on a substrate 61. Although the first winding 11 and the second winding 12 are formed in different layers of the substrate 61, the present disclosure is not limited thereto. The first winding 11 and the second winding 12 may be formed on the same layer of the substrate 61.

The first input terminal IN+ and the second input terminal IN- of the first winding 11 are formed on the left side in FIG. The first winding 11 has a substantially circular shape. The center tap 11c of the first winding 11 is located at the right end of the first winding 11 in FIG. A bias voltage is input from the DC power supply 51 to the center tap 11c.

The output terminal OUT of the second winding 12 is formed on the right side in FIG. The second winding 12 makes approximately one circuit around the inside of the first winding 11, then straddles the first winding 11 and makes approximately one circuit around the outside of the first winding. The other end of the second winding 12 is electrically connected to a reference potential.

A current 71 flowing through the first winding 11 and a current 72 flowing through the second winding 12 flow in a direction in which the directions of the magnetic fields of the first winding 11 and the second winding 12 are common.

In an output matching circuit, the output impedance (for example, 50Ω) is often larger than the load impedance. Therefore, the inductance value of the second winding 12 is often larger than the inductance value of the first winding 11.

The capacitor C _a and the inductor L _a are, for example, SMDs (Surface Mount Devices), but the present disclosure is not limited thereto.

Although the capacitor C _a is exemplified as being placed near the first input terminal IN+, the present disclosure is not limited thereto. For example, the distance between the capacitor C _a and the first input terminal IN+ is exemplified as being shorter than the distance between the other components and the first input terminal IN+.

The inductance value of the inductor _La is often a relatively large value. For example, the signal frequency is 1.85 GHz (gigahertz), the turns ratio of the second winding 12 and the first winding 11 is 2:1, and C _P1 = C _P2 = C _a = 1.0 pF (picofarad). ), the inductance value of the inductor _La is 15.5 nH (nanoHenry). Therefore, the inductor L _a can be designed including the inductance value of the wiring 62 and the wiring 63 connected in series.

In the second embodiment, the signal conversion circuit 1A of the first embodiment can be realized on the substrate 61, and the circuit can be physically realized.

<Third embodiment>
Among the constituent elements of the third embodiment, the same constituent elements as those of the other embodiments are given the same reference numerals and the explanation thereof will be omitted.

FIG. 5 is a diagram showing the configuration of a signal conversion circuit according to the third embodiment.

Compared to the signal conversion circuit 1 (see FIG. 2), the signal conversion circuit 1B includes a negative capacitance circuit 81 as an example of negative capacitance -C _b . The negative capacitance circuit 81 is an active negative capacitance circuit realized using active elements (transistors).

The first terminal 81a and the second terminal 81b of the negative capacitance circuit 81 are electrically connected to the power supply potential VCC and have a DC level, as will be explained later. Therefore, a DC cut capacitor _CDC is provided between the second input terminal IN- and the first terminal 81a. Note that a DC cut capacitor _CDC2 may be added to the output side as well, if necessary.

FIG. 6 is a diagram showing the configuration of the negative capacitance circuit of the signal conversion circuit according to the third embodiment.

Negative capacitance circuit 81 includes a resistor 91 and a resistor 92, a transistor 93 and a transistor 94, a capacitor 95, and a constant current source 96 and a constant current source 97.

Although transistor 93 and transistor 94 are bipolar transistors, the present disclosure is not limited thereto. The transistor 93 and the transistor 94 may be FETs (Field Effect Transistors). When the transistors 93 and 94 are FETs, the source corresponds to the emitter, the gate corresponds to the base, and the drain corresponds to the collector.

Although the resistance value of the resistor 91 and the resistance value of the resistor 92 are assumed to be the same, the present disclosure is not limited thereto. Although the electrical characteristics of the transistor 93 and the electrical characteristics of the transistor 94 are assumed to be the same, the present disclosure is not limited thereto. Although it is assumed that the current value of constant current source 96 and the current value of constant current source 97 are the same, the present disclosure is not limited thereto.

The resistance values of the resistor 91 and the resistor 92 are set based on the power supply potential VCC, the electrical characteristics of the transistor 93 and the transistor 94, and the like.

One end of resistor 91 is electrically connected to power supply potential VCC. The other end of the resistor 91 is electrically connected to the first terminal 81a, the collector of the transistor 93, and the base of the transistor 94.

One end of resistor 92 is electrically connected to power supply potential VCC. The other end of the resistor 92 is electrically connected to the second terminal 81b, the collector of the transistor 94, and the base of the transistor 93.

The base of the transistor 93 is electrically connected to the second terminal 81b. The base of the transistor 94 is electrically connected to the first terminal 81a.

One end of capacitor 95 is electrically connected to the emitter of transistor 93. The other end of capacitor 95 is electrically connected to the emitter of transistor 94.

Constant current source 96 is electrically connected between the emitter of transistor 93 and a reference potential.

Constant current source 97 is electrically connected between the emitter of transistor 94 and a reference potential.

The DC level of the first terminal 81a is the level obtained by subtracting the voltage drop across the resistor 91 from the power supply potential VCC. Similarly, the DC level of the second terminal 81b is the level obtained by subtracting the voltage drop across the resistor 92 from the power supply potential VCC.

In terms of direct current, the transistor 93 is supplied with a collector bias voltage and a base bias voltage, and a collector current I ₃₁ and an emitter current I ₃₂ flow therethrough. Similarly, the transistor 94 is supplied with a collector bias voltage and a base bias voltage in terms of direct current, and a collector current I ₄₁ and an emitter current I ₄₂ flow therethrough.

The operation of the negative capacitance circuit 81 when the voltage at the first terminal 81a decreases in an alternating current manner and the voltage at the second terminal 81b increases in an alternating current manner will be described.

Since the base voltage of the transistor 93 increases, the collector current I ₃₁ and the emitter current I ₃₂ increase. On the other hand, since the base voltage of the transistor 94 decreases, the collector current I ₄₁ and the emitter current I ₄₂ decrease.

An increased amount of emitter current I ₃₂ flows through capacitor 95 to constant current source 97 .

The current flowing in alternating current from the first terminal 81a increases because the collector current _I31 increases. The current flowing in alternating current from the second terminal 81b decreases because the collector current _I41 decreases.

When the voltage at the first terminal 81a increases in an alternating current manner and the voltage at the second terminal 81b decreases in an alternating current manner, the operation of the negative capacitance circuit 81 is opposite to that described above.

When an inductor L _a is used instead of a negative capacitance, ω _c L _a =1/(ω _c C _b ) holds only at a certain angular frequency ω _c . In comparison, using the transistor 93 and the transistor 94 allows operation over a wide band. Therefore, the negative capacitance circuit 81 can realize a negative capacitance with a wider band than the inductor _La .

Thereby, the signal conversion circuit 1B can eliminate asymmetry over a wide band compared to the signal conversion circuit 1 and the signal conversion circuit 1A.

<Fourth embodiment>
Among the constituent elements of the fourth embodiment, the same constituent elements as those of the other embodiments are given the same reference numerals and the explanation thereof will be omitted.

FIG. 7 is a diagram showing the configuration of a negative capacitance circuit according to the fourth embodiment.

The negative capacitance circuit 81A includes a transistor 98 and a transistor 99 instead of the resistor 91 and the resistor 92, compared to the negative capacitance circuit 81 (see FIG. 6).

Although transistor 98 and transistor 99 are bipolar transistors, the present disclosure is not limited thereto. Transistor 98 and transistor 99 may be FETs.

Although the electrical characteristics of transistor 98 and the electrical characteristics of transistor 99 are assumed to be the same, the present disclosure is not limited thereto.

A collector of transistor 98 is electrically connected to power supply potential VCC. The base of the transistor 98 is electrically connected to the second terminal 81b. The emitter of transistor 98 is electrically connected to the base of transistor 93. In other words, transistor 98 is connected as an emitter follower.

A collector of transistor 99 is electrically connected to power supply potential VCC. The base of the transistor 99 is electrically connected to the first terminal 81a. The emitter of transistor 99 is electrically connected to the base of transistor 94. In other words, transistor 99 is connected as an emitter follower.

Compared to the negative capacitance circuit 81, the negative capacitance circuit 81A includes a transistor 98 and a transistor 99 that are connected as emitter followers, so that the maximum allowable voltage of the voltage input to the first terminal 81a and the second terminal 81b is reduced. The amplitude can be increased. Note that the resistors 91 and 92 shown in FIG. 6 are omitted here. If an appropriate DC bias is applied to the first terminal 81a and the second terminal 81b, the resistors 91 and 92 can be omitted.

<Fifth embodiment>
Among the constituent elements of the fifth embodiment, the same constituent elements as those of the other embodiments are given the same reference numerals and the explanation thereof will be omitted.

FIG. 8 is a diagram showing the configuration of a negative capacitance circuit according to the fifth embodiment.

Negative capacitance circuit 81B includes a transistor 101 and a transistor 102 instead of resistor 91 and resistor 92 and transistor 93 and transistor 94, compared to negative capacitance circuit 81 (see FIG. 6). Transistor 101 and transistor 102 are FETs.

Although the electrical characteristics of the transistor 101 and the electrical characteristics of the transistor 102 are the same, the present disclosure is not limited thereto.

The drain of the transistor 101 is electrically connected to the first terminal 81a. The gate of the transistor 101 is electrically connected to the second terminal 81b. A source of the transistor 101 is electrically connected to one end of a capacitor 95 and a constant current source 96.

The drain of the transistor 102 is electrically connected to the second terminal 81b. A gate of the transistor 102 is electrically connected to the first terminal 81a. A source of the transistor 102 is electrically connected to the other end of the capacitor 95 and a constant current source 97.

In this way, the negative capacitance circuit 81B can be realized using FETs as active elements. Note that the resistors 91 and 92 shown in FIG. 6 are omitted here. If an appropriate DC bias is applied to the first terminal 81a and the second terminal 81b, the resistors 91 and 92 can be omitted.

<Additional notes>
In the third to fifth embodiments, active elements (transistors) are used to realize negative capacitance circuits, but the present disclosure is not limited thereto. A negative capacitance circuit can also be realized using a material having negative capacitance characteristics, such as HfO ₂ (hafnium dioxide).

<Configuration example of the present disclosure>
The present disclosure can also have the following configuration.

(1)
A signal conversion circuit that converts a first signal and a second signal forming a differential signal into a single-ended third signal,
A first signal is input to one end of the primary winding, a second signal is input to the other end of the primary winding, and a third signal having the same polarity as the first signal is output from one end of the secondary winding. a transformer in which the other end of the secondary winding is electrically connected to a reference potential;
a first capacitor electrically connected between one end of the primary winding and a reference potential;
a negative capacitor electrically connected between the other end of the primary winding and one end of the secondary winding;
including,
Signal conversion circuit.

(2)
The signal conversion circuit according to (1) above,
Negative capacitance is an inductor,
Signal conversion circuit.

(3)
The signal conversion circuit according to (1) above,
The negative capacity is
An active negative capacitance circuit including an active element,
Signal conversion circuit.

(4)
The signal conversion circuit according to (3) above,
Active negative capacitance circuit is
a first transistor whose collector or drain is electrically connected to a first terminal and whose base or gate is electrically connected to a second terminal;
a second transistor whose collector or drain is electrically connected to the second terminal and whose base or gate is electrically connected to the first terminal;
a first constant current source electrically connected to the emitter or source of the first transistor;
a second constant current source electrically connected to the emitter or source of the second transistor;
a second capacitor electrically connected between the emitter or source of the first transistor and the emitter or source of the second transistor;
including,
Signal conversion circuit.

(5)
The signal conversion circuit according to (4) above,
Active negative capacitance circuit is
a third transistor whose emitter or source is electrically connected to the base or gate of the first transistor, whose base or gate is electrically connected to the second terminal, and whose collector or drain is electrically connected to the power supply potential;
a fourth transistor whose emitter or source is electrically connected to the base or gate of the second transistor, whose base or gate is electrically connected to the first terminal, and whose collector or drain is electrically connected to the power supply potential;
further including;
Signal conversion circuit.

Note that the above-described embodiments are intended to facilitate understanding of the present invention, and are not intended to be interpreted as limiting the present invention. The present invention may be modified/improved without departing from its spirit, and the present invention also includes equivalents thereof.

1, 201 Signal conversion circuit 10 Transformer 11 First winding 12 Second winding 31, 32 Amplifier 41, 42, 93, 94, 98, 99, 101, 102 Transistor 51 DC power supply 61 Substrate 81 Negative capacitance circuit 91, 92 Resistor 95 Capacitor 96, 97 Constant current source _CP1 , _CP2 Parasitic capacitance C _a capacitance -C _b negative capacitance L _a inductor

Claims (5)

A signal conversion circuit that converts a first signal and a second signal forming a differential signal into a single-ended third signal,
The first signal is input to one end of the primary winding, the second signal is input to the other end of the primary winding, and the third signal of the same polarity as the first signal is input from one end of the secondary winding. a transformer to which a signal is output and the other end of the secondary winding is electrically connected to a reference potential;
a first capacitor electrically connected between one end of the primary winding and a reference potential;
a negative capacitor electrically connected between the other end of the primary winding and one end of the secondary winding;
including,
Signal conversion circuit. The signal conversion circuit according to claim 1,
the negative capacitance is an inductor;
Signal conversion circuit. The signal conversion circuit according to claim 1,
The negative capacitance is
An active negative capacitance circuit including an active element,
Signal conversion circuit. The signal conversion circuit according to claim 3,
The active negative capacitance circuit is
a first transistor whose collector or drain is electrically connected to a first terminal and whose base or gate is electrically connected to a second terminal;
a second transistor whose collector or drain is electrically connected to the second terminal and whose base or gate is electrically connected to the first terminal;
a first constant current source electrically connected to the emitter or source of the first transistor;
a second constant current source electrically connected to the emitter or source of the second transistor;
a second capacitor electrically connected between the emitter or source of the first transistor and the emitter or source of the second transistor;
including,
Signal conversion circuit. The signal conversion circuit according to claim 4,
The active negative capacitance circuit is
A third transistor whose emitter or source is electrically connected to the base or gate of the first transistor, whose base or gate is electrically connected to the second terminal, and whose collector or drain is electrically connected to the power supply potential. and,
A fourth transistor whose emitter or source is electrically connected to the base or gate of the second transistor, whose base or gate is electrically connected to the first terminal, and whose collector or drain is electrically connected to the power supply potential. and,
further including;
Signal conversion circuit.

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