JP2023523677A - Sidewall Notch Reduction for High Aspect Ratio 3D NAND Etch - Google Patents

Abstract

A method and apparatus are provided for etching high aspect ratio features in a stack on a substrate. Features may be formed in a process that forms a 3D NAND device. Stacks typically include alternating layers of materials such as silicon oxide and silicon nitride or silicon oxide and polysilicon. WF6 is provided in the etch chemistry, which substantially reduces or eliminates the problematic sidewall notch. Advantageously, this sidewall notch improvement provides other tradeoffs such as increased curvature, decreased selectivity, increased capping, or decreased etch rate. no. [Selection drawing] Fig. 3

Description

INCORPORATION BY REFERENCE A PCT request form is filed herewith as part of this application. Each application to which this application claims the benefit or priority to which it is set forth in the concurrently filed PCT request form is hereby incorporated by reference in its entirety for all purposes.

Embodiments herein relate to methods and apparatus for manufacturing semiconductor devices and, more particularly, to reduce sidewall notches and etch high aspect ratio features in dielectric-containing materials without profile trade-offs. It relates to a method and apparatus.

One process frequently used in the fabrication of semiconductor devices is the formation of etched cylinders or other recessed features in stacks of dielectric-containing materials. For example, such processes are widely used in memory applications such as the fabrication of 3D NAND (also called vertical NAND or V-NAND) structures. As the semiconductor industry advances and device dimensions shrink, it becomes increasingly difficult to etch such features uniformly, especially for high aspect ratio cylinders that are narrow and/or deep. ing.

The background information provided herein is for the purpose of generally presenting the context of the present disclosure. To the extent set forth in this Background section, the presently specified inventor's work, and aspects of the description that may not qualify as prior art at the time of filing, are expressly or implicitly incorporated by reference into this disclosure. is not admitted to be prior art against

Certain embodiments herein relate to methods and apparatus for etching features in stacks containing dielectric materials. Typically, features are etched into the stack during fabrication of 3D NAND structures on the substrate.

In one aspect of the embodiments herein, a method is provided for etching features in a stack including a dielectric material in fabricating a 3D NAND structure, the method comprising: A substrate is received, the substrate including a stack and a mask layer patterned on top of the stack, the stack comprising (a) alternating layers of silicon oxide and silicon nitride, or (b) silicon oxide and poly. exposing the substrate to a plasma in a reaction chamber to thereby etch features in the stack on the substrate, the plasma containing any of the alternating layers with silicon, the plasma containing _WF6 , one or more fluorocarbons; and/or a hydrofluorocarbon, and a plasma-generating gas comprising one or more oxidants, the flow rate of _WF6 is about 0.1-10 sccm, the plasma is a capacitively coupled plasma, and the substrate has a frequency of about 20 kHz to Biased at a frequency of 1.5 MHz and an RF power level of about 500 W to 20 kW per substrate, the WF ₆ and fluorocarbons and/or hydrofluorocarbons form a tungsten-based polymer film on the sidewalls of the features during the etching process. The polymer film promotes a uniform etch rate between alternating layers of silicon oxide and silicon nitride or between alternating layers of silicon oxide and polysilicon to prevent feature sidewall notching during the etching process. .

In certain embodiments, during the etching process, _WF6 may dissociate into tungsten-containing fragments and fluorine-containing fragments, where the tungsten-containing fragments are relatively high near the top of the feature compared to the fluorine-containing fragments. Remaining concentrated, the fluorine-containing fraction penetrates deeper into the feature compared to the tungsten-containing fraction. In some such embodiments, the tungsten-based polymer film is such that the tungsten-based polymer film near the top of the feature has a greater percentage of tungsten as compared to the tungsten-based polymer film near the bottom of the feature. Additionally, there is compositional non-uniformity along the sidewalls of the feature.

In some cases, specific conditions may be used in the process. For example, the plasma may be generated with an excitation frequency of approximately 20 MHz to 100 MHz and an RF power of approximately 6.3 kW or less. In these cases or other cases, the oxidant may be O ₂ and the flow rate of O ₂ may be about 20-150 sccm. In these cases or other cases, the plasma-generating gas may further include SF ₆ and the flow rate of SF ₆ may be between about 1-20 sccm. In these cases or other cases, the plasma-generating gas may further include Kr, and the flow rate of Kr may be between about 30-120 sccm. In these cases or other cases, the plasma-generating gas may further include _NF3 , and the flow rate of _NF3 may be less than or equal to about 30 sccm. In these instances or other instances, the fluorocarbon or hydrofluorocarbon may include one _or more of _{C4F8 , C3F8 , C4F6} , and _CH2F2 , _{fluorocarbons} and hydrofluorocarbons. The total fluorocarbon flow rate may be about 30-240 sccm. In these cases or other cases, the substrate support may be maintained at a temperature of about 20-80° C. while etching the substrate. In these cases or other cases, the pressure in the reaction chamber may be maintained at about 10-80 mTorr while etching the substrate. In these or other cases, features may be etched in alternating layers of silicon oxide and silicon nitride. In these cases or other cases, the flow rate of WF ₆ may be between about 0.02% and 10% of the total flow rate of the plasma-generating gases. In these cases or other cases, the flow rate of WF ₆ may be between about 0.02% and 1% of the total plasma-generating gas flow rate. In these cases or other cases, the flow rate of WF ₆ may be between about 0.02% and 0.5% of the total flow rate of the plasma-generating gases. In these cases or other cases, the substrate may be biased with an RF frequency of about 300 kHz to 600 kHz. For example, the substrate may be biased with an RF frequency of approximately 400 kHz. In these cases or other cases, the tungsten-based polymer film may be formed on a layer of silicon oxide with a first thickness and formed on a layer of silicon nitride or polysilicon with a second thickness. The thickness is different from the second thickness.

In another aspect of the disclosed embodiments, an apparatus is provided for etching features in a stack including a dielectric material in fabricating a 3D NAND structure on a substrate, the apparatus having a substrate support therein. a chamber, a capacitively coupled plasma generator; an inlet for introducing material into the reaction chamber, and an outlet for removing material from the reaction chamber. and a controller configured to perform any of the methods described herein.

For example, certain aspects of the disclosed embodiments provide an apparatus for etching features in a stack including a dielectric material in fabricating a 3D NAND structure on a substrate, the apparatus including a substrate support therein. a capacitively coupled plasma generator; an inlet for introducing material into the reaction chamber; an outlet for removing material from the reaction chamber; and the substrate includes a stack and a mask layer patterned on top of the stack, the stack comprising (a) alternating layers of silicon oxide and silicon nitride, or (b) silicon oxide and polysilicon and a plasma-generating gas comprising _WF6 , one or more fluorocarbons and/or hydrofluorocarbons, and one or more oxidants, wherein the flow rate of _WF6 is about 0.0. 1-10 sccm, biasing the substrate with an RF power level of about 500 W-20 kW at a frequency of about 20 kHz-1.5 MHz and exposing the substrate to a plasma in the reaction chamber, thereby forming features in the stack on the substrate. Etch and the _WF6 and fluorocarbons and/or hydrofluorocarbons form a tungsten-based polymer film on the sidewalls of the feature during the etching process, the tungsten-based polymer film between alternating layers of silicon oxide and silicon nitride, or a controller configured to promote a uniform etch rate between alternating layers of silicon oxide and polysilicon to prevent sidewalls of the feature from notching during the etching process.

These and other features are described below with reference to the associated drawings.

FIG. 3 shows a stack of alternating materials.

FIG. 2 shows a substantial notch in the sidewall after etching the substrate of FIG. 1;

2 is a view of the substrate of FIG. 1 after etching according to embodiments herein; FIG.

4 is a flow chart illustrating etching methods according to various embodiments herein.

1 is a diagram of a reaction chamber that may be used to perform the etching processes described herein according to certain embodiments; FIG. 1 is a diagram of a reaction chamber that may be used to perform the etching processes described herein according to certain embodiments; FIG. 1 is a diagram of a reaction chamber that may be used to perform the etching processes described herein according to certain embodiments; FIG.

1 and 2 illustrate a substrate 101 including a 3D NAND structure fabricated in part by etching high aspect ratio features 102 into a stack 103 comprising alternating layers of first material 104 and second material 105. FIG. is shown. FIG. 1 shows the structure before etching and FIG. 2 shows the structure after etching the high aspect ratio feature 102 . In one example, the first material is silicon oxide and the second material is silicon nitride. In another example, the first material is silicon oxide and the second material is polysilicon. Alternating layers form material pairs. For clarity, FIGS. 1 and 2 show etched features with only a few material pairs. However, it is understood that the etching operation will typically etch with more material pairs than this. In some cases, the number of material pairs may be at least about 20, at least about 30, at least about 40, at least about 60, or at least about 75. Each layer of stack 103 may have a thickness of about 20-50 nm, for example about 30-40 nm. Overlying the stack 103 is a mask layer 106 . The mask layer 106 is patterned with openings where the high aspect ratio features 102 are to be etched. Examples of mask materials include, but are not limited to amorphous carbon, polysilicon, and other common mask materials. The thickness of the mask layer before etching may be about 1-2.5 μm. The depth of the high aspect ratio features 102 etched into the stack 103 may be about 3-10 μm, such as about 5-10 μm. The width/diameter of the high aspect ratio features 102 may be about 50-150 nm, such as about 60-110 nm. In some cases, the feature width may be about 100 nm or less. The pitch between adjacent features may be about 100-200 nm, such as about 120-170 nm.

A substrate 101, shown in FIG. 1, is prepared in a semiconductor processing apparatus for etching. Suitable devices are described below. After the substrate 101 is introduced into the processing apparatus, plasma is generated within the processing apparatus and the substrate 101 is exposed to the plasma. After a period of time, this plasma exposure etches areas of substrate 101 not protected by mask layer 106, thereby forming high aspect ratio features 102, as shown in FIG. Mask layer 106 is resistant to etching chemistries, but typically undergoes some erosion during the etching process. Therefore, the mask layer 106 shown in FIG. 2 is thinner than the mask layer 106 shown in FIG. When the stack 103 is etched, a passivation layer 107 is formed on the sidewalls of the high aspect ratio features 102 . Passivation layer 107 is a mixed layer formed from the combination of the material of laminate 103 and one or more materials resulting from the etching chemistry. Therefore, the composition of the passivation layer 107 varies depending on the composition of the layer to be formed. For example, the portion of passivation layer 107 forming the sidewalls of a silicon oxide layer typically has a composition including at least silicon, oxygen, and carbon, whereas the portion of passivation layer 107 forming the sidewalls of a silicon nitride layer typically has a composition that includes at least silicon, oxygen, and carbon. Some typically have compositions that include at least silicon, nitrogen, and carbon. Similarly, the portion of passivation layer 107 forming the sidewalls of the polysilicon layer typically has a composition that includes at least silicon and carbon. Often the passivation layer is a fluorocarbon film, which can be a polymer.

Although FIG. 2 shows that the passivation layer 107 is deposited relatively uniformly and uniformly, this may not be the case. In some cases, passivation layer 107 may be concentrated near the top of high aspect ratio features 102 with little or no passivation layer 107 near the bottom of the feature. In some cases, the passivation layer 107 may be unevenly formed between the layer of first material 104 and the layer of second material 105, as discussed further below.

One problem that can arise when etching a stack of alternating layers, as shown in FIG. 2, is non-uniformity in the etch rate between the two different layers. In many cases, silicon oxide materials etch vertically faster than silicon nitride or polysilicon materials. Such a high vertical etch rate of the oxide material results in relatively little horizontal etching of the oxide layer. In contrast, the nitride layer etches slowly in the vertical direction and widely in the horizontal direction. As a result of this etch rate mismatch, the sidewalls of the silicon nitride material (or polysilicon material) can form over-etched regions, thereby becoming notched (notched). ) becomes a certain side wall. In the example of FIG. 2, a layer of first material 104 (eg, silicon oxide) is laterally etched less than a layer of second material 105 (eg, silicon nitride or polysilicon). Over time, this non-uniform etch results in notched sidewalls as shown in FIG. This notch is undesirable. Although not shown in FIG. 2, notches can cause significant ion scattering, which can lead to the formation of large bows (e.g., the central portion of the feature is overetched compared to the top of the feature). (if any). Notches can also adversely affect the dielectric properties of the laminate material.

Although FIG. 2 shows each layer of stack 103 as having vertical sidewalls, this is not necessarily the case. In various implementations, a horizontally overetched layer of material (e.g., silicon nitride in a stack of oxide and nitride, or polysilicon in a stack of oxide and polysilicon) is removed from the top of the layer. The largest overetch in the vicinity creates an undercut just below the other layers of material. The bottom portion of the overetched layer may be less overetched or may not be overetched at all. As such, the sidewalls of the overetched layer may be slanted, curved, or non-vertical.

While not wishing to be bound by theory or mechanism of action, it is believed that sidewall notches may be caused by uneven formation of passivation layer 107 on different materials of laminate 103 . For example, passivation layer 107 may have a greater thickness on the sidewalls of the layer of first material 104 (eg, silicon oxide) than on the sidewalls of the layer of second material 105 (eg, silicon nitride or polysilicon). may be formed by The thicker the passivation layer 107, the greater the protection against lateral etching. Thus, the layer of the first material is laterally etched less than the layer of the second material on which the thin passivation layer 107 rests.

Alternatively or additionally, sidewall notches may be caused by non-uniform etch rates of two different materials. In some cases, this can result in the formation of corners, particularly at intersections between upper layers that etch at a first rate and lower layers that etch at a different rate. Such corners are exposed to ion bombardment, which can lead to the formation of undercuts, especially in the upper regions of overetched layers.

Sidewall notches can also be caused by stress differences between two dissimilar layers. Clearly, sidewall notching occurs regardless of one or more causes.

Certain techniques have been developed to reduce sidewall notches. These techniques often involve adjusting the composition of the etch chemistry. More specifically, etch chemistries have been tuned by controlling the ratios of nitrogen-, oxygen-, carbon-, and fluorine-containing species in the plasma that etches the substrate. However, these techniques typically result in tradeoffs involving the profile of the etched features. For example, such techniques can create bowing (e.g., if the central portion of the feature is overetched relative to the top of the feature), reduce selectivity, increase capping, or reduce etch rate. sometimes Any such result is undesirable.

The inclusion of tungsten hexafluoride ( _WF6 ) in the etch chemistry has been found to eliminate or substantially reduce sidewall notches without trade-offs in bowing, selectivity, capping, or etch rate. rice field. As a result, the sidewalls of etched features are much smoother. This result is highly desirable.

Without wishing to be bound by theory or mechanism of action, it is believed that WF ₆ is a vertical and/or horizontal polarizer between a first material (e.g. silicon oxide) and a second material (e.g. silicon nitride or polysilicon). It is believed that the etch rates in the directions may be made more equal. For example, _WF6 reduces the vertical etch rate of the first material (eg, thereby increasing the horizontal etch rate of the first material) and/or increases the vertical etch rate of the second material. (eg, thereby reducing the horizontal etch rate of the second material). Alternatively, or in addition, _WF6 slows the formation of a passivation layer on the sidewalls of the first material (eg silicon oxide) and/or reduces the formation rate of the passivation layer on the sidewalls of the second material (eg silicon nitride or polysilicon). It may speed up the formation of the passivation layer on the sidewalls. Alternatively or additionally, WF ₆ may counter differences in film stress or other properties between two different types of layers.

_WF6 may result in a more uniform etch rate between the first material and the second material as a result of excess F* in the plasma. Alternatively or additionally, WF ₆ may produce a tungsten-based (eg, possibly tungsten oxide-based) sidewall polymer film, similar to passivation layer 107 of FIG. The tungsten-based sidewall polymer film may smoothly deposit on the sidewalls of the various layers, thereby preventing notch formation.

_WF6 is widely used to deposit tungsten-based films. However, _WF6 is not commonly used as part of etch chemistries. It was unexpected that sidewall notch improvement was observed with the addition of _WF6 to the etch chemistry.

FIG. 3 shows the substrate 101 of FIG. 1 after an etching process according to one embodiment herein. In this case the etch chemistry includes _WF6 . As a result, the first material 104 and the second material 105 are etched at a uniform rate and the resulting sidewalls are smooth. The passivation layer 107 is shown in FIG. 3 as having the same shape and uniformity. However, this is not necessarily the case. Passivation layer 107 may not be uniform in thickness and/or composition. For example, it may be relatively thick near the top of the feature and relatively thin or absent near the bottom of the feature (or vice versa). In one case, passivation layer 107 may have a composition that is relatively tungsten-rich near the top of the feature and relatively tungsten-poor near the bottom of the feature (or vice versa). In these cases or other cases, the passivation layer 107 may be relatively carbon-poor on the top of the feature and relatively carbon-rich on the bottom of the feature (or vice versa). In certain embodiments, passivation layer 107 may include two passivation layers, one of which is tungsten-based and the other is carbon-based. The two passivation layers may overlap each other (e.g., as separate layers or as intermingled layers) and/or may be formed at different vertical locations within the feature (e.g., a tungsten-based passivation layer may be , closer to the top of the feature or the bottom of the feature compared to carbon-based passivation layers). As discussed above with respect to FIG. 2, the composition of passivation layer 107 may also depend on the composition of layers formed in contact therewith.

In one particular embodiment, tungsten in the passivation layer may be concentrated towards the top of the feature as compared to the bottom of the feature. In other words, most of the tungsten from _WF6 stays near the top of the feature. This may help retain the mask layer in some cases. A concentration of tungsten near the top of the feature may result in a higher sticking coefficient for tungsten and tungsten-containing species. When such high sticking coefficient species contact the sidewalls, they are very likely to "stick" deep into the feature without rebounding. Fluorine from WF ₆ has a much lower sticking coefficient and can penetrate the bottom of features more easily, thus contributing to increased etch rates. Both of these factors (e.g., tungsten-containing species remaining near the top of the feature and fluorine-containing species migrating to the bottom of the feature to further etch the stack) ensure that the etch selectivity remains desirably high. become.

FIG. 4 is a flow chart describing a method of etching features of a stack including dielectric material, according to various embodiments of the present invention. The method begins with operation 401 where a substrate is provided in a reaction chamber. The substrate may be, for example, the substrate described with respect to FIG. Next, in operation 403, a plasma is generated from the plasma-generating gas. The plasma generating gas contains at least _WF6 . The plasma-generating gas also includes etch chemistries suitable for etching the laminate material. In various examples, the etch chemistries include, for example, one or more oxygen-containing species, one or more carbon-containing species, and one or more fluorine-containing species. Examples _of materials commonly _used for etch chemistries include _C3F8 , _{C4F8 , C4F6} , _CH2F2 , _{CH3F , CHF3} , _{C5F8 , C6F6 ,} etc. fluorocarbons and hydrofluorocarbons, oxidants such as _O2 , _O3 , CO, _CO2 , COS, and _NF3 . Inert species may also be provided in the plasma generating gas.

The flow rate of _WF6 in the plasma-generating gas may be at least about 0.1 seem, or at least about 0.2 seem, or at least about 0.5 seem, or at least about 1 seem. In these or other cases, the flow rate of _WF6 may be about 20 seem or less, such as about 10 seem or less, or about 5 seem or less, or about 2 seem or less, or about 1 seem or less, or about 0.5 seem or less. In certain embodiments, the WF ₆ flow rate may be about 0.1-10 seem. The total plasma-generating gas flow rate may be at least about 1 sccm, at least about 10 sccm, at least about 50 sccm, or at least about 80 sccm. In these or other cases, the total plasma-generating gas flow rate may be about 600 sccm or less, or about 500 sccm or less, or about 300 sccm or less, or about 200 sccm or less, or about 100 sccm or less, or about 50 sccm or less. . Optionally, one or more fluorocarbon sources may be mixed (before or after delivery to the reaction chamber) to provide, for example, the desired proportions of carbon and fluorine. In some examples, the C ₄ F ₈ and/or C ₃ F ₈ and/or C ₄ F ₆ flow rate may be between about 20-120 sccm. In these or other examples, the CH ₂ F ₂ flow rate may be about 10-120 sccm. In various embodiments, the total flow rate of fluorocarbons and hydrofluorocarbons can be about 30-240 sccm. In these or other examples, the NF ₃ flow rate may be about 0-30 sccm. In these or other examples, the O ₂ flow rate may be about 20-150 sccm. In these or other examples, the SF ₆ flow rate may be about 1-20 sccm. In these or other examples, the Kr flow rate may be about 30-120 sccm. In various instances, _WF6 is at least about 0.02%, or at least about 0.05%, or at least about 0.1%, or at least about 0.5%, or at least about It may account for 1%, or at least about 3%. In these or other cases, WF ₆ may comprise about 10% or less, or about 5% or less, or about 1% or less, or about 0.5% or less of the volumetric flow rate of the plasma-generating gas.

In various instances, the following conditions may be used to generate the plasma. The plasma may be a capacitively coupled plasma. The plasma may be generated at an excitation frequency of about 13-169 MHz, such as about 20-100 MHz (eg, 60 MHz in particular cases), at a power level of about 0 Watts to 6.3 kW per 300 mm substrate. In various instances, the power levels used to generate the plasma may be particularly high, for example about 5 kW or more, or about 6 kW or more per 300 mm substrate. For example, a relatively high bias may be applied to the substrate to promote a fast vertical etch rate. The bias is at a frequency of about 20 kHz to 1.5 MHz, or about 200 kHz to 1.5 MHz, or about 300 kHz to 600 kHz (eg, about 400 kHz in certain cases) at about 500 W to 20 kW per 300 mm substrate, or about 2.5 MHz per 300 mm substrate. A power level of ~10 kW may be applied to the substrate. In a particular embodiment, the substrate is biased at a power level of about 500W-20kW at 400kHz. The pressure within the reaction chamber may be at least about 10 mTorr or at least about 30 mTorr. In these cases or other cases, the pressure in the reaction chamber may be about 500 mTorr or less, such as 100 mTorr or less, or about 80 mTorr or less, or about 30 mTorr or less. In some cases, the pressure may remain relatively low during etching (eg, 10-80 mTorr), but higher pressures (eg, 100-500 mTorr, or 300-500 mTorr, or 400-500 mTorr). A substrate support underlying the provided substrate may be maintained at a temperature of about -80°C to 130°C (eg, by heating and/or cooling). In some cases, the substrate support is at least about −80° C., or at least about −50° C., or at least about −20° C., or at least about 0° C., or at least about 20° C., or at least about 50° C., or at least about A temperature of 70°C is maintained. In these or other cases, the substrate support is about 130° C. or less, or about 120° C. or less, or about 100° C. or less, or about 80° C. or less, or about 50° C. or less, or about 20° C. or less, or A temperature of about 0° C. or less, or about -20° C. or less, or about -50° C. or less may be maintained. In certain cases, the substrate support may be maintained at a temperature of about 20-80°C. These temperatures may relate to the temperature of the substrate support being controlled while the substrate is exposed to the plasma.

After a period of time, features begin to form in the laminate. As shown in FIG. 3, the substrate is removed from the reaction chamber in operation 405 after the features have reached their final etch depth. Compared to conventional techniques, the method described with respect to FIG. 4 is capable of forming deep features with relatively few (or no) notches. The inclusion of _WF6 in the plasma-generating gas substantially reduces or eliminates sidewall notches when supplied at appropriate flow rates and under appropriate plasma conditions. Advantageously, this reduction in sidewall notch does not provide trade-offs with respect to feature curvature, selectivity, capping, or etch rate.

Apparatus The methods described herein may be performed in any suitable apparatus. A suitable apparatus includes hardware for implementing processing operations and a system controller that includes instructions for controlling processing operations according to the present embodiments. For example, in some embodiments, hardware may include one or more processing stations included in a processing tool.

5A-5C illustrate an embodiment of an adjustable gap capacitively coupled confined RF plasma reactor 500 that may be used to perform the etching operations described herein. As shown, vacuum chamber 502 has a chamber housing 504 enclosing an interior space that houses lower electrode 506 . At the top of chamber 502 , upper electrode 508 is vertically spaced from lower electrode 506 . The planar surfaces of the upper and lower electrodes 508, 506 are substantially parallel and perpendicular to the vertical between the electrodes. The upper and lower electrodes 508, 506 are preferably circular and coaxial with respect to the vertical axis. The lower surface of upper electrode 508 faces the upper surface of lower electrode 506 . The faces of the electrodes that face apart define an adjustable gap 510 therebetween. During operation, lower electrode 506 is RF powered by RF power supply (match) 520 . RF power is supplied to lower electrode 506 via RF supply tube 522 , RF strap 524 and RF power member 526 . A ground shield 536 may surround the RF power member 526 to provide a uniform RF field over the bottom electrode 506 . Wafers are inserted through wafer port 582 and processed for processing, as described in commonly owned U.S. Patent Application No. 7,732,728, which is incorporated herein by reference in its entirety. supported in gap 510 above lower electrode 506, a process gas is supplied to gap 510 and excited by RF power into a plasma state. The upper electrode 508 can be powered or grounded.

In the embodiment shown in FIGS. 5A-5C, lower electrode 506 is supported on lower electrode support plate 516 . An insulating ring 514 interposed between the lower electrode 506 and the lower electrode support plate 516 insulates the lower electrode 506 from the support plate 516 .

RF bias housing 530 supports lower electrode 506 on RF bias housing bowl 532 . Bowl 532 is coupled to conduit support plate 538 through an opening in chamber wall plate 518 by arm 534 of RF bias housing 530 . In the preferred embodiment, RF bias housing bowl 532 and RF bias housing arm 534 are integrally formed as one component, but arm 534 and bowl 532 are two separate pieces that are bolted or joined together. can also be a component of

The RF bias housing arm 534 routes RF power and equipment (gas coolant, liquid coolant, RF energy, cables for lift pin control, signals to electrically monitor and activate, etc.) in the space behind the lower electrode 506. , has one or more hollow passageways for passing from outside the vacuum chamber 502 to inside the vacuum chamber 502 . RF feed tube 522 is insulated from RF bias housing arm 534 , which provides a return path for RF power back to RF power supply 520 . Facility lines 540 provide passageways for facility elements. Further details of the equipment elements are described in US Pat. Nos. 5,948,704 and 7,732,728 and are not presented here for the sake of brevity. Gap 510 is preferably surrounded by a confinement ring assembly or shroud (not shown), further details of which can be found in commonly owned U.S. Pat. incorporated herein by reference. The interior of vacuum chamber 502 is maintained at a low pressure by connecting to a vacuum pump through vacuum inlet 580 .

Conduit support plate 538 is attached to actuation mechanism 542 . Details of the actuation mechanism are described in commonly owned US Pat. No. 7,732,728, which is hereby incorporated by reference. An actuation mechanism 542, such as a servomechanical motor, stepper motor, etc., is mounted to a vertical linear bearing 544 by a screw gear 546, such as, for example, a ball screw and a motor that rotates the ball screw. In operation to adjust the size of gap 510 , actuation mechanism 542 moves along vertical linear bearing 544 . FIG. 5A shows the configuration when the actuation mechanism 542 is high above the linear bearing 544, thereby creating a small gap 510a. FIG. 5B shows the configuration when actuation mechanism 542 is in an intermediate position on linear bearing 544 . As shown, lower electrode 506, RF bias housing 530, conduit support plate 538, and RF power source 520 have all moved downward relative to chamber housing 504 and upper electrode 508, resulting in intermediate sized gap 510b. It has become.

FIG. 5C shows a large gap 510c when the actuation mechanism 542 is in the low position on the linear bearing. Preferably, the upper and lower electrodes 508, 506 remain coaxial while adjusting the gap and the facing surfaces of the upper and lower electrodes remain parallel throughout the gap.

In this embodiment, in order to maintain uniform etching across large diameter substrates, such as 300 mm wafers and flat panel displays, during multi-step process recipes (such as BARC, HARC and STRIP), It is possible to adjust the gap 510 between the lower electrode 506 and the information electrode 508 of the . In particular, this chamber relates to a mechanical arrangement that allows the linear motion necessary to achieve an adjustable gap between lower electrode 506 and upper electrode 508 .

FIG. 5A shows a laterally deflected bellows 550 sealed at its proximal end to the conduit support plate 538 and at its distal end to the stepped flange 528 of the chamber wall plate 518 . The inner diameter of the stepped flange defines an opening 512 in the chamber wall plate 518 through which the RF bias housing arm 534 passes. The distal end of bellows 550 is clamped with clamp ring 552 .

Laterally deflected bellows 550 provides a vacuum seal and allows vertical movement of RF bias housing 530, conduit support plate 538 and actuation mechanism 542. FIG. RF bias housing 530, conduit support plate 538 and actuation mechanism 542 can be referred to as a cantilever assembly. Preferably, the RF power source 520 moves with the cantilever assembly and can be attached to the conduit support plate 538 . FIG. 5B shows bellows 550 in a neutral position when the cantilever assembly is in an intermediate position. FIG. 5C shows lateral deflection of the bellows 550 when the cantilever assembly is in the low position.

Labyrinth seal 548 provides a particle barrier between bellows 550 and the interior of plasma processing chamber housing 504 . A stationary shield 556 is immovably mounted inside the inner wall of the chamber housing 504 at the chamber wall plate 518 to form a labyrinth groove 560 (slot) within which a movable shield plate 558 moves vertically. Accommodates vertical movement of the cantilever assembly. The outer portion of movable shield plate 558 remains in the slot at any vertical position of lower electrode 506 .

In the illustrated embodiment, labyrinth seal 548 has a stationary shield 556 mounted to the inner surface of chamber wall plate 518 around opening 512 in chamber wall plate 518 defining labyrinth groove 560 . Movable shield plate 558 is attached to RF bias housing arm 534 and extends radially therefrom where arm 534 passes through opening 512 in chamber wall plate 518 . The movable shield plate 558 extends into the labyrinth groove 560 but is separated from the stationary shield 556 by a first gap and from the inner surface of the chamber wall plate 518 by a second gap so that the cantilever assembly is vertical. You can move in any direction. The labyrinth seal 548 prevents particles detached from the bellows 550 from migrating into the vacuum chamber interior 505 and prevents radicals from the process gas plasma from migrating to the bellows 550 . Radicals can form deposits in the bellows, which are later stripped.

FIG. 5A shows movable shield plate 558 in labyrinth groove 560 high position above RF bias housing arm 534 when cantilever assembly is in high position (small gap 510a). FIG. 5C shows movable shield plate 558 in labyrinth groove 560 low position over RF bias housing arm 534 when cantilever assembly is in low position (large gap 510c). FIG. 5B shows the movable shield plate 558 in a neutral or intermediate position within the labyrinth groove 560 when the cantilever assembly is in an intermediate position (middle gap 510b). Although the labyrinth seal 548 is shown as being symmetrical about the RF biased housing arm 534 , in other embodiments the labyrinth seal 548 may be asymmetrical about the RF biased arm 534 .

FIG. 6 depicts a semiconductor process cluster architecture in which various modules interface with a vacuum transfer module 638 (VTM). The configuration of transport modules for "transporting" substrates among multiple storage facilities and processing modules is sometimes referred to as a "cluster tool architecture" system. An airlock 630, also known as a loadlock or transfer module, is shown within a VTM 638 having four processing modules 620a-620d, which are individually optimized to perform various manufacturing processes. may be By way of example, processing modules 620a-620d may also perform substrate etching, deposition, ion implantation, substrate cleaning, sputtering, and/or other semiconductor processes, as well as laser metrology and other methods of detecting and identifying defects. may be implemented to One or more processing modules (any of 620a-620d) may be implemented as disclosed herein, ie, for etching recessed features in a substrate. Airlock 630 and processing modules 620a-620d are sometimes referred to as "stations." Each station has a facet 636 that interfaces the station to VTM 638 . Inside the facet, sensors 1-18 are used to detect the passage of substrate 626 as it moves between respective stations.

A robot 622 transports substrates between stations. In one implementation, the robot may have one arm, and in another implementation the robot may have two arms, where each arm is for picking up and carrying a substrate. of end effectors 624 . A front-end robot 632 at atmospheric transfer module (ATM) 640 may be used to transfer substrates from cassettes or Front Opening Unified Pods (FOUPs) 634 in load port module (LPM) 642 to airlock 630 . A module center 628 within the processing modules 620a-620d may be one location for placing substrates. An aligner 644 in ATM 640 may be used to align the substrates.

In one exemplary processing method, a substrate is placed in one of the FOUPs 634 within the LPM 642 . A front-end robot 632 transports the substrate from the FOUP 634 to the aligner 644, which allows the substrate 626 to be properly centered, deposited on, or processed prior to etching. After alignment, the substrate is moved to airlock 630 by front-end robot 632 . The airlock module functions to match the environment between the ATM and VTM so that substrates can be transferred between the two pressure environments without damage. Substrates are moved from airlock module 630 by robot 622 through VTM 638 to one of processing modules 620a-620d, eg, processing module 620a. To accomplish this substrate movement, robot 622 uses end effectors 624 on each arm. In processing module 620a, the substrate undergoes etching as described. Robot 622 then moves the substrate from processing module 620a to the next desired location.

It is noted that the computer that controls the movement of the substrate can be local to the cluster architecture, located external to the cluster architecture at the manufacturing site, or remotely located and connected to the cluster architecture via a network. sea bream.

In some implementations, the controller is part of the system, which may be part of the examples above. Such systems may include one or more processing tools, one or more chambers, one or more platforms for processing, and/or specific processing components (wafer pedestals, gas flow systems, etc.). A semiconductor processing apparatus comprising: These systems may be integrated with electronics that control the operation of the system before, during, and after processing semiconductor wafers or substrates. The electronics may be referred to as "controllers" and may control various components or sub-parts of one or more systems. Depending on the process requirements and/or type of system, the controller may control process gas supply, temperature settings (e.g., heating and/or cooling), pressure settings, vacuum settings, power settings, radio frequency (RF) generation tool settings, RF matching circuit settings, frequency settings, flow rate settings, fluid supply settings, potential and operation settings, wafer transfer into and out of tools and other transfer tools and/or connected to a particular system; It may be programmed to control any of the processes disclosed herein, such as loadlocks bounded by a particular system.

Generally, the controller includes various integrated circuits, logic circuits, memory, and/or software that receive and issue commands, control operations, enable cleaning operations, enable endpoint measurements, and the like. may be defined as an electronic device that has An integrated circuit may be a chip in firmware form storing program instructions, a digital signal processor (DSP), a chip defined as an application specific integrated circuit (ASIC), and/or one or more microprocessors, or program instructions (e.g. software). Program instructions are communicated to the controller in the form of various individual settings (or program files) that define operating parameters for performing specific processes on or for a semiconductor wafer or to the system. may be an instruction to The operating parameters, in some embodiments, are one or more layers, materials, metals, oxides, silicon, silicon dioxide, surfaces, circuits, and/or one or more processing steps in the process of manufacturing a wafer die. may be part of a recipe defined by the process engineer to achieve

The controller, in some embodiments, may be part of a computer that is integrally connected to the system, networked with the system, or a combination thereof, or may be connected to the computer. You may have For example, the controller may be in the "cloud" or may be all or part of a fab host computer system that can allow remote access for wafer processing. The computer monitors the current progress of manufacturing operations, examines the history of past manufacturing operations, examines trends or performance metrics from multiple manufacturing operations, changes parameters of the current process, and sets process steps. Remote access to the system may be enabled in order to follow the current process or initiate a new process. In some examples, a remote computer (eg, server) can provide processing recipes to the system over a network, which may include a local network or the Internet. The remote computer may contain a user interface that allows the entry or programming of parameters and/or settings, which are then communicated from the remote computer to the system. In some examples, the controller receives instructions in the form of data that specify parameters for each processing step to be performed during one or more operations. It should be appreciated that the parameters may be specific to the type of processing being performed and the type of tool the controller is configured to interface with or control. Thus, as previously mentioned, the controllers may be distributed, such as by having one or more separate controllers that are networked together and serve a common purpose, such as the processing and control described herein. . An example of a distributed controller to do so is on a chamber that communicates with one or more remotely located integrated circuits (e.g., at the platform level or as part of a remote computer), in combination with There will be one or more integrated circuits that control the processing on this chamber.

Non-limiting example systems include plasma etch chambers or modules, deposition chambers or modules, spin rinse chambers or modules, metal plating chambers or modules, cleaning chambers or modules, bevel edge etch chambers or modules, physical vapor deposition ( PVD) chambers or modules, chemical vapor deposition (CVD) chambers or modules, atomic layer deposition (ALD) chambers or modules, atomic layer etch (ALE) chambers or modules, ion implantation chambers or modules, track chambers or modules, and semiconductor wafers. There may be any other semiconductor processing system that may be associated with or used in the manufacture and/or production of.

As noted above, depending on the one or more processing steps performed by the tool, the controller may select other tool circuits or modules, other tool components, cluster tools, other tool interfaces, adjacent tools, neighborhood tools, tools located throughout the factory, main computers, separate controllers, or containers of wafers used to transport materials to and from tool locations and/or load ports within a semiconductor manufacturing plant. may communicate with one or more of the tools.

Additional Embodiments The various hardware and method embodiments described above may be used in conjunction with lithographic patterning tools or processes, for example, for fabrication or manufacturing of semiconductor devices, displays, LEDs, photovoltaic panels, and the like. you can Typically, but not necessarily, such tools/processes are used or performed together at a common manufacturing facility.

Lithographic patterning of films typically involves some or all of the following steps, each of which can be accomplished in many possible tools. (1) A workpiece, for example, a substrate having a silicon nitride film formed thereon, is coated with photoresist using a spin-on tool or a spray-on tool. (2) Cure the photoresist using a hot plate or oven or other suitable curing tool. (3) Exposing the photoresist to visible or UV or X-ray light using a tool such as a wafer stepper. (4) develop the resist to selectively remove the resist, thereby patterning the resist using a tool such as a wet bench or spray developer; (5) transfer the pattern of the resist into the underlying film or workpiece using a dry etch or plasma assisted etch tool; and (6) using a tool such as an RF or microwave plasma resist stripper to remove the resist. In some embodiments, an ashable hardmask layer (such as an amorphous carbon layer) and another suitable hardmask (such as an antireflective layer) may be deposited prior to applying the photoresist.

Because the configurations and/or techniques described herein are illustrative in nature and many variations are possible, these particular embodiments or examples should be construed in a limiting sense. It should be understood that it is not The particular procedures or methods described herein may represent one or more of any number of processing strategies. As such, various acts shown may be performed in the order shown, in other orders, in parallel, or in some cases omitted. Likewise, the order of the above processes may be changed. Certain references are incorporated herein by reference. It is understood that any disclaimers or disclaimers made in such references do not necessarily apply to the embodiments described herein. Similarly, features described where appropriate in such references may be omitted from the embodiments herein.

As used herein, the terms "semiconductor wafer," "wafer," "substrate," "wafer substrate," and "partially fabricated integrated circuit" are used interchangeably. Those skilled in the art will appreciate that the term "partially fabricated integrated circuit" can refer to a silicon wafer at any of a number of integrated circuit fabrication stages. Wafers or substrates used in the semiconductor device industry typically have a diameter of 200 mm, or 300 mm, or 450 mm. The detailed description above assumes that the embodiments are implemented on a wafer. However, embodiments are not so limited. Workpiece shapes, sizes and materials may vary. In addition to semiconductor wafers, other workpieces that may utilize the disclosed embodiments include various articles such as printed circuit boards, magnetic recording media, magnetic recording sensors, mirrors, optical elements, micromechanical devices, and the like. Unless otherwise specified for a particular parameter, the terms "about" and "approximately" as used herein are intended to mean ±10% relative to the relevant value.

In the above description, numerous specific details are set forth in order to provide a thorough understanding of the present embodiments. The disclosed embodiments may be practiced without some or all of these specific details. In other instances, well known processing operations have not been described in detail so as not to unnecessarily obscure the disclosed embodiments. While the disclosed embodiments have been described in conjunction with specific embodiments, it will be understood that they are not intended to limit the disclosed embodiments. The subject matter of the present disclosure covers all novel and non-obvious combinations and subcombinations of the various processes, systems and configurations and other features, functions, acts and/or properties disclosed herein, and any and all combinations thereof. Including equivalents and all equivalents.

Claims (19)

A method of etching features in a stack including a dielectric material in fabricating a 3D NAND structure, comprising:
receiving a substrate on a substrate support within a reaction chamber, said substrate comprising said stack and a mask layer patterned on top of said stack, said stack comprising (a) alternating silicon oxide and silicon nitride; or (b) alternating layers of silicon oxide and polysilicon,
exposing the substrate to a plasma in the reaction chamber thereby etching the feature in the stack on the substrate;
said plasma is generated from a plasma-generating gas comprising _WF6 , one or more fluorocarbons and/or hydrofluorocarbons, and one or more oxidants, wherein the flow rate of _WF6 is about 0.1-10 sccm;
the plasma is a capacitively coupled plasma;
the substrate is biased at a frequency of about 20 kHz to 1.5 MHz at an RF power level of about 500 W to 20 kW per substrate;
said _WF6 and said fluorocarbons and/or hydrofluorocarbons form a tungsten-based polymer film on the sidewalls of said features during an etching process, said tungsten-based polymer film between said alternating layers of silicon oxide and silicon nitride; or promoting a uniform etch rate between said alternating layers of silicon oxide and polysilicon so that said sidewalls of said features are not notched during the etching process;
Method. 2. The method of claim 1, wherein during etching, the _WF6 dissociates into tungsten-containing fragments and fluorine-containing fragments, and the tungsten-containing fragments are more concentrated in the feature than the fluorine-containing fragments. Remaining relatively concentrated near the top, the fluorine-containing fragment penetrates deeper into the feature compared to the tungsten-containing fragment. 3. The method of claim 2, wherein the tungsten-based polymer film has a proportion of tungsten in the tungsten-based polymer film near the top of the feature that is less than the tungsten-based polymer film near the bottom of the feature. The method, wherein composition is non-uniform along said sidewalls of said feature to a greater extent. 2. The method of claim 1, wherein the plasma is generated at an excitation frequency of approximately 20 MHz to 100 MHz and an RF power of approximately 6.3 kW or less. 5. The method of claim 4, wherein the oxidant is _O2 and the flow rate of _O2 is between about 20-150 seem. 6. The method of claim 5, wherein the plasma-generating gas further comprises _SF6 , and the flow rate of said _SF6 is between about 1-20 seem. 7. The method of claim 6, wherein the plasma-generating gas further comprises Kr, and the Kr flow rate is about 30-120 sccm. 8. The method of claim 7, wherein the plasma-generating gas further comprises _NF3 , and the flow rate of _NF3 is less than or equal to about 30 sccm. 9. The method of claim 8, wherein _the fluorocarbon or _{hydrofluorocarbon} comprises _one or more of _C4F8 , _{C3F8 , C4F6} , and _CH2F2 , the fluorocarbon and The method, wherein the total hydrofluorocarbon flow rate is about 30-240 sccm. 10. The method of claim 9, wherein the substrate support is maintained at a temperature of about 20-80°C while etching the substrate. 11. The method of claim 10, wherein the pressure within the reaction chamber is maintained at about 10-80 mTorr while etching the substrate. 12. The method of claim 11, wherein the features are etched into the alternating layers of silicon oxide and silicon nitride. 12. The method of claim 11, wherein the flow rate of _WF6 is between about 0.02% and 10% of the total flow rate of the plasma-generating gases. 14. The method of claim 13, wherein the flow rate of _WF6 is between about 0.02% and 1% of the total flow rate of the plasma-generating gas. 15. The method of claim 14, wherein the flow rate of _WF6 is between about 0.02% and 0.5% of the total flow rate of the plasma-generating gases. 2. The method of claim 1, wherein the substrate is biased with an RF frequency between about 300 kHz and 600 kHz. 17. The method of Claim 16, wherein the substrate is biased at an RF frequency of about 400 kHz. 18. The method of any one of claims 1-17, wherein the tungsten-based polymer film is formed with a first thickness on the layer of silicon oxide and a second thickness on the layer of silicon nitride or polysilicon. 2 thicknesses, wherein said first thickness and said second thickness are different. An apparatus for etching features in a stack including a dielectric material in fabricating a 3D NAND structure on a substrate, the apparatus comprising:
a reaction chamber having a substrate support therein;
a capacitively coupled plasma generator;
an inlet for introducing material into the reaction chamber;
an outlet for removing material from the reaction chamber;
a controller, the controller comprising:
receiving the substrate on the substrate support within the reaction chamber, the substrate comprising the stack and a mask layer patterned on top of the stack, the stack comprising: a) silicon oxide and silicon nitride; or (b) alternating layers of silicon oxide and polysilicon,
generating a plasma from a plasma-generating gas comprising WF ₆ , one or more fluorocarbons and/or hydrofluorocarbons, and one or more oxidants, wherein the flow rate of WF ₆ is between about 0.1 and 10 sccm;
biasing the substrate with an RF power level of about 500 W to 20 kW at a frequency of about 20 kHz to 1.5 MHz;
exposing the substrate to the plasma in the reaction chamber thereby etching the feature in the stack on the substrate;
The _WF6 and the fluorocarbons and/or hydrofluorocarbons form a tungsten-based polymer film on the sidewalls of the features during the etching process, the tungsten-based polymer film between the alternating layers of silicon oxide and silicon nitride. or an apparatus configured to promote a uniform etch rate between said alternating layers of silicon oxide and polysilicon such that said sidewalls of said feature are not notched during the etching process.

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