JP2023517921A - Processors and implementations, electronics, and storage media - Google Patents

Abstract

The present disclosure discloses a processor and implementation method, an electronic device and a storage medium in the fields of artificial intelligence and deep learning, wherein the processor is a system controller for sending predetermined data packet information to a data packing and unpacking module. acquires corresponding data packet data from the storage array module based on the data packet information, packs it with the data packet information, transmits the packed first data packet to the arithmetic module for arithmetic processing, and the arithmetic module performs a data packing and unpacking module for obtaining the returned second data packet, obtaining operation result data by unpacking, and storing in the storage array module; a storage array module for performing data storage; an arithmetic module for performing arithmetic processing on the first data packet, generating a second data packet based on the arithmetic result data, and returning the second data packet to the data packing and unpacking module. By applying the schemes described in the present disclosure, it is possible to reduce design difficulty and improve overall processing efficiency. [Selection drawing] Fig. 1

Description

[Cross reference to related applications]
This disclosure claims priority to a Chinese patent application with filing date Aug. 21, 2020, filing number 2020108517577 and titled "Processor and implementation method, electronic device, and storage medium" do.
The present disclosure relates to computer application technology, and more particularly to processors and implementation methods, electronic devices, and storage media in the fields of artificial intelligence and deep learning.

Increasingly intelligent applications are making neural network algorithms more diverse, making the overall neural network model more complex, and correspondingly more computational and data-storage interactions, thus requiring more neural network processors (NPUs). There is increasing emphasis on neural network-based processors such as Network Processing Unit chips.

The current NPU includes two mainstream design methods, one with accelerator as the core and the other with instruction extension as the core, the former design method being inferior in versatility and expandability. Therefore, it is rarely used, and the latter design method is mainly used. However, in the latter design method, it is necessary to expand the complicated instruction set corresponding to the arithmetic operation of the neural network, and it is necessary to develop a dedicated compiler to support it. The difficulty becomes even higher when applying to real-time processing of

The present disclosure provides processors and implementations, electronics, and storage media.

a processor, including a system controller, a storage array module, a data packing and unpacking module, and a computing module;
the system controller is used to send predetermined data packet information to the data packing and unpacking module;
The data packing and unpacking module obtains corresponding data packet data from the storage array module based on the data packet information, packs the data packet data and the data packet information, and packs a first packed data packet. to the arithmetic module for arithmetic processing, obtaining a second data packet returned by the arithmetic module, unpacking the second data packet to obtain arithmetic result data, and storing the storage used to store in the array module,
The storage array module is used to store data,
The arithmetic module is used to perform arithmetic processing on the obtained first data packet, generate the second data packet based on the arithmetic result data, and return the second data packet to the data packing and unpacking module. .

A processor implementation method comprising:
building a processor consisting of a system controller, a storage array module, a data packing and unpacking module, and a computing module;
performing neural network operations using the processor, wherein the system controller is used to send predetermined data packet information to the data packing and unpacking module, the data packing and unpacking module comprising: obtaining corresponding data packet data from the storage array module based on the data packet information, packing the data packet data and the data packet information, and transmitting a packed first data packet to the computing module; used to perform arithmetic processing, obtain a second data packet returned by the arithmetic module, and unpack the second data packet to obtain arithmetic result data for storage in the storage array module; The storage array module is used for data storage, and the arithmetic module performs arithmetic processing on the obtained first data packet, and generates the second data based on the arithmetic result data. Used to generate packets and return them to the data packing and unpacking module.

An electronic device comprising at least one processor and a memory communicatively coupled to the at least one processor, the memory storing instructions executable by the at least one processor, the instructions comprising: When executed by the at least one processor, the at least one processor causes the above method to be performed.

A non-transitory computer-readable storage medium having computer instructions stored thereon, said computer instructions causing said computer to perform the above method.

One embodiment of the above disclosure has advantages or beneficial effects. Propose an integrated implementation method of storage and computing, complete the overall interaction of neural network from memory to operation in the processor, avoid complicated instruction design and difficult compiler development, etc., and design difficulty reduce the speed and improve the overall processing efficiency, etc.

It should be understood that nothing described herein is intended to identify key or critical features of embodiments of the disclosure, nor is it used to limit the scope of the disclosure. Other features of the present disclosure can be readily understood through the following specification.

The drawings are for a better understanding of the disclosure and do not limit the disclosure.
1 is a schematic structural diagram of the configuration of a first embodiment of a processor 10 of the present disclosure; FIG. FIG. 4 is a schematic structural diagram of the configuration of the second embodiment of the processor 10 of the present disclosure; 3 is a schematic structural diagram of the configuration of the third embodiment of the processor 10 of the present disclosure; FIG. 4 is a flowchart of an embodiment of a processor-implemented method of the present disclosure; FIG. 3 is a block diagram of the electronics of the method according to an embodiment of the present disclosure;

Exemplary embodiments of the present disclosure will now be described with reference to the drawings. Various details of the embodiments of the disclosure are included for ease of understanding and should be considered as exemplary only. Accordingly, those skilled in the art should appreciate that various changes and modifications can be made to the embodiments described herein without departing from the scope and spirit of the disclosure. Similarly, for the sake of clarity, descriptions of well-known functions and constructions are omitted in the following description.

Also, the term "and/or" in this specification describes only the related relationship of related objects, and represents that three types of relationships can exist, for example, A and / or B is A Three cases can be represented: there is only A, A and B are present at the same time, or only B is present. It should be understood that the symbol "/" generally indicates that the related objects before and after are in an "or" relationship.

FIG. 1 is a schematic structural diagram of the configuration of the first embodiment of processor 10 of the present disclosure. As shown in FIG. 1, it includes a system controller 101 , a storage array module 102 , a data packing and unpacking module 103 and an arithmetic module 104 .

System controller 101 is used to send predetermined data packet information to data packing and unpacking module 103 .

The data packing and unpacking module 103 obtains corresponding data packet data from the storage array module 102 based on the data packet information, packs the data packet data and the data packet information, and sends the packed first data packet to the computing module. 104 to perform arithmetic processing, obtain a second data packet returned by the arithmetic module 104, unpack the second data packet to obtain arithmetic result data, and store in the storage array module 102. used for

Storage array modules 102 are used to provide data storage.

The arithmetic module 104 is used to perform arithmetic processing on the acquired first data packet, generate a second data packet based on the arithmetic result data, and return it to the data packing and unpacking module 103 .

The above embodiment presents an integrated realization of storage and computing, in which the neural network completes the overall interaction from memory to operation in the processor, eliminating complex instruction design and difficult compiler development, etc. It can be seen that it avoids, reduces the design difficulty, and improves the overall processing efficiency.

Based on what is shown in FIG. 1, processor 10 further includes one or all of a Direct Memory Access (DMA) module, a routing and switching module.

Preferably, the above two modules can be included at the same time, accordingly, FIG. 2 is a schematic structural diagram of the configuration of the second embodiment of the processor 10 of the present disclosure. As shown in FIG. 2, it includes a system controller 101 , a storage array module 102 , a data packing and unpacking module 103 , an arithmetic module 104 , a DMA module 105 and a routing and switching module 106 .

Among them, the DMA module 105 is used to realize high-speed exchange of external storage data and internal storage array data of the storage array module 103 under the control of the system controller 101 .

The routing switch module 106 sends the first data packet obtained from the data packing and unpacking module 103 to the computing module 104 and sends the second data packet obtained from the computing module 104 to the data packing and unpacking module 103. used for

As shown in FIG. 2, computing module 104 may further include general computing module 1041 and activation computing module 1042 . As the names suggest, general purpose operation module 1041 can be used to perform general purpose operations and activation operation module 1042 can be used to perform activation operations.

System controller 101 may use a simple control logic or state machine design and may also include complex processor IP, IP being an abbreviation for Intellectual Property, e.g. The processor IP may include advanced reduced instruction set machine (ARM, Advanced RISC Machine), Digital Signal Processing (DSP, Digital Signal Processing), X86, Microcontroller Unit (MCU, Microcontroller Unit) core IP, and the like.

The storage array module 102 is composed of multiple static random-access memories (SRAMs), supports high-speed simultaneous reading or writing of multiple ports, and uses a matrix scheme for high-speed caching of data. Or memory can be realized. The data stored in the storage array module 102 may include neural network model data, external input data, intermediate layer temporary data, and the like.

The data packing and unpacking module 103 performs data read and storage operations on the storage array module 102, performs packing operations on data packet information obtained from the system controller 101 and data packet data in the storage array module 102, and performs packing. The first data packet received is sent to the computing module 104 via the routing switch module 106, and the computing module 104 unpacks the second data packet returned via the routing switch module 106 to obtain the obtained Operation result data may be stored in the storage array module 102 .

Accordingly, the routing exchange module 106 can receive the data packets of the data packing and unpacking module 103 and the computing module 104 for data exchange and the like.

General-purpose operations performed by general-purpose operation module 1041 may include general-purpose vector operations such as vector arithmetic, logic operations, comparison operations, dot multiplication, accumulation, and addition. The activation operations performed by the activation operations module 1042 may include one or more of the nonlinear functions sigmoid, tanh, relu, softmax operations, and the like.

The system controller 101 can manage and control the whole, for example, the above data packet information is sent to the data packing and unpacking module 102, and the data packing and unpacking module 102 performs data packing and unpacking work. In this way, the DMA module 105 can be activated to realize high-speed exchange of external storage data and internal storage array data in the storage array module 102 .

As can be seen, in the above embodiment, the whole processor uses the body structure of storage array module + data packing and unpacking module + routing exchange module to allow the neural network to complete the overall interaction from storage to operation. , Avoid complex instruction design and difficult compiler development, etc., reduce design difficulty, improve overall processing efficiency, etc.

FIG. 3 is a schematic structural diagram of the configuration of the third embodiment of the processor 10 of the present disclosure. As shown in FIG. 3, it includes a system controller 101 , a storage array module 102 , a data packing and unpacking module 103 , an arithmetic module 104 , a DMA module 105 and a routing and switching module 106 . Therein, the storage array module 102 can include N1 storage units 1021, each storage unit 1021 can be a set of SRAMs, etc., and the data packing and unpacking module 103 can store N2 data can include packing and unpacking units 1031, each data packing and unpacking unit 1031 can be respectively connected to the routing switching module 106 via one data channel, N1 and N2 are both positive integers greater than 1; and the general-purpose computing module 1041 can include M computing units 10411, the activation computing module 1042 can include P computing units 10421, and each computing unit 10411/10421 can Each can be connected to the routing switching module 106 via one data channel, and both M and P are positive integers greater than one. Specific values of N1, N2, M and P can be determined according to actual needs.

Accordingly, the data packing and unpacking unit 1031 packs the data packet data obtained from the storage unit 1021 and the data packet information obtained from the system controller 101, and uses the data channel to generate the packed first data packet. to the arithmetic unit 10411/10421 via the routing switch module 106 for arithmetic processing, and uses the data channel to send the second data packet returned by the arithmetic unit 10411/10421 via the routing switch module , and unpacking the second data packet to obtain operation result data, which can be stored in the storage unit 1021 .

In a practical application, the system controller 101 can simulate the details of each neural network operation, such as what data to get, where to get it from, what operations need to be performed, and so on. to generate and send data packet information to the associated data packing and unpacking unit 1031 . Each data packing and unpacking unit 1031 can work in parallel, for example, obtain data packet information respectively from the system controller 101 and perform packing and unpacking operations.

Accordingly, the data packet information may include source channel, source address, destination channel (operation channel), operation type and data packet length, and the like. The data packing and unpacking unit 1031 can obtain the data packet data from the source address of the storage unit 1021 corresponding to the source channel, and the routing switching module 106 converts the obtained first data packet to the destination channel. It can be sent to the arithmetic unit 10411/10421, and the arithmetic unit 10411/10421 can perform the corresponding type of arithmetic processing based on the operation type.

Preferably, the values of N1 and N2 are the same, i.e. the number of storage units 1021 and data packing and unpacking units 1031 are the same, each data packing and unpacking unit 1031 corresponds to one storage unit 1021 respectively, Data packet data can be obtained from the corresponding storage unit 1021 . In this way, the parallelism of each data packing and unpacking unit 1031 can be better guaranteed, and assuming both data packing and unpacking units 1031 retrieve data from a particular storage unit 1021, the wait situations may arise, i.e. one data packing and unpacking unit 1031 in it needs to retrieve data only after waiting for another data packing and unpacking unit 1031 to complete retrieving data. Therefore, it causes a decrease in efficiency.

In the above processing method, by dividing the units, the parallel processing capability is increased, and the interaction capability of data storage and the like are further improved.

In existing instruction extension-core NPUs, data store interactions are inefficient, using unified load/store modes, sequential synchronous operations. After using the processing scheme described in this disclosure, processing can be performed in parallel, avoiding latency delays due to synchronization operations, etc., making system control and data storage interactions, etc. more efficient.

Data packet information may further include destination addresses or storage strategies. If the data packet information contains a destination address, the data packing and unpacking unit 1031 can store the operation result data in the corresponding storage unit 1021 according to the destination address, and the data packet information includes a storage strategy. If included, the data packing and unpacking unit 1031 can store the operation result data in the corresponding storage unit 1021 based on the storage strategy. The storage strategy may be a storage strategy that achieves data alignment.

After the operation unit 10411/10421 completes the operation, the operation result data can be replaced with the data of the data segment in the first data packet, and the data length is usually changed, so the data The data length information in the packet needs to be modified, and the generated second data packet is returned to the data packing and unpacking unit 1031 according to the transmission path of the first data packet, and the data packing and unpacking unit 1031 A related issue is how to store the operation result data after it has been parsed from the second data packet.

Accordingly, the data packet information may include source channel, source address, destination channel, destination address, etc., i.e., source address, destination address and channel addresses on both sides, thus: For the obtained operation result data, the data packing and unpacking unit 1031 can store it in the corresponding storage unit 1021 based on the destination address. Alternatively, the data packet information does not include the destination address, but may include the storage strategy, and the data packing and unpacking unit 1031 may store the operation result data in the corresponding storage unit 1021 based on the storage strategy. It is possible to realize automatic sorting of data.

What kind of storage strategy is specifically can be determined according to actual needs. For example, performing a filling process, etc.).

Arithmetic operations on neural networks result in data shrinkage or dilation, i.e., the above data length changes, post-operation data misalignment becomes easy, and NPUs with existing instruction extensions at their core usually add additional Data transformation or transposition solves the data alignment problem, such additional operations reduce the overall processing efficiency, and neural network operations involve large amounts of repeated memory operations interaction iteration operations, so the overall processing efficiency make a big impact. In the processing method described in the present disclosure, the routing exchange method realizes the free interaction of storage and operation, the storage strategy automatically completes storage, the automatic data alignment is achieved, and the implementation method is simple. Yes, and improve overall processing efficiency.

As shown in FIG. 3, the system controller 101 can interact with the processing unit via an external bus interface, and the DMA module 105 can communicate with a Double Data Rate (DDR) external memory via an external bus storage interface. It can interact with the storage unit, etc., and the specific realization is existing technology.

The above is the description of the device embodiments, and the following will further describe the solutions described in the present disclosure through the method embodiments.

FIG. 4 is a flow chart of an embodiment of a processor-implemented method of the present disclosure. As shown in FIG. 4, it includes the following specific implementation schemes.

At 401, build a processor consisting of a system controller, a storage array module, a data packing and unpacking module, and a computing module.

At 402, a processor is used to perform neural network operations, and a system controller is used to send predetermined data packet information to a data packing and unpacking module, which, based on the data packet information, Obtain corresponding data packet data from the storage array module, pack the data packet data and the data packet information, send the packed first data packet to the computing module for computing, and return by the computing module used to obtain a second data packet, unpack the second data packet to obtain operation result data, and store in the storage array module, the storage array module used to perform data storage; , the operation module is used to perform operation processing on the obtained first data packet, generate a second data packet based on the operation result data, and return it to the data packing and unpacking module.

Based on the above, a DMA module can also be added to the processor, the DMA module to realize high-speed exchange of external storage data and internal storage array data in the storage array module under the control of the system controller. can be used.

In addition, a routing exchange module can be added to the processor, the routing exchange module sending the first data packet obtained from the data packing and unpacking module to the computing module, and the second data packet obtained from the computing module. It can be used to send packets to the data packing and unpacking module.

The computing modules can include a general-purpose computing module for performing general-purpose computing and an activation computing module for performing activation computing.

Also, the storage array module may include N1 storage units, and the data packing and unpacking module may include N2 data packing and unpacking units, each data packing and unpacking unit each having one It is connected to the routing switching module via a data channel, and both N1 and N2 are positive integers greater than one. The general purpose computing module may contain M computing units and the activation computing module may contain P computing units, each of which communicates with the routing switch module via one data channel respectively. , and both M and P are positive integers greater than one.

In response, the data packing and unpacking unit packs the data packet data obtained from the storage unit and the data packet information obtained from the system controller, and uses the data channel to route and exchange the packed first data packet. module to an arithmetic unit for arithmetic processing, uses the data channel to obtain a second data packet returned by the arithmetic unit through the routing exchange module, and unloads the second data packet. It can be used to obtain operation result data by packing and store it in a storage unit.

Data packet information may include source channel, source address, destination channel, and operation type. Correspondingly, the data packet data may be the data packet data obtained by the data packing and unpacking unit from the source address of the storage unit corresponding to the source channel, the arithmetic unit obtaining the first data packet: It may be an arithmetic unit corresponding to the destination channel determined by the routing exchange module, and the arithmetic operation may be an arithmetic operation of said arithmetic type performed by the arithmetic unit.

Preferably, the values of N1 and N2 are the same, and each data packing and unpacking unit respectively corresponds to one storage unit and obtains data packet data from the corresponding storage unit.

Data packet information may further include destination addresses or storage strategies. If the data packet information includes a destination address, the data packing and unpacking unit can store the operation result data in the corresponding storage unit based on the destination address, and the data packet information includes a storage strategy. If so, the data packing and unpacking unit can store the operation result data in the corresponding storage unit based on the storage strategy. The storage strategy may be a storage strategy that achieves data alignment.

The specific workflow of the method embodiment shown in FIG. 4 is referred to the related description of the apparatus embodiment above and is not described here.

In short, using the schemes described in the method embodiments of the present disclosure, an integrated realization of storage and computing is presented, and the neural network completes the overall interaction from memory to operation in the processor. , Avoid complex instruction design and difficult compiler development, etc., reduce design difficulty, improve overall processing efficiency, etc.

According to embodiments of the disclosure, the disclosure further provides an electronic device and a readable storage medium.

As shown in FIG. 5, it is a block diagram of an electronic device according to the method of an embodiment of the present disclosure. Electronic equipment is intended to represent various forms of digital computers such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. Electronics can also represent various forms of mobile devices such as personal digital assistants, cell phones, smart phones, wearable devices, and other similar computing devices. The components, their connections and relationships, and their functionality illustrated herein are merely examples and are not intended to limit the description and/or required implementation of the disclosure herein.

As shown in FIG. 5, the electronic device includes one or more processors Y01, memory Y02, and interfaces for connecting components including high-speed interfaces and low-speed interfaces. Each component is interconnected by a different bus and can be mounted on a common motherboard or otherwise mounted based on needs. The processor processes instructions executed within the electronic device, including instructions stored in memory for displaying graphical information of the GUI on an external input/output device (such as a display device coupled to the interface). can be done. In other implementations, multiple processors and/or multiple buses can be used, along with multiple memories and multiple memories, if desired. Similarly, multiple electronic devices can be connected, and each electronic device can provide a partial required operation (eg, be a server array, blade server, or multi-processor system). In FIG. 5, one processor Y01 is taken as an example.

Memory Y02 is a non-transitory computer-readable storage medium provided by the present disclosure. Therein, the memory stores instructions to be executed by at least one processor to enable the at least one processor to perform the methods provided by the present disclosure. A non-transitory computer-readable storage medium of the present disclosure stores computer instructions for a computer to perform the methods provided by the present disclosure.

Memory Y02 is a non-transitory computer-readable storage medium, such as program instructions/modules corresponding to the methods in the embodiments of the present disclosure, non-transitory software programs, non-transitory computer-executable programs and used to store modules. Processor Y01 performs the various functional applications and data processing of the server by executing non-transitory software programs, instructions and modules stored in memory Y02, i.e. the method in the above method embodiment. Realize

The memory Y02 can include a storage program area and a storage data area, wherein the storage program area can store an operating system, application programs required for at least one function, and the storage data area can: It can store data and the like created by using an electronic device. Also, memory Y02 can include high-speed random storage memory, and can further include non-transitory memory, such as at least one disk storage device, flash memory device, or other non-transitory solid-state memory device. It is a state storage device. In some embodiments, memory Y02 may include memory located remotely to processor Y01, and these remote memories may be connected to electronic equipment via a network. Examples of such networks include, but are not limited to, the Internet, intranets, local area networks, mobile communication networks, and combinations thereof.

The electronic device can further include an input device Y03 and an output device Y04. The processor Y01, the memory Y02, the input device Y03, and the output device Y04 can be connected via a bus or other methods, and the connection via a bus is taken as an example in FIG.

The input device Y03 can receive input numeric or character information, and can generate key signal input for user installation and function control of the electronic equipment that implements the method, such as touch screen, key Input devices such as pads, mice, trackpads, touchpads, pointers, one or more mouse buttons, trackballs, and joysticks. Output devices Y04 may include display devices, auxiliary lighting devices, haptic feedback devices (eg, vibration motors), and the like. Such display devices can include, but are not limited to, liquid crystal displays, light emitting diode displays, and plasma displays. In some implementations, the display device may be a touch screen.

Various implementations of the systems and techniques described herein may be implemented in digital electronic circuit systems, integrated circuit systems, application specific integrated circuits, computer hardware, firmware, software, and/or combinations thereof. can be done. These various implementations can include being embodied in one or more computer programs, which are executed and executed in a programmable system including at least one programmable processor. /or may be interpreted, the programmable processor may be an application-specific or general-purpose programmable processor, receives data and instructions from a storage system, at least one input device, and at least one output device; Data and instructions can be transmitted to the storage system, the at least one input device, and the at least one output device.

These computing programs (also called programs, software, software applications, or code) are written in programmable processor machine instructions, high-level process and/or object-oriented programming languages, and/or assembly/machine language to Including implementing the program. As used herein, the terms "machine-readable medium" and "computer-readable medium" refer to any computer program product that can be used to provide machine instructions and/or data to a programmable processor. , apparatus, and/or apparatus (eg, magnetic disk, optical disk, memory, programmable logic device), including machine-readable media for receiving machine instructions, which are machine-readable signals. The term "machine-readable signal" refers to any signal for providing machine instructions and/or data to a programmable processor.

To provide interaction with a user, the systems and techniques described herein can be implemented on a computer, which includes a display device (e.g., cathode ray tube or liquid crystal display) for displaying information to the user. display monitor), and a keyboard and pointing device (eg, mouse or trackball) through which a user can provide input to the computer. Other types of devices can also be used to provide interaction with a user, for example, the feedback provided to the user can be any form of sensing feedback (e.g., visual, auditory, or tactile feedback). ) and can receive input from the user in any form (including acoustic, speech, and tactile input).

The systems and techniques described herein may be computing systems that include back-end components (e.g., data servers), or computing systems that include middleware components (e.g., application servers), or computing systems that include front-end components. A system (e.g., a user computer having a graphical user interface or web browser, through which the user interacts with implementations of the systems and techniques described herein), or such a back-end component , middleware components, and front-end components in any combination. The components of the system can be interconnected by any form or medium of digital data communication (eg, a communication network). Examples of communication networks include local area networks (LANs), wide area networks (WANs), blockchain networks, and the Internet.

The computer system can include clients and servers. A client and server are generally remote from each other and typically interact through a communication network. The relationship of client and server is created by computer programs running on corresponding computers and having a client-server relationship to each other. The server may be a cloud server, also called cloud computing or cloud host, which is one host product in the cloud computing service system, and the existing physical host and VPS service have a high management difficulty , to solve the defect of weak business extensibility.

It should be appreciated that steps may be reordered, added, or deleted using the various types of processes shown above. For example, each step described in the present disclosure may be performed in parallel, sequentially, or in a different order, but the techniques disclosed in the present disclosure The scheme is not limited herein so long as it can achieve the desired result.

The above specific implementation manners do not constitute a limitation of the protection scope of this disclosure. Those skilled in the art can make various modifications, combinations, subcombinations, and substitutions based on design requirements and other factors. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of this disclosure shall all fall within the protection scope of this disclosure.

Claims (20)

a processor,
including a system controller, a storage array module, a data packing and unpacking module, and a computing module;
said system controller sending predetermined data packet information to said data packing and unpacking module;
The data packing and unpacking module obtains corresponding data packet data from the storage array module based on the data packet information, packs the data packet data and the data packet information, and packs a first packed data packet. to the arithmetic module for arithmetic processing, obtaining a second data packet returned by the arithmetic module, unpacking the second data packet to obtain arithmetic result data, and storing the storage stored in the array module,
the storage array module provides data storage;
The arithmetic module performs arithmetic processing on the obtained first data packet, generates the second data packet based on the arithmetic result data, and returns the second data packet to the data packing and unpacking module.
processor. further comprising a direct memory access module for providing high speed exchange of external storage data with internal storage array data within said storage array module under control of said system controller;
2. The processor of claim 1. a routing switch module for transmitting the first data packet obtained from the data packing and unpacking module to the computing module, and transmitting the second data packet obtained from the computing module to the data packing and unpacking module; include,
2. The processor of claim 1. The computing module includes a general computing module and an activation computing module,
The general-purpose operation module performs general-purpose operations, and the activation operation module performs activation operations.
4. The processor of claim 3. the storage array module includes N1 storage units;
The data packing and unpacking module includes N2 data packing and unpacking units, each data packing and unpacking unit is respectively connected to the routing switching module via one data channel, N1 and N2 are both 1 is a positive integer greater than
The general purpose computing module comprises M computing units, the activation computing module comprises P computing units, each computing unit is respectively connected to the routing switching module via one data channel, and M and P are all positive integers greater than 1,
The data packing and unpacking unit packs the data packet data obtained from the storage unit and the data packet information obtained from the system controller, and uses the data channel to generate the packed first data packet. to an arithmetic unit through the routing exchange module for arithmetic processing, and using the data channel to obtain the second data packet returned by the arithmetic unit through the routing exchange module. , unpacking the second data packet to obtain operation result data and storing it in the storage unit;
5. The processor of claim 4. the data packet information includes source channel, source address, destination channel, and operation type;
the data packing and unpacking unit obtains the data packet data from the source address of a storage unit corresponding to the source channel;
The routing switch module sends the first data packet to an arithmetic unit corresponding to the destination channel for arithmetic processing of the arithmetic type.
6. The processor of claim 5. The N1 and N2 values are the same, and each data packing and unpacking unit respectively corresponds to one storage unit and obtains the data packet data from the corresponding storage unit.
7. The processor of claim 6. the data packet information further includes a destination address or storage strategy;
if the data packet information includes the destination address, the data packing and unpacking unit stores the operation result data in a corresponding storage unit based on the destination address;
if the data packet information includes the storage strategy, the data packing and unpacking unit stores the operation result data in a corresponding storage unit based on the storage strategy;
8. The processor of claim 7. the storage strategy includes a storage strategy that achieves data alignment;
9. The processor of claim 8. A processor implementation method comprising:
building a processor consisting of a system controller, a storage array module, a data packing and unpacking module, and a computing module;
performing neural network operations using the processor;
said system controller sending predetermined data packet information to said data packing and unpacking module;
The data packing and unpacking module obtains corresponding data packet data from the storage array module based on the data packet information, packs the data packet data and the data packet information, and packs a first packed data packet. to the arithmetic module for arithmetic processing, obtaining a second data packet returned by the arithmetic module, unpacking the second data packet to obtain arithmetic result data, and storing the storage stored in the array module,
the storage array module provides data storage;
The arithmetic module performs arithmetic processing on the obtained first data packet, generates the second data packet based on the arithmetic result data, and returns the second data packet to the data packing and unpacking module.
A processor implementation. further comprising adding a direct memory access module to the processor;
the direct memory access module provides high-speed exchange of external storage data with internal storage array data within the storage array module under control of the system controller;
11. A processor implementation method according to claim 10. further comprising adding a routing exchange module to the processor;
The routing exchange module transmits the first data packet obtained from the data packing and unpacking module to the computing module, and transmits the second data packet obtained from the computing module to the data packing and unpacking module. do,
11. A processor implementation method according to claim 10. The arithmetic module includes a general-purpose arithmetic module that performs general-purpose arithmetic and an activation arithmetic module that performs activation arithmetic,
13. A processor implementation method as claimed in claim 12. the storage array module includes N1 storage units;
The data packing and unpacking module includes N2 data packing and unpacking units, each data packing and unpacking unit is respectively connected to the routing switching module via one data channel, N1 and N2 are both 1 is a positive integer greater than
The general purpose computing module comprises M computing units, the activation computing module comprises P computing units, each computing unit is respectively connected to the routing switching module via one data channel, and M and P are all positive integers greater than 1,
The data packing and unpacking unit packs the data packet data obtained from the storage unit and the data packet information obtained from the system controller, and uses the data channel to generate the packed first data packet. to an arithmetic unit through the routing exchange module for arithmetic processing, and using the data channel to obtain the second data packet returned by the arithmetic unit through the routing exchange module. , unpacking the second data packet to obtain operation result data and storing it in the storage unit;
14. A processor implementation method as claimed in claim 13. the data packet information includes source channel, source address, destination channel, and operation type;
the data packet data is data packet data obtained by the data packing and unpacking unit from the source address of the storage unit corresponding to the source channel;
the computing unit that obtained the first data packet is the computing unit corresponding to the destination channel determined by the routing switch module;
The arithmetic processing is arithmetic processing of the arithmetic type performed by the arithmetic unit,
15. A processor implementation method as claimed in claim 14. The N1 and N2 values are the same, and each data packing and unpacking unit respectively corresponds to one storage unit and obtains the data packet data from the corresponding storage unit.
16. A processor implementation method as claimed in claim 15. the data packet information further includes a destination address or storage strategy;
if the data packet information includes the destination address, the data packing and unpacking unit stores the operation result data in a corresponding storage unit based on the destination address;
if the data packet information includes the storage strategy, the data packing and unpacking unit stores the operation result data in a corresponding storage unit based on the storage strategy;
17. A processor implementation method according to claim 16. the storage strategy includes a storage strategy that achieves data alignment;
18. A processor implementation method as claimed in claim 17. an electronic device,
at least one processor;
a memory communicatively coupled to the at least one processor;
Instructions executable by the at least one processor are stored in the memory, and when the instructions are executed by the at least one processor, the at least one processor performs the operation of any one of claims 10 to 18. executing the processor implementation described in
Electronics. a program,
cause a computer to perform the processor implementation method according to any one of claims 10 to 18,
program.

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