JP2023516524A - System and method for calibrating a digital phase-locked loop - Google Patents

Abstract

A clock generator calibration system includes a phase-locked loop (PLL) and a correction circuit. The PLL can generate an output clock signal, and the correction circuit can adjust the frequency signal of the PLL based on the digital signal of the PLL. A digital signal is generated based on the frequency signal being adjusted.

Description

Aspects described herein generally relate to digital phase-locked loops (PLLs), which are digital-to-time converters. A system and method for estimating and calibrating the integral nonlinearity of a time converter (DTC).

Wireless communication and radar systems with increased data rates require highly accurate synchronous clock generation. Such systems may use one or more PLLs. A conventional PLL consists of a dedicated full-range time-to-digital converter (TDC) with high resolution, a dedicated short-TDC with high resolution and programmable delay elements. resolution and a configurable delay element), and dedicated feedback. Conventional systems also require dedicated hardware such as TDCs, analog-to-digital converters (ADCs), and/or feedback to the digital domain.

BRIEF DESCRIPTION OF THE DRAWINGS The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate aspects of the disclosure and, together with the description, explain the principles of those aspects. and to enable one of ordinary skill in the relevant arts to make and use the multiple embodiments thereof.

1 illustrates a communication apparatus in accordance with one exemplary aspect of the present disclosure; 1 illustrates a clock generator in accordance with one exemplary aspect of the present disclosure; 1 illustrates a clock generator in accordance with one exemplary aspect of the present disclosure; 4 illustrates histogram distributions in accordance with example aspects of the present disclosure; 4 illustrates a flow chart of a coarse correction method according to one exemplary aspect of the present disclosure; 4 illustrates a flow chart of a fine correction method according to one exemplary aspect of the present disclosure;

Exemplary aspects of the disclosure are described with reference to the accompanying drawings. The drawing in which an element first appears is typically indicated by the leftmost digit or digit(s) in the corresponding reference number.

In the following description, numerous specific details are set forth in order to provide a thorough understanding of these aspects of the disclosure. However, it will be apparent to one skilled in the art that aspects thereof, including structures, systems and methods, may be practiced without these specific details. The descriptions and representations herein are the general means used by those skilled in the art or those skilled in the art to most effectively convey the substance of their work to others skilled in the art. be. In other instances, well-known methods, procedures, components and circuits have not been described in detail to avoid unnecessarily obscuring aspects of the disclosure.

Aspects described herein generally relate to digital phase-locked loops (PLLs), which are digital-to-time converters. A system and method for estimating and calibrating the integrated-nonlinearity of a time converter (DTC).

A wireless communication device may be configured for multiple radio access technologies (RATs). In these examples, one or more transceivers of the communication device may be configured to perform carrier aggregation. Exemplary RATs include (but are not limited to) 2G, 3G, 4G, LTE, 5G, satellite navigation technologies (e.g., GNSS), BT, WiFi, CDMA, or as will be understood by those skilled in the art. Including one or more other wireless technologies.

Aspects herein are applicable to transmitters, receivers, and other electronic devices requiring accurate clock generation or clocks, as those skilled in the art will appreciate. Although aspects are described with respect to wireless communications, this disclosure is not limited to implementations of wireless communications and may include other applications, such as wired communications, data processing, or cryptography. Use a clock generator and synchronization that uses one or more such generated clocks, including synchronization, etc.

FIG. 1 illustrates a communication device 100 according to one exemplary aspect of the present disclosure. Communication device 100 is configured to transmit and/or receive wireless communications via one or more wireless technologies. For example, the communication device 100 may be compliant with one or more fifth generation (5G) "New Radio" cellular communication protocols, such as, for example, one or more 5G protocols as those skilled in the art will appreciate. It may be configured for suitable wireless communication. Communication device 100 is not limited to these communication protocols, and may be compliant with one or more protocols of the 3rd Generation Partnership Project (eg, Long-Term Evolution (LTE)), one or more wireless local area networking (WLAN) communication protocol, and/or one or more other communication protocols as will be understood by those skilled in the relevant arts. may be configured for alternative or alternative wireless and/or wireline communication protocols.

Communication device 100 may include, for example, one or more base stations, one or more access points, one or more other communication devices, and/or one or more others as will be understood by those skilled in the art. may be configured to communicate with one or more other communication devices, including devices of Although exemplary aspects of communication device 100 are described with respect to wireless communications, communication device 100 may be configured for one or more wired communication technologies as will be understood by those skilled in the art. .

In one exemplary aspect, communication device 100 includes controller 140 communicatively coupled to one or more transceivers 105 . Transceiver 105 is configured to transmit and/or receive wireless communications via one or more wireless technologies. In one exemplary aspect, transceiver 105 includes processor circuitry configured to transmit and/or receive wireless communications conforming to one or more wireless protocols. In other aspects, additionally or alternatively, transceiver 105 is configured to transmit and/or receive wired communications over one or more wired technologies. In one exemplary aspect, the processor circuitry of transceiver 105 is configured to transmit and/or receive wired communications conforming to one or more wired protocols.

In one exemplary aspect, the transceiver 105 includes a transmitter 110 and a receiver 120 that transmit multiple wireless communications via one or more antennas 130, respectively. and configured to receive In the wired communication aspect, transmitter 110 and receiver 120 are configured to transmit and receive wired communications, respectively.

In embodiments with two or more transceivers 105, those two or more transceivers 105 may have their own antenna 130 or share a common antenna via a duplexer. good too. In one exemplary aspect, transceiver 105 (including transmitter 110 and/or receiver 120) is capable of (e.g., media access control (MAC), encoding/decoding, modulation/demodulation , data symbol mapping, error correction, etc.).

In one exemplary aspect, transceiver 105 additionally includes clock generator 125, which is configured to generate one or more high precision synchronous clock signals. Those one or more clock signals may be used by one or more other components of transmitter 110, receiver 120, transceiver 105, controller 140, and/or one or more other components of communication device 100. May be used by elements. In one exemplary aspect, the clock generator 125 includes processor circuitry that performs one or more operations of the clock generator 125 including generation of one or more clock signals and/or configured to perform a function.

Antenna 130 may be a single antenna, may include multiple antennas, or may include one or more antenna elements forming an integer array of antenna elements. In one exemplary embodiment, antenna 130 is a phased array antenna that includes a plurality of radiating elements (multiple antenna elements), each of the plurality of radiating elements having a corresponding It has a phase adjuster. Antenna 130, configured as a phased array antenna, may be configured to perform one or more beamforming and/or beam scanning operations. These beamforming operations produce beams formed by phase-shifting the signals radiated from each radiating element to provide constructive/non-constructive interference, resulting in beams It may include steering in a desired direction.

In one exemplary aspect, controller 140 includes processor circuitry 150 configured to control overall operation of communication device 100, such as operation of one or more transceivers 105. be done. Processor circuitry 150 controls the transmission and/or reception of wireless communications by one or more of the transceivers 105 and/or phase shifts and/or amplifier gains associated with the antenna elements of antenna 130. It may be configured to control the value.

In one exemplary aspect, the processor circuit 150 cooperates with the transceiver 105 or instead of such operations/functions performed by the transceiver 105 (e.g., media access control (MAC), code encoding/decoding, modulation/demodulation, data symbol mapping, error correction, etc.). Processor circuitry 150, in one or more aspects, may be used to control one or more applications and/or operating systems, power management (e.g., battery control and monitoring), display settings, volume control, and/or (e.g., , keyboard, touch screen display, microphone, speaker, etc.).

In one exemplary aspect, controller 140 further includes memory 160 that stores data and/or instructions. When the instructions are executed by processor circuitry 150, processor circuitry 150 performs the associated functions described herein.

Memory 160 may be any well-known volatile and/or non-volatile memory, such as read-only memory (ROM), random-access It includes memory (RAM), flash memory, magnetic storage media, optical disks, erasable and programmable read-only memory (EPROM), and programmable read-only memory (PROM). Memory 160 may be non-removable, removable, or a combination of both. Controller 140 may additionally or alternatively be configured to access external memory to store data into or retrieve data from the external memory.

Multiple examples of communication device 100 include mobile computing devices such as (but not limited to) laptop computers, tablet computers, mobile phones or smart phones, "phablets," personal digital assistants (PDAs), and mobile media players. devices (mobile devices), wearable computing devices such as computerized watches or "smart" watches and computerized glasses, and/or Internet of Things (IoT) devices. In some of the aspects of the present disclosure, communication device 100 may be a non-handheld communication device, such as a personal computer (PC), desktop computer, television, smart home devices, security devices (e.g., electronic locks/smart locks, etc.), automated teller machines, computerized kiosks, self-driving vehicles, drones, and/or embedded computers in vehicles/aircraft/ships; Includes stationary computing devices such as terminals.

In one or more aspects, the communication device 100 or one or more components of the communication device 100 additionally or alternatively include digital signal processing (eg, using a digital signal processor (DSP)), modulation and/or demodulation (using a modulator/demodulator), digital-to-analog conversion (DAC) and/or analog-to-digital conversion (ADC) (using a DA converter and AD converter, respectively), (e.g. Use an encoder/decoder with convolutional encoder/decoder capability, tail-biting convolutional encoder/decoder capability, turbo encoder/decoder capability, Viterbi encoder/decoder capability, and/or low density parity check (LDPC) encoder/decoder capability ) encoding/decoding, frequency transform (e.g., using mixers, local oscillators, and filters), fast Fourier transform (FFT), precoding, and/or signal constellation mapping/signal inverse mapping, It is configured to receive and/or transmit multiple wireless communications conforming to one or more wireless protocols and/or to facilitate beamforming scan operations and/or beamforming communication operations.

FIG. 2A illustrates a clock generator 200 according to one exemplary aspect of this disclosure. FIG. 2B illustrates a clock generator 201 according to one exemplary aspect of this disclosure. Clock generators 200 and 201 may be implemented in communication device 100 as clock generator 125 in one or more aspects.

In one exemplary aspect, the clock generator 200/201 includes a phase-locked loop (PLL) 203 and a calibration circuit 205 configured to calibrate the clock generator 200/201. be. A reference clock signal generated by a reference clock oscillator 250, such as a crystal oscillator, may be provided to PLL 203 (eg, PLL 203 may be driven by the reference clock signal). Although the illustrated examples show oscillator 250 external to clock generator 200 and PLL 203, in one or more aspects oscillator 250 is included within clock generator 200. good too. In alternative embodiments, oscillator 250 is included within controller 140 or within other components of communication device 100 .

In one exemplary embodiment, the PLL 203 includes a time-to-digital converter (TDC) 210, a loop filter 215, a digital-to-time converter (DTC). 220 , a voltage-controlled oscillator (VCO) 225 , and an N-divider 230 . In one exemplary embodiment, loop filter 215 is configured to filter a digital output signal (eg, a 1-bit signal) of DTC 220 and generate a filtered signal that drives VCO 225. be done. In one exemplary aspect, VCO 225 is configured to generate one or more clock signals (F_vco) at one or more respective frequencies controlled by the filtered signal provided by loop filter 215. Configured.

In operation, the output clock signal of VCO 225 is fed back to N divider 230 . In one exemplary aspect, N divider 230 is configured to divide the output clock signal from VCO 225 by N to obtain a feedback signal (F_vco/N). The feedback signal is then provided to DTC 220 as shown in FIG. 2A or to TDC 210 as shown in FIG. 2B. For example, N divider 230 can be adjusted (eg, the value of N can be adjusted) based on an external frequency programming signal. In one exemplary aspect, N divider 230 is a frequency or fractional divider.

In one exemplary embodiment shown in FIG. 2A, clock generator 200 modulates VCO 225 output signal (F_vco/N) with DTC 220 in the feedback path of PLL 203 to It is configured to generate a modulated signal (F_mod). In an alternative embodiment of clock generator 200 illustrated in FIG. 2B, DTC 220 modulates a reference clock signal (F_ref) of reference clock oscillator 250 to generate a modulated reference clock signal (F_ref'). and provides a modulated reference clock signal (F_ref′) to TDC 210 . In one exemplary aspect, one or more of the plurality of components of PLL 203 includes processor circuitry, which processor circuitry operates one or more of the respective components of PLL 203 and/or configured to perform a function.

In one exemplary embodiment, TDC 210 is a bang-bang TDC, but is not so limited. In one exemplary embodiment illustrated in FIG. 2A, TDC 210 is configured to receive a reference clock signal (F_ref) generated by reference oscillator 250 and a modulated signal (F_mod) generated by DTC 220. be done. In this example, DTC 220 generates its modulated signal (F_mod) based on the feedback signal from VCO 225 being divided by N divider 230 . The TDC 210 can compare the reference clock signal and the DTC output signal and generate a digital output signal (eg, a 1-bit signal) based on the comparison of the reference clock signal and the DTC output signal. .

In one exemplary aspect, the TDC 210 measures a time interval of the reference clock signal and/or the feedback signal and compares the reference clock signal, the feedback signal, and/or the reference clock and feedback signals. to a digital output (eg, binary output). The digital output signal produced by TDC 210 is then provided from TDC 210 to loop filter 215 . In one exemplary aspect, the TDC 210 is configured to determine which signal edge it is (a reference signal edge or a DTC output signal edge). In this example, the output of TDC 210 is positive 1 (+1) when the reference edge is first and negative 1 (-1) when the TDC output signal edge is first.

In one exemplary aspect, calibration circuit 205 is configured to calibrate clock generator 200/201 to compensate for integral nonlinearity (INL) of DTC 220 of PLL 203 . Before correction, INL may be referred to as an inherent impairment of DTC220. After correction/pre-distortion, any remaining INL may be referred to as residual INL.

In one exemplary embodiment, the calibration circuit 205 includes a code ramp 235, a pre-distortion (PD) look-up table (LUT) 240, and a statistics processor. )245. In one exemplary aspect, one or more of the plurality of components of calibration circuit 205 includes a processor circuit that operates one or more of the respective components of calibration circuit 205. configured to perform operations and/or functions;

In one exemplary embodiment, code ramp 235 is configured to generate a desired DTC code (eg, code ramp) to control operation of PD-LUT 240 . In this example, PD-LUT 240 is configured to generate a control signal for DTC 220, such as modulation of a feedback signal (of FIG. 2A) or modulation of a reference clock signal (of FIG. 2B). ) control the modulation operation.

In one exemplary embodiment, statistics processor 245 receives (eg, samples) the output of TDC 210 and the output of the desired DTC code generated by code ramp 235. Configured. Statistical processor 245 determines a distribution (e.g., the histogram distribution shown in FIG. 3) of the TDC output signal, and based on the determined distribution (e.g., an offset It is configured to generate a correction signal (such as an offset value) to correct the control signal generated by the PD-LUT 240 . In one exemplary embodiment, the collection of statistics by statistics processor 245 is performed after VCO 225 has locked onto a frequency.

In one exemplary aspect, statistical processor 245 is configured to determine the distribution based on the received TDC output signal and the DTC code generated by code ramp 235 . In this example, statistical processor 245 counts the number of times the TDC output goes to −1 and the number of times the TDC output goes to +1 for the corresponding DTC code provided by code ramp 235 . From these statistics, statistics processor 245 is configured to adapt PD-LUT 240 using the determined adjustment/offset values. For example, a DTC code having a value of k will cause the output of the TDC 210 to have a 30:70 distribution (e.g., the TDC output will be -1 30% of the time and +1 70% of the time). , the PD-LUT 240 is corrected/adjusted by the statistical processor 245 to offset the output of the PD-LUT 240 so that the resulting TDC 210 approaches a 50:50 distribution and/or , to achieve a 50:50 distribution.

For example, if a DTC code has an integral nonlinearity (e.g., 5 [ps]) and (e.g., all of the noise in the system has a total RMS A DTC code will produce significant offsets between edges (at the input of the TDC 210) if its integral nonlinearity significantly exceeds the system jitter (such as reaching a jitter of ). As shown in FIG. 3, this causes the output of TDC 210 to almost always return a value of +1. This will produce the histogram distribution 303 shown in FIG.

Alternatively, if the DTC code has an integral nonlinearity whose value (such as 1 [ps]) is closer to the jitter (such as 0.5 [ps]), the output of the TDC 210 may be Returns +1 for the corresponding DTC code (due to Gaussian distribution of jitter), -1 otherwise. This scenario is illustrated in histogram distribution 301 of FIG.

That is, in scenarios where the integral nonlinearity is significantly greater than the RMS of the jitter, the statistical processor 245 is configured to detect the sign of the integral nonlinearity, but the magnitude of the integral nonlinearity and the RMS magnitude of the jitter Its magnitude is not detectable until the difference between is closer. When the difference between the magnitude of the integral nonlinearity and the RMS magnitude of the jitter becomes significantly smaller, the statistics processor 245 generates statistics on the output of the TDC 210 (eg, 30% −1s, 70% +1s, etc.). value may be determined. Based on these statistics, and as described in more detail below, statistical processor 245 is advantageously able to accurately calculate the magnitude of the integral nonlinearity.

In one exemplary aspect, statistical processor 245 is configured to perform a calibration process to adapt and tune PD-LUT 240 . The calibration process may include (1) a coarse correction process and/or (2) a fine correction process.

In one exemplary embodiment, the histogram distribution for a particular DTC code exhibits both positive and negative integral nonlinearity values when the integral nonlinearity is significantly greater than the RMS of the jitter. Until then, statistical processor 245 may employ a coarse correction process. Statistics processor 245 may then employ a fine correction process. The coarse correction process and the fine correction process are described in detail below.

Coarse Correction Process In one exemplary aspect, (e.g., if the jitter distribution has only positive inertial nonlinearity values or negative inertial nonlinearity values), Statistical processor 245 iteratively performs a coarse correction ( . The coarse correction process will be described with reference to FIG.

FIG. 4 illustrates a flowchart 400 of a coarse correction method according to one exemplary aspect of this disclosure. The flowchart 400 is described with reference to FIGS. 1-3.

Flowchart 400 begins at operation 405 and transitions to operation 410 where the sign of the integral nonlinearity (INL) is determined. In one exemplary embodiment, code ramp 235 and PD-LUT 240 perform a calibration sequence in which PD-LUT 240 produces an output corresponding to the desired DTC codeword. Statistics processor 245 then records the output of TDC 210 . This output recording is repeated until the statistical processor 245 obtains a sufficient number of records to determine the sign of the INL. In one exemplary aspect, statistical processor 245 is configured to control code ramp 235 and PD-LUT 240 to perform a calibration sequence.

After operation 410, flowchart 400 transitions to operation 415 where PD-LUT 240 is updated based on the determined sign of INL. In this example, statistical processor 245 adjusts the output of PD-LUT 240 (ie, PD code) based on its determined sign of INL. For example, if the DTC code produces more +1 results from the TDC 210, then decrease the PD code. Alternatively, increase the PD code if the DTC code produces more -1 results from the RDC 210 . Here, the INL remaining after that adjustment is referred to as the residual INL.

After operation 415, the flowchart 400 transitions to operation 420, in which additional statistics for the DTC code are obtained (eg, by the statistics processor 245) and their distributions are calculated (eg, by the statistics processor 245). analyse. In one exemplary embodiment, PD-LUT 240 produces output corresponding to the desired DTC codeword, and statistics processor 245 records the TDC 210 output. This recording of output is repeated until a sufficient number of records have been obtained by the statistics processor 245 .

After operation 420, the flowchart 400 transitions to operation 425, where the INL (eg, residual INL) is determined (eg, whether (INL value)≈(jitter range)). Determine if the value is within the jitter range. In one exemplary embodiment, (e.g., by statistical processor 245) (e.g., PD-LUT 240 output toggles around the optimal value), TDC 210 output is 50: Histogram distribution for a particular DTC code has a positive integral nonlinearity value and a negative integral nonlinearity value, such as approaching a distribution of 50 and/or achieving a 50:50 distribution. Determines whether to generate both negative integral nonlinearity values.

If operation 425 is affirmative (Yes), flowchart 400 transitions to operation 430 and flowchart 400 ends. Otherwise (No at operation 425), the flowchart 400 returns to operation 410 and the method repeats through the iterative process.

Fine Correction Process The fine correction process will be described with reference to FIG. 5, which illustrates a flowchart 500 of a fine correction method. In one exemplary embodiment, the INL value lies within the jitter range (eg, (INL value)≈(jitter range)) such that the histogram distribution for a particular DTC code is , produces both positive and negative integral nonlinearity values, and performs the fine correction process when the TDC 210 output approaches and/or achieves a 50:50 distribution. Execute. The coarse correction process and the fine correction process may be performed continuously or (e.g., if the DTC code produces both positive and negative integral nonlinearity values, the INL value may be jittered). The fine correction process may be performed without previously performing the coarse correction process (if, for example, within the range).

In one exemplary aspect, the statistics processor 245 is configured to determine a fractional value of the PD-LUT (this determined fractional value is later subjected to rounding or dithering). may be used for dithering). In this example, the two nearest integer values (lower and upper values) for PD-LUT 240 are known as the desired DTC code. This desired DTC code may be known, for example, based on the adjustment of PD-LUT 240 in the coarse correction process.

In one exemplary aspect, statistical processor 245 is configured to control PD-LUT 240 and code ramp 235 to drive DTC 220 by their two closest integer values. The statistics processor 245 then collects the statistics and calculates when smaller integer values (lower bound/floor values) are used to tune the PD-LUT 240. Determine the number of DTC210 output values of +1 and DTC210 output values of -1 (operation 510), the larger integer value (upper bound/ceiling value) used to tune the PD-LUT240. Determines the number of DTC 210 output values of +1 and DTC 210 output values of -1, when done (operation 515).

を使用して決定される。
上記の式において、
LUT_PD(C)は、下限値/床値であり、
Q^－1(・)は、逆Q関数であり、
f_－1は、下限値/床値を伝送するときに受信する－1[s]の数であり、
f_＋1は、下限値/床値を伝送するときに受信する＋1[s]の数であり、
c_－1は、上限値/天井値を伝送するときに受信する－1[s]の数であり、
c_＋1は、上限値/天井値を伝送するときに受信する＋1[s]の数である。 Based on the determined number, determine the fractional value of the corrected signal for statistical processor 245 (operation 520). In one exemplary aspect, the LUT _fractional (C) is the formula

is determined using
In the above formula,
LUT _PD (C) is the lower/floor value,
Q ⁻¹ (・) is the inverse Q function,
f _-1 is the number of -1 [s] received when transmitting the lower limit/floor value,
f ₊₁ is the number of +1 [s] received when transmitting the lower limit/floor value,
c _-1 is the number of -1 [s] received when transmitting the upper limit/ceiling value,
c ₊₁ is the number of +1 [s] received when transmitting the upper limit/ceiling value.

Advantageously, the fractional value determination can be determined according to several exemplary aspects without requiring knowledge of jitter/sigma/RMS. However, as will be appreciated by those skilled in the art, the fractional value calculations are not limited to these exemplary aspects.

In one example, when the jitter is very small compared to the DTC resolution, the clock generator 200 increases the number of samples (ie, the number of statistics obtained) and/or increases the jitter sigma. may be configured to Increased jitter sigma may be achieved by decreasing the bandwidth of loop filter 215 . In this example, a decrease in bandwidth would increase VCO jitter.

In one exemplary embodiment, an initial calibration of PLL 203 can be performed to correct for INL due to production variations (ie, production induced INL). This initial calibration can use both coarse and fine corrections. An online calibration can then be performed to compensate for environmental changes (eg, temperature) or changes in the frequency of the VCO, and the like. Considering that adjustments during on-line calibration are likely to be minimal, only fine corrections are most likely required, and coarse corrections can be employed if necessary.

Examples The following examples relate to several further aspects.

Example 1 is a clock generator calibration system comprising:
a phased-locked loop (PLL) configured to generate an output clock signal;
a correction circuit configured to adjust the frequency signal of the PLL based on the digital signal of the PLL, the digital signal being generated based on the frequency signal being adjusted. clock generator calibration system.

Example 2 is the subject of Example 1, wherein said frequency signal is a reference clock signal and said output clock signal is generated based on said reference clock signal.

Example 3 is the subject of Example 1, wherein said frequency signal corresponds to said output clock signal and said frequency signal is a feedback signal into said PLL.

Example 4 is the subject of any of Examples 1-3, wherein the PLL comprises:
a time-to-digital converter configured to generate the digital signal, wherein the output clock signal is generated based on the digital signal; and ,
a digital-to-time converter configured to generate the adjusted frequency signal based on the digital signal.

Example 5 is the subject of any of Examples 1-4, wherein the correction circuit is configured to determine a statistic of the value of the digital signal, and the adjustment of the frequency signal is the determined Based on statistics.

Example 6 is the subject of any of Examples 1-5, wherein the correction circuit comprises:
a code ramp configured to generate code;
a statistics processor configured to generate a correction signal based on the code being generated and the digital signal;
A pre-distortion lookup table (PD-LUT) configured to generate a control signal, the control signal based on the correction signal and the code being generated to: a predistortion lookup table that controls the adjustment of the frequency signal.

Example 7 is the subject of any of Examples 1 and 3-6, the PLL comprising:
a time-to-digital converter configured to generate the digital signal based on the frequency signal being adjusted and a reference signal;
a controlled oscillator configured to generate the output clock signal based on the digital signal, wherein the frequency signal is based on the output clock signal; ,
A digital-to-time converter in the feedback loop of the PLL, wherein the digital-to-time converter is configured to receive the frequency signal via the feedback loop. and a digital-to-time converter configured to generate the adjusted frequency signal based on the digital signal.

Example 8 is the subject of any of Examples 1, 2, and 4-6, wherein the PLL comprises:
a time-to-digital converter configured to generate the digital signal based on a feedback signal associated with the output clock signal and the adjusted frequency signal;
a controlled oscillator configured to generate the output clock signal based on the digital signal;
a digital-to-time converter configured to receive the frequency signal and configured to generate the adjusted frequency signal based on the digital signal; and a digital-to-time converter, wherein the frequency signal is a reference clock signal.

Example 9 is the subject of any of Examples 1-8, the correction circuit comprising:
a code ramp configured to generate code;
a statistics processor configured to generate a correction signal based on the generated code and the digital signal;
a pre-distortion lookup table (PD-LUT) configured to generate a control signal and to provide the control signal to the digital-to-time converter ), wherein the control signal controls the adjustment of the frequency signal by the digital-to-time converter based on the correction signal and the generated code.

Example 10 is the subject of any of Examples 4-8, wherein the time-to-digital converter is a bang-bang time-to-digital converter.

Example 11 is the subject of Example 9 and the time-to-digital converter is a bang-bang time-to-digital converter.

Example 12 is a non-transitory computer-readable storage medium storing an executable computer program, the program comprising:
generating an output clock signal based on the reference clock signal by a phased-locked loop (PLL); and
non-transitory computer readable memory for adjusting a frequency signal of the PLL based on the digital signal of the PLL, the digital signal being generated based on the frequency signal being adjusted is a medium.

Example 13 is the subject of Example 12, wherein said frequency signal is a reference clock signal and said output clock signal is generated based on said reference clock signal.

Example 14 is the subject of Example 12, wherein said frequency signal corresponds to said output clock signal and said frequency signal is a feedback signal into said PLL.

Example 15 is the subject of any of Examples 12-14, the PLL comprising:
a time-to-digital converter configured to generate the digital signal, wherein the output clock signal is generated based on the digital signal; and ,
a digital-to-time converter configured to generate the adjusted frequency signal based on the digital signal.

Example 16 is the subject of any of Examples 12-15, the program further instructing the processor to determine a statistic of the values of the digital signal, wherein the adjustment of the frequency signal comprises: , based on the determined statistics.

Example 17 is the subject of any of Examples 12-16, wherein the frequency signal is adjusted using a correction circuit, the correction circuit comprising:
a code ramp configured to generate code;
a statistics processor configured to generate a correction signal based on the code being generated and the digital signal;
A pre-distortion lookup table (PD-LUT) configured to generate a control signal, the control signal based on the correction signal and the code being generated to: a predistortion lookup table that controls the adjustment of the frequency signal.

Example 18 is the subject of any of Examples 12 and 14-17, the PLL comprising:
a time-to-digital converter configured to generate the digital signal based on the frequency signal being adjusted and a reference signal;
a controlled oscillator configured to generate the output clock signal based on the digital signal, wherein the frequency signal is based on the output clock signal; ,
A digital-to-time converter in the feedback loop of the PLL, wherein the digital-to-time converter is configured to receive the frequency signal via the feedback loop. and a digital-to-time converter configured to generate the adjusted frequency signal based on the digital signal.

Example 19 is the subject of any of Examples 12, 13, and 15-17, the PLL comprising:
a time-to-digital converter configured to generate the digital signal based on a feedback signal associated with the output clock signal and the adjusted frequency signal;
a controlled oscillator configured to generate the output clock signal based on the digital signal;
a digital-to-time converter configured to receive the frequency signal and configured to generate the adjusted frequency signal based on the digital signal; and a digital-to-time converter, wherein the frequency signal is a reference clock signal.

Example 20 is the subject of any of Examples 18-19, wherein the frequency signal is adjusted using a correction circuit, the correction circuit comprising:
a code ramp configured to generate code;
a statistics processor configured to generate a correction signal based on the generated code and the digital signal;
a pre-distortion lookup table (PD-LUT) configured to generate a control signal and to provide the control signal to the digital-to-time converter ), wherein the control signal controls the adjustment of the frequency signal by the digital-to-time converter based on the correction signal and the generated code.

Example 21 is a communication device comprising a clock generator calibration system according to any of claims 1-11.

Example 22 is the subject of Example 21, wherein the clock generator calibration system is included in the transceiver of the communication device.

Example 23 is a clock generator calibration method comprising:
generating an output clock signal based on the reference clock signal with a phased-locked loop (PLL);
adjusting a frequency signal of the PLL based on the digital signal of the PLL, wherein the digital signal is generated based on the frequency signal being adjusted. The method.

Example 24 is the subject of Example 23, wherein said frequency signal is a reference clock signal and said output clock signal is generated based on said reference clock signal.

Example 25 is the subject of Example 23, wherein said frequency signal corresponds to said output clock signal and said frequency signal is a feedback signal into said PLL.

Example 26 is the subject of any of Examples 23-25, the PLL comprising:
a time-to-digital converter configured to generate the digital signal, wherein the output clock signal is generated based on the digital signal; and ,
a digital-to-time converter configured to generate the adjusted frequency signal based on the digital signal.

Example 27 is the subject of any of Examples 23-26, further comprising determining a statistic of values of the digital signal, wherein the adjustment of the frequency signal is based on the determined statistic. ing.

Example 28 is the subject of any of Examples 23-27, wherein the frequency signal is adjusted using a correction circuit, the correction circuit comprising:
a code ramp configured to generate code;
a statistics processor configured to generate a correction signal based on the code being generated and the digital signal;
A pre-distortion lookup table (PD-LUT) configured to generate a control signal, the control signal based on the correction signal and the code being generated to: a predistortion lookup table that controls the adjustment of the frequency signal.

Example 29 is the subject of any of Examples 23 and 25-28, the PLL comprising:
a time-to-digital converter configured to generate the digital signal based on the frequency signal being adjusted and a reference signal;
a controlled oscillator configured to generate the output clock signal based on the digital signal, wherein the frequency signal is based on the output clock signal; ,
A digital-to-time converter in the feedback loop of the PLL, wherein the digital-to-time converter is configured to receive the frequency signal via the feedback loop. and a digital-to-time converter configured to generate the adjusted frequency signal based on the digital signal.

Example 30 is the subject of any of Examples 23, 24, and 26-28, wherein the PLL comprises:
a time-to-digital converter configured to generate the digital signal based on a feedback signal associated with the output clock signal and the adjusted frequency signal;
a controlled oscillator configured to generate the output clock signal based on the digital signal;
a digital-to-time converter configured to receive the frequency signal and configured to generate the adjusted frequency signal based on the digital signal; and a digital-to-time converter, wherein the frequency signal is a reference clock signal.

Example 31 is the subject of any of Examples 29-30, wherein the frequency signal is adjusted using a correction circuit, the correction circuit comprising:
a code ramp configured to generate code;
a statistics processor configured to generate a correction signal based on the generated code and the digital signal;
a pre-distortion lookup table (PD-LUT) configured to generate a control signal and to provide the control signal to the digital-to-time converter ), wherein the control signal controls the adjustment of the frequency signal by the digital-to-time converter based on the correction signal and the generated code.

Example 32 is a non-transitory computer-readable storage medium storing an executable computer program, the program instructing a processor to perform the operations of any of Examples 23-31. instruct.

Example 33 is a computer program product comprising a computer program directly loadable into the memory of a controller, which, when executed by said controller, causes said controller to perform the operations of any of Examples 23-31. Let

Example 34 is the device shown and described.

Example 35 is the method shown and described.

Example 36 is a non-transitory computer-readable storage medium containing an executable computer program that directs a processor to carry out the method of Example 35.

CONCLUSION The above description of certain aspects may be used by others, by applying the knowledge of those of ordinary skill in the art, without undue experimentation and without departing from the general concepts of this disclosure. It will be sufficient to make clear the general nature of the disclosure that such specific aspects can be readily modified and/or adapted for any application. Therefore, such adaptations and modifications are intended to be within the meaning and range of equivalents of the disclosed aspects, based on the teaching and advice presented herein. be. The phrases or terminology herein are for the purpose of description and are not intended to be limiting, and, as a result, the phrases or terminology herein are intended to be appropriate in light of their teachings and advice. It should be understood that it should be interpreted by the trader.

References in the specification to "an embodiment," "an embodiment," "an exemplary embodiment," etc., imply that the embodiment being described refers to a particular feature, structure, or property. , but not necessarily all aspects include that particular feature, structure, or property. Moreover, such phrases are not necessarily referring to the same aspect. Furthermore, also, when a particular feature, structure, or characteristic is described in relation to one aspect, it may also be , it is noted that it is within the knowledge of one skilled in the art to affect such features, structures, or properties.

The several exemplary aspects thereof described herein are provided for illustrative purposes and are not intended to be limiting. Other example aspects are possible and modifications may be made to those example aspects. Accordingly, the specification is not intended to limit the disclosure. Rather, the scope of the disclosure is defined solely in accordance with the inventions set forth in the following claims and their equivalents.

Aspects may be implemented by hardware (eg, circuits), firmware, software, or any combination thereof. Aspects may also be implemented as instructions stored on a machine-readable medium, which may be read and executed by one or more processors. A machine-readable medium may include any mechanism for storing or transmitting information in a form readable by a machine (eg, a computing device, etc.). For example, machine-readable media include read-only memory (ROM), random-access memory (RAM), magnetic disk storage media, optical storage media, flash memory devices, and (e.g., carrier waves, infrared signals, digital signals, etc.). ) may include electrical, optical, acoustic or other forms of propagating signals, and the like. Further, firmware, software, routines, instructions may be described herein as performing certain actions. However, such description is for convenience only, and in fact such operations may be performed on any computing device, processor, controller, or other device executing firmware, software, routines, instructions, etc. It should be understood that the Moreover, any of the multiple implementation variations may also be performed by a general-purpose computer.

For the purposes of this description, the term "processor circuitry" should be understood as one or more circuits, one or more processors, logic, or a combination thereof. For example, a circuit may include analog circuitry, digital circuitry, state machine logic, data processing circuitry, programmable processing circuitry, other structural electronic hardware, or combinations thereof. A processor may include a microprocessor, a digital signal processor (DSP), a central processor (CPU), an application specific instruction set processor (ASIP), a graphics and/or image processor, a multi-core processor, or other hardware processor. A processor may be "hard-coded" with instructions that perform one or more corresponding functions in accordance with the aspects described herein. Alternatively, the processor may access internal and/or external memory to retrieve instructions stored within that memory, which instructions, when executed by the processor, may be to perform one or more corresponding functions associated with the processor and/or one or more functions and/or operations associated with the operation of components having the processor embedded therein.

In one or more of the exemplary aspects described herein, processor circuitry may include memory to store data and/or instructions. The memory may be, for example, read-only memory (ROM), random-access memory (RAM), flash memory, magnetic storage media, optical discs, erasable and programmable read-only memory (EPROM), and programmable read-only memory. It may be any well-known volatile and/or non-volatile memory (including PROM). The memory may be non-removable memory, removable memory, or a combination of both.

As would be apparent to one of ordinary skill in the art based on the teachings herein, the exemplary aspects are not limited to the communication protocols described herein. These exemplary aspects may be applied to other wireless communication protocols/standards (e.g., LTE or other cellular protocols, other IEEE 802.11 protocols, etc.) as will be appreciated by those skilled in the art. .

Claims (26)

A clock generator calibration system comprising:
a phase-locked loop (PLL) configured to generate an output clock signal;
a correction circuit configured to adjust the frequency signal of the PLL based on the digital signal of the PLL, the digital signal being generated based on the frequency signal being adjusted.
Clock generator calibration system. 2. The clock generator calibration system of claim 1, wherein the frequency signal is a reference clock signal and the output clock signal is generated based on the reference clock signal. 2. The clock generator calibration system of claim 1, wherein said frequency signal corresponds to said output clock signal, said frequency signal being a feedback signal into said PLL. The PLL is
a time-to-digital converter configured to generate the digital signal, wherein the output clock signal is generated based on the digital signal;
and a digital-to-time converter configured to generate the adjusted frequency signal based on the digital signal. calibration system. 5. Any one of claims 1 to 4, wherein the correction circuit is configured to determine a statistic of the values of the digital signal, and the adjustment of the frequency signal is based on the determined statistic. A clock generator calibration system as described in Clause. The correction circuit is
a code lamp configured to generate a code;
a statistical processor configured to generate a correction signal based on the code being generated and the digital signal;
A predistortion lookup table (PD-LUT) configured to generate a control signal, the control signal performing the adjustment of the frequency signal based on the correction signal and the code being generated. 6. A clock generator calibration system according to any preceding claim, comprising a controlling predistortion lookup table. The PLL is
a time-to-digital converter configured to generate the digital signal based on the frequency signal being adjusted and a reference signal;
a controlled oscillator configured to generate the output clock signal based on the digital signal, wherein the frequency signal is based on the output clock signal;
A digital-to-time converter in the feedback loop of the PLL, the digital-to-time converter configured to receive the frequency signal via the feedback loop and to convert the digital signal into and a digital-to-time converter configured to generate the frequency signal being adjusted based on system. The PLL is
a time-to-digital converter configured to generate the digital signal based on a feedback signal associated with the output clock signal and the adjusted frequency signal;
a controlled oscillator configured to generate the output clock signal based on the digital signal;
a digital-to-time converter configured to receive the frequency signal and configured to generate the adjusted frequency signal based on the digital signal, the frequency signal being a reference 7. A clock generator calibration system according to any one of claims 1, 2 and 4-6, comprising a clock signal, a digital-to-time converter. The correction circuit is
a code lamp configured to generate a code;
a statistical processor configured to generate a correction signal based on the generated code and the digital signal;
a predistortion lookup table (PD-LUT) configured to generate a control signal and provide the control signal to the digital-to-time converter, the control signal being the correction signal and the 9. A clock generator calibration system according to any preceding claim, controlling the adjustment of the frequency signal by the digital-to-time converter based on the generated code. 9. A clock generator calibration system according to any one of claims 4-8, wherein the time-to-digital converter is a bang-bang time-to-digital converter. A communication device comprising a clock generator calibration system according to any of claims 1-10. An executable computer program, wherein when the executable computer program is executed by a processor, the executable computer program causes the processor to:
generating an output clock signal based on the reference clock signal by a phase-locked loop (PLL); and
adjusting a frequency signal of the PLL based on the digital signal of the PLL, the digital signal being generated based on the frequency signal being adjusted;
executable computer program. 13. The executable computer program product of claim 12, wherein the frequency signal is a reference clock signal and the output clock signal is generated based on the reference clock signal. 13. The executable computer program product of claim 12, wherein said frequency signal corresponds to said output clock signal, said frequency signal being a feedback signal into said PLL. The PLL is
a time-to-digital converter configured to generate the digital signal, wherein the output clock signal is generated based on the digital signal;
and a digital-to-time converter configured to generate the adjusted frequency signal based on the digital signal. computer program. 3. The executable computer program further instructs the processor to determine a statistic of the value of the digital signal, and wherein the adjustment of the frequency signal is based on the determined statistic. 16. An executable computer program product according to any one of claims 12-15. The frequency signal is adjusted using a correction circuit, the correction circuit comprising:
a code lamp configured to generate a code;
a statistical processor configured to generate a correction signal based on the code being generated and the digital signal;
A predistortion lookup table (PD-LUT) configured to generate a control signal, the control signal performing the adjustment of the frequency signal based on the correction signal and the code being generated. 17. An executable computer program as claimed in any one of claims 12 to 16, comprising a controlling predistortion lookup table. The PLL is
a time-to-digital converter configured to generate the digital signal based on the frequency signal being adjusted and a reference signal;
a controlled oscillator configured to generate the output clock signal based on the digital signal, wherein the frequency signal is based on the output clock signal;
A digital-to-time converter in the feedback loop of the PLL, the digital-to-time converter configured to receive the frequency signal via the feedback loop and to convert the digital signal into and a digital-to-time converter configured to generate the adjusted frequency signal based on program. The PLL is
a time-to-digital converter configured to generate the digital signal based on a feedback signal associated with the output clock signal and the adjusted frequency signal;
a controlled oscillator configured to generate the output clock signal based on the digital signal;
a digital-to-time converter configured to receive the frequency signal and configured to generate the adjusted frequency signal based on the digital signal, the frequency signal being a reference 18. An executable computer program product according to any one of claims 12, 13 and 15-17, comprising a clock signal, a digital-to-time converter. The frequency signal is adjusted using a correction circuit, the correction circuit comprising:
a code lamp configured to generate a code;
a statistical processor configured to generate a correction signal based on the generated code and the digital signal;
a predistortion lookup table (PD-LUT) configured to generate a control signal and provide the control signal to the digital-to-time converter, the control signal being the correction signal and the 20. An executable computer program as claimed in any one of claims 18 to 19, for controlling said adjustment of said frequency signal by said digital-to-time converter based on said generated code. A clock generator calibration system comprising:
a phase-locked loop (PLL) that generates an output clock signal;
correction means for adjusting the frequency signal of the PLL based on the digital signal of the PLL, wherein the digital signal is generated based on the frequency signal being adjusted;
Clock generator calibration system. 22. The clock generator calibration system of claim 21, wherein said frequency signal is a reference clock signal and said output clock signal is generated based on said reference clock signal. 22. The clock generator calibration system of claim 21, wherein said frequency signal corresponds to said output clock signal, said frequency signal being a feedback signal into said PLL. The PLL is
a time-to-digital converter for generating the digital signal, wherein the output clock signal is generated based on the digital signal;
24. A clock generator calibration system according to any one of claims 21 to 23, comprising a digital-to-time converter for generating said adjusted frequency signal based on said digital signal. said correction means determining a statistic of the values of said digital signal, said adjustment of said frequency signal being based on said determined statistic;
The corrective means are
a code lamp for generating code;
a statistical processor that generates a correction signal based on the code being generated and the digital signal;
A predistortion lookup table (PD-LUT) that generates a control signal, the control signal controlling the adjustment of the frequency signal based on the correction signal and the code being generated. 25. A clock generator calibration system as claimed in any one of claims 21 to 24, comprising a lookup table. A non-transitory computer readable storage medium storing an executable computer program according to any one of claims 12-20.

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