JP2023173353A - Delay analysis system, delay analysis method, and delay analysis program - Google Patents

Abstract

To analyze a delay of a host machine with higher accuracy.SOLUTION: A delay analysis system includes: a host machine that executes both a virtualized controller and a host communication unit which manages communication between the controller and another apparatus; and a delay analysis device that inputs a delay investigation packet for measuring a delay of processing of the host machine, into the host machine, analyzes the delay investigation packet processed by the host machine, and measures the delay of processing of the host machine. The controller processes the delay investigation packet, writes a time stamp on the delay investigation packet, and outputs the packet to the host communication unit. The host communication unit processes the delay investigation packet, writes a time stamp on the delay investigation packet, and outputs the packet to the delay analysis device. The delay analysis device calculates processing time for each unit, based on the time stamp of the controller and the time stamp of the host communication unit which are written on the delay investigation packet.SELECTED DRAWING: Figure 3

Description

The present disclosure relates to a delay analysis system, a delay analysis method, and a delay analysis program.

As a device that controls the operation of a controlled object, there is a host machine (control device) that uses a virtualization controller that virtualizes a plurality of control functions in one calculation unit. The control device executes multiple control functions using multiple control software of multiple virtualization controllers, and transfers data of multiple virtualization controllers to a virtualization control unit of operating system software (OS (Operating System) software) or It is processed on the OS or by virtualization software (hypervisor, etc.) independent of the OS, and outputs a control signal to the device to be controlled (see Patent Document 1). Furthermore, Patent Document 1 describes predicting the load of a plurality of virtualized controls and performing load distribution processing.

JP 2020-201953 Publication

Here, even if processing is performed to distribute the load, the efficiency of the virtualization controller may not be improved. Here, as a process for evaluating the communication delay of the Internet communication network, there is a method of monitoring the processing in each part using a separate monitoring device. When a monitoring device is provided with a virtualization controller, a certain processing load is generated on the host machine, and the evaluation is performed in a state different from the actual processing state.

The present disclosure has been made in view of the above problems, and aims to provide a delay analysis system, a delay analysis method, and a delay analysis program that can analyze the delay of a host machine with higher accuracy.

The present disclosure provides a host machine that executes a virtualized controller, a host communication unit that manages communication between the controller and other devices, and a delay investigation packet that measures processing delays of the host machine. a delay analysis device that measures a processing delay of the host machine by analyzing a delay investigation packet input to the host machine and processed by the host machine; The host communication unit processes the packet and writes a timestamp into the delay checking packet and outputs it to the host communication unit, and the host communication unit processes the delay checking packet and writes the timestamp into the delay checking packet. The delay analyzer calculates the processing time of each unit based on the time stamp of the controller and the time stamp of the host communication unit written in the delay investigation packet. We provide a delay analysis system that calculates

The present disclosure is a delay analysis method that uses a delay measurement device to analyze a delay in control of a host machine that executes a virtualized controller and a host communication unit that manages communication between the controller and other devices. , inputting a delay checking packet to the host machine to measure the processing delay of the host machine; and the controller processing the delay checking packet and writing a timestamp to the delay checking packet. , a step of outputting the delay check packet to the host communication unit; a step of the host communication unit processing the delay check packet, writing a timestamp to the delay check packet, and outputting the same to the delay analysis device; A delay analysis method is provided, which includes the step of calculating the processing time of each unit based on the time stamp of the controller and the time stamp of the host communication unit written in a delay investigation packet.

The present disclosure provides a delay analysis system that uses a delay measurement device to analyze a delay in control of a host machine that executes a virtualized controller and a host communication unit that manages communication between the controller and other devices. inputting a delay checking packet for measuring a processing delay of the host machine into the host machine; the controller processing the delay checking packet and writing a timestamp to the delay checking packet; outputting to a host communication unit; the host communication unit processing the delay investigation packet, writing a timestamp to the delay investigation packet, and outputting it to the delay analyzer; and the delay investigation A delay analysis program is provided that executes the step of calculating the processing time of each unit based on the time stamp of the controller and the time stamp of the host communication unit written in the packet.

With the above configuration, it is possible to analyze the delay of the host machine with higher accuracy.

FIG. 1 is a block diagram showing an example of the configuration of a delay analysis system. FIG. 2 is a block diagram showing an example of the functional configuration of the delay analysis system. FIG. 3 is an explanatory diagram showing an example of processing of the delay analysis system. FIG. 4 is an explanatory diagram showing an example of the data structure of a delay investigation packet. FIG. 5 is an explanatory diagram conceptually showing an example of delay time evaluation. FIG. 6 is an explanatory diagram conceptually showing an example of delay time evaluation. FIG. 7 is an explanatory diagram conceptually showing an example of evaluation of delay time. FIG. 8 is an explanatory diagram conceptually showing an example of delay time evaluation. FIG. 9 is an explanatory diagram showing an example of processing of the delay analysis system. FIG. 10 is an explanatory diagram showing an example of processing of the delay analysis system.

Embodiments according to the present disclosure will be described in detail below based on the drawings. Note that the present invention is not limited to this embodiment. Furthermore, the constituent elements in the embodiments described below include those that can be easily replaced by those skilled in the art, or those that are substantially the same. Furthermore, the constituent elements described below can be combined as appropriate, and if there are multiple embodiments, it is also possible to combine each embodiment.

FIG. 1 is a block diagram showing an example of the configuration of a delay analysis system. The delay analysis system 10 includes a host machine 12, a delay analysis device 14, and a synchronization device 16. The delay analysis system 10 analyzes the processing time of each part of the host machine 12 using a delay analysis device 14.

The host machine 12 executes the function of a virtualization controller that executes multiple controls. The host machine 12 communicates with the device to be controlled, and outputs a control signal generated by the virtualization controller to the device to be controlled. The host machine 12 includes a calculation section 20, a storage section 22, and a communication section 24.

The calculation unit 20 includes an integrated circuit (processor) such as a CPU (Central Processing Unit) or a GPU (Graphics Processing Unit), and a memory serving as a work area, and can execute various programs using these hardware resources. Execute various processing by. Specifically, the arithmetic unit 20 reads a program stored in the storage unit 22, loads it into the memory, and causes the processor to execute instructions included in the program loaded in the memory, thereby executing various processes.

The storage unit 22 is made of a nonvolatile storage device such as a magnetic storage device or a semiconductor storage device, and stores various programs and data. The communication unit 24 uses a communication interface to transmit data. The communication unit 24 transmits various data and programs acquired through communication with external devices to the storage unit 22 and stores them therein. The communication unit 24 may be connected to an external device via a wired communication line or may be connected to an external device via a wireless communication line.

The delay analysis device 14 is a device that acquires information on the processing time of each section executed inside the host machine 12 and analyzes the occurrence of processing delays. The delay analysis device 14 includes an input section 30, an output section 32, a calculation section 34, a storage section 36, and a communication section 38.

The input unit 30 includes an input device such as a keyboard and mouse, a touch panel, or a microphone that collects speech from an operator, and outputs a signal corresponding to an operation performed by the operator on the input device to the calculation unit 34. The output unit 32 includes a display device such as a display, and displays a screen containing various information such as processing results and images to be processed based on the display signal output from the calculation unit 34. Furthermore, the output unit 32 may include a recording device that outputs data on a recording medium. The communication unit 38 transmits and receives data using a communication interface.

The calculation unit 34 includes an integrated circuit (processor) such as a CPU (Central Processing Unit) or a GPU (Graphics Processing Unit), and a memory serving as a work area, and can execute various programs using these hardware resources. Execute various processing by. Specifically, the arithmetic unit 34 reads a program stored in the storage unit 36, loads it into the memory, and causes the processor to execute instructions included in the program loaded in the memory, thereby executing various processes.

The storage unit 36 is composed of a nonvolatile storage device such as a magnetic storage device or a semiconductor storage device, and stores various programs and data. The communication unit 38 sends various data and programs acquired through communication with external devices to the storage unit 36 and stores them therein. The communication unit 38 may be connected to an external device via a wired communication line or may be connected to an external device via a wireless communication line.

The synchronizer 16 communicates with the host machine 12 and the delay analyzer 14, and synchronizes the time functions of the host machine 12 and the delay analyzer 14. The synchronizer 16 synchronizes the time functions of the host machine 12 and the delay analyzer 14 using a high precision absolute time synchronization method such as PTP (Precision Time Protocol). Software (program) for time synchronization is input to the host machine 12 and the delay analysis device 14 based on information acquired from the synchronization device 16, and synchronization processing is performed.

FIG. 2 is a block diagram showing an example of the functional configuration of the delay analysis system. The host machine 12 includes a plurality of virtualization controllers 40 , a virtualization host OS section 42 , and a NIC (Network Interface Card) 44 . Here, the virtualized OS refers to a host OS that has a virtualization control unit, or system software that includes virtualization software (such as a hypervisor) that is independent of the host OS. The plurality of virtualization controllers 40 and the virtualization host OS unit 42 are functions that are realized by executing programs stored in the storage unit 22 in the calculation unit 20. The NIC 44 is a function realized by the communication unit 24. The NIC 44 serves as a host communication unit that manages communication between the virtualization controller 40 and other devices.

The virtualization controller 40 includes a plurality of control software 50, a delay investigation packet transmission program 51, and a communication interface 52. In this embodiment, there is a plurality of control software 50, but there may be only one. Furthermore, the control software 50 executed by each virtualization controller 40 may be the same or different.

The control software 50 is a program that executes functions set in the virtualization controller 40. The plurality of control software 50 executes respective functions and realizes a function as a controller. The control software 50 executes processing based on the data acquired via the virtualization host OS unit 42 and outputs the calculated control information. The virtualization controller 40 may process a plurality of control software 50 in parallel or in conjunction with each other.

The delay investigation packet transmission program 51 is a program that creates and transmits a delay investigation packet used to measure the processing delay of the host machine 12. The delay investigation packet transmission program 51 serves as an investigation packet creation section. The delay investigation packet includes an instruction for executing processing for measuring processing delays of the host machine 12, and an area for storing information for evaluating delays acquired by each section. The delay checking packet transmission program 51 creates a delay checking packet that causes the virtualization controller 40 to execute a process of evaluating the delay in the processing time of the control executed.

The communication interface 52 is a connection unit for virtualized communication, and communicates with the virtualization host OS unit 42 .

The virtualization host OS unit 42 communicates with the communication interface 52 of each virtualization controller 40 and communicates with the NIC 44. The virtualization host OS unit 42 is a network in which a virtual bridge 60 and a communication line 62 are connected via software, and processes data transmission and reception between the virtualization controllers 40 and data transmission and reception between each virtualization controller 40 and the NIC 44. I do. The virtual bridge 60 relays the communication line 62. The virtualization host OS unit 42 can change the connection relationship of the communication lines 62, and can change the paths between the virtualization controllers 40 and the paths between each virtualization controller 40 and the NIC 44.

The NIC 44 is a connection unit that transmits and receives data to and from external equipment. The NIC 44 may communicate with external devices either by wire or wirelessly. The NIC 44 also executes processing for exchanging IDs with external devices and establishing connections based on communication protocols. The NIC 44 is connected to the delay analyzer 14 and devices to be controlled by the host machine 12 .

The delay analysis device 14 includes a packet reception section 70, an analysis section 72, a delay investigation packet transmission program 74, and a NIC 76. The functions of the packet receiving section 70, the analyzing section 72, and the delay checking packet transmission program 74 are realized by executing the program stored in the storage section 36 in the calculation section 34. The NIC 76 is a function realized by the communication unit 38.

The packet receiving unit 70 receives the delay investigation packet that has passed through the route to be evaluated. The packet receiving unit 70 outputs the received delay investigation packet to the analyzing unit 72.

The analysis section 72 analyzes the delay investigation packet output from the packet reception section 70, and obtains information on the processing timing of each section through which the delay investigation packet passes. The analysis unit 72 analyzes processing delays in each part of the host machine 12 including the virtualization controller 40 and in each part of a device that communicates with the host machine 12, based on the acquired processing timing information of each part.

The delay investigation packet transmission program 74 is a program that creates and transmits a delay investigation packet used to measure the processing delay of the host machine 12. The delay investigation packet transmission program 74 serves as an investigation packet creation section. The delay investigation packet transmission program 74 measures the time of each process that is output from the delay analyzer 14 to the host machine 12, reaches the virtualization controller 40, and is output from the virtualization controller 40 to the delay analyzer 14. Create a research packet.

The NIC 76 is a connection unit that transmits and receives data to and from external equipment. The NIC 76 may communicate with external devices either by wire or wirelessly. The NIC 76 also executes processes for exchanging IDs with external devices and establishing connections based on communication protocols. The NIC 76 is connected to the host machine 12.

Next, an example of processing of the delay analysis system will be described using FIG. 3. FIG. 3 is an explanatory diagram showing an example of processing of the delay analysis system. Although FIG. 3 shows a case where only the delay (processing time) of one virtualization controller is evaluated, similar processing can be executed for each of a plurality of virtualization controllers.

In the example shown in FIG. 3, a delay investigation packet is created by the delay investigation packet transmission program 51 of the virtualization controller 40, and processing is executed. The host machine 12 and the delay analysis device 14 have time stamp sections 82, 84, 86, and 88 in each section that processes delay investigation packets. The time stamp units 82, 84, 86, and 88 are part of the control functions of each unit. The time stamp section 82 is included in the delay investigation packet transmission program 51. The timestamp unit 84 is included in the communication interface 52. The time stamp unit 86 is included in the NIC 44. The time stamp unit 88 is included in the NIC 76. Note that the time stamp section may be placed on the object whose processing time is desired to be measured. For example, it may also be provided in the virtual bridge of the virtualization host OS unit 42. The time stamp units 82, 84, 86, and 88 write information indicating the time of passage into the delay investigation packets that pass.

The delay checking packet in the example shown in FIG. 3 is created by the delay checking packet transmission program 51, passes through various parts on the data path 100, and reaches the packet receiving unit 70. Specifically, the delay investigation packet is created by the delay investigation packet transmission program 51, passes through the communication interface 52, passes through the virtualization host OS section 42, and is sent from the NIC 44 to the delay analysis device 14. Output. The delay checking packet is received by the NIC 76 and reaches the packet receiving unit 70.

The time stamp section 82 performs stamping processing 102 on the delay checking packet that is created by the delay checking packet transmission program and output to the communication interface 52 . The time stamp unit 84 performs stamping processing 104 on the delay checking packet output from the communication interface 52 to the virtualization host OS unit 42 . The time stamp unit 86 performs stamping processing 106 on the delay checking packet output from the NIC 44 to the NIC 76. The time stamp section 88 performs stamping processing 108 on the delay checking packet output from the NIC 76 to the packet receiving section 70 .

FIG. 4 is an explanatory diagram showing an example of the data structure of a delay investigation packet. The delay checking packet 90 passes through the data path 100 and is subjected to stamping processes 102, 104, 106, and 108, thereby storing data of a plurality of time stamps 92, 94, 96, and 98. The timestamps 92, 94, 96, and 98 include times when the stamping processes 102, 104, 106, and 108 were performed. Since the data path 100 is defined in the delay investigation packet, it is not necessary to include the identification information of the stamped time stamp part. By processing the identification information in chronological order, the passage time of each part can be detected. Here, in the delay investigation packet, the payload of the packet to which a timestamp is added may be added to an area determined at each timestamp acquisition point, with an area for adding a timestamp left open in advance. A method for determining which packets should be added with a timestamp can be such that a code for determining the packet is added to the payload at the time of socket creation. This allows the code to be referenced and determined at each timestamp acquisition point.

The delay analysis system 10 repeatedly executes the process shown in FIG. 3, and obtains a predetermined number of delay investigation packets in which information on the processing time of each part is stored. Here, the number of times of repeated processing is not particularly limited, but is, for example, several thousand times to tens of thousands of times. The delay analysis device 14 calculates the processing time in each part based on information on repeated execution of the same process on the same route. Specifically, the processing time of each part is calculated based on the time difference between the time stamps of each part.

5 to 8 are explanatory diagrams each conceptually showing an example of evaluation of delay time. In the delay analysis device 14, the analysis section 72 calculates the processing time of each section from the time stamp of each section. Specifically, the processing time of the process executed between each time stamp is calculated from the time difference between the time stamps. The delay analysis device 14 calculates processing time statistics for each process. The calculation results are as shown in FIGS. 5 to 8, for example. In FIGS. 5 to 8, the horizontal axis represents processing time, and the vertical axis represents frequency (number of times). As shown in FIGS. 5 and 6, when there is little variation in processing time, it can be determined that appropriate processing is being performed. It can also be determined that the process in FIG. 6 takes more time than the process in FIG. On the other hand, as shown in FIG. 7, if there are many fluctuations in processing time, it can be determined that a delay may occur. Furthermore, it is also possible to detect sudden occurrences of delays, such as at measurement points in range 120 shown in FIG. The delay analysis device 14 may set a threshold value for the delay time and determine the delay based on the threshold value. For example, the delay analysis device 14 determines that a delay has occurred when the number of times that a process has been performed with a delay exceeding a threshold value is equal to or greater than a set number of times. Alternatively, a threshold value may be set for the average value of the delay times, and the determination may be made based on the entire delay time. Further, the delay analysis device 14 may output a warning when determining that a delay has occurred based on the analysis result. Further, the delay analysis device 14 may calculate the processing time in real time and output a warning when the measured delay time exceeds a threshold value. In other words, the determination is not limited to multiple times of processing, and one time of processing may be determined.

The delay analysis system 10 inputs a delay investigation packet for analyzing delay time to the host machine 12 to be analyzed, processes the delay investigation packet in the processing unit to be analyzed, and The processing unit writes the timestamp into the delay investigation packet. Here, the processing section includes both a section that processes data and a section that transmits and receives data. The delay analysis system 10 calculates the time difference between the time stamps of the delay investigation packets in which the time stamps are stored in the delay analyzer 14, thereby calculating the time required for processing between the timestamps of the data path 100. can be calculated, and the time spent in each processing section can be calculated. Thereby, it is possible to detect the delay time of processing in each part of the host machine 12.

The delay analysis system 10 can calculate the delay time of each virtualized processing section of the host machine 12 by simply stamping a time stamp. Further, the delay time analysis device 12 can analyze the delay time of the host machine 12 by analyzing the information in the delay investigation packet. This eliminates the need for the host machine to calculate the processing time and obtain process monitoring logs, which is required in conventional processing, and thus suppresses the increase in calculation processing in the calculation unit 20 of the host machine 12. At the same time, the delay time can be calculated. Further, since the processing for calculating the delay time can be reduced in the calculation unit 20 of the host machine 12, the processing of each part of the host machine 12 can be analyzed with higher accuracy. By being able to analyze the delay status of each processing unit with high precision and understanding where delays are occurring, the connection relationships, placement, and settings of virtualized control units such as the virtualization controller and virtualization host OS unit can be adjusted appropriately. improvements that reduce the latency of the host machine 12 can be made more easily.

In addition, the delay analysis system 10 includes time stamp units 82 and 88, and stores the time stamps at the start and end of processing of the delay investigation packet for delay time determination, so that each unit of the host machine 12 processing time can be detected more appropriately.

Further, the processing time including the stamping process of the time stamp section is sufficiently small compared to the processing time of each processing section and the processing related to passage of the data path 100. Therefore, as described above, the processing time of the delay investigation packet can be measured with high accuracy. Here, when considering the influence of the processing time of the timestamp section, it is possible to obtain timestamps before and after the timestamp section, and measure packet discrimination and timestamp addition processing from the difference. In addition, a packet for delay investigation when stamping the time stamp section to be evaluated is performed, and a packet for delay investigation when stamping the time stamp section to be evaluated is not performed, are obtained and the entire processing is performed. The difference in time may be calculated as the processing time of the stamping process of the time stamp part to be evaluated.

The delay analyzer 14 can identify the cause of the delay by acquiring delay investigation packets multiple times, detecting the processing time distribution, and analyzing the fluctuations (jitter) in the processing timing in each process. .

Note that the location where the time stamp is obtained is not limited to this embodiment. Further, each processing unit may stamp a time stamp each time the delay investigation packet is received and transmitted. This makes it possible to evaluate the time required for processing by one processing unit.

Further, in the present embodiment, a timestamp, which is time information, is written in the delay investigation packet, but delay factor investigation information may be further added to the delay investigation packet. The delay factor investigation information may be written by the delay investigation packet transmission program when creating the delay investigation packet, or may be written by the time stamp section of each processing section of the host machine 12 and the delay analysis device 14 at the same time as stamping processing. The delay factor investigation information includes the number of software loops, variable values, CPU usage rate, internal error codes, and the like. By adding the delay factor investigation information to the delay investigation packet, the delay analyzer 14 can analyze the delay state in each processing unit with higher accuracy. For example, if software loop count information is added to the packet as information for investigating delay causes, and if the loop count is large at a point where the delay is large, the delay can be reduced by reducing the loop count and distributing the amount processed at once. Countermeasures can be output as analysis results. In addition, by acquiring delay cause investigation information from both the virtualization controller of the host machine and the delay analysis device, when a processing delay occurs, the delay cause investigation information can be used to obtain information from both the virtualization controller and the delay analysis device. , or both can analyze related delay factors.

The delay checking packet transmission program may create a delay checking packet that does not include instructions for processing to be executed by the control software 50 in order to measure the processing time for data transmission and reception in each section. Further, the delay checking packet transmission program may create a delay checking packet including a command to be executed by the processing in the control software 50 in order to compare the processing time in each part.

FIG. 9 is an explanatory diagram showing an example of processing of the delay analysis system. In the example shown in FIG. 9, a delay investigation packet is created by the delay investigation packet transmission program 51 of the virtualization controller 40, and the processing is executed by control software.

The delay checking packet in the example shown in FIG. 9 is created by the delay checking packet transmission program 51, passes through various parts on the data path 140, and reaches the packet receiving unit 70. Specifically, the delay check packet is created by the delay check packet transmission program 51 and input to the control software 50. The delay investigation packet is processed by the control software 50, passes through the delay investigation packet transmission program 51, the communication interface 52, the virtualization host OS unit 42, and is output from the NIC 44 to the delay analysis device 14. . The delay checking packet is received by the NIC 76 and reaches the packet receiving unit 70.

When the time stamp units 82, 84, 86, and 88 detect a delay investigation packet, they determine whether the delay investigation packet is a delay investigation packet to be stamped or not to be stamped. The time stamp sections 82, 84, 86, and 88 determine that the delay investigation packet created by the delay investigation packet transmission program 51 is a delay investigation packet to be stamped. The time stamp unit 82 performs stamping processing 102 on the delay checking packet created by the delay checking packet transmission program 51 and output to the communication interface 52 . The time stamp unit 84 performs stamping processing 104 on the delay checking packet output from the communication interface 52 to the virtualization host OS unit 42 . The time stamp unit 86 performs stamping processing 106 on the delay checking packet output from the NIC 44 to the NIC 76. The time stamp section 88 performs stamping processing 108 on the delay checking packet output from the NIC 76 to the packet receiving section 76 .

By analyzing the delay time of the data path 140 shown in FIG. 9, it is possible to analyze the delay time of the data path 142 to which the delay investigation packet for processing executed by the control software 51 is sent. Here, the data path 142 is a control packet that is processed by the control software 50, passes through the communication interface 52, passes through the virtualization host OS unit 42, and is output from the NIC 44 to the control target. It is a packet that does not exist.

In this way, by using the delay investigation packet to be processed by the control software 50, the delay time of the control software 50 can also be analyzed.

It is preferable that the delay checking packet transmitted on the data path 140 is a packet whose processing is executed by the control software 50 in the same manner as the control packet transmitted on the data path 142. This makes it possible to analyze the delay of the control software 50 in actual processing.

The delay analysis system 10 uses the time stamp units 82, 84, 86, and 88 to determine whether or not the delay investigation packet is to be stamped, thereby determining whether the delay investigation packet is controlled by the virtualization controller 40. In other words, there is no need to perform stamping on the delay investigation packets passing through the data path 142, and the influence on control of the host machine 12 other than during delay analysis can be reduced.

In the above embodiment, only the delay (processing time) of one virtualization controller was evaluated, but the delay time can be similarly evaluated even when multiple virtualization controllers perform interlocking control. For example, a delay check packet passes through one virtualization controller 40 and is output to the virtualization host OS section 42, and then is input to another virtualization controller 40, passes through it, and is output to the virtualization host OS section 42. 42 and then output to the packet receiving section 70. In this case as well, by writing a time stamp in the delay investigation packet at the time of passage, the analysis unit 72 can analyze the delay time of each process.

FIG. 10 is an explanatory diagram showing an example of processing of the delay analysis system. The process shown in FIG. 10 shows an example in which a delay investigation packet is created by the delay investigation packet creation program 74 of the delay analyzer 14 and the delay of the host machine 12 is analyzed. The host machine 12 and the delay analysis device 14 have time stamp sections 84, 86, 88, and 89 in each section that processes delay investigation packets. The time stamp section 89 is included in the control software 50.

The delay checking packet in the example shown in FIG. 10 is created by the delay checking packet transmission program 74, passes through various parts on the data path 150, and reaches the packet receiving unit 70 after passing through the host machine 12. Specifically, the delay check packet is created by the delay check packet transmission program 74, output from the NIC 76 to the NIC 44, passes through the virtualization host OS unit 42, passes through the communication interface 52, and The control software 51 is reached. The delay investigation packet is processed by the control software 51, passes through the communication interface 52, passes through the virtualization host OS unit 42, and is output from the NIC 44 to the delay analysis device 14. The delay checking packet is received by the NIC 76 and reaches the packet receiving unit 70.

The time stamp unit 88 performs stamping processing 151 on the delay checking packet output from the NIC 76 to the NIC 44. The time stamp section 86 performs stamping processing 152 on the delay checking packet output from the NIC 44 to the virtualization host OS section 42 . The time stamp unit 84 performs stamping processing 154 on the delay checking packet output from the communication interface 52 to the control software 50 . The time stamp section 140 performs stamping processing 156 on the delay investigation packet received by the control software 50. The time stamp section 140 performs stamping processing 158 on the delay checking packet output from the control software 50 to the communication interface 52 . The time stamp unit 84 performs stamping processing 160 on the delay checking packet output from the communication interface 52 to the OS unit 42 . The time stamp unit 86 performs stamping processing 162 on the delay checking packet output from the NIC 44 to the NIC 76. The time stamp section 88 performs stamping processing 164 on the delay checking packet output from the NIC 76 to the packet receiving section 70 .

The delay analysis system 10 creates a delay investigation packet using the delay investigation packet transmission program 74 of the analysis processing device 12, inputs it to the host machine 12, processes it in the host machine 12, and sends it from the host machine 12 to the analysis processing device 12. By processing the delay checking packet on the data path 150 that is output to the data path 150 and acquiring a time stamp, the delay checking packet is input from the device controlled by the virtualization controller 40 and processed by the virtualization controller 40. By using this method, it is possible to measure the delay time that occurs in the same process as the route that outputs the delay investigation packet to the device to be controlled. Further, it is also possible to analyze the delay time before a delay investigation packet is input from a device to be controlled by the virtualization controller 40 and reaches the virtualization controller 40. Thereby, it is possible to analyze a wider range of delay times caused by processing with devices to be controlled by the virtualization controller 40. The delay analysis system 10 can analyze not only processing delays of output commands to controlled objects, but also processing delays of sensor input signals and the like from controlled objects.

By using the synchronization device 16, the delay analysis system 10 of this embodiment can perform time synchronization between the host machine 12 and the delay analysis device 14 with high accuracy. There is no need to consider differences in time precision or time differences set in the processing units of each virtualization controller 40, host machine 12, and delay analysis device 14, and processing time can be easily calculated. In this embodiment, the synchronization device 16 is provided separately from the host machine 12 and the delay analysis device 14, but it may be integrated with either the host machine 12 or the delay analysis device 14. That is, the host machine 12 and the delay analysis device 14 may be provided with a function to synchronize the times. Moreover, although it is preferable that the delay analysis system 10 is provided with the synchronization device 16, it may be configured without the synchronization device 16.

This disclosure discloses the following inventions. Note that the examples are not limited to the following.
(1) A host machine that executes a virtualized controller, a host communication unit that manages communication between the controller and other devices, and a delay investigation packet that measures the processing delay of the host machine. a delay analysis device that analyzes a delay investigation packet input to a host machine and processed by the host machine to measure a processing delay of the host machine; and writes a timestamp into the delay checking packet and outputs it to the host communication unit, and the host communication unit processes the delay checking packet and writes the timestamp into the delay checking packet. and outputs it to the delay analysis device, and the delay analysis device calculates the processing time of each section based on the controller time stamp and the host communication section time stamp written in the delay investigation packet. Delay analysis system to calculate.

As a result, each virtualized processing section of the host machine can calculate the delay time of each processing section only by stamping a time stamp. Further, the delay time analysis device can analyze the delay time of the host machine by analyzing the information in the delay investigation packet. This eliminates the need for the host machine to calculate processing time and obtain process monitoring logs, which is required in conventional processing, and thus suppresses the increase in arithmetic processing in the host machine's arithmetic unit. Delay time can be calculated.

(2) The delay analysis system according to (1), wherein the delay analysis device acquires a timestamp at the time of reception of the delay investigation packet output from the host machine. Thereby, the processing time in each part can be detected more appropriately.

(3) When receiving the delay investigation packet, the controller creates an area for storing a timestamp in the delay investigation packet, and writes a timestamp at the time of creation into the area for storing the timestamp (1) Or the delay analysis system described in (2). Thereby, the processing time in each part can be detected more appropriately.

(4) The controller is virtualized and has a virtual communication interface that sends and receives data to and from other devices, and the virtual communication interface sets the time stamp at the time of communication to the delay when communicating the delay investigation packet. The delay analysis system according to any one of (1) to (3), which writes in the investigation packet. Thereby, the processing time in each part can be detected more appropriately.

(5) The controller includes a check packet creation unit that creates the delay check packet, and the check packet creation unit creates an area for storing a timestamp in the delay check packet, and stores the time stamp. The delay analysis system according to (1) or (2), wherein a time stamp at the time of creation of the delay investigation packet is written in the area where the delay investigation packet is created. Thereby, the processing time in each part can be detected more appropriately.

(6) The delay analysis device includes an investigation packet creation section that creates the delay investigation packet, and the investigation packet creation section creates an area for storing a timestamp in the delay investigation packet, and the time stamp. The delay analysis system according to (1) or (2), wherein a timestamp at the time of creation of the delay investigation packet is written in an area for storing the delay investigation packet. Thereby, the processing time in each part can be detected more appropriately.

(7) The controller determines whether or not the delay check packet is to write a time stamp, and the host communication unit determines whether the delay check packet is to write a time stamp (1 ) to (6). This makes it possible to reduce the influence on control of the host machine other than during delay analysis.

(8) The host machine has a communication unit that sends and receives data to and from the delay analysis device, and the communication unit adds a timestamp at the time of communication to the delay investigation packet when communicating the delay investigation packet. The delay analysis system according to any one of writing (1) to (7). Thereby, the processing time in each part can be detected over a wider range.

(9) At least one of the timestamps is written together with delay factor investigation information, and the delay analysis device, based on the delay factor investigation information in addition to the timestamp written in the delay investigation packet, The delay analysis system according to any one of (1) to (8), which evaluates processing delays in each part. This allows the processing time in each section to be analyzed with higher accuracy.

(10) The delay analysis system according to any one of (1) to (9), further comprising a synchronization device that connects to the host machine and the delay analysis device and synchronizes time information with the host machine and the delay analysis device. . This allows the processing time in each section to be analyzed with higher precision.

(11) A delay analysis method that uses a delay measurement device to analyze the control delay of a host machine that executes a virtualized controller and a host communication unit that manages communication between the controller and other devices, the method comprising: inputting a delay investigation packet for measuring a processing delay of the host machine into the host machine, the controller processing the delay investigation packet, and writing a timestamp to the delay investigation packet; outputting to the host communication unit, the host communication unit processing the delay investigation packet, writing a timestamp to the delay investigation packet, and outputting it to the delay analysis device; A delay analysis method comprising the step of calculating processing time of each unit based on a time stamp of the controller and a time stamp of the host communication unit written in an investigation packet.

As a result, each virtualized processing section of the host machine can calculate the delay time of each processing section only by stamping a time stamp. Further, the delay time analysis device can analyze the delay time of the host machine by analyzing the information in the delay investigation packet. This eliminates the need for the host machine to calculate processing time and obtain process monitoring logs, which is required in conventional processing, and thus suppresses the increase in arithmetic processing in the host machine's arithmetic unit. Delay time can be calculated.

(12) A delay analysis system that uses a delay measurement device to analyze the control delay of a host machine that executes a virtualized controller and a host communication unit that manages communication between the controller and other devices. inputting a delay checking packet for measuring a processing delay of a machine into the host machine; the controller processing the delay checking packet and writing a timestamp to the delay checking packet; a step of outputting to a communication unit, a step of the host communication unit processing the delay investigation packet, writing a timestamp to the delay investigation packet, and outputting it to the delay analysis device; A delay analysis program that executes the step of calculating processing time of each unit based on a time stamp of the controller and a time stamp of the host communication unit written in a packet.

As a result, each virtualized processing section of the host machine can calculate the delay time of each processing section only by stamping a time stamp. Further, the delay time analysis device can analyze the delay time of the host machine by analyzing the information in the delay investigation packet. This eliminates the need for the host machine to calculate processing time and obtain process monitoring logs, which is required in conventional processing, and thus suppresses the increase in arithmetic processing in the host machine's arithmetic unit. Delay time can be calculated.

10 Delay analysis system 12 Host machine 14 Delay analysis device 16 Synchronization device 20, 34 Arithmetic unit 22, 36 Storage unit 24, 38 Communication unit 30 Input unit 32 Output unit 40 Virtualization controller 42 Virtualization host OS unit 44, 76 NIC
50 Control software (virtualization control unit)
51, 74 Delay investigation packet transmission program 52 Communication interface (virtualization communication interface)
60 Virtual bridge 62 Communication line 70 Packet receiving section 72 Analysis section 82, 84, 86, 88, 89 Time stamp section 90 Delay investigation packet 92, 94, 96 Time stamp data 100, 142, 150 Data path 102, 104, 106 , 108, 151, 152, 154, 156, 158, 160, 162, 164 Embossing processing

Claims (12)

a host machine that executes a virtualized controller and a host communication unit that manages communication between the controller and other devices;
Delay analysis that measures the processing delay of the host machine by inputting a delay investigation packet to the host machine and analyzing the delay investigation packet processed by the host machine. having a device;
The controller processes the delay checking packet, writes a timestamp in the delay checking packet, and outputs it to the host communication unit,
The host communication unit processes the delay investigation packet, writes a timestamp to the delay investigation packet, and outputs it to the delay analysis device;
The delay analysis device is a delay analysis system that calculates the processing time of each unit based on the time stamp of the controller and the time stamp of the host communication unit written in the delay investigation packet. 2. The delay analysis system according to claim 1, wherein the delay analysis device obtains a timestamp at the time of reception of the delay investigation packet output from the host machine. 2. The controller according to claim 1, when receiving the delay checking packet, creates a time stamp storage area in the delay checking packet, and writes a time stamp at the time of creation into the time stamp storage area. Delay analysis system. The controller is virtualized and has a virtual communication interface that sends and receives data to and from other devices,
2. The delay analysis system according to claim 1, wherein the virtual communication interface writes a timestamp at the time of communication into the delay investigation packet when communicating the delay investigation packet. The controller includes a check packet creation unit that creates the delay check packet,
2. The check packet creation unit creates a time stamp storage area in the delay check packet, and writes a timestamp at the time of creation of the delay check packet into the time stamp storage area. Delay analysis system. The delay analysis device includes a check packet creation unit that creates the delay check packet,
2. The check packet creation unit creates a time stamp storage area in the delay check packet, and writes a timestamp at the time of creation of the delay check packet into the time stamp storage area. Delay analysis system. The controller determines whether it is the delay investigation packet in which a timestamp is written,
7. The delay analysis system according to claim 1, wherein the host communication unit determines whether or not the delay investigation packet is a packet for writing a time stamp. The host machine has a communication unit that sends and receives data to and from the delay analysis device,
The delay analysis system according to any one of claims 1 to 6, wherein the communication unit writes a timestamp at the time of communication into the delay investigation packet when communicating the delay investigation packet. at least one of the timestamps is written with delay factor investigation information;
7. The delay analysis device evaluates processing delays in each section based on delay factor investigation information in addition to the time stamp written in the delay investigation packet. The delay analysis system described in Section. The delay analysis system according to any one of claims 1 to 6, further comprising a synchronization device that connects to the host machine and the delay analysis device and synchronizes time information with the host machine and the delay analysis device. A delay analysis method that uses a delay measurement device to analyze a delay in control of a host machine that executes a virtualized controller and a host communication unit that manages communication between the controller and other devices, the method comprising:
inputting a delay investigation packet to the host machine to measure the processing delay of the host machine;
the controller processing the delay checking packet, writing a timestamp in the delay checking packet, and outputting the same to the host communication unit;
the host communication unit processing the delay investigation packet, writing a timestamp in the delay investigation packet, and outputting it to the delay analysis device;
A delay analysis method comprising the step of calculating processing time of each unit based on a time stamp of the controller and a time stamp of the host communication unit written in the delay investigation packet. A delay analysis system that uses a delay measurement device to analyze the control delay of a host machine that executes a virtualized controller, a host communication unit that manages communication between the controller and other devices,
inputting a delay investigation packet to the host machine to measure the processing delay of the host machine;
the controller processes the delay check packet, writes a timestamp to the delay check packet, and outputs the same to the host communication unit;
the host communication unit processing the delay investigation packet, writing a timestamp in the delay investigation packet, and outputting it to the delay analysis device;
A delay analysis program that executes the step of calculating a processing time of each unit based on a time stamp of the controller and a time stamp of the host communication unit written in the delay investigation packet.

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