JP2023163856A - Semiconductor device - Google Patents

Abstract

To provide a semiconductor device which can achieve both of miniaturization and improvement in reliability.SOLUTION: A semiconductor module 1 comprises: an insulation substrate 123; a first conductive layer 11 which is formed on the insulation substrate 123 and has a first region 111 and a second region 112; a plurality of first transistors 200 which are provided on the first region 111 of the first conductive layer 11 and are electrically connected in parallel to each other; and a plurality of first diodes 300 which are provided on the second region 112 of the first conductive layer 11. The first diodes 300 are electrically connected in parallel to the first transistors 200. The average interval of the first transistors 200 is greater than the average interval of the first diodes 300.SELECTED DRAWING: Figure 1

Description

The present disclosure relates to a semiconductor device.

Regarding multiple semiconductor devices connected in parallel on the same heat sink, the spacing between the multiple semiconductor devices may be changed from the edge of the heat sink to improve the heat dissipation of the semiconductor devices in the center of the heat sink. A configuration in which the center portion is enlarged is known (for example, see Patent Document 1).

Japanese Patent Application Publication No. 2005-136229

In conventional semiconductor devices, it is difficult to achieve both miniaturization and improved reliability.

An object of the present disclosure is to provide a semiconductor device that can achieve both miniaturization and improved reliability.

A semiconductor device of the present disclosure includes an insulating substrate, a conductive layer formed on the insulating substrate and having a first region and a second region, and a conductive layer provided on the first region of the conductive layer and electrically connected to each other. a plurality of switching elements connected in parallel, and a plurality of diode elements provided on the second region of the conductive layer, and the plurality of diode elements are connected to the plurality of switching elements. The plurality of switching elements are electrically connected in parallel, and an average interval between the plurality of switching elements is larger than an average interval between the plurality of diode elements.

According to the present disclosure, it is possible to achieve both miniaturization and improved reliability.

FIG. 1 is a top view showing a semiconductor module according to a first embodiment. FIG. 2 is a cross-sectional view (part 1) showing the semiconductor module according to the first embodiment. FIG. 3 is a cross-sectional view (part 2) showing the semiconductor module according to the first embodiment. FIG. 4 is a circuit diagram showing the semiconductor module according to the first embodiment. FIG. 5 is a top view showing the semiconductor module according to the second embodiment. FIG. 6 is a top view showing a semiconductor module according to a third embodiment. FIG. 7 is a cross-sectional view (part 1) showing a semiconductor module according to a third embodiment. FIG. 8 is a cross-sectional view (part 2) showing the semiconductor module according to the third embodiment.

The embodiment will be described below.

[Description of embodiments of the present disclosure]
First, embodiments of the present disclosure will be listed and described. In the following description, the same or corresponding elements are given the same reference numerals, and the same description will not be repeated.

[1] A semiconductor device according to one aspect of the present disclosure includes an insulating substrate, a conductive layer formed on the insulating substrate and having a first region and a second region, and a conductive layer formed on the first region of the conductive layer. and a plurality of switching elements provided on the second region of the conductive layer, the plurality of diode elements are provided on the second region of the conductive layer, and the plurality of diode elements are provided on the second region of the conductive layer. , electrically connected in parallel to the plurality of switching elements, and the average spacing of the plurality of switching elements is larger than the average spacing of the plurality of diode elements.

Since the average spacing between the plurality of switching elements is larger than the average spacing between the plurality of diode elements, it is easy to radiate heat generated by the switching elements. Furthermore, it is not necessary to increase the average spacing of the diode elements. Therefore, it is possible to achieve both miniaturization and improved reliability.

[2] In [1], the heat generation density during operation of the switching element may be greater than the heat generation density during operation of the diode element. Switching elements tend to reach higher temperatures than diode elements. Therefore, by making the average spacing between the plurality of switching elements larger than the average spacing between the plurality of diode elements, reliability can be easily improved by improving heat dissipation of the switching elements.

[3] In [1] or [2], the plurality of switching elements may be arranged in a line at equal intervals. In this case, it is easy to arrange the switching elements.

[4] In any one of [1] to [3], the plurality of diode elements may be arranged at equal intervals. In this case, it is easy to arrange the diode element.

[5] In [1] or [2], the first region is the smallest first rectangular region surrounding the plurality of switching elements in plan view, and the first region is the smallest first rectangular region surrounding the plurality of switching elements in a plan view, and The interval between the switching elements may be larger for a combination of switching elements closer to the center of gravity of the first rectangular area. In this case, it is easier to release the heat generated in the switching elements near the center of gravity of the first rectangular area.

[6] In [1], [2] or [5], the second region is the smallest second rectangular region surrounding the plurality of diode elements in plan view, and the second region is the smallest second rectangular region surrounding the plurality of diode elements in a plan view, and The distance between two matching diode elements may be larger for a combination of diode elements closer to the center of gravity of the second rectangular area. In this case, the heat generated in the diode element near the center of gravity of the second rectangular region is more easily dissipated.

[7] In any one of [1] to [6], the switching element may be a silicon carbide-based transistor element. In this case, it is easy to obtain an excellent breakdown voltage for the switching element.

[8] In any one of [1] to [7], the diode element may be a silicon carbide-based Schottky barrier diode element. In this case, it is easy to obtain an excellent breakdown voltage for the diode element.

[9] In any one of [1] to [8], the device includes the same number of first bonding materials as the switching elements and the same number of second bonding materials as the diode elements, and each of the first bonding materials may bond one of the switching elements to the conductive layer, and each of the second bonding materials may bond one of the diode elements to the conductive layer. In this case, it is easy to suppress misalignment of the switching element and the diode element during manufacturing.

[10] In any one of [1] to [9], the material of the first bonding material and the material of the second bonding material may be the same. In this case, it is easy to form the first bonding material and the second bonding material at the same time.

[11] In any one of [1] to [10], the thickness of the first bonding material and the thickness of the second bonding material may be equal. In this case, it is easy to form the first bonding material and the second bonding material at the same time.

[Details of embodiments of the present disclosure]
Hereinafter, embodiments of the present disclosure will be described in detail, but the embodiments are not limited thereto. Note that, in this specification and the drawings, components having substantially the same functional configurations may be given the same reference numerals to omit redundant explanation. In this specification and the drawings, the X1-X2 direction, the Y1-Y2 direction, and the Z1-Z2 direction are directions that are orthogonal to each other. The plane including the X1-X2 direction and the Y1-Y2 direction is the XY plane, the plane including the Y1-Y2 direction and the Z1-Z2 direction is the YZ plane, and the plane including the Z1-Z2 direction and the X1-X2 direction is the ZX plane. do. For convenience, the Z1 direction is defined as an upward direction, and the Z2 direction is defined as a downward direction. Furthermore, in the present disclosure, planar view refers to viewing the object from the Z1 side.

(First embodiment)
First, a first embodiment will be described. The first embodiment relates to a semiconductor module. FIG. 1 is a top view showing a semiconductor module according to a first embodiment. 2 and 3 are cross-sectional views showing the semiconductor module according to the first embodiment. FIG. 2 corresponds to a cross-sectional view taken along line II-II in FIG. FIG. 3 corresponds to a cross-sectional view taken along line III-III in FIG.

As shown in FIGS. 1 to 3, the semiconductor module 1 according to the first embodiment includes a heat sink 121, a housing 122, a P terminal 101, an N terminal 102, an O terminal 103, and a first gate terminal. 104, a second gate terminal 105, a first sense source terminal 106, and a second sense source terminal 107. The semiconductor module 1 further includes a first conductive layer 11, a second conductive layer 12, a third conductive layer 13, a fourth conductive layer 14, a fifth conductive layer 15, a sixth conductive layer 16, and a third conductive layer 13. 7 conductive layer 17 and an insulating substrate 123. The semiconductor module 1 further includes a plurality of first transistors 200, a plurality of second transistors 400, a plurality of first diodes 300, and a plurality of second diodes 500. The numbers of the first transistor 200, the second transistor 400, the first diode 300, and the second diode 500 are not limited, and in one example, are all three. The semiconductor module 1 is an example of a semiconductor device.

The heat sink 121 is, for example, a rectangular plate-shaped body having a uniform thickness when viewed from above. The material of the heat sink 121 is a metal having high thermal conductivity, such as copper (Cu), copper alloy, aluminum (Al), or the like. The heat sink 121 is fixed to a cooler or the like using a thermal interface material (TIM) or the like.

The housing 122 is formed, for example, in a frame shape in a plan view, and the outer shape of the housing 122 is the same as the outer shape of the heat sink 121. The material of the housing 122 is an insulator such as resin. The housing 122 has a pair of side walls 191 and 192 that face each other, and a pair of end walls 193 and 194 that connect both ends of the side walls 191 and 192. The side walls 191 and 192 are arranged parallel to the ZX plane, and the end walls 193 and 194 are arranged parallel to the YZ plane. The side wall 191 is arranged on the Y1 side of the side wall 192, and the end wall 193 is arranged on the X1 side of the end wall 194.

A first gate terminal 104 and a first sense source terminal 106 are arranged on the upper surface of the side wall portion 191 (surface on the Z1 side), and a second gate terminal 105 and a second sense source terminal are arranged on the upper surface of the side wall portion 192 (surface on the Z1 side). A terminal 107 is arranged.
The first gate terminal 104, the first sense source terminal 106, the second gate terminal 105, and the second sense source terminal 107 are each made of a metal plate.

A P terminal 101 and an N terminal 102 are arranged on the upper surface of the end wall section 193 (surface on the Z1 side), and an O terminal 103 is arranged on the upper surface of the end wall section 194 (surface on the Z1 side). For example, the N terminal 102 is arranged on the Y2 side of the P terminal 101. The P terminal 101, the N terminal 102, and the O terminal 103 are each made of a metal plate.

Inside the housing 122, an insulating substrate 123 is arranged on the Z1 side of the heat sink 121. The first conductive layer 11, the second conductive layer 12, the third conductive layer 13, the fourth conductive layer 14, the fifth conductive layer 15, the sixth conductive layer 16, and the seventh conductive layer 17 are located on the Z1 side of the insulating substrate 123. It is placed on the surface. The eighth conductive layer 18 is provided on the Z2 side surface of the insulating substrate 123. The eighth conductive layer 18 is bonded to the heat sink 121 by a fifth bonding material 138. The material of the insulating substrate 123 is, for example, silicon nitride (SiN), silicon oxide (SiO), or aluminum nitride (AlN). The material of the fifth bonding material 138 is, for example, solder such as lead-free solder containing tin (Sn).

P terminal 101 is electrically connected to first conductive layer 11 , O terminal 103 is electrically connected to second conductive layer 12 , and N terminal 102 is electrically connected to third conductive layer 13 . The first gate terminal 104 is electrically connected to the fourth conductive layer 14 , the second gate terminal 105 is electrically connected to the fifth conductive layer 15 , and the first sense source terminal 106 is electrically connected to the sixth conductive layer 16 . The second sense source terminal 107 is electrically connected to the seventh conductive layer 17 .

The first transistor 200 and the first diode 300 are provided on the first conductive layer 11 . A drain electrode 233 of the first transistor 200 is bonded to the first conductive layer 11 by a first bonding material 131. A cathode electrode 333 of the first diode 300 is bonded to the first conductive layer 11 with a second bonding material 141 . The material of the first bonding material 131 and the second bonding material 141 is, for example, solder such as lead-free solder containing tin (Sn). A source electrode 232 of the first transistor 200 is connected to the second conductive layer 12 by a plurality of bonding wires 161. A gate electrode 231 of the first transistor 200 is connected to the fourth conductive layer 14 by a bonding wire 162. The source electrode 232 of the first transistor 200 is also connected to the sixth conductive layer 16 by a bonding wire 163. An anode electrode 332 of the first diode 300 is connected to the second conductive layer 12 by a plurality of bonding wires 164. The thicknesses of the first transistor 200 and the first diode 300 are, for example, approximately 100 μm or more and 200 μm or less. The first transistor 200 is an example of a switching element, and the first diode 300 is an example of a diode element.

The first conductive layer 11 has a first region 111 and a second region 112. The first region 111 and the second region 112 have, for example, a rectangular planar shape with a longitudinal direction in the X1-X2 direction and a transverse direction in the Y1-Y2 direction. The first area 111 is on the X2 side of the second area 112.

The plurality of first transistors 200 are arranged in the first region 111. The plurality of first transistors 200 are arranged in a line in the X1-X2 direction at a constant interval Dsw1. The distance Dsw1 is, for example, 2 mm or more and 10 mm or less. The average distance ADsw1 between the plurality of first transistors 200 in the X1-X2 direction is the distance Dsw1.

The plurality of first diodes 300 are arranged in the second region 112. The plurality of first diodes 300 are arranged in a line in the X1-X2 direction at a constant interval Ddi1. The interval Ddi1 is smaller than the interval Dsw1. The distance Ddi1 is, for example, 1 mm or more and 9 mm or less. The average distance ADdi1 between the plurality of first diodes 300 in the X1-X2 direction is the distance Ddi1.

The average spacing ADsw1 of the first transistors 200 is larger than the average spacing ADdi1 of the first diodes 300.

A second transistor 400 and a second diode 500 are provided on the second conductive layer 12. A drain electrode 433 of the second transistor 400 is bonded to the second conductive layer 12 by a third bonding material 132. A cathode electrode 533 of the second diode 500 is bonded to the second conductive layer 12 by a fourth bonding material 142 . The material of the third bonding material 132 and the fourth bonding material 142 is, for example, solder such as lead-free solder containing tin (Sn). A source electrode 432 of the second transistor 400 is connected to the third conductive layer 13 by a plurality of bonding wires 171. A gate electrode 431 of the second transistor 400 is connected to the fifth conductive layer 15 by a bonding wire 172. The source electrode 432 of the second transistor 400 is also connected to the seventh conductive layer 17 by a bonding wire 173. An anode electrode 532 of the second diode 500 is connected to the third conductive layer 13 by a plurality of bonding wires 174. The thicknesses of the second transistor 400 and the second diode 500 are, for example, approximately 100 μm or more and 200 μm or less. The second transistor 400 is an example of a switching element, and the second diode 500 is an example of a diode element.

The second conductive layer 12 has a third region 113 and a fourth region 114. The third region 113 and the fourth region 114 have, for example, a rectangular planar shape with a longitudinal direction in the X1-X2 direction and a transversal direction in the Y1-Y2 direction. The third area 113 is located on the X1 side of the fourth area 114.

The plurality of second transistors 400 are arranged in the third region 113. The plurality of second transistors 400 are arranged in a line in the X1-X2 direction at a constant interval Dsw2. For example, the spacing Dsw2 is equal to the spacing Dsw1. The distance Dsw2 is, for example, 2 mm or more and 10 mm or less. The average distance ADsw2 between the plurality of second transistors 400 in the X1-X2 direction is the distance Dsw2.

A plurality of second diodes 500 are arranged in the fourth region 114. The plurality of second diodes 500 are arranged in a line in the X1-X2 direction at a constant interval Ddi2. The interval Ddi2 is smaller than the interval Dsw2. For example, the interval Ddi2 is equal to the interval Ddi1. The distance Ddi2 is, for example, 1 mm or more and 9 mm or less. The average distance ADdi2 between the plurality of second diodes 500 in the X1-X2 direction is the distance Ddi2.

The average spacing ADsw2 of the second transistors 400 is larger than the average spacing ADdi2 of the second diodes 500.

The first region 111 is the smallest rectangular region (an example of a first rectangular region) surrounding the plurality of first transistors 200 in plan view, and the second region 112 is the smallest rectangular region surrounding the plurality of first diodes 300 in plan view. area (an example of a second rectangular area). Further, the third region 113 is the smallest rectangular region (an example of a first rectangular region) surrounding the plurality of second transistors 400 in plan view, and the fourth region 114 is the smallest rectangular region surrounding the plurality of second diodes 500 in plan view. This is a rectangular area (an example of a second rectangular area).

Here, the circuit configuration of the semiconductor module 1 according to the first embodiment will be explained. FIG. 4 is a circuit diagram showing the semiconductor module according to the first embodiment.

The plurality of first transistors 200 are electrically connected to each other in parallel. The plurality of first diodes 300 are electrically connected to each other in parallel. The plurality of second transistors 400 are electrically connected to each other in parallel. The plurality of second diodes 500 are electrically connected to each other in parallel. Note that FIG. 4 shows only one first transistor 200, one first diode 300, one second transistor 400, and one second diode 500.

As shown in FIG. 4, the drain electrode 233 of the first transistor 200 and the cathode electrode 333 of the first diode 300 are commonly connected to the P terminal 101, and the source electrode 232 of the first transistor 200 and the anode of the first diode 300 are connected in common to the P terminal 101. The electrode 332 is commonly connected to the O terminal 103. That is, the first transistor 200 and the first diode 300 are connected in parallel between the P terminal 101 and the O terminal 103. Further, the drain electrode 433 of the second transistor 400 and the cathode electrode 533 of the second diode 500 are commonly connected to the O terminal 103, and the source electrode 432 of the second transistor 400 and the anode electrode 532 of the second diode 500 are connected to the N terminal 103. They are commonly connected to the terminal 102. That is, the second transistor 400 and the second diode 500 are connected in parallel between the N terminal 102 and the O terminal 103. An upper arm 181 includes a first transistor 200 and a first diode 300, and a lower arm 182 includes a second transistor 400 and a second diode 500.

The heat generation density during operation of the first transistor 200 is greater than the heat generation density during operation of the first diode 300. Here, the heat generation density of an element is a value obtained by dividing the amount of heat (heat generation amount) generated when the element is operated by the area of a plane perpendicular to the thickness direction of the element. The amount of heat generated is equal to the sum of conduction loss and switching loss of the element. When the planar shape of the first transistor 200 is 3 mm x 3 mm and the total heat generation amount of the three first transistors 200 is 80 W, the heat generation density of each first transistor 200 is 80 W/(9 mm ² x 3). It is 2.96W/ ^mm2 . The first diode 300 improves recovery loss during switching operation of the first transistor 200. Therefore, although loss occurs in the first diode 300 during switching operation, conduction loss does not occur. Therefore, the heat generation density during operation of the first diode 300 is lower than the heat generation density during operation of the first transistor 200.

Since the heat generation density of the first diode 300 is low, the interval Ddi1 between the first diodes 300 may be small. On the other hand, when the distance Dsw1 between the first transistors 200 is equal to the distance Ddi1, the temperature variation of the first transistors 200 increases as follows.

Here, among the three first transistors 200, the one placed at the end on the X1 side is the first transistor 200A, the one placed in the center is the first transistor 200B, and the one placed at the end on the X2 side is the first transistor 200A. It is assumed that the first transistor is 200C. The heat generated in the first transistor 200 is propagated from the drain electrode 233 to the heat sink 121 via the first bonding material 131, the first conductive layer 11, the insulating substrate 123, the eighth conductive layer 18, and the fifth bonding material 138. . Also, heat propagates radially. Therefore, when the distance Dsw1 is equal to the distance Ddi1, the heat generated in the first transistor 200B is less likely to be released to the outside than the heat generated in the first transistor 200A and the heat generated in the first transistor 200C. As a result, the temperature variation of the first transistor 200 increases. On the other hand, in this embodiment, the distance Dsw1 between the first transistors 200 is larger than the distance Ddi1 between the first diodes 300. Therefore, the heat generated in the first transistor 200B is also easily released to the outside, and variations in the temperature of the first transistor 200 are reduced.

Furthermore, the heat generation density during operation of the second transistor 400 is greater than the heat generation density during operation of the second diode 500. When the distance Dsw2 between the second transistors 400 is equal to the distance Ddi2 between the second diodes 500, the temperature variation of the second transistors 400 increases. On the other hand, in this embodiment, since the distance Dsw2 between the second transistors 400 is larger than the distance Ddi2 between the second diodes 500, the heat generated in the second transistor 400 in the center is also easily released to the outside, and the temperature of the second transistor 400 decreases. variation is reduced.

Therefore, according to this embodiment, it is possible to achieve miniaturization while extending the life span and improving reliability. In other words, according to this embodiment, it is possible to achieve both miniaturization and improved reliability.

Further, when the distance Dsw1 is constant, it is easy to arrange the first transistor 200, and when the distance Ddi1 is constant, it is easy to arrange the first diode 300. When the distance Dsw2 is constant, it is easy to arrange the second transistor 400, and when the distance Ddi2 is constant, it is easy to arrange the second diode 500.

However, the interval Dsw1 and the interval Ddi1 do not need to be constant, and it is sufficient that the average interval ADsw1 is larger than the average interval ADdi1. Further, the interval Dsw2 and the interval Ddi2 do not need to be constant, and it is sufficient that the average interval ADsw2 is larger than the average interval ADdi2.

The first bonding material 131, the second bonding material 141, the third bonding material 132, and the fourth bonding material 142 can be formed, for example, by reflowing paste-like or pellet-like solder. When using paste solder, it may be applied all at once by a printing method.

Each of the first bonding materials 131 bonds one first transistor 200 to the first conductive layer 11 , and each of the second bonding materials 141 bonds one first diode 300 to the first conductive layer 11 . There is. Therefore, it is easy to suppress misalignment of the first transistor 200 and the first diode 300 during manufacturing. Further, each of the third bonding materials 132 bonds one second transistor 400 to the second conductive layer 12 , and each of the fourth bonding materials 142 bonds one second diode 500 to the second conductive layer 12 . are doing. Therefore, it is easy to suppress misalignment of the second transistor 400 and the second diode 500 during manufacturing.

It is preferable that the material of the first bonding material 131 and the material of the second bonding material 141 are the same. This is because it is easy to form the first bonding material 131 and the second bonding material 141 at the same time. Similarly, it is preferable that the material of the third bonding material 132 and the material of the fourth bonding material 142 are the same. This is because it is easy to form the third bonding material 132 and the fourth bonding material 142 at the same time. In particular, it is preferable that the first bonding material 131, the second bonding material 141, the third bonding material 132, and the fourth bonding material 142 are made of the same material.

Furthermore, it is preferable that the thickness of the first bonding material 131 and the thickness of the second bonding material 141 be equal. This is because it is easy to form the first bonding material 131 and the second bonding material 141 at the same time. Similarly, it is preferable that the thickness of the third bonding material 132 and the thickness of the fourth bonding material 142 be equal. This is because it is easy to form the third bonding material 132 and the fourth bonding material 142 at the same time. In particular, it is preferable that the first bonding material 131, the second bonding material 141, the third bonding material 132, and the fourth bonding material 142 have the same thickness.

The first transistor 200 and the second transistor 400 may be field effect transistors such as a MOS (metal-oxide-semiconductor) field effect transistor configured using silicon carbide. That is, first transistor 200 and second transistor 400 may be silicon carbide-based transistor elements. The first diode 300 and the second diode 500 may be Schottky barrier diodes made of silicon carbide. That is, first diode 300 and second diode 500 may be silicon carbide-based Schottky barrier diode elements. By using silicon carbide, excellent pressure resistance can be obtained.

(Second embodiment)
Next, a second embodiment will be described. The second embodiment differs from the first embodiment mainly in the arrangement of diodes. FIG. 5 is a top view showing the semiconductor module according to the second embodiment.

As shown in FIG. 5, in the semiconductor module 2 according to the second embodiment, the number of first diodes 300 and second diodes 500 is six.

Six first diodes 300 are arranged in the second region 112. Three first diodes 300 are arranged in the X1-X2 direction and two in the Y1-Y2 direction. The distance between the first diodes 300 in the X1-X2 direction and the distance in the Y1-Y2 direction is the distance Ddi1. Between the first diodes 300 arranged in the Y1-Y2 direction, the anode electrodes 332 are connected to each other by a plurality of bonding wires 165.

Similarly, six second diodes 500 are arranged in the fourth region 114. Three second diodes 500 are arranged in the X1-X2 direction and two in the Y1-Y2 direction. The distance between the second diode 500 in the X1-X2 direction and the distance in the Y1-Y2 direction is the distance Ddi2. Between the second diodes 500 arranged in the Y1-Y2 direction, the anode electrodes 532 are connected to each other by a plurality of bonding wires 175.

Also in the second embodiment, the interval Ddi1 is smaller than the interval Dsw1, and the interval Ddi2 is smaller than the interval Dsw2. Furthermore, the average spacing ADsw1 of the first transistors 200 is larger than the average spacing ADdi1 of the first diodes 300, and the average spacing ADsw2 of the second transistors 400 is larger than the average spacing ADdi2 of the second diodes 500.

The other configurations are the same as in the first embodiment. The semiconductor module 2 is an example of a semiconductor device.

According to the second embodiment as well, variations in temperature of the first transistor 200 and variations in temperature of the second transistor 400 are reduced, lengthening the life and improving reliability.

Note that when the diode elements are arranged in a plurality of rows as in the second embodiment, the spacing between the diode elements includes not only the spacing in the X1-X2 direction but also the spacing in the Y1-Y2 direction. It will be done. That is, the average interval is the average value of the intervals in the X1-X2 direction and the Y1-Y2 direction.

(Third embodiment)
Next, a third embodiment will be described. The third embodiment differs from the first embodiment mainly in the arrangement of transistors and diodes. FIG. 6 is a top view showing a semiconductor module according to a third embodiment. 7 and 8 are cross-sectional views showing a semiconductor module according to a third embodiment. FIG. 7 corresponds to a cross-sectional view taken along line VII-VII in FIG. FIG. 8 corresponds to a cross-sectional view taken along line VIII-VIII in FIG.

As shown in FIGS. 6 to 8, in the semiconductor module 3 according to the third embodiment, the number of first transistors 200, second transistors 400, first diodes 300, and second diodes 500 are all four.

The four first transistors 200 are arranged in a line in the X1-X2 direction. The distance between the two first transistors 200 arranged at the center in the X1-X2 direction is a distance Dsw1a. The interval between the two first transistors 200 arranged at the end on the X1 side is the interval Dsw1b, and the interval between the two first transistors 200 arranged at the end on the X2 side is the interval Dsw1b. The interval Dsw1a is larger than the interval Dsw1b. In this way, the distance between two adjacent first transistors 200 among the four first transistors 200 is larger as the combination of first transistors 200 is closer to the center of gravity G1 of the first region 111. The distance Dsw1a is, for example, 2 mm or more and 10 mm or less, and the distance Dsw1b is, for example, 2 mm or more and 10 mm or less.

The four first diodes 300 are arranged in a line in the X1-X2 direction. The distance between the two first diodes 300 arranged at the center in the X1-X2 direction is a distance Ddi1a. The interval between the two first diodes 300 arranged at the end on the X1 side is the interval Ddi1b, and the interval between the two first diodes 300 arranged at the end on the X2 side is the interval Ddi1b. The interval Ddi1a is larger than the interval Ddi1b. In this way, the distance between two adjacent first diodes 300 among the four first diodes 300 is larger as the combination of first diodes 300 is closer to the center of gravity G2 of the second region 112. The interval Ddi1a is, for example, 1 mm or more and 8 mm or less, and the interval Ddi1b is, for example, 2 mm or more and 9 mm or less.

Further, the average spacing between the first transistors 200 is larger than the average spacing between the first diodes 300. It is preferable that the distances Ddi1a and Ddi1b are smaller than the distances Dsw1a and Dsw1b.

The four second transistors 400 are arranged in a line in the X1-X2 direction. The distance between the two second transistors 400 arranged at the center in the X1-X2 direction is a distance Dsw2a. The interval between the two second transistors 400 arranged at the end on the X1 side is the interval Dsw2b, and the interval between the two second transistors 400 arranged at the end on the X2 side is the interval Dsw2b. The interval Dsw2a is larger than the interval Dsw2b. In this way, the distance between two adjacent second transistors 400 among the four second transistors 400 is larger as the combination of second transistors 400 is closer to the center of gravity G3 of the third region 113. The distance Dsw2a is, for example, 3 mm or more and 10 mm or less, and the distance Dsw2b is, for example, 2 mm or more and 9 mm or less.

The four second diodes 500 are arranged in a line in the X1-X2 direction. The distance between the two second diodes 500 arranged at the center in the X1-X2 direction is a distance Ddi2a. The interval between the two second diodes 500 arranged at the end on the X1 side is the interval Ddi2b, and the interval between the two second diodes 500 arranged at the end on the X2 side is the interval Ddi2b. The interval Ddi2a is larger than the interval Ddi2b. In this way, the distance between two adjacent second diodes 500 among the four second diodes 500 is larger as the combination of second diodes 500 is closer to the center of gravity G4 of the fourth region 114. The distance Ddi2a is, for example, 2 mm or more and 9 mm or less, and the distance Ddi2b is, for example, 1 mm or more and 8 mm or less.

Furthermore, the average spacing between the second transistors 400 is larger than the average spacing between the second diodes 500. It is preferable that the distances Ddi2a and Ddi2b are smaller than the distances Dsw2a and Dsw2b.

The other configurations are the same as in the first embodiment. The semiconductor module 3 is an example of a semiconductor device.

According to the third embodiment as well, variations in temperature of the first transistor 200 and variations in temperature of the second transistor 400 are reduced, lengthening the life and improving reliability. Furthermore, among the four first transistors 200, the heat generated in the first transistor 200 that is closer to the center of gravity of the first region 111 is more easily dissipated, and among the four second transistors 400, the heat generated in the first transistor 200 that is closer to the center of gravity of the third region 113 is released. It is possible to more easily dissipate heat generated in the second transistor 400 near the second transistor 400 . Moreover, it is easier to release the heat generated in the first diode 300 which is closer to the center of gravity of the second region 112 among the four first diodes 300; The heat generated in the second diode 500 near the second diode 500 can be more easily released. Therefore, it is easy to further improve reliability.

Further, in the present disclosure, the distance between adjacent switching elements does not need to be constant, and the distance between adjacent diode elements does not need to be constant. However, it is preferable that the minimum value of the interval between adjacent switching elements is larger than the maximum value of the interval between adjacent diode elements.

Although the embodiments have been described in detail above, they are not limited to specific embodiments, and various modifications and changes are possible within the scope of the claims.

1, 2, 3: Semiconductor module (semiconductor device)
11: First conductive layer 12: Second conductive layer 13: Third conductive layer 14: Fourth conductive layer 15: Fifth conductive layer 16: Sixth conductive layer 17: Seventh conductive layer 18: Eighth conductive layer 101: P terminal 102: N terminal 103: O terminal 104: First gate terminal 105: Second gate terminal 106: First sense source terminal 107: Second sense source terminal 111: First region 112: Second region 113: Third Region 114: Fourth region 121: Heat sink 122: Housing 123: Insulating substrate 131: First bonding material 132: Third bonding material 138: Fifth bonding material 141: Second bonding material 142: Fourth bonding material 161, 162, 163, 164, 165, 171, 172, 173, 174, 175: Bonding wire 181: Upper arm 182: Lower arm 191, 192: Side wall portion 193, 194: End wall portion 200: First transistor (switching element)
231, 431: Gate electrode 232, 432: Source electrode 233, 433: Drain electrode 300: First diode (diode element)
332, 532: Anode electrode 333, 533: Cathode electrode 400: Second transistor (switching element)
500: Second diode (diode element)

Claims (11)

an insulating substrate;
a conductive layer formed on the insulating substrate and having a first region and a second region;
a plurality of switching elements provided on the first region of the conductive layer and electrically connected to each other in parallel;
a plurality of diode elements provided on the second region of the conductive layer;
has
The plurality of diode elements are electrically connected in parallel to the plurality of switching elements,
A semiconductor device in which an average interval between the plurality of switching elements is larger than an average interval between the plurality of diode elements. 2. The semiconductor device according to claim 1, wherein the heat generation density during operation of the switching element is greater than the heat generation density during operation of the diode element. 3. The semiconductor device according to claim 1, wherein the plurality of switching elements are arranged in a line at equal intervals. 3. The semiconductor device according to claim 1, wherein the plurality of diode elements are arranged at equal intervals. The first region is the smallest first rectangular region surrounding the plurality of switching elements in a plan view,
3. The semiconductor device according to claim 1, wherein the distance between two adjacent switching elements among the plurality of switching elements is larger as the combination of switching elements is closer to the center of gravity of the first rectangular region. The second region is the smallest second rectangular region surrounding the plurality of diode elements in plan view,
3. The semiconductor device according to claim 1, wherein the distance between two adjacent diode elements among the plurality of diode elements is larger as the combination of diode elements is closer to the center of gravity of the second rectangular region. 3. The semiconductor device according to claim 1, wherein the switching element is a silicon carbide transistor element. 3. The semiconductor device according to claim 1, wherein the diode element is a silicon carbide-based Schottky barrier diode element. the same number of first bonding materials as the switching elements;
a second bonding material in the same number as the diode elements;
has
each of the first bonding materials bonding one of the switching elements to the conductive layer;
3. The semiconductor device according to claim 1, wherein each of the second bonding materials bonds one of the diode elements to the conductive layer. 10. The semiconductor device according to claim 9, wherein the first bonding material and the second bonding material are the same material. The semiconductor device according to claim 9, wherein the thickness of the first bonding material and the thickness of the second bonding material are equal.

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