JP2023158144A - Memory system and control method - Google Patents

Abstract

To provide a memory system capable of accessing a non-volatile memory without a die contention.SOLUTION: A controller of a memory system classifies a plurality of non-volatile memory dies into a first die group and a second die group so that each of the plurality of non-volatile memory dies connected to a plurality of channels belongs to only one die group. When the controller receives a first write command specifying a first name space from a host, the controller writes first data to be written into the first name space into a first write destination block selected from the first die group. When the controller receives a second write command specifying a second name space from the host, the controller writes second data to be written into the second name space into a second write destination block selected from the second die group.SELECTED DRAWING: Figure 3

Description

Embodiments of the present invention relate to techniques for controlling nonvolatile memory.

In recent years, memory systems including nonvolatile memory have become widespread.

As one such memory system, a solid state drive (SSD) based on NAND flash technology is known. SSDs are used as storage in various computers due to their low power consumption and high performance characteristics.

Typically, an SSD is equipped with a large number of nonvolatile memory dies to increase its capacity. Each non-volatile memory die can operate independently. Therefore, each nonvolatile memory can function as a unit of parallel processing.

US Patent Application Publication No. 2013/019057

However, operations on a single non-volatile memory die are typically not performed in parallel but sequentially. Therefore, if a read request occurs to a nonvolatile memory die on which a write operation is being performed (die contention), the response time (read latency) of the read request may become extremely long.

Therefore, there is a need to implement new functionality to allow hosts to access SSDs without die contention.

The problem to be solved by the present invention is to provide a memory system and control method that can access non-volatile memory without die contention.

According to embodiments, a memory system connectable to a host is a non-volatile memory including a plurality of channels and a plurality of non-volatile memory dies connected to the plurality of channels, each non-volatile memory die having a plurality of blocks. and a controller connected to the plurality of non-volatile memory dies via the plurality of channels and configured to control the plurality of non-volatile memory dies. The controller allocates logical address space of the memory system to a plurality of namespaces including at least a first namespace and a second namespace. The controller classifies the plurality of non-volatile memory dies into a first die group and a second die group such that each of the plurality of non-volatile memory dies belongs to only one die group. When the controller receives a first write command specifying the first namespace corresponding to the first die group from the host, the controller writes the first data to be written to the first namespace. Writing to a first destination block selected from a first die group. When the controller receives a second write command specifying the second namespace corresponding to the second die group from the host, the controller writes the second data to be written to the second namespace. Writing to a second destination block selected from a second die group.

FIG. 1 is a block diagram illustrating a configuration example of a memory system according to an embodiment. FIG. 2 is a block diagram illustrating a plurality of non-volatile memory sets (NVM sets) each spanning a plurality of channels, obtained by sorting a plurality of NAND flash memory dies in the memory system of the embodiment. FIG. 3 is a block diagram showing the relationship between block management corresponding to each NVM set in FIG. 2 and one or more areas (name space) corresponding to each NVM set. FIG. 6 is a diagram illustrating host write/garbage collection operations for separated NVM sets performed by the memory system of the embodiment. FIG. 6 is a diagram illustrating host write/garbage collection operations for a shared NVM set performed by the memory system of the embodiment. FIG. 3 is a block diagram illustrating a plurality of NVM sets, each including a set of NAND flash memory dies connected to the same channel, obtained by sorting a plurality of NAND flash memory dies in the memory system of the embodiment. FIG. 7 is a block diagram showing the relationship between block management corresponding to each NVM set in FIG. 6 and one or more areas (name space) corresponding to each NVM set. FIG. 2 is a diagram schematically showing a flash memory package applied to the memory system of the same embodiment. 9 is a cross-sectional view showing the structure of the flash memory package of FIG. 8. FIG. FIG. 3 is a diagram showing the relationship between a plurality of NVM sets each including a set of NAND flash memory dies connected to the same channel and one or more flash memory packages used as these NVM sets. FIG. 6 is a diagram illustrating a portion of a garbage collection operation for a certain NVM subset performed by the memory system of the embodiment. FIG. 6 is a diagram illustrating a remaining part of the garbage collection operation for a certain NVM subset performed by the memory system of the same embodiment. FIG. 7 is a diagram illustrating the remaining portions of the garbage collection operation for an NVM subset performed by the memory system of the same embodiment. FIG. 6 is a diagram showing an inter-NVM set copy operation executed by the memory system of the embodiment. 15 is a diagram showing the relationship between the contents of the address conversion table before the inter-NVM set copy operation in FIG. 14 and the contents of the address conversion table after the NVM set-to-NVM set copy operation. FIG. FIG. 6 is a diagram illustrating a portion of the NVM set-to-NVM set copy operation executed by the memory system of the embodiment. FIG. 7 is a diagram illustrating the remaining part of the NVM inter-set copy operation executed by the memory system of the embodiment. FIG. 7 is a diagram illustrating the remaining portions of the NVM inter-set copy operation executed by the memory system of the embodiment. FIG. 3 is a diagram for explaining an overview of an NVM set exchange operation executed by the memory system of the embodiment. FIG. 6 is a diagram illustrating a host write/garbage collection operation performed for two NVM sets prior to an NVM set exchange operation. FIG. 3 is a diagram illustrating a host write/garbage collection operation performed between two NVM sets for an NVM set exchange operation. FIG. 3 is a diagram illustrating an overview of a new NVM set creation operation executed by the memory system of the embodiment. FIG. 4 is a diagram for explaining host write/garbage collection operations executed to create a new NVM set. FIG. 6 is a diagram illustrating a part of the new NVM set creation operation executed by the memory system of the embodiment. FIG. 7 is a diagram showing the remaining part of the new NVM set creation operation executed by the memory system of the embodiment. FIG. 7 is a diagram illustrating the remaining part of the new NVM set creation operation executed by the memory system of the embodiment. FIG. 3 is a diagram illustrating an overview of an NVM set combination operation executed by the memory system of the embodiment. FIG. 6 is a diagram for explaining host write/garbage collection operations performed for NVM set combination. 3 is a flowchart showing a part of the procedure of data write/read operations executed by the memory system of the same embodiment. 7 is a flowchart showing the remaining part of the data write/read operation procedure executed by the memory system of the embodiment. 7 is a flowchart showing the procedure of a garbage collection operation executed for each NVM subset by the memory system of the embodiment. 7 is a flowchart showing a procedure for an inter-NVM set copy operation executed by the memory system of the embodiment. 7 is a flowchart illustrating another procedure of the NVM set-to-set copy operation executed by the memory system of the embodiment. 7 is a flowchart showing the procedure of a new NVM set creation operation executed by the memory system of the embodiment. 7 is a flowchart showing another procedure of the new NVM set creation operation executed by the memory system of the embodiment. FIG. 3 is a block diagram illustrating a configuration example of a host applied to the memory system of the embodiment. FIG. 2 is a block diagram showing a configuration example of a computer including a memory system and a host according to the embodiment.

Hereinafter, embodiments will be described with reference to the drawings.
First, with reference to FIG. 1, the configuration of an information processing system 1 including a memory system according to an embodiment will be described.

The memory system is a semiconductor storage device configured to write data to and read data from non-volatile memory. This memory system is realized, for example, as a solid state drive (SSD) 3 based on NAND flash technology.

The information processing system 1 includes a host (host device) 2 and an SSD 3. The host 2 is an information processing device such as a server or a personal computer. A typical example of a server functioning as the host 2 is a server in a data center.

In the case where the host 2 is realized by a server in a data center, this host (server) 2 may be connected to a plurality of end user terminals 51 via a network 50. The host 2 can provide various services to these end user terminals 51. Multiple virtual machines may be executed on this physical server functioning as the host (server) 2. These virtual machines can function as virtual servers configured to provide various services to corresponding clients (end user terminals 51).

The SSD 3 may be used as the main storage of an information processing apparatus (computing device) functioning as the host 2. The SSD 3 may be built into the information processing device, or may be connected to the information processing device via a cable or a network.

Interfaces for interconnecting the host 2 and the SSD 3 include SCSI, Serial Attached SCSI (SAS), ATA, Serial ATA (SATA), PCI Express (PCIe), Ethernet (registered trademark), Fibre channel, and NV. M Express ( NVMe) (registered trademark), etc. may be used.

The SSD 3 includes a controller 4 and a nonvolatile memory (NAND flash memory) 5. SSD 3 may also include random access memory, for example DRAM 6.

The NAND flash memory 5 includes a memory cell array including a plurality of memory cells arranged in a matrix. The NAND flash memory 5 may be a two-dimensional NAND flash memory or a three-dimensional NAND flash memory.

The memory cell array of the NAND flash memory 5 includes a plurality of blocks B0 to Bm-1. Each of blocks B0 to Bm-1 is organized by a number of pages (pages P0 to Pn-1 here). Blocks B0 to Bm-1 function as erase units. A block is sometimes referred to as an "erase block" or "physical block." Each of pages P0 to Pn-1 includes a plurality of memory cells connected to the same word line. Pages P0 to Pn-1 are units of data write operations and data read operations.

The controller 4 is electrically connected to the NAND flash memory 5 via a NAND interface 13 such as Toggle, an open NAND flash interface (ONFI), and a plurality of channels (Ch). The NAND interface 13 functions as a NAND control circuit configured to control the NAND flash memory 5.

As shown in FIG. 2, the NAND flash memory 5 includes a plurality of NAND flash memory dies (indicated as "NAND dies" in FIG. 2). Each NAND flash memory die is a nonvolatile memory die that includes a memory cell array including a plurality of blocks and peripheral circuitry that controls the memory cell array. Each NAND flash memory die can operate independently. Therefore, a NAND flash memory die functions as a single parallel operating unit. A NAND flash memory die is also referred to as a "NAND flash memory chip."

In FIG. 2, a plurality of channels Ch0, Ch1, Ch2, ... ChN are connected to the NAND interface 13, and each of these channels Ch0, Ch1, Ch2, ... ChN has the same number of dies (for example, K dies per channel, A case is illustrated in which NAND flash memory dies (K is an integer of 2 or more) are connected. Each channel includes a communication line (memory bus) for communicating with a corresponding NAND flash memory die.

In FIG. 2, NAND flash memory dies 600, 601, 602-606 are connected to channel Ch0. NAND flash memory dies 610, 611, 612-616 are connected to channel Ch1. NAND flash memory dies 620, 621, 622-626 are connected to channel Ch2. Similarly, NAND flash memory dies 640, 641, 642-646 are connected to channel ChN.

The controller 4 controls the NAND flash memory 5 via channels Ch0, Ch1, Ch2, . . . ChN. The controller 4 can drive channels Ch0, Ch1, Ch2, . . . ChN simultaneously. That is, the NAND interface 13 includes N NAND control circuits corresponding to channels Ch0, Ch1, Ch2, . . . ChN, respectively. By using these NAND control circuits, the controller 4 can drive channels Ch0, Ch1, Ch2, . . . ChN independently of each other.

In this embodiment, the controller 4 classifies the K×N NAND flash memory dies 600 to 646 into a plurality of die groups so that each NAND flash memory die belongs to only one die group. Hereinafter, this die group will be referred to as a "non-volatile memory subset (NVM set)".

In FIG. 2, each NVM set spans multiple channels Ch0, Ch1, Ch2,...ChN. For example, the NVM set 60 includes NAND flash memory dies 600, 610, 620, . . . 640 connected to channels Ch0, Ch1, Ch2, . . . ChN, respectively. The NVM set 61 includes NAND flash memory dies 601, 611, 621, . . . 641 connected to channels Ch0, Ch1, Ch2, . . . ChN, respectively. The NVM set 62 includes NAND flash memory dies 602, 603, ... 605, 606 connected to channel Ch0, NAND flash memory dies 612, 613, ... 615, 616 connected to channel Ch1, and NAND flash memory dies 612, 613, ... 615, 616 connected to channel Ch2. 625, 626, and NAND flash memory dies 642, 643, . . . 645, 646 connected to the channel ChN.

Thus, in FIG. 2, the K×N NAND flash memory dies 600-646 are classified into multiple NVM sets, each spanning multiple channels. In each NVM set, data write/read operations can be performed simultaneously on a maximum of N NAND flash memory dies.

A plurality of areas that can be specified by the host 2 can be associated with each of these plurality of NVM sets. These multiple areas are logical areas that can be accessed by the host 2. The number of areas corresponding to each NVM set may be one, or may be two or more. Furthermore, the number of regions corresponding to each NVM set may be different for each NVM set.

The controller 4 can simultaneously execute a plurality of I/O commands (write commands or read commands) each specifying a different area corresponding to a different NVM set without die contention. Therefore, for example, even if a read command directed to the area corresponding to the NVM set 61 is received from the host 2 while a data write operation is being executed for the NVM set 60, the controller 4 waits for the completion of this data write operation. Therefore, the data read operation corresponding to this read command can be executed immediately.

In the SSD 3 shown in FIG. 1, the controller 4 also functions as a flash translation layer (FTL) configured to perform data management of the NAND flash memory 5 and block management of the NAND flash memory 5. be able to.

Data management performed by this FTL includes (1) management of mapping information indicating the correspondence between each logical address and each physical address of the NAND flash memory 5, (2) read/write in page units, This includes block-by-block erase operations and processing for concealing them. The logical address is the address used by the host 2 to address the SSD 3. A logical block address (LBA) is normally used as this logical address.

Management of the mapping between each logical block address (LBA) and each physical address is performed using a look-up table (LUT) that functions as an address translation table (logical-physical address translation table). A physical address corresponding to a certain LBA indicates a physical storage position in the NAND flash memory 5 to which data of this LBA has been written. The look-up table (LUT) may be loaded from the NAND flash memory 5 to the DRAM 6 when the SSD 3 is powered on. Generally, the size of each lookup table is relatively large. Therefore, at least a portion of each lookup table may be stored in the DRAM 6 as an address translation table cache.

In the NAND flash memory 5, data can be written to a page only once per erase cycle. Therefore, the controller 4 writes update data corresponding to a certain LBA to a different physical storage location, rather than to the physical storage location where the previous data corresponding to this LBA is stored. Controller 4 then updates a corresponding look-up table (LUT) to associate this LBA with this other physical storage location. As a result, previous data corresponding to this LBA is invalidated.

In this embodiment, a plurality of look-up tables (LUTs) 40, 41, 42, . . . are used. These lookup tables (LUTs) 40, 41, 42, . . . basically correspond to a plurality of NVM sets, respectively. Note that each lookup table may be associated with one area or one group of garbage collection.

Each NVM set includes at least one group for garbage collection. A group for garbage collection includes a plurality of blocks and is used as a unit for garbage collection. For NVM sets containing only one group for garbage collection, only one lookup table may be used. For NVM sets that include multiple groups for garbage collection, multiple lookup tables may be used.

The controller 4 further has a multi-name space control function. The multi-name space control function allows multiple logical address spaces (LBA spaces) to be assigned to the SSD 3 in order to treat one storage device as if it were multiple drives.

Each of the multiple areas described above may be implemented by a namespace. Each name space corresponds to an area within the NAND flash memory 5. Each namespace is assigned a logical address range (LBA range). The size of the LBA range (ie, the number of LBAs) is variable for each namespace. Each LBA range starts at LBA0. Individual namespaces are identified by their namespace identifiers.

The write command from the host 2 includes an identifier for a specific namespace, ie, a namespace ID (NSID). Based on the namespace ID in the write command from the host 2, the controller 4 determines the access target area (namespace) into which the write data is to be written. Similarly, a read command from the host 2 also includes a namespace ID corresponding to a specific namespace. Based on the namespace ID in the read command from the host 2, the controller 4 determines the area (namespace) to be accessed from which data is to be read.

Block management includes bad block management, wear leveling, garbage collection, etc.

Wear leveling is an operation to equalize the wear of each block.

Garbage collection is an operation to increase the number of free blocks into which data can be written. In the garbage collection operation, the controller 4 copies only valid data in some blocks in which valid data and invalid data are mixed to another block (for example, a free block). Here, valid data refers to data that is referenced from the LUT (that is, data that is linked as the latest data from the logical address) and that may be read from the host 2 later. . Invalid data means data that can no longer be read by the host 2. For example, data that is associated with a certain logical address is valid data, and data that is not associated with any logical address is invalid data. Then, the controller 4 maps each LBA of the copied valid data to the copy destination physical address of the valid data. A block whose valid data is copied to another block and contains only invalid data is released as a free block. This allows this block to be reused after its erase operation has been performed.

Next, the configuration of the controller 4 will be explained.

The controller 4 includes a host interface 11, a CPU 12, a NAND interface 13, a DRAM interface 14, and the like. These CPU 12, NAND interface 13, and DRAM interface 14 are interconnected via a bus 10.

This host interface 11 is a host interface circuit configured to communicate with the host 2. This host interface 11 may be, for example, a PCIe controller (NVMe controller). The host interface 11 receives various commands (write commands, read commands, various control commands, UNMAP commands, etc.) from the host 2 .

The write command requests the SSD 3 to write data specified by this write command. The write command may include a starting LBA, transfer length, and ID. The ID in the write command is an identifier for uniquely identifying the area in which data is to be written. This ID may be a namespace ID. The read command requests the SSD 3 to read the data specified by this read command. The read command may include a starting LBA, transfer length, and ID. The ID in the read command is an identifier for uniquely identifying the area from which data is to be read. This ID may be a namespace ID.

The CPU 12 is a processor configured to control the host interface 11, the NAND interface 13, and the DRAM interface 14. The CPU 12 loads a control program (firmware) from the NAND flash memory 5 or a ROM (not shown) into the DRAM 6 in response to power-on of the SSD 3, and executes the firmware to perform various processes. Note that the firmware may be loaded onto an SRAM (not shown) in the controller 4. This CPU 12 is capable of executing command processing for processing various commands from the host 2, for example, in addition to the above-mentioned FTL processing. The operation of the CPU 12 is controlled by the above-mentioned firmware executed by the CPU 12. Note that part or all of the FTL processing and command processing may be executed by dedicated hardware within the controller 4.

The CPU 12 functions as an NVM set control unit 21, a garbage collection (GC) operation control unit 22, an inter-NVM set copy control unit 23, a new NVM set creation control unit 24, an NVM set exchange control unit 25, and an NVM set combination unit 26. be able to.

The NVM set control unit 21 connects the K×N NAND flash memory dies 600 to 646 to multiple NVM sets so that each of the K×N NAND flash memory dies 600 to 646 belongs to only one NVM set. Classify into. Then, the NVM set control unit 21 controls the number of areas within the plurality of NVM sets in response to an I/O command from the host 2 that specifies any one of the plurality of areas including at least one area corresponding to each NVM set. Perform data write/read operations for one NVM set. For example, in a case where a plurality of NVM sets include a first NVM set and a second NVM set, the NVM set control unit 21 receives a message from the host 2 that specifies at least one area corresponding to the first NVM set. a second I/O command from the host 2 that performs a data write/read operation for the first NVM set and specifies at least one region corresponding to the second NVM set; Performing data write/read operations for the second NVM set in response to the /O command.

Further, the NVM set control unit 21 individually controls free block groups in the NAND flash memory 5 (a large number of NAND flash memory dies) 5 for each NVM set by using a plurality of free block pools respectively corresponding to the plurality of NVM sets. to be managed. A free block means a block that does not hold valid data. For example, each free block belonging to a first NVM set is managed by a first free block pool corresponding to the first NVM set, and each free block belonging to a second NVM set is managed by a first free block pool corresponding to the first NVM set. managed by a corresponding second free block pool. During the operation of initializing the SSD 3, the NVM set control unit 21 places all blocks belonging to the first NVM set in the first free block pool, and places all blocks belonging to the second NVM set in the first free block pool. Place it in the 2nd free block pool.

For each of the plurality of NVM sets, the NVM set control unit 21 stores one of the free blocks in the corresponding free block pool as user data (write data from the host 2 or data to be copied for garbage collection). the act of allocating this user data as a block to be written to, the act of writing this user data into the allocated block, the act of managing the block filled with this user data by a data block pool (also known as the active block pool), and and returning blocks that are managed by the pool and do not hold valid data to the corresponding free block pool.

As a result, blocks placed in the free block pool corresponding to a certain NVM set can be used only by one or more areas corresponding to this NVM set, so that die contention does not occur between multiple NVM sets. It becomes possible to guarantee. Note that the data block pool refers to a pool for managing each block that belongs to a corresponding NVM set and holds valid data.

In this embodiment, two types of NVM sets can be handled: a separated NVM set and a shared NVM set.

A separated NVM set is an NVM set that includes only one garbage collection group (only one data block pool). That is, the free block pool corresponding to a separated NVM set is a free block pool dedicated to a single data block pool that manages each block that belongs to this NVM set and holds valid data. In an isolated NVM set, a single data block pool occupies the free block pool corresponding to the isolated NVM set.

The shared NVM set is an NVM set that includes multiple garbage collection groups (multiple data block pools). In other words, a free block pool corresponding to a shared NVM set is a free block pool shared by a plurality of data block pools that manage blocks that belong to this NVM set and hold valid data, respectively. In a shared NVM set, multiple data block pools share a free block pool that corresponds to the shared NVM set.

The garbage collection (GC) operation control unit 22 independently executes garbage collection for each of the above-mentioned garbage collection groups.

In garbage collection of a separated NVM set, that is, garbage collection of a group of blocks within a single data block pool belonging to a separated NVM set, the GC operation control unit 22 (1) corresponds to the separated NVM set; (2) Allocate one of the free blocks in the free block pool to be the copy destination block, and (2) copy only valid data from one or more blocks included in this data block pool and in which valid data and invalid data are mixed. and (3) return the block, which has become only invalid data due to the copying of valid data to the copy destination block, to the free block pool corresponding to the separated NVM set. This allows free blocks created by GC of a certain isolated NVM set to be used only by one or more regions corresponding to this NVM set, ensuring that die contention does not occur between multiple NVM sets. It becomes possible to guarantee this.

In garbage collection of a shared NVM set, that is, garbage collection of a group of blocks in one data block pool of a plurality of data block pools belonging to the shared NVM set, the GC operation control unit 22 performs the following steps: (1) corresponding to the shared NVM set; Allocate one of the free blocks in the free block pool as the copy destination block, and (2) copy only valid data from one or more blocks included in one data block pool and in which valid data and invalid data are mixed. and (3) returning one or more blocks, which are reduced to only invalid data by copying valid data to the destination block, to the free block pool corresponding to the shared NVM set. This ensures that die contention does not occur between multiple NVM sets, since free blocks created by the GC of a certain shared NVM set can be used only by one or more regions corresponding to this shared NVM set. It becomes possible to do so.

The inter-NVM set copy control unit 23 executes an inter-NVM set copy operation in order to equalize the degree of wear (number of program/erase cycles) of each NVM set. This inter-NVM set copy operation can be used, for example, to copy valid data stored in a separate NVM set with a high degree of wear to a separate NVM set with a low degree of wear. This makes it possible to equalize the degree of wear of these NVM sets. The host 2 can send to the SSD 3 an inter-NVM set copy command that includes parameters specifying a copy source NVM set and a copy destination NVM set.

The inter-NVM set copy control unit 23 (1) selects a block that holds valid data from the blocks belonging to the copy source NVM set as a copy source block, and (2) transfers only the valid data in the copy source block to the copy destination NVM. (3) update the lookup table that manages the mapping between each logical address and each physical address of the source NVM set; The physical address indicating the physical storage location in the copy destination block where the valid data has been copied is mapped to the logical address corresponding to the valid data that has been copied, and (4) if there is no valid data from the copy source block, the copy source block is returned to the free block pool corresponding to the copy source NVM set, and (5) operations (1) to (4) are repeated until there are no blocks holding valid data in the copy source NVM set. This allows data in the source NVM set (data with a high update frequency) to be moved to a destination NVM set with a lower number of program/erase cycles. As a result, a copy destination NVM set with a low degree of wear is used for writing data having a high update frequency. Therefore, it is possible to delay the timing at which the number of program/erase cycles of the copy source NVM set reaches the limit value.

The new NVM set creation control unit 24 creates a new NVM set from other NVM sets. For example, the new NVM set creation control unit 24 can create a part of the NAND flash memory die set in a certain NVM set as a new NVM set. This allows one NVM set to be divided into two NVM sets.

The NVM set exchange control unit 25 executes an NVM set exchange operation in order to equalize the degree of wear (number of program/erase cycles) of each NVM set. This NVM set exchange operation can be used, for example, to exchange data between a separate NVM set with high wearout and a separate NVM set with low wearout. This makes it possible to equalize the degree of wear of these NVM sets. The host 2 can send to the SSD 3 an NVM set exchange command that includes parameters specifying two NVM sets (a first NVM set, a second NVM set) with which stored data should be exchanged.

The NVM set exchange control unit 25 operates to copy only valid data in the first NVM set to the second NVM set, and to copy only valid data in the second NVM set to the first NVM set. and execute.

In the operation of copying only valid data in the first NVM set to the second NVM set, the NVM set exchange control unit 25 (1) extracts blocks holding valid data from blocks belonging to the first NVM set; (2) copy only the valid data in the copy source block to the copy destination block allocated from the free block pool corresponding to the second NVM set, and (3) copy each logical address and the Update the lookup table that manages the mapping between each physical address in the NVM set of 1 to the physical storage location in the destination block where the valid data was copied to the logical address corresponding to the copied valid data. (4) If there is no valid data from the copy source block, return the copy source block to the free block pool corresponding to the first NVM set, and (5) return the copy source block to the free block pool corresponding to the first NVM set. The operations (6) to (9) are repeated until there are no more blocks holding valid data.

In the operation of copying only valid data in the second NVM set to the first NVM set, the NVM set exchange control unit 25 (1) extracts blocks holding valid data from blocks belonging to the second NVM set; (2) copy only the valid data in the copy source block to the copy destination block allocated from the free block pool corresponding to the first NVM set, and (3) copy each logical address and the Update the lookup table that manages the mapping between each of the physical addresses of the NVM set of 2 and the physical storage location in the destination block where the valid data was copied to the logical address corresponding to the copied valid data. (4) If there is no valid data from the copy source block, return the copy source block to the free block pool corresponding to the second NVM set, and (5) return the copy source block to the free block pool corresponding to the second NVM set. The operations (1) to (4) are repeated until there are no more blocks holding valid data.

This makes it possible to equalize the degree of consumption of these two NVM sets.

The NVM set combining unit 26 combines two or more NVM sets into one NVM set. Two or more NVM sets to be combined and one NVM set to be combined can be specified by the host 2.

The NAND interface 13 controls the NAND flash memory 5 under the control of the CPU 12. DRAM interface 14 is a DRAM controller configured to control DRAM 6 under the control of CPU 12. A part of the storage area of the DRAM 6 is used as a write buffer (WB) for temporarily storing write data from the host 2. In this embodiment, a plurality of write buffers (WB) 30, 31, 32, . . . are used. At least one write buffer (WB) may be provided for each NVM set. Further, another part of the storage area of the DRAM 6 is used to store the above-mentioned look-up tables (LUTs) 40, 41, 42, . . . .

FIG. 3 shows an example of the relationship between block management corresponding to each NVM set in FIG. 2 and one or more areas (name space) corresponding to each NVM set.

The NVM set 60 includes a NAND flash memory die 600 connected to channel Ch0, a NAND flash memory die 610 connected to channel Ch1, a NAND flash memory die 620 connected to channel Ch2, ... connected to channel ChN. It includes a NAND type flash memory die 640. Each block (free block) that belongs to the NVM set 60 and does not hold valid data is managed by a free block pool 80 corresponding to the NVM set 60. In the process of initializing the SSD 3, the controller 4 transfers all blocks belonging to the NVM set 60, that is, all blocks in the NAND flash memory die 600, 610, 620, ... 640, to the free memory corresponding to the NVM set 60. Place it in the block pool 80.

Blocks belonging to NVM set 60 are managed using free block pool 80 and NVM subset 90. The NVM subset 90 is a data block pool for managing each block that belongs to the NVM set 60 and holds valid data. A group of blocks included in this NVM subset 90 constitutes one garbage collection group.

Free block pool 80 is a free block pool dedicated to one NVM subset 90. Therefore, NVM set 60 functions as an NVM set (separated NVM set) that is occupied by one NVM subset 90. One write buffer (WB) 30 is associated with the NVM subset 90.

The NVM set 60 is used as a physical storage space for at least one area (name space) that can be specified by the host 2. NVM set 60 may be a physical storage space dedicated to only one namespace. In FIG. 3, a case is illustrated in which the NVM set 60 is used as a physical storage space for two namespaces 100 and 101.

The NVM set 61 includes a NAND flash memory die 601 connected to channel Ch0, a NAND flash memory die 611 connected to channel Ch1, a NAND flash memory die 621 connected to channel Ch2, ... connected to channel ChN. It includes a NAND type flash memory die 641. Each block (free block) that belongs to the NVM set 61 and does not hold valid data is managed by a free block pool 81 corresponding to the NVM set 61. In the process of initializing the SSD 3, the controller 4 transfers all blocks belonging to the NVM set 61, that is, all blocks in the NAND flash memory die 601, 611, 621, ... 641, to the free memory corresponding to the NVM set 61. Place it in the block pool 81.

Blocks belonging to NVM set 61 are managed using free block pool 81 and NVM subset 91. The NVM subset 91 is a data block pool for managing each block that belongs to the NVM set 61 and holds valid data. A group of blocks included in this NVM subset 91 constitutes one garbage collection group. Free block pool 81 is a free block pool dedicated to one NVM subset 91. Therefore, the NVM set 61 functions as an NVM set (separated NVM set) that is exclusively occupied by one NVM subset 91. One write buffer (WB) 31 is associated with the NVM subset 91.

The NVM set 61 is used as a physical storage space for at least one area (namespace). NVM set 61 may be a physical storage space dedicated to only one namespace. In FIG. 3, a case is illustrated in which the NVM set 61 is used as a physical storage space for one namespace 102.

The NVM set 62 includes NAND flash memory dies 602, 603, ... 605, 606 connected to channel Ch0, NAND flash memory dies 612, 613, ... 615, 616 connected to channel Ch1, and NAND flash memory dies 612, 613, ... 615, 616 connected to channel Ch2. NAND flash memory dies 622, 623, . . . 625, 626, . . . NAND flash memory dies 642, 643, . Each block (free block) that belongs to the NVM set 62 and does not hold valid data is managed by a free block pool 82 corresponding to the NVM set 62. In the process of initializing the SSD 3, the controller 4 places all blocks belonging to the NVM set 62, that is, all blocks in the NAND flash memory dies 602 to 646, in the free block pool 82 corresponding to the NVM set 62. do.

Blocks belonging to NVM set 62 are managed using free block pool 82 and NVM subsets 92, 93, 94, and 95. Each of the NVM subsets 92, 93, 94, and 95 is a data block pool for managing blocks that belong to the NVM set 62 and hold valid data. A group of blocks included in NVM subset 92 constitutes one group for garbage collection, a group of blocks included in NVM subset 93 constitutes another group for garbage collection, and a group of blocks included in NVM subset 94 constitutes yet another group for garbage collection. A group for garbage collection is constituted, and a group of blocks included in the NVM subset 95 constitutes another group for garbage collection. Free block pool 82 is a free block pool shared by NVM subsets 92, 93, 94, 95. Therefore, NVM set 62 functions as a shared NVM set shared by multiple NVM subsets 92-95. Write buffers (WB) 32, 33, 34, and 35 are associated with NVM subsets 92, 93, 94, and 95, respectively.

The NVM set 62 is used as a physical storage space for at least one area (namespace). NVM set 62 may be a physical storage space dedicated to only one namespace, or may be a physical storage space for multiple namespaces. In FIG. 3, a case is illustrated in which the NVM set 62 is used as a physical storage space for four name spaces 103, 104, 105, and 106.

Further, in FIG. 3, a case is illustrated in which the name space 103 uses two NVM subsets 92 and 93. For example, the LBA range corresponding to namespace 103 may be divided into two sub-LBA ranges. Write data (for example, cold data with low update frequency) corresponding to one sub-LBA range may be written to an input block (write destination block) for the NVM subset 92 via the write buffer (WB) 32. . Write data (for example, frequently updated hot data (metadata)) corresponding to the other sub-LBA range is written to the input block (write destination block) for the NVM subset 93 via the write buffer (WB) 33. It's okay.

In FIG. 3, data write/read operations are performed on the NVM set 60 in response to an I/O command from the host 2 that includes the ID of the namespace 100 or 101. Further, data write/read operations for the NVM set 61 are executed in response to an I/O command from the host 2 that includes the ID of the namespace 102. Further, data write/read operations for the NVM set 62 are executed in response to an I/O command from the host 2 that includes the ID of any of the name spaces 103 to 106. Therefore, each of the NVM sets 60, 61, and 62 can be accessed simultaneously, and long latency (especially long read latency) caused by die contention can be suppressed.

Additionally, since garbage collection is performed independently for each NVM subset, a namespace that owns one or more NVM subsets will be affected by the garbage collection of other NVM subsets used by other namespaces (GC controllers). tension).

The shared NVM set 62 has the following characteristics.

Inside the shared NVM set 62, the free block pool 82 is shared among the plurality of NVM subsets 92-95, so die contention may occur. However, when a new input block allocation for a certain NVM subset is required, the controller 4 selects a block with a small number of program/erase cycles from the free blocks in the shared free block pool 82; This block can be assigned as a new input block. This makes it possible to equalize the wear and tear of each of the NVM subsets 92, 93, 94, and 95.

Furthermore, the separated NVM sets 60 and 61 have the following characteristics.

Within each separated NVM set 60, 61, one NVM subset can occupy one free block pool. Therefore, if one namespace corresponds to this one NVM subset, this namespace can occupy a separate NVM set without die contention. However, since isolated NVM sets do not share free block groups with other NVM sets, if the data stored in a particular isolated NVM set is frequently rewritten, this NVM set will become exhausted. A situation may arise where the degree of exhaustion is higher than the degree of consumption of other NVM sets. Such uneven consumption becomes a factor that reduces the lifespan of the SSD 3.

In this embodiment, a shared NVM set and a separated NVM set can coexist within one SSD 3. Therefore, for example, it is possible to use a shared NVM set and a separate NVM set depending on the workload.

Further, in the case of FIG. 3, the following environment is provided for each namespace.

<NVM set 60>
Namespaces 100, 101 share one NVM subset 90. Although die contention between namespaces 100, 101 and other namespaces does not occur, GC contention between namespaces 100, 101 may occur.

<NVM set 61>
Namespace 102 occupies one NVM subset 91. No die contention or GC contention occurs between the namespace 102 and other namespaces.

<NVM set 62>
Namespace 103 occupies two NVM subsets 92, 93. Although die contention between namespace 103 and other namespaces using NVM set 62 may occur, there is no GC contention between namespace 103 and other namespaces.

Namespaces 104, 105 share one NVM subset 94. Die contention between namespaces 104, 105 and other namespaces using NVM set 62 may occur. Furthermore, although no GC contention occurs between the namespaces 104 and 105 and other namespaces, GC contention between the namespaces 104 and 105 may occur.

Namespace 106 occupies one NVM subset 95. Although die contention between namespace 106 and other namespaces using NVM set 62 may occur, there is no GC contention between namespace 106 and other namespaces.

Referring now to FIG. 4, host write/garbage collection operations for separated NVM sets 60, 61 will now be described.

The top left of FIG. 4 shows host write/garbage collection operations for NVM set 60.

(1) Allocation of User Input Block First, one free block in the free block pool 80 is allocated as the user input block 210. The user input block 210 is a block for writing write data from the host 2, and is also referred to as a write destination block. Note that this operation is not performed if the user input block 210 has already been allocated.

(2) Host writing Write data from the host 2 is written from the write buffer 30 to the user input block 210. The write buffer 30 temporarily stores write data associated with the name space 100 or the name space 101. Then, the lookup table corresponding to the NVM set 60 is updated, so that the logical address (LBA) corresponding to the write data is set to the physical address indicating the physical storage location in the user input block 210 where this write data is written. mapped.

(3) Movement of User Input Block When the user input block 210 is filled with write data, the user input block 210 is moved to the NVM subset (data block pool) 90. That is, the user input blocks 210 filled with data are managed by the NVM subset (data block pool) 90.

(4) Allocation of GC input blocks When it becomes necessary to perform garbage collection in the NVM set 60, the garbage collection operation for the blocks in the NVM subset 90 is performed independently of other NVM sets. . For example, if the number of blocks included in the NVM subset 90 is greater than a certain threshold value X1 corresponding to the NVM subset 90, it may be determined that a garbage collection operation is necessary. Threshold X1 may be determined based on the total number of blocks that can be allocated for NVM subset 90. For example, a value remaining after subtracting a predetermined number from the total number of blocks that can be allocated for the NVM subset 90 may be used as a certain threshold value X1 corresponding to the NVM subset 90.

When a garbage collection operation is required in NVM set 60, one free block in free block pool 80 is assigned as GC input block 200. The GC input block 210 is a block to which valid data is copied during garbage collection, and is also referred to as a copy destination block.

(5) Copying Valid Data One or more blocks in which valid data and invalid data coexist are selected from among the blocks in the NVM subset 90 as copy source blocks. Only valid data of the selected block is copied to the GC input block 200. The lookup table corresponding to the NVM set 60 is then updated, thereby assigning the physical storage location in the GC input block 200 to which the valid data was copied to the logical address (LBA) corresponding to the copied valid data. The indicated physical address is mapped.

(6) Movement of GC Input Block Once the GC input block 200 is filled with valid data, the GC input block 200 is moved to the NVM subset 90. That is, the GC input block 200 filled with valid data is managed by the NVM subset (data block pool) 90.

(7) Returning Blocks Blocks that are managed by the NVM subset 90 and do not hold valid data are returned from the NVM subset 90 to the free block pool 80. A block that does not hold valid data is a block that has had all its data invalidated by a host write, or a block that has had all its valid data copied to a destination block by a garbage collection operation.

The bottom left of FIG. 4 shows host write/garbage collection operations for NVM set 61.

(1) Allocation of User Input Block One free block in the free block pool 81 is allocated as the user input block 211.

(2) Host writing Write data from the host 2 is written from the write buffer 31 to the user input block 211. Write data associated with the name space 102 is temporarily stored in the write buffer 31. Then, the lookup table corresponding to the NVM set 61 is updated, so that the logical address (LBA) corresponding to the write data is set to the physical address indicating the physical storage location in the user input block 211 where this write data is written. mapped.

(3) Movement of user input block When the user input block 211 is filled with write data, the user input block 211 is moved to the NVM subset (data block pool) 91. That is, the user input blocks 211 filled with data are managed by the NVM subset (data block pool) 91.

(4) Allocation of GC input blocks When it becomes necessary to perform garbage collection in the NVM set 61, the garbage collection operation for the blocks in the NVM subset 91 is performed independently of other NVM sets. . For example, if the number of blocks included in the NVM subset 91 is greater than a certain threshold value X1 corresponding to the NVM subset 91, it may be determined that a garbage collection operation is necessary. Threshold X1 may be determined based on the total number of blocks that can be allocated for NVM subset 91. For example, a value remaining after subtracting a predetermined number from the total number of blocks that can be allocated for the NVM subset 91 may be used as a certain threshold value X1 corresponding to the NVM subset 91.

When a garbage collection operation is required in the NVM set 61, one free block in the free block pool 81 is assigned as the GC input block 201.

(5) Copying Valid Data One or more blocks containing a mixture of valid data and invalid data are selected from among the blocks in the NVM subset 91 as copy source blocks. Only valid data of the selected block is copied to the GC input block 201. The lookup table corresponding to the NVM set 61 is then updated, thereby assigning the physical storage location in the GC input block 201 to which this valid data was copied to the logical address (LBA) corresponding to the copied valid data. The indicated physical address is mapped.

(6) Movement of GC input block When the GC input block 201 is filled with valid data, the GC input block 201 is moved to the NVM subset 91. That is, the GC input block 201 filled with valid data is managed by the NVM subset (data block pool) 91.

(7) Returning Blocks Blocks that are managed by the NVM subset 91 and do not hold valid data are returned from the NVM subset 91 to the free block pool 81. A block that does not hold valid data is a block that has had all its data invalidated by a host write, or a block that has had all its valid data copied to a destination block by a garbage collection operation.

FIG. 5 illustrates host write/garbage collection operations performed for shared NVM set 62. Here, it is assumed that the shared NVM set 62 includes only two NVM subsets 94 and 95.

Host write/garbage collection operations for NVM subset 94 are performed as follows.

(1) Allocation of User Input Block One free block in the free block pool 82 is allocated as the user input block 214.

(2) Host writing Write data from the host 2 is written from the write buffer 34 to the user input block 214. The write buffer 34 temporarily stores write data associated with the namespace 104 or 105. Then, the lookup table corresponding to the NVM subset 94 is updated, so that the logical address (LBA) corresponding to the write data is set to the physical address indicating the physical storage location in the user input block 214 where this write data is written. mapped.

(3) Movement of User Input Blocks Once a user input block 214 is filled with write data, the user input block 214 is moved to the NVM subset (data block pool) 94. That is, the user input blocks 214 filled with data are managed by the NVM subset (data block pool) 94.

(4) Allocation of GC input blocks When it becomes necessary to perform garbage collection in the NVM subset (data block pool) 94, the NVM subset Garbage collection operations for blocks within 94 are performed. For example, if the number of blocks included in the NVM subset 94 is greater than a certain threshold value X1 corresponding to the NVM subset 94, it may be determined that a garbage collection operation is necessary. Threshold X1 may be determined based on the total number of blocks that can be allocated for NVM subset 94. For example, a value remaining after subtracting a predetermined number from the total number of blocks that can be allocated for the NVM subset 94 may be used as a certain threshold value X1 corresponding to the NVM subset 94.

When a garbage collection operation is required in NVM subset 94, one free block in free block pool 82 is assigned as GC input block 204.

(5) Copying Valid Data One or more blocks containing a mixture of valid data and invalid data are selected from among the blocks in the NVM subset 94 as copy source blocks. Only valid data of the selected block is copied to the GC input block 204. The lookup table corresponding to NVM subset 94 is then updated, thereby assigning the logical address (LBA) corresponding to the copied valid data to the physical storage location within GC input block 204 where this valid data was copied. The indicated physical address is mapped.

(6) Moving the GC Input Block Once the GC input block 204 is filled with valid data, the GC input block 204 is moved to the NVM subset 94. That is, the GC input block 204 filled with valid data is managed by the NVM subset (data block pool) 94.

(7) Returning Blocks Blocks that are managed by the NVM subset 94 and do not hold valid data are returned from the NVM subset 94 to the free block pool 82 . A block that does not hold valid data is a block that has had all its data invalidated by a host write, or a block that has had all its valid data copied to a destination block by a garbage collection operation.

Host write/garbage collection operations for NVM subset 95 are performed in a similar manner to host write/garbage collection operations for NVM subset 94.

FIG. 6 shows another example configuration of multiple NVM sets.

In FIG. 6, each NVM set includes a collection of NAND flash memory dies connected to the same channel. That is, the NVM set 110 includes NAND flash memory dies 600, 601, 602, 603, . . . 605, 606 connected to channel Ch0. NVM set 111 includes NAND flash memory dies 610, 611, 612, 613, . . . 615, 616 connected to channel Ch1. The NVM set 112 includes NAND flash memory dies 620, 621, 622, 623, ... 625, 626 connected to channel Ch2, and NAND flash memory dies 640, 641, 642, 643, connected to channel ChN. ...645, 646 are included.

In the NVM set configuration of FIG. 6, access to NVM sets 110, 111, 112 is performed via different channels. Therefore, even if a data write/read operation is being performed on any NAND flash memory die in one NVM set, a data write/read operation on any NAND flash memory die in another NVM set is immediately performed. can do.

In the NVM set configuration of FIG. 2 where each NVM set spans multiple channels, one channel is shared between the NVM sets. Therefore, in the NVM set configuration of FIG. 2, if a write/read request to the NAND flash memory die 600 in the NVM set 60 and a write/read request to the NAND flash memory die 601 in the NVM set 61 occur simultaneously. In this case, an increase in latency may occur due to contention for access to channel Ch0.

In the NVM set configuration shown in FIG. 6, access to NVM sets 110, 111, and 112 is performed through different channels, so even if write/read requests to each of NVM sets 110, 111, and 112 occur simultaneously. , these write/read requests can be executed immediately. Therefore, the latency for access requests from the host 2 can be reduced.

However, in the NVM set configuration of FIG. 6, the peak I/O performance of each NVM set is limited to the performance of a single channel. Therefore, the NVM set configuration of FIG. 6 is preferably used in combination with mechanisms that can improve single channel performance.

FIG. 7 shows the relationship between block management corresponding to each NVM set in FIG. 6 and one or more areas (name space) corresponding to each NVM set.

NVM set 110 may function as a separate NVM set, similar to NVM set 60 of FIG. In the process of initializing the SSD 3, all blocks belonging to the NVM set 110 are placed in a free block pool 80 dedicated to the NVM subset 90. NVM set 111 may function as a separate NVM set, similar to NVM set 61 of FIG. In the process of initializing the SSD 3, all blocks belonging to the NVM set 111 are placed in the free block pool 81 dedicated to the NVM subset 91. NVM set 112 may function as a shared NVM set, similar to NVM set 62 of FIG. In the process of initializing the SSD 3, all blocks belonging to the NVM set 112 are placed in the free block pool 82 shared by the NVM subsets 92-95.

FIG. 8 schematically shows a flash memory package that can be used as the NAND flash memory 5 mounted on the SSD 3.

This flash memory package 910 uses TSV (Through Silicon Via) technology, which uses electrodes that vertically penetrate inside the stacked NAND flash memory die inside the package, to speed up data input/output and reduce power consumption. This is a memory package that makes it possible to reduce In flash memory package 910, a plurality of stacked NAND flash memory dies are housed in a single package. Here, the case where eight NAND type flash memory dies D0 to D7 are housed in a single package is illustrated, but the number of NAND type flash memory dies housed in the package is different from this example. Not limited.

This flash memory package 910 includes a package substrate 911 such as a printed wiring board, an interface die (also referred to as an interface chip) Ce, and the above-described stacked NAND type flash memory dies D0 to D7. A plurality of solder bumps 916 that function as a plurality of external I/O terminals (electrodes) for inputting and outputting signals are arranged on the back surface of the package substrate 911. These signals include 8-bit wide I/O signals and various control signals (chip enable signals CE, command latch enable signals CLE, address latch enable signals ALE, write enable signals WE, read enable signals RE, ready/busy signal RB, etc.). Eight-bit wide I/O signals are used to transmit commands, addresses, data, etc. Part of the address may include a chip address. A NAND flash memory die to be accessed may be selected by a combination of a chip enable signal CE and a chip address.

An interface die Ce is arranged on the surface of the package substrate 911. The interface die Ce is connected to a plurality of solder bumps 916 via a wiring layer (not shown).

The stacked NAND flash memory dies D0-D7 are interconnected by a number of vertical vias 925. The interface die Ce transmits I/O signals, chip enable signal CE, command latch enable signal CLE, address latch enable signal ALE, write enable signal WE, read enable signal RE, etc. through these many vertical vias 925 in NAND type. The I/O signals, ready/busy signals RB, etc. are transmitted to the flash memory dies D0-D7 and received from the NAND-type flash memory dies D0-D7 through these multiple vertical vias 925.

The interface die Ce may include a parallel/serial conversion circuit. The interface die Ce converts the 8-bit wide I/O signal from the controller 4 into a 64-bit wide I/O signal using a parallel/serial conversion circuit, and converts these 64-bit wide I/O signals into , may be transmitted to the NAND flash memory die D0-D7 through specific 64 vertical vias included in the number of vertical vias 925.

Each of the vertical vias 925 connects a plurality of through electrodes V that penetrate the semiconductor substrates of the stacked NAND flash memory dies D0 to D7, and a plurality of through electrodes V that connect the stacked NAND flash memory dies D0 to D7, respectively. bump electrodes (solder bumps) 919.

In conventional memory packages that use wire bonding, as the number of stacked dies increases, the parasitic capacitance and parasitic resistance of the package's external I/O terminals increases, making it difficult for the memory package to operate at high frequencies. becomes difficult.

In the flash memory package 910 of FIG. 8, stacked NAND flash memory dies D0-D7 are interconnected by a number of vertical vias 925 instead of bonding wires. Therefore, the parasitic capacitance and parasitic resistance of the external I/O terminal can be reduced, and each NAND flash memory die in the flash memory package 910 can be operated at a high frequency.

FIG. 9 is a cross-sectional view of flash memory package 910.

On the surface of the support substrate 912, stacked NAND flash memory dies D0 to D7 are mounted. A through electrode V is embedded in each of the NAND flash memory dies D0 to D7. The through electrode V is an electrode that penetrates the semiconductor substrate within the corresponding NAND flash memory die. The through electrodes V of two adjacent NAND flash memory dies are connected by solder bumps 919 . In this case, on the surface of each NAND flash memory die, the through electrode V may be connected to the solder bump 919 via a wiring layer provided above the semiconductor substrate. Further, two adjacent NAND flash memory dies may be physically coupled via an adhesive layer 915.

An interface die Ce is mounted on the back surface of the support substrate 912. A wiring layer 923 is formed on the support substrate 912. Interface die Ce is connected to wiring layer 923 via a plurality of solder bumps 918. Each through electrode V of the lowest layer NAND flash memory die D0 is connected to the wiring layer 923. Thereby, the interface die Ce is electrically connected to the NAND flash memory dies D0 to D7.

Support substrate 912 is connected to package substrate 911 via a plurality of solder bumps 917. The interface die Ce is sealed with a sealing resin 921. The NAND flash memory dies D0 to D7 are sealed with a sealing resin 922. The outer circumferences of the sealing resins 921 and 922 are sealed with a sealing resin 920, and the upper part of the sealing resin 922 is sealed with a metal plate 913.

FIG. 10 shows the relationship between the plurality of NVM sets described in FIG. 6 and one or more flash memory packages used as these NVM sets. A case is illustrated in which the NVM sets 130 and 131 are classified into two NVM sets 130 and 131. NVM sets 130 and 131 correspond to the separated NVM sets 110 and 111 described in FIG. 6, respectively. NVM set 130 includes NAND flash memory dies D0 to D7, each connected to channel Ch0, and NVM set 131 includes NAND flash memory dies D10 to D17, each connected to channel Ch1.

NAND flash memory dies D0 to D7 in the NVM set 130 are realized by a single flash memory package 910. In the flash memory package 910, as explained in FIGS. 8 and 9, NAND type flash memory dies D0 to D7 are stacked, and these NAND type flash memory dies D0 to D7 are connected to a large number of vertical vias (each vertical via). The vias are interconnected by vias (including through electrodes V and solder bumps 919). A plurality of external I/O terminals (solder bumps 916) provided on the back surface of the package substrate 911 of the flash memory package 910 are connected to a plurality of signal lines in the channel Ch0. These signal lines include an 8-bit wide I/O signal line and various control signals (multiple chip enable signals CE, command latch enable signal CLE, address latch enable signal ALE, write enable signal WE, read enable signal RE, It may include multiple control signal lines for multiple ready/busy signals RB, etc.). These signals received from the NAND interface 13 via channel Ch0 are transmitted to the NAND flash memory dies D0-D7 via the interface die Ce and a number of vertical vias.

Similarly, the NAND flash memory dies D10 to D17 in the NVM set 131 are also realized by a single flash memory package 930. Flash memory package 930 has a similar structure to flash memory package 910. That is, in the flash memory package 930, NAND type flash memory dies D10 to D17 are stacked, and these NAND type flash memory dies D10 to D17 have a large number of vertical vias (each vertical via is connected to a through electrode V and a solder bump 939). interconnected by A plurality of external I/O terminals (solder bumps 936) provided on the back surface of the package substrate 931 of the flash memory package 930 are connected to a plurality of signal lines in the channel Ch1. These signal lines include an 8-bit wide I/O signal line and various control signals (multiple chip enable signals CE, command latch enable signal CLE, address latch enable signal ALE, write enable signal WE, read enable signal RE, It may include multiple control signal lines for multiple ready/busy signals RB, etc.). These signals received from the NAND interface 13 via the channel Ch1 are transmitted to the NAND flash memory dies D10-D17 via the interface die Ce and a number of vertical vias.

The controller 4 executes data write/read operations for the NVM set 130 via the channel Ch0 in response to an I/O command from the host 2 that specifies an area (name space) corresponding to the NVM set 130. Further, the controller 4 executes data write/read operations for the NVM set 131 via the channel Ch1 in response to an I/O command from the host 2 that specifies an area (name space) corresponding to the NVM set 131.

In the configuration of Figure 10, the peak I/O performance of each NVM set is limited to the performance of a single channel, but the performance of each channel is limited using a typical memory package that connects multiple die with wire bonds. It will be better than if you did it. Therefore, the configuration of FIG. 10 makes it possible to simultaneously execute write/read requests for each of the NVM sets 130 and 131, and to minimize the decline in peak I/O performance of each NVM set. .

Note that although FIG. 10 shows an example in which multiple NAND flash memory dies included in each separated NVM set are realized by a memory package using a large number of vertical vias (TSV), Multiple NAND flash memory dies can also be implemented with memory packages using multiple vertical vias (TSVs).

Additionally, if a single memory package using many vertical vias (TSV) supports two or more channels, multiple NAND types in two or more NVM sets corresponding to the two or more channels A flash memory die may be implemented with a single memory package.

Next, with reference to FIGS. 11 to 13, the garbage collection operation for the NVM set 60 described in FIGS. 2 and 3 will be specifically described.

In FIGS. 11 to 13, for ease of illustration, it is assumed that the NVM set 60 includes two NAND flash memory dies 1 to 2, and each die has two blocks including pages P1 to P4. do.

As shown in FIG. 11, a free block in the free block pool 80 (here, free block #21) is allocated as a GC input block 200.

Next, a block (block #11) in which valid data and invalid data are mixed is selected from the NVM subset 90 as a copy source block, and only valid data in this selected copy source block (block #11) is input to the GC. Copied to block 200 (block #21).

In block #11, if valid data d1, d3 and invalid data d2, d4 coexist, only valid data d1 and data d3 are copied to GC input block 200 (block #21). At this time, data d1 is copied to page P1 of block #21, and data d3 is copied to page P2 of block #21.

When valid data (data d1 and data d3) of block #11 is copied to GC input block 200 (block #21), data d1 and data d3 of block #11 are invalidated. As a result, block #11 has become a block that does not hold valid data, so block #11 is returned to the free block pool 80 as shown in FIG.

The NVM subset 90 includes a block #12 in which valid data d5, d7 and invalid data d6, d8 coexist. When block #12 is selected as a copy source block, only valid data (data d5 and data d7) of block #12 is copied to GC input block 200 (block #21). At this time, data d5 is copied to page P3 of block #21, and data d7 is copied to page P4 of block #21.

When valid data (data d5 and data d7) of block #12 is copied to GC input block 200 (block #21), data d5 and data d7 of block #12 are invalidated. As a result, block #12 has become a block that does not hold valid data, so block #12 is returned to the free block pool 80 as shown in FIG. Furthermore, when data d5 and data d7 are copied to GC input block 200 (block #21), block #21 is filled with valid data. In this case, block #21 is moved to NVM subset 90.

FIG. 14 shows the NVM set-to-set copy operation. Here, the explanation will be given assuming that the NVM set 60 in FIG. 2 is the copy source NVM set, and the NVM set 61 in FIG. 2 is the copy destination NVM set. The host 2 can specify a copy source NVM set and a copy destination NVM set. The copy destination NVM set may be an NVM set that is not currently used by the host 2. By using an NVM set that is not currently used by host 2 as the copy destination NVM set, it is possible to prevent hot data and cold data from being mixed in the copy destination NVM set due to the copy operation between NVM sets. . Note that if there is no NVM set that is currently not in use, the host 2 may send a command to the SSD 3 requesting the creation of a new NVM set.

The inter-NVM set copy operation is executed in the following steps.

(1) Allocation of User Input Block In the copy destination NVM set (NVM set 61), one free block in the free block pool 81 is allocated as the user input block 211.

(2) Host writing Write data from the host 2 is written from the write buffer 31 to the user input block 211. Normally, write data associated with the name space 102 corresponding to the copy destination NVM set is stored in the write buffer 31, but after the copy operation between NVM sets is started, the write data associated with the name space 102 corresponding to the copy source NVM set is stored in the write buffer 31. Write data associated with space 100 or 101 is stored in write buffer 31. Then, the lookup table corresponding to the NVM subset 90 is updated, so that the logical address (LBA) corresponding to the write data is set to the physical address indicating the physical storage location in the user input block 211 where this write data is written. mapped.

In this way, before the NVM set-to-NVM set copy operation, the writing destination of the write data associated with the name space 101 or name space 100 was the user input block 210 of the copy source NVM set (NVM set 60); After the inter-set copy operation, the write data associated with the name space 101 or the name space 100 is written to the user input block 211 of the copy destination NVM set (NVM set 61).

(3) Movement of user input block When the user input block 211 is filled with write data, the user input block 211 is moved to the NVM subset (data block pool) 91. That is, the user input blocks 211 filled with data are managed by the NVM subset (data block pool) 91.

(4) Allocation of GC input block In the copy destination NVM set (NVM set 61), one free block in the free block pool 81 is allocated as the GC input block 201.

(5) Copying valid data from the copy source NVM set to the copy destination NVM set A block holding valid data is selected as the copy source block from the blocks in the NVM subset 90 of the copy source NVM set (NVM set 60). . Then, only the valid data in this copy source block is copied to the GC input block (copy destination block) 201 of the copy destination NVM set (NVM set 61). In this case, first, valid data to be copied is selected from this copy source block. The selected valid data is then read from the copy source block and written to the GC input block (copy destination block) 201.

When valid data is copied to the GC input block 201, the lookup table corresponding to the NVM subset 90 is updated, thereby causing the valid data to be copied to the logical address (LBA) corresponding to the copied valid data. A physical address indicating a physical storage location within the GC input block 201 is mapped.

(6) Moving the GC input block When the GC input block 201 in the copy destination NVM set (NVM set 61) is filled with valid data from the block in the copy source NVM set (NVM set 60), the GC input block 201 moves to the NVM is moved to subset 91. That is, the GC input block 201 filled with valid data is managed by the NVM subset (data block pool) 91.

(7) Returning Blocks In the copy destination NVM set (NVM set 61), blocks that are managed by the NVM subset 91 and do not hold valid data are returned from the NVM subset 91 to the free block pool 81. For example, if all data held in a certain block in the NVM subset 91 is invalidated by writing new write data to the user input block 211, this block is transferred from the NVM subset 91 to the free block pool 81. will be returned to.

(7) 'Return of copy source block In the copy source NVM set (NVM set 60), when the valid data of the copy source block is copied to the GC input block 201, so that no valid data exists in this copy source block. , this copy source block is returned from the NVM subset 90 to the free block pool 80.

Through this NVM set-to-NVM set copy operation, for example, the physical storage space for data (hot data) stored in the copy source NVM set is transferred to the copy destination NVM set that has a lower number of rewrites (lower number of program/erase cycles). Can be changed. Therefore, wear leveling can be performed to equalize the degree of wear among NVM sets.

Note that before the valid data selected as a copy target is actually copied to the GC input block 201, write data (new data corresponding to this LBAx) having the same LBAx as this valid data is copied to the user input block 211. may be written to. When write data (new data corresponding to this LBAx) is written to the user input block 211, the lookup table corresponding to the NVM subset 90 is updated, so that this write data is written to the LBAx corresponding to this write data. A physical address indicating the physical storage location within the written user input block 211 is mapped.

In this case, the selected valid data will be old data that is no longer read by the host 2. Therefore, if write data having the same LBAx as that of this valid data is written to the user input block 211 before the valid data selected as a copy target is actually copied to the GC input block 201, this The copy operation of valid data may be aborted. This can prevent unnecessary copy operations from being executed.

Alternatively, instead of canceling the valid data copy operation, the selected valid data copy operation itself may be performed and the lookup table corresponding to the NVM subset 90 may not be updated. This can prevent the physical address corresponding to LBAx from being changed to a value indicating the physical storage location to which this valid data (old data) has been copied. More specifically, each time valid data corresponding to a certain LBA is copied to the GC input block 201, the physical address corresponding to this LBA is determined from the copy source NVM set (NVM set 60) or the copy source by referring to the lookup table. It may be determined which of the previous NVM sets (NVM set 61) the physical address corresponds to. If this physical address corresponds to the copy destination NVM set (NVM set 61), it is recognized that new data corresponding to this LBA has been written to the user input block 211, and the lookup table update is executed. Not done. On the other hand, if this physical address corresponds to the copy source NVM set (NVM set 60), the copied valid data is recognized as the latest data corresponding to this LBA, and the lookup table is updated. be done. By updating the lookup table, this LBA is mapped to a physical address indicating the physical storage location where the valid data has been copied.

FIG. 15 shows the relationship between the contents of the address translation table before the inter-NVM set copy operation in FIG. 14 and the contents of the address translation table after the inter-NVM set copy operation.
Before the inter-NVM set copy operation is performed, the LUT 40 corresponding to the NVM subset 90 holds only the physical address of the copy source NVM set (NVM set 60).

When the inter-NVM set copy operation starts from the copy source NVM set (NVM set 60) to the copy destination NVM set (NVM set 61), the physical addresses of the LUT 40 are sequentially updated. For example, when data d10 corresponding to LBA10 is copied from the copy source NVM set (NVM set 60) to the GC input block 201 of the copy destination NVM set (NVM set 61), data d10 is copied to LBA10 of LUT40. A physical address indicating a physical storage location within the copy destination NVM set (NVM set 61) is mapped. Therefore, when the inter-NVM set copy operation is completed, the LUT 40 will hold only the physical address of the NVM set 61.

In this way, by executing the copy operation between NVM sets using a mechanism similar to GC, the controller 4 creates address translation information corresponding to the data copied to the copy destination NVM set (NVM set 61). The data requested by the host 2 can be read from the copy destination NVM set (NVM set 61) by referring to the LUT 40 without performing any special processing.

Next, the inter-NVM set copy operation will be specifically described with reference to FIGS. 16 to 18.

In FIGS. 16 to 18, for ease of illustration, NVM set 60 includes NAND flash memory dies 1 to 2, NVM set 61 includes NAND flash memory dies 3 to 4, and each die has a page. Assume that there are two blocks each including P1 to P4. It is also assumed that valid data is copied from the NVM set 60 to the NVM set 61.

As shown in FIG. 16, a free block (here, block #41) in the free block pool 81 is allocated as the GC input block 201 in the copy destination NVM set (NVM set 61).

Next, in the copy source NVM set (NVM set 60), a block holding valid data from the blocks in the NVM subset 90 is selected as a copy source block, and the valid data in this selected copy source block (block #11) is selected as a copy source block. Only data is copied to the GC input block 201 (block #41) of the copy destination NVM set (NVM set 61).

In block #11, if valid data d1, d3 and invalid data d2, d4 coexist, only valid data d1 and data d3 are copied to GC input block 201 (block #41). At this time, data d1 is copied to page P1 of block #41, and data d3 is copied to page P2 of block #41.

When valid data (data d1 and data d3) of block #11 is copied to GC input block 201 (block #41), data d1 and data d3 of block #11 are invalidated. As a result, block #11 has become a block that does not hold valid data, so block #11 is returned to the free block pool 80 as shown in FIG.

The NVM subset 90 includes a block #12 in which valid data d5, d7 and invalid data d6, d8 coexist. When block #12 is selected as a copy source block, only valid data (data d5 and data d7) of block #12 is copied to GC input block 201 (block #41). At this time, data d5 is copied to page P3 of block #41, and data d7 is copied to page P4 of block #41.

When valid data (data d5 and data d7) of block #12 is copied to GC input block 201 (block #41), data d5 and data d7 of block #12 are invalidated. As a result, block #12 has become a block that does not hold valid data, so block #12 is returned to the free block pool 80 as shown in FIG. Furthermore, when data d5 and data d7 are copied to GC input block 201 (block #41), block #41 is filled with valid data. In this case, block #41 is moved to NVM subset 91.

FIG. 19 shows an overview of an NVM set exchange operation for exchanging data between two NVM sets (NVM set #1, NVM set #2).

Here, it is assumed that NVM set #1 is NVM set 60 and NVM set #2 is NVM set 61. Furthermore, before the NVM set exchange operation, data A (data with high update frequency) is stored in NVM set #1 (NVM set 60), and data B (data with low update frequency) is stored in NVM set #2 (NVM set 61). It is assumed that data with frequency) is stored.

In this case, the number of rewrites (number of program/erase cycles) of NVM set #1 (NVM set 60) is greater than the number of rewrites (number of program/erase cycles) of NVM set #2 (NVM set 61). Here, the number of rewrites (number of program/erase cycles) of an NVM set may be expressed by the average number of program/erase cycles of all blocks belonging to this NVM set, or may be expressed by the average number of program/erase cycles of all blocks belonging to this NVM set. It may be expressed by the sum of the number of program/erase cycles for the block.

For example, NVM set #1 (NVM set 60) is rewritten 800 times in a period of 100 days (number of program/erase cycles = 800), whereas NVM set #2 (NVM set 61) is rewritten 800 times during a period of 100 days. It can only be rewritten 100 times during the day (number of program/erase cycles = 100 times). For example, if the limit value of the number of rewrites for each block is 1000 times, when rewrites (program/erase operations) for 200 times (=1000 times - 800 times) are executed in NVM set #1, the NVM set The number of times #1 is rewritten reaches this limit value. In this case, each block in NVM set #1 is likely to no longer be able to function properly.

In this embodiment, an operation of exchanging data between NVM set #1 (NVM set 60) and NVM set #2 (NVM set 61) can be performed as necessary. For example, when 100 days have passed since the start of use of the SSD 3, NVM set #1 (NVM set 60) and NVM set #2 (NVM set 61) are replaced in response to a command from host 2 requesting NVM set replacement. Data may be exchanged between them.

In the NVM set exchange operation, valid data stored in NVM set #1 (NVM set 60) is copied to NVM set #2 (NVM set 61). Then, the lookup table corresponding to NVM set #1 (NVM set 60) is updated, and as a result, the valid data is copied to the logical address (LBA) of NVM set #2 that corresponds to the copied valid data. A physical address indicating a physical storage location within (NVM set 61) is mapped.

Furthermore, valid data stored in NVM set #2 (NVM set 61) is copied to NVM set #1 (NVM set 60). Then, the lookup table corresponding to NVM set #2 (NVM set 61) is updated, and as a result, the valid data is copied to the logical address (LBA) of NVM set #1 that corresponds to the copied valid data. A physical address indicating a physical storage location within (NVM set 60) is mapped.

Once the NVM set exchange operation is completed, the physical storage space for data A (data with a high update frequency) is changed to NVM set #2 (NVM set 61), and the physical storage space for data B (data with a low update frequency) is changed to NVM set #2 (NVM set 61). The storage space is changed to NVM set #1 (NVM set 60).

The number of times that NVM set #2 (NVM set 61) is rewritten immediately after the completion of the NVM set exchange operation is 100 times, and the number of times that NVM set #2 (NVM set 61) is rewritten immediately after the completion of data exchange is 100 times. The number of rewrites of NVM set #1 (NVM set 60) is 800 times.

After this, data A is updated at a high frequency again, and as a result, the number of rewrites of NVM set #2 increases by 800 times in 100 days. On the other hand, data B is also updated at a relatively low frequency, and as a result, the number of rewrites of NVM set #1 increases by 100 times in 100 days. As a result, after 200 days have passed since the initial state (100 days have passed since NVM set replacement), the number of rewrites for NVM set #2 (NVM set 61) is 900, and the number of rewrites for NVM set #1 (NVM set 60) will be 900 times.

In this way, by executing the NVM set exchange operation, it is possible to equalize the number of rewrites of blocks belonging to each between NVM set #1 (NVM set 60) and NVM set #2 (NVM set 61). can. Therefore, it is possible to equalize the degree of wear among NVM sets.

FIG. 20 shows host write/garbage collection operations performed for two NVM sets prior to the NVM set exchange operation.
Before the NVM set exchange operation is performed, host write/garbage collection operations are performed independently of each other in NVM set #1 (NVM set 60) and NVM set #2 (NVM set 61). The details are as explained in FIG. 4.

FIG. 21 illustrates host write/garbage collection operations performed between two NVM sets for an NVM set exchange operation.
(1) Allocation of User Input Block In NVM set #1, one block in the free block pool 80 is allocated as the user input block 210. Furthermore, in NVM set #2, one block in the free block pool 81 is allocated as the user input block 211.

(2) Host writing Write data from the host 2 is written from the write buffer 30 to the user input block 210. Normally, write data associated with the name space 100 or name space 101 corresponding to NVM set #1 (NVM set 60) is stored in the write buffer 30, but after the NVM set exchange operation is started, Write data associated with the name space 102 corresponding to NVM set #2 (NVM set 61) is stored in the write buffer 30. Then, the lookup table corresponding to NVM set #2 (NVM set 61) is updated, and thereby the physical memory in the user input block 210 in which this write data is written to the logical address (LBA) corresponding to the write data. A physical address indicating the location is mapped.

In this way, before the NVM set exchange operation, the write data associated with the namespace 102 was written to the user input block 211 of NVM set #2 (NVM set 61), but the NVM set exchange operation started. Then, the writing destination of the write data associated with the name space 102 is changed to the user input block 210 of NVM set #1 (NVM set 60).

Further, write data from the host 2 is written from the write buffer 31 to the user input block 211. Normally, write data associated with the name space 102 corresponding to NVM set #2 (NVM set 61) is stored in the write buffer 31, but after the NVM set exchange operation is started, write data associated with the name space 102 corresponding to NVM set #2 (NVM set 61) is stored in the write buffer 31. Write data associated with the namespace 100 or 101 corresponding to (NVM set 60) is stored in the write buffer 31. Then, the lookup table corresponding to NVM set #1 (NVM set 60) is updated, and the physical memory in the user input block 211 in which this write data has been written is thereby updated to the logical address (LBA) corresponding to the write data. A physical address indicating the location is mapped.

In this way, before the NVM set exchange operation, the write data associated with namespace 101 or namespace 100 was written to the user input block 210 of NVM set #1 (NVM set 60), but When the exchange operation is started, the writing destination of the write data associated with the name space 101 or name space 100 is changed to the user input block 211 of NVM set #2 (NVM set 61).

(3) Movement of User Input Block When the user input block 210 is filled with write data, the user input block 210 is moved to the NVM subset (data block pool) 90. That is, the user input blocks 210 filled with data are managed by the NVM subset (data block pool) 90.

Further, when the user input block 211 is filled with write data, the user input block 211 is moved to the NVM subset (data block pool) 91. That is, the user input blocks 211 filled with data are managed by the NVM subset (data block pool) 91.

(4) Allocation of GC input block In NVM set #1 (NVM set 60), one free block in free block pool 80 is allocated as GC input block 200.

Furthermore, in the NVM set (NVM set 61), one free block in the free block pool 81 is allocated as the GC input block 201.

(5) Exchange of valid data A block holding valid data is selected as a copy source block from the blocks in the NVM subset 90 of the copy source NVM set (NVM set 60). Then, only the valid data in this copy source block is copied to the GC input block 201 of NVM set #2 (NVM set 61). The lookup table corresponding to the NVM subset 90 is then updated, thereby assigning the logical address (LBA) corresponding to the copied valid data to the physical storage location in the GC input block 201 where this valid data was copied. The indicated physical address is mapped.

A block holding valid data is selected as a copy source block from the blocks in NVM subset 91 of NVM set #2 (NVM set 61). Then, only the valid data in this copy source block is copied to the GC input block 200 of NVM set #1 (NVM set 60). The lookup table corresponding to the NVM subset 91 is then updated, thereby assigning the physical storage location in the GC input block 200 to which the valid data was copied to the logical address (LBA) corresponding to the copied valid data. The indicated physical address is mapped.

(6) GC input block movement In NVM set #1 (NVM set 60), when the GC input block 200 is filled with valid data from one or more blocks of NVM set #2 (NVM set 61), the GC input block 200 is moved to NVM subset 90. That is, the GC input block 200 filled with valid data is managed by the NVM subset (data block pool) 90.

Also, in NVM set #2 (NVM set 61), when the GC input block 201 is filled with valid data from one or more blocks of NVM set #1 (NVM set 60), the GC input block 201 is transferred to the NVM subset 91. will be moved. That is, the GC input block 201 filled with valid data is managed by the NVM subset (data block pool) 91.

(7) Return of copy source blocks In NVM set #1 (NVM set 60), blocks that are managed by NVM subset 90 and do not hold valid data are returned from NVM subset 90 to free block pool 80. For example, if all data held by a block in NVM subset 90 is invalidated by writing new write data to user input block 210, then this block is transferred from NVM subset 90 to free block pool 80. will be returned to.

In NVM set #2 (NVM set 61), blocks that are managed by NVM subset 91 and do not hold valid data are returned from NVM subset 91 to free block pool 81. For example, if all data held by a block in NVM subset 91 is invalidated by writing new write data to user input block 211, then this block is transferred from NVM subset 91 to free block pool 81. will be returned to.

FIG. 22 shows an overview of the new NVM set creation operation.
Now, assume that an NVM set 160 including NAND flash memory dies 600-606, 610-616, 620-626, . . . 640-646 is being used. In this NVM set 160, a free block pool 180 exists. Free block pool 180 is shared by NVM subset 190B and NVM subset 190C. Furthermore, a write buffer 130B is provided corresponding to the NVM subset 190B, and a write buffer 130C is provided corresponding to the NVM subset 190C.

The controller 4 can create a new NVM set 161 from the NVM set 160, as shown at the bottom of FIG. In this case, first, a NAND flash memory die to be reserved for the new NVM set 161 is determined from among the plurality of NAND flash memory dies included in the NVM set 160. In the example of FIG. 22, NAND flash memory dies 600, 610, 620, . . . , 640 are determined as NAND flash memory dies for the NVM set 161. Valid data in these NAND flash memory dies 600, 610, 620, . . . 640 is copied to blocks belonging to the remaining NAND flash memory dies in the NVM set 160.

As a result, a free block pool 181, an NVM subset 190A, and a write buffer 130A for the NVM set 161 are created. Each free block in the NAND flash memory die 600, 610, 620, . . . 640 is managed by a free block pool 181 for the NVM set 161. The original NVM set 160 becomes the reduced NVM set. The free block pool 180 manages only free block groups belonging to the remaining dies excluding the NAND flash memory dies 600, 610, 620, . . . 640.

FIG. 23 illustrates host write/garbage collection operations performed for new NVM set creation. Here, it is assumed that a new NVM set 161 is created from an original NVM set 160 that includes two NVM subsets.

(1) User Input Block Allocation One free block in the free block pool 180 corresponding to the original NVM set 160 is allocated as the user input block 410 corresponding to the NVM subset 190B. Also, one free block in free block pool 180 is allocated as user input block 411 corresponding to NVM subset 190C. Note that this operation is not performed if the user input blocks 410 and 411 have already been allocated.

(2) Host writing Write data from the host 2 is written from the write buffer 130B to the user input block 410. Then, the lookup table corresponding to NVM subset 190B is updated, so that the logical address (LBA) corresponding to the write data is set to the physical address indicating the physical storage location in user input block 410 where this write data is written. mapped.

Further, write data from the host 2 is written from the write buffer 130C to the user input block 411. Then, the lookup table corresponding to the NVM subset 190C is updated, so that the logical address (LBA) corresponding to the write data is set to the physical address indicating the physical storage location in the user input block 411 where this write data is written. mapped.

(3) Movement of user input block When the user input block 410 is filled with write data, the user input block 410 is moved to the NVM subset (data block pool) 190B. That is, user input blocks 410 filled with data are managed by NVM subset (data block pool) 190B.

Further, when the user input block 411 is filled with write data, the user input block 411 is moved to the NVM subset (data block pool) 190C. That is, user input blocks 411 filled with data are managed by NVM subset (data block pool) 190C.

(4) Allocation of GC input block In the original NVM set (NVM set 160), one block from the free blocks in the free block pool 180 is allocated as the GC input block 400 corresponding to the NVM subset 190B. Furthermore, one block from the free blocks in the free block pool 180 is allocated as the GC input block 401 corresponding to the NVM subset 190C.

(5) Copying valid data One or more blocks in which valid data and invalid data are mixed are selected as a copy source block from the blocks in the NVM subset 190B (or NVM subset 190C), and the valid data in the copy source block is only is copied to GC input block 400 (or GC input block 401). The lookup table corresponding to NVM subset 190B (or NVM subset 190C) is then updated, thereby causing the GC input block 400 to which the valid data has been copied to the logical address (LBA) corresponding to the copied valid data. A physical address indicating a physical storage location within (or GC input block 401) is mapped.

(6) Movement of GC input block When GC input block 400 (or GC input block 401) is filled with valid data, GC input block 400 (or GC input block 401) moves to NVM subset 190B (or NVM subset 190C). be done. That is, GC input blocks filled with valid data are managed by the corresponding NVM subset (data block pool).

(7), (7)'Returning blocks Blocks that are managed by the NVM subset 190B (or NVM subset 190C) and do not hold valid data are returned to free blocks. In this case, blocks that do not belong to the die set to be allocated to the new NVM set 161 are returned to the free block pool 180 from the NVM subset 190B (or NVM subset 190C). On the other hand, blocks that do not belong to the die set to be allocated to the new NVM set 161 are returned from the NVM subset 190B (or NVM subset 190C) to the free block pool 181 of the new NVM set.

In addition, in the above description, a case where GC is performed for the entire original NVM set 160 has been described, but from blocks that belong to the die set to be allocated to the new NVM set 161, blocks holding valid data are prioritized as copy source blocks. , and only valid data in this copy source block may be copied to the GC input block (copy destination block). This makes it possible to create a new NVM set 161 in a short time.

Next, the new NVM set creation operation will be specifically explained using FIGS. 24 to 26. In FIGS. 24-26, for ease of illustration, NVM set 330 (NVM set A) includes NAND flash memory dies 1-4, and each die has two NAND flash memory dies 1-4 each containing pages P1-P4. Assume a case with blocks.

First, from the NAND flash memory dies 1 to 4 belonging to NVM set A, NAND flash memory dies 1 to 2 to be reserved for the new NVM set B are determined.

Next, as shown in FIG. 24, a block in the free block pool 300 of NVM set A (here, block #41) is allocated as a GC input block 320. Also, a block (block #11 in this case) that holds valid data from the blocks of NAND flash memory die 1 and 2 reserved for NVM set B is selected as a copy source block, and this selected copy source block Valid data in (block #11) is copied to GC input block 320 (block #41).

In block #11, if valid data d1, d3 and invalid data d2, d4 coexist, only valid data d1 and data d3 are copied to GC input block 320 (block #41). At this time, data d1 is copied to page P1 of block #41, and data d3 is copied to page P2 of block #41.

When valid data (data d1 and data d3) of block #11 is copied to GC input block 320 (block #41), data d1 and data d3 of block #11 are invalidated. As a result, block #11 has become a block that does not hold valid data, so as shown in FIG. will be returned.

In the NAND flash memory die reserved for NVM set B, there is a block #12 in which valid data d5, d7 and invalid data d6, d8 coexist. When block #12 is selected as a copy source block, only valid data (data d5 and data d7) of block #12 is copied to GC input block 320 (block #41). At this time, data d5 is copied to page P3 of block #21, and data d7 is copied to page P4 of block #41.

When valid data (data d5 and data d7) of block #12 is copied to GC input block 320 (block #41), data d5 and data d7 of block #12 are invalidated. As a result, block #12 has become a block that does not hold valid data, so block #12 is returned to NVM set B (new NVM set) free block pool 301, as shown in FIG.

FIG. 27 shows an overview of NVM set join operations.
FIG. 27 shows the operation of combining NVM set #1 (NVM set 163) and NVM set #2 (NVM set 164) into NVM set #3 (NVM set 165).

NVM set #1 (NVM set 163) includes NAND flash memory dies 600, 610, 620, . . . 640. NVM set #2 (NVM set 164) includes NAND flash memory dies 601, 611, 621, . . . 641. NVM set #3 (NVM set 165) includes NAND flash memory dies 602-606, 612-616, 622-626, . . . 642-646.

When NVM set #1 (NVM set 163) and NVM set #2 (NVM set 164) are combined with NVM set #3 (NVM set 165), the free block pool corresponding to NVM set #1 (NVM set 163) 183, and free block pool 184 corresponding to NVM set #2 (NVM set 164) is also combined with free block pool 185 corresponding to NVM set #1 (NVM set 165). NVM subset 190A of NVM set #1 (NVM set 163) and NVM subset 190B of NVM set #2 (NVM set 164) are also combined with NVM subset 190C of NVM set #3 (NVM set 165).

FIG. 28 illustrates host write/garbage collection operations performed for NVM set binding.
Before the NVM set combination operation is performed, write data write operations and garbage collection operations are performed independently of each other in NVM sets #1 to #3.

(1) Allocation of User Input Block One free block in the free block pool 183 is allocated as the user input block 413. Additionally, one free block within free block pool 184 is assigned as user input block 414 . Additionally, one free block within free block pool 185 is assigned as user input block 415 . Note that this operation is not performed if the user input blocks 413, 414, and 415 have already been allocated.

(2) Host writing In NVM set #1 (NVM set 163), write data from host 2 is written from write buffer 130A to user input block 413. Write data associated with the NVM subset 190A is temporarily stored in the write buffer 130A. Then, the lookup table corresponding to the NVM set 163 is updated, so that the logical address (LBA) corresponding to the write data is set to the physical address indicating the physical storage location in the user input block 413 where this write data is written. mapped.

Further, in NVM set #2 (NVM set 164), write data from the host 2 is written from the write buffer 130B to the user input block 414. Write data associated with the NVM subset 190B is temporarily stored in the write buffer 130B. Then, the lookup table corresponding to the NVM set 164 is updated, so that the logical address (LBA) corresponding to the write data is set to the physical address indicating the physical storage location in the user input block 414 where this write data is written. mapped.

Furthermore, in NVM set #3 (NVM set 165), write data from host 2 is written from write buffer 130C to user input block 415. Write data associated with the NVM subset 190C is temporarily stored in the write buffer 130C. Then, the lookup table corresponding to the NVM set 165 is updated, so that the logical address (LBA) corresponding to the write data is set to the physical address indicating the physical storage location in the user input block 415 where this write data is written. mapped.

(3) Movement of user input block When the user input block 415 is filled with write data in NVM set #3, the user input block 415 is moved to the NVM subset (data block pool) 190C. That is, user input blocks 415 filled with data are managed by NVM subset (data block pool) 190C.

Before the NVM set join operation is performed, when the user input block 413 is filled with write data in NVM set #1, the user input block 413 is moved to the NVM subset (data block pool) 190A and the user input block 413 is moved to the NVM set At #2, once the user input block 414 is filled with write data, the user input block 414 is moved to the NVM subset (data block pool) 190B. However, after the NVM set combination operation is executed, the operation shown in (3)' is executed instead of (3).

(3) 'Moving the user input block to the destination NVM set When the user input block 413 in NVM set #1 is filled with write data, the user input block 413 is moved to the NVM subset 190C of NVM set #3. be done. That is, user input blocks 413 filled with data are managed by NVM subset (data block pool) 190C.

Additionally, when the user input block 414 in NVM set #2 is filled with write data, that user input block 414 is moved to NVM subset 190C in NVM set #3. That is, user input blocks 414 filled with data are managed by NVM subset (data block pool) 190C.

(4) Allocation of GC input blocks When it becomes necessary to perform garbage collection in the NVM subset (data block pool) 190A, garbage collection for blocks in the NVM subset 190A is performed independently of other NVM sets. Action is performed. For example, if the number of blocks included in NVM subset 190A is greater than a certain threshold value X1 corresponding to NVM subset 190A, it may be determined that a garbage collection operation is necessary. Threshold X1 may be determined based on the total number of blocks that can be allocated for NVM subset 190A. For example, a value remaining after subtracting a predetermined number from the total number of blocks that can be allocated for NVM subset 190A may be used as a certain threshold value X1 corresponding to NVM subset 190A.

When a garbage collection operation is required in NVM subset 190A, one free block in free block pool 183 is assigned as GC input block 403.

Furthermore, when it becomes necessary to perform garbage collection in NVM subset (data block pool) 190B, garbage collection operations are performed for the blocks in NVM subset 190B independently of other NVM sets. For example, if the number of blocks included in NVM subset 190B is greater than a certain threshold value X1 corresponding to NVM subset 190B, it may be determined that a garbage collection operation is necessary. Threshold X1 may be determined based on the total number of blocks that can be allocated for NVM subset 190B. For example, a value remaining after subtracting a predetermined number from the total number of blocks that can be allocated for NVM subset 190B may be used as a certain threshold value X1 corresponding to NVM subset 190B.

When a garbage collection operation is required in NVM subset 190B, one free block in free block pool 184 is assigned as GC input block 404.

When garbage collection needs to be performed in NVM subset (data block pool) 190C, garbage collection operations are performed for the blocks in NVM subset 190C independently of other NVM sets. For example, if the number of blocks included in NVM subset 190C is greater than a certain threshold value X1 corresponding to NVM subset 190C, it may be determined that a garbage collection operation is necessary. Threshold X1 may be determined based on the total number of blocks that can be allocated for NVM subset 190C. For example, a value remaining after subtracting a predetermined number from the total number of blocks that can be allocated for the NVM subset 190C may be used as a certain threshold value X1 corresponding to the NVM subset 190C.

When a garbage collection operation is required in NVM subset 190C, one free block in free block pool 185 is assigned as GC input block 405.

(5) Copying Valid Data One or more blocks containing a mixture of valid data and invalid data are selected as copy source blocks from among the blocks in the NVM subset 190A. Only the valid data of the selected block is copied to the GC input block 403. The lookup table corresponding to the NVM set 163 is then updated, thereby assigning the physical storage location in the GC input block 403 to which the valid data was copied to the logical address (LBA) corresponding to the copied valid data. The indicated physical address is mapped.

Furthermore, one or more blocks containing a mixture of valid data and invalid data are selected as copy source blocks from among the blocks in the NVM subset 190B. Only valid data of the selected block is copied to the GC input block 404. The lookup table corresponding to NVM set 164 is then updated, thereby assigning the logical address (LBA) corresponding to the copied valid data to the physical storage location within GC input block 404 where this valid data was copied. The indicated physical address is mapped.

Furthermore, one or more blocks in which valid data and invalid data coexist are selected from among the blocks in the NVM subset 190C as copy source blocks. Only the valid data of the selected block is copied to the GC input block 405. The lookup table corresponding to NVM set 165 is then updated, thereby assigning the logical address (LBA) corresponding to the copied valid data to the physical storage location in GC input block 405 where this valid data was copied. The indicated physical address is mapped.

(6) Movement of GC input block In NVM set #3, when GC input block 405 is filled with valid data, GC input block 403 is moved to NVM subset 190C. That is, the GC input block 405 filled with valid data is managed by the NVM subset (data block pool) 190C.

Before the NVM set join operation is performed, in NVM set #1, when GC input block 403 is filled with valid data, GC input block 403 is moved to NVM subset 190A; in NVM set #2, GC input block 403 is moved to NVM subset 190A; Once 404 is filled with valid data, GC input block 404 is moved to NVM subset 190B. However, after the NVM set combination operation is executed, the operation shown in (6)' is executed instead of (6).

(6) 'Moving the GC input block to the destination NVM set When the GC input block 403 in NVM set #1 is filled with valid data, the GC input block 403 is moved to the NVM subset 190C in NVM set #3. Ru. User input blocks 403 filled with valid data are managed by NVM subset (data block pool) 190C.

Additionally, once the GC input block 404 in NVM set #2 is filled with valid data, the GC input block 404 is moved to NVM subset 190C in NVM set #3. User input blocks 403 filled with valid data are managed by NVM subset (data block pool) 190C.

(7) Return of blocks In NVM set #3, blocks that are managed by the NVM subset 190C and do not hold valid data are returned from the NVM subset 190C to the free block pool 185. A block that does not hold valid data is a block that has had all its data invalidated by a host write, or a block that has had all its valid data copied to a destination block by a garbage collection operation.

Before the NVM set join operation is performed, in NVM set #1, blocks that are managed by NVM subset 190A and do not hold valid data are returned from NVM subset 190A to free block pool 183 and are returned to free block pool 183 by NVM subset 190B. Blocks that are managed and do not hold valid data are returned from NVM subset 190B to free block pool 184. However, after the NVM set combination operation is executed, the operation shown in (7)' is executed instead of (7).

(7) 'Moving blocks of NVM subset to destination NVM set Blocks of NVM subset 190A are moved to NVM subset 190C of NVM set #3. That is, the blocks of NVM subset 190A are managed by NVM subset (data block pool) 190C.

Also, the block in NVM subset 190B is moved to NVM subset 190C in NVM set #3. That is, the blocks of NVM subset 190B are managed by NVM subset (data block pool) 190C.

(8) Movement of free blocks to combination destination NVM set Free blocks in free block pool 183 of NVM set #1 are moved to free block pool 185 of NVM set #3. Additionally, free blocks in the free block pool 184 of NVM set #2 are moved to the free block pool 185 of NVM set #3.

The flowcharts in FIGS. 29 and 30 show the procedure of data write/read operations performed by the controller 4.

When a command from the host 2 is received (YES in step S101), the NVM set control unit 21 checks the namespace ID included in the received command (step S102). If the area corresponding to NVM set #1 is specified by the received command (YES in step S103), the NVM set control unit 21 determines NVM set #1 to be accessed (step S104). For example, in a case where the namespace of NSID1 corresponds to NVM set #1, if the received command includes NSID1, it may be determined that the area corresponding to NVM set #1 has been specified.

If the received command is a write command (YES in step S105), the NVM set control unit 21 determines whether it is necessary to allocate a new user input block (step S106). If it is necessary to allocate a new user input block (YES in step S106), the NVM set control unit 21 allocates a free block in the free block pool of NVM set #1 as a user input block (step S107), and The write data is written to the user input block (step S108). If it is not necessary to allocate a new user input block (NO in step S106), the NVM set control unit 21 writes write data to the already allocated user input block (step S108).

When write data is written to the user input block, the NVM set control unit 21 updates the LUT corresponding to NVM set #1 (step S109). Then, the NVM set control unit 21 returns a write completion response to the host 2 (step S110).

If the received command is a read command (NO in step S105, YES in step S111), the NVM set control unit 21 refers to the LUT corresponding to NVM set #1 (step S112), and reads the information in the read command. Obtain the physical address corresponding to the starting LBA of. Based on this physical address, the NVM set control unit 21 reads the data specified by the read command from the block of the NVM subset belonging to NVM set #1 (step S113). Then, the NVM set control unit 21 returns the read data and a read completion response to the host 2 (step S114).

If the area corresponding to NVM set #1 is not specified by the received command (NO in step S103), the NVM set control unit 21 determines that the area corresponding to NVM set #2 is specified by the received command. It is determined whether or not (step S115). If the area corresponding to NVM set #2 is specified by the received command (YES in step S115), the NVM set control unit 21 determines NVM set #2 to be accessed (step S116). For example, in a case where the namespace of NSID2 corresponds to NVM set #2, if the received command includes NSID2, it may be determined that the area corresponding to NVM set #2 has been specified.

If the received command is a write command (YES in step S117), the NVM set control unit 21 determines whether it is necessary to allocate a new user input block (step S118). If it is necessary to allocate a new user input block (YES in step S118), the NVM set control unit 21 allocates a free block in the free block pool of NVM set #2 as a user input block (step S119), and The write data is written to the user input block that was created (step S120). If it is not necessary to allocate a new user input block (NO in step S118), the NVM set control unit 21 writes write data to the already allocated user input block (step S120).

When write data is written to the user input block, the NVM set control unit 21 updates the LUT corresponding to NVM set #2 (step S121). Then, the NVM set control unit 21 returns a write completion response to the host 2 (step S122).

If the received command is a read command (NO in step S117, YES in step S123), the NVM set control unit 21 refers to the LUT corresponding to NVM set #2 (step S124), and reads the information in the read command. Obtain the physical address corresponding to the starting LBA of. Based on this physical address, the NVM set control unit 21 reads the data specified by the read command from the block of the NVM subset belonging to NVM set #2 (step S125). Then, the NVM set control unit 21 returns the read data and a read completion response to the host 2 (step S126).

The flowchart in FIG. 31 shows the procedure of the garbage collection operation executed by the GC operation control unit 22 for each NVM subset belonging to a certain NVM set.

The GC operation control unit 22 determines whether the number of blocks included in NVM subset #1 belonging to NVM set #1 has reached the threshold value X1 corresponding to NVM subset #1 (step S201). If the number of blocks included in NVM subset #1 belonging to NVM set #1 reaches the threshold value X1 (YES in step S201), the GC operation control unit 22 starts GC of NVM subset #1.

The GC operation control unit 22 first allocates a free block in the free block pool of NVM set #1 as a copy destination block (step S202). Then, the GC operation control unit 22 selects a block containing a mixture of valid data and invalid data from the blocks of NVM subset #1 as a copy source block (step S203).

Next, the GC operation control unit 22 copies only the valid data of the selected block (copy source block) to the copy destination block (step S204). Then, the GC operation control unit 22 updates the LUT corresponding to NVM subset #1 (step S205). After that, the GC operation control unit 22 returns the block containing only invalid data (copy source block) to the free block pool of NVM set #1 (step S206).

Subsequently, the GC operation control unit 22 determines whether the number of blocks included in NVM subset #1 has decreased to a threshold value X2 (<X1) or less corresponding to NVM subset #1 (step S207). If the number of blocks included in NVM subset #1 falls below the threshold value X2 (<X1) (YES in step S207), the GC operation control unit 22 ends the garbage collection operation. If the number of blocks included in NVM subset #1 has not decreased to below the threshold value X2 (<X1) (NO in step S207), the GC operation control unit 22 continues the garbage collection operation (steps S202 to S206).

The flowchart in FIG. 32 shows the procedure of the inter-NVM set copy operation executed by the inter-NVM set copy control unit 23.

When an inter-NVM set copy command including a parameter specifying a copy source NVM set and a copy destination NVM set is received from the host 2 (YES at step S301), the inter-NVM set copy control unit 23 specifies the copy destination NVM set. A free block in the free block pool is allocated as a copy destination block (step S302). Then, the inter-NVM set copy control unit 23 selects a block having valid data from the blocks belonging to the copy source NVM set as a copy source block (step S303).

Next, the NVM inter-set copy control unit 23 copies valid data from the copy source block to the copy destination block (step S304). When the effective data is copied, the inter-NVM set copy control unit 23 updates the LUT corresponding to the NVM subset of the copy source NVM set (step S305).

Subsequently, the inter-NVM set copy control unit 23 returns the copy source block that no longer has valid data to the free block pool of the copy source NVM set (step S306).

The inter-NVM set copy control unit 23 repeats the processes of steps S302 to S306 until there is no block with valid data in the copy source NVM set (step S307).

The flowchart in FIG. 33 shows another procedure of the inter-NVM set copy operation executed by the inter-NVM set copy control unit 23. Here, it is assumed that the host write operation is permitted during the NVM set-to-NVM set copy operation.

When an inter-NVM set copy command including a parameter specifying a copy source NVM set and a copy destination NVM set is received from the host 2 (YES in step S401), the inter-NVM set copy control unit 23 selects the copy destination NVM set. A free block in the free block pool is allocated as a copy destination block (step S402). Then, the inter-NVM set copy control unit 23 selects a block having valid data from the blocks belonging to the copy source NVM set as a copy source block (step S403).

Next, the NVM inter-set copy control unit 23 copies valid data from the copy source block to the copy destination block (step S404). When the effective data is copied, the inter-NVM set copy control unit 23 updates the LUT corresponding to the NVM subset of the copy source NVM set (step S405).

Subsequently, the inter-NVM set copy control unit 23 returns the copy source block that no longer has valid data to the free block pool of the copy source NVM set (step S406).

Next, the inter-NVM set copy control unit 23 determines whether or not there is no block having valid data in the copy source NVM set (step S407). If there is no block having valid data in the copy source NVM set (YES in step S407), the inter-NVM set copy control unit 23 ends the inter-NVM set copy operation.

On the other hand, if there is a block with valid data in the copy source NVM set (NO in step S407), the NVM set control unit 21 of the controller 4 receives write data to the NVM subset belonging to the copy source NVM set. It is determined whether or not (step S408). If write data to the NVM subset belonging to the copy source NVM set has not been received (NO in step S408), the process proceeds to step S402.

If write data to the NVM subset belonging to the copy source NVM set has been received (YES in step S408), the NVM control unit 21 allocates a free block in the free block pool of the copy destination NVM set as the write destination block ( Step S409). Then, the NVM control unit 21 writes write data to the allocated block (step S410). When the write data is written, the NVM control unit 21 updates the LUT corresponding to the NVM subset belonging to the copy source NVM set (step S411).

Next, the controller 4 returns a write completion response to the host 2 (step S412). When a write completion response is returned to the host 2, the process advances to step S402.

The processes of steps S402 to S412 are repeated until there are no blocks with valid data in the copy source NVM set (step S407).

The flowchart in FIG. 34 shows the procedure of the new NVM set creation operation executed by the new NVM set creation control unit 24.

When the new NVM set creation command is received (YES in step S501), the new NVM set creation control unit 24 selects the NAND flash memory dies that are reserved for the new NVM set from among all the NAND flash memory dies that belong to the original NVM set. A group of NAND flash memory dies to be used is determined (step S502). The original NVM set may be replaced by a new NVM set creation command.

Subsequently, the new NVM set creation control unit 24 allocates a free block in the free block pool of the original NVM set as a copy destination block (step S503). Then, the new NVM set creation control unit 24 selects a block that holds valid data as a copy source block from the blocks that belong to the new NVM set (that is, blocks that belong to the group of secured NAND flash memory dies) (step S504).

Next, the new NVM set creation control unit 24 copies valid data from the copy source block to the copy destination block (step S505). When the valid data is copied, the new NVM set creation control unit 24 updates the LUT corresponding to the NVM subset of the copy source NVM set (step S506). Subsequently, the new NVM set creation control unit 24 returns the copy source block that no longer has valid data to the free block pool of the new NVM set (step S507).

Next, the new NVM set creation control unit 24 determines whether or not there is no block having valid data in the new NVM set (step S508). If there is no block with valid data in the new NVM set (YES in step S508), the new NVM set creation control unit 24 ends the new NVM set creation operation. If a block having valid data exists in the new NVM set (NO in step S508), the new NVM set creation control unit 24 continues the new NVM set creation operation (steps S503 to S507).

The processes of steps S503 to S507 are repeated until there are no blocks with valid data in the new NVM set.

The flowchart in FIG. 35 shows another procedure for the new NVM set creation operation executed by the new NVM set creation control unit 24. Here, a procedure is shown in which a new NVM set creation operation and a garbage collection operation on the original NVM set are executed in parallel.

When a new NVM set creation command is received (step S601), the new NVM set creation control unit 24 determines a group of NAND flash memory dies to be secured for the new NVM set (step S602). Subsequently, the new NVM set creation control unit 24 allocates a free block in the free block pool of the original NVM set as a copy destination block (step S603). Then, the new NVM set creation control unit 24 selects a block containing a mixture of valid data and invalid data as a copy source block from the blocks belonging to the original NVM set (step S604). In step S604, the new NVM set creation control unit 24 may preferentially select a block with less valid data as the copy source block.

Next, the new NVM set creation control unit 24 copies valid data from the copy source block to the copy destination block (step S605). When the valid data is copied, the new NVM set creation control unit 24 updates the LUT corresponding to the NVM subset of the copy source NVM set (step S606).

Next, the new NVM set creation control unit 24 determines whether the physical location of the copy source block that no longer has valid data belongs to the new NVM set (step S607). If the physical location of the copy source block that no longer has valid data belongs to the new NVM set (YES in step S607), the new NVM set creation control unit 24 transfers the copy source block that no longer has valid data to the new NVM set. The block is returned to the free block pool (step S608). If the physical location of the copy source block that no longer has valid data does not belong to the new NVM set (NO in step S607), the new NVM set creation control unit 24 restores the copy source block that no longer has valid data to the original NVM set. The block is returned to the free block pool of the NVM set (step S609).

Next, the new NVM set creation control unit 24 determines whether or not there is no block having valid data in the new NVM set (step S610). If there is no block with valid data in the new NVM set (YES in step S610), the new NVM set creation control unit 24 ends the new NVM set creation operation. If there is a block with valid data in the new NVM set (NO in step S610), the new NVM set creation control unit 24 executes the process in step S603.

The processes of steps S603 to S607 are repeated until there are no blocks with valid data in the new NVM set.

FIG. 36 shows an example of the hardware configuration of an information processing apparatus (computing device) functioning as the host 2. As shown in FIG.

This information processing apparatus is realized as a computing device such as a server. This information processing device includes a processor (CPU) 801, a main memory 802, a BIOS-ROM 803, a network controller 805, a peripheral interface controller 806, a controller 807, an embedded controller (EC) 808, and the like.

Processor 801 is a CPU configured to control the operation of each component of this information processing apparatus. This processor 801 executes various programs loaded into the main memory 802 from any one of the plurality of SSDs 3. Main memory 802 is comprised of random access memory such as DRAM. Further, this program may include a setting program for issuing commands instructing the above-described inter-NVM set copy, NVM set exchange, new NVM set creation, and NVM set combination.

Processor 801 also executes a basic input/output system (BIOS) stored in BIOS-ROM 803, which is a non-volatile memory. BIOS is a system program for controlling hardware.

The network controller 805 is a communication device such as a wired LAN controller or a wireless LAN controller. Peripheral interface controller 806 is configured to perform communications with peripheral devices, such as USB devices.

Controller 807 is configured to communicate with devices connected to each of the plurality of connectors 807A. A plurality of SSDs 3 may be respectively connected to a plurality of connectors 807A. The controller 807 is a SAS expander, a PCIe Switch, a PCIe expander, a flash array controller, a RAID controller, or the like.

The EC 808 functions as a system controller configured to perform power management of the information processing device.

FIG. 37 shows a configuration example of an information processing device (server) including a plurality of SSDs 3 and a host 2.

This information processing device (server) includes a thin box-shaped housing 901 that can be accommodated in a rack. A large number of SSDs 3 may be placed within the housing 901. In this case, each SSD 3 may be removably inserted into a slot provided on the front surface 901A of the housing 901.

A system board (motherboard) 902 is placed inside the housing 901 . Various electronic components including a CPU 801, a main memory 802, a network controller 805, and a controller 807 are mounted on the system board (motherboard) 902. These electronic components function as the host 2.

As described above, according to the present embodiment, the NAND flash memory dies are classified into a plurality of NVM sets such that each of the NAND flash memory dies belongs to only one NVM set. Then, data write/read operations are performed on one of the plurality of NVM sets in response to an I/O command from the host that specifies at least one area (for example, namespace) corresponding to each NVM set. . Therefore, a plurality of I/O commands (write commands or read commands) each specifying a different area corresponding to a different NVM set can be executed simultaneously without die contention. Therefore, for example, even if a read command directed to an area corresponding to another NVM set is received from the host 2 while a data write operation for a certain NVM set is being executed, the controller 4 waits for the completion of this data write operation. The data read operation corresponding to this read command can be immediately executed without any trouble.

Further, the free block group of the NAND flash memory 5 is managed individually for each NVM set by a plurality of free block pools corresponding to a plurality of NVM sets. Then, for each of the plurality of NVM sets, an operation of allocating one of the free blocks in the corresponding free block pool as an input block (user input block or GC input block), an operation of writing write data to the input block, and a write operation are performed. The operations of managing input blocks filled with data by the NVM subset and returning blocks that are managed by the NVM subset and do not hold valid data to the corresponding free block pool are performed. In this way, by using free blocks corresponding to each of a plurality of NVM sets, input block allocation and free block return can be executed independently for each NVM set. Thereby, it is possible to prevent a block within a die belonging to a certain NVM set from being allocated as an input block for another NVM set. Therefore, it is possible to ensure that die contention does not occur.

Additionally, there are shared NVM sets in which the free block pool is shared by multiple NVM subsets (multiple garbage collection groups), and separated NVM sets in which the free block pool is dedicated to one NVM subset (one garbage collection group). The NVM set can coexist within one SSD 3.

Note that in this embodiment, a NAND flash memory is exemplified as the nonvolatile memory. However, the functions of this embodiment are, for example, MRAM (Magnetoresistive
Random Access Memory), PRAM (Phase change
It is also applicable to various other non-volatile memories such as Random Access Memory (Random Access Memory), ReRAM (Resistive Random Access Memory), or FeRAM (Ferroelectric Random Access Memory).

Although several embodiments of the invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and changes can be made without departing from the gist of the invention. These embodiments and their modifications are included within the scope and gist of the invention, as well as within the scope of the invention described in the claims and its equivalents.

2... Host, 3... SSD, 4... Controller, 5... NAND flash memory, 21... NVM set control unit, 22... GC operation control unit, 23... Copy control unit between NVM sets, 24... New NVM set creation control unit , 25... NVM exchange control unit, 26... NVM set coupling unit, 60, 61, 62... NVM set, 80, 81, 82... Free block pool, 90, 91, 92, 93, 94, 95... NVM subset.

Claims (17)

A memory system connectable to a host,
multiple channels and
a non-volatile memory comprising a plurality of non-volatile memory dies connected to the plurality of channels, each non-volatile memory die including a plurality of blocks;
a controller connected to the plurality of non-volatile memory dies via the plurality of channels, the controller configured to control the plurality of non-volatile memory dies;
The controller includes:
allocating a logical address space of the memory system to a plurality of namespaces including at least a first namespace and a second namespace;
classifying the plurality of nonvolatile memory dies into a first die group and a second die group such that each of the plurality of nonvolatile memory dies belongs to only one die group;
When a first write command specifying the first namespace corresponding to the first die group is received from the host, first data to be written to the first namespace is written to the first die group. Write to the first write destination block selected from the group,
When a second write command specifying the second namespace corresponding to the second die group is received from the host, the second data to be written to the second namespace is written to the second die group. configured to write to a second destination block selected from the group;
memory system. The controller includes:
If a first read command specifying the first namespace is received from the host while the second data write operation is being executed, the second data write operation is executed without waiting for the completion of the second data write operation. configured to read data from one die group;
The memory system according to claim 1. A free block group belonging to the first die group is managed by a first free block pool corresponding to the first die group, and a free block group belonging to the second die group is managed by a first free block pool corresponding to the first die group. managed by a second free block pool corresponding to the group;
The first free block pool is a free block pool dedicated to a first data block pool that manages each block that belongs to the first die group and holds valid data, and the second free block pool is a shared free block pool shared by a plurality of second data block pools that manage blocks that belong to the second die group and hold valid data, respectively;
The memory system according to claim 1. The controller includes:
In garbage collection of a group of blocks in the first data block pool, one of the free blocks in the first free block pool is allocated as a first copy destination block, and one of the blocks included in the first data block pool is allocated as a first copy destination block. and copying only valid data from one or more blocks in which valid data and invalid data are mixed to the first copy destination block, and copying the valid data to the first copy destination block to copy only the invalid data to the first copy destination block. performing an operation of returning the one or more blocks that have become free to the first free block pool;
In garbage collection of a group of blocks in one second data block pool of the plurality of second data block pools, garbage collection of blocks in the second free block pool shared by the plurality of second data block pools is performed. One of the free blocks is allocated as a second copy destination block, and only valid data is transferred from one or more blocks included in the one second data block pool and containing a mixture of valid data and invalid data to the second copy destination block. copying the valid data to the second copy destination block and returning the one or more blocks, which have become only invalid data by copying the valid data to the second copy destination block, to the second free block pool. is configured to
The memory system according to claim 3. A free block group belonging to the first die group is managed by a first free block pool corresponding to the first die group, and a free block group belonging to the second die group is managed by a first free block pool corresponding to the first die group. managed by a second free block pool corresponding to the group;
The first free block pool is a free block pool dedicated to a first data block pool that manages each block that belongs to the first die group and holds valid data, and the second free block pool is a free block pool dedicated to a second data block pool that manages each block that belongs to the second die group and holds valid data;
The memory system according to claim 1. The controller includes:
In garbage collection of a group of blocks in the first data block pool, one of the free blocks in the first free block pool is allocated as a first copy destination block, and one of the blocks included in the first data block pool is allocated as a first copy destination block. and copying only valid data from one or more blocks in which valid data and invalid data are mixed to the first copy destination block, and copying the valid data to the first copy destination block to copy only the invalid data to the first copy destination block. performing an operation of returning the one or more blocks that have become free to the first free block pool;
In garbage collection of a group of blocks in the second data block pool, one of the free blocks in the second free block pool is allocated as a second copy destination block, and the blocks included in the second data block pool are and copying only valid data from one or more blocks in which valid data and invalid data are mixed to the second copy destination block, and copying the valid data to the second copy destination block to copy only the invalid data. configured to perform an operation of returning the one or more blocks that have become free to the second free block pool;
The memory system according to claim 5. A free block group belonging to the first die group is managed by a first free block pool corresponding to the first die group, and a free block group belonging to the second die group is managed by a first free block pool corresponding to the first die group. managed by a second free block pool corresponding to the group;
The first free block pool is a shared free block pool shared by a plurality of first data block pools that manage blocks that belong to the first die group and hold valid data, and The free block pool is a shared free block pool shared by a plurality of second data block pools that manage blocks that belong to the second die group and hold valid data, respectively.
The memory system according to claim 1. The controller includes:
In garbage collection of blocks in one first data block pool of the plurality of first data block pools, garbage collection of blocks in the first free block pool shared by the plurality of first data block pools is performed. One of the free blocks is allocated as a first copy destination block, and only valid data is transferred from one or more blocks included in the one first data block pool and containing a mixture of valid data and invalid data to the first copy destination block. copying the valid data to the first copy destination block and returning the one or more blocks, which have become only invalid data by copying the valid data to the first copy destination block, to the first free block pool. death,
In garbage collection of a group of blocks in one second data block pool of the plurality of second data block pools, garbage collection of blocks in the second free block pool shared by the plurality of second data block pools is performed. One of the free blocks is allocated as a second copy destination block, and only valid data is transferred from one or more blocks included in the one second data block pool and containing a mixture of valid data and invalid data to the second copy destination block. copying the valid data to the second copy destination block and returning the one or more blocks, which have become only invalid data by copying the valid data to the second copy destination block, to the second free block pool. is configured to
The memory system according to claim 7. The first die group includes a set of a plurality of first nonvolatile memory dies each connected to the plurality of channels, and the second die group includes a set of a plurality of first nonvolatile memory dies each connected to the plurality of channels. 2 non-volatile memory dies;
The memory system according to claim 1. The first die group includes a set of first nonvolatile memory dies each connected to a first channel of the plurality of channels, and the second die group includes a set of first nonvolatile memory dies connected to a first channel of the plurality of channels. a plurality of second non-volatile memory dies each connected to a channel of the second non-volatile memory die;
The memory system according to claim 1. The number of non-volatile memory dies belonging to the first die group is different from the number of non-volatile memory dies belonging to the second die group.
The memory system according to claim 1. The controller classifies the plurality of nonvolatile memory dies into the first die group and the second die group in response to receiving a command from the host.
The memory system according to claim 1. A control method for controlling a plurality of non-volatile memory dies connected to a plurality of channels by a controller connected to the plurality of non-volatile memory dies via the plurality of channels, wherein each non-volatile memory die controls a plurality of blocks. including,
allocating the logical address space to a plurality of namespaces including at least a first namespace and a second namespace;
classifying the plurality of non-volatile memory dies into a first die group and a second die group such that each of the plurality of non-volatile memory dies belongs to only one die group;
When a first write command specifying the first namespace corresponding to the first die group is received from the host, the first data to be written to the first namespace is written to the first die group. writing to a first write destination block selected from;
When a second write command specifying the second namespace corresponding to the second die group is received from the host, the second data to be written to the second namespace is written to the second die group. writing to a second write destination block selected from the group. A free block group belonging to the first die group is managed by a first free block pool corresponding to the first die group, and a free block group belonging to the second die group is managed by a first free block pool corresponding to the first die group. managed by a second free block pool corresponding to the group;
The first free block pool is a free block pool dedicated to a first data block pool that manages each block that belongs to the first die group and holds valid data, and the second free block pool 14. The control method according to claim 13, wherein the second data block pool is a shared free block pool shared by a plurality of second data block pools that manage blocks that belong to the second die group and hold valid data, respectively. In garbage collection of a group of blocks in the first data block pool, one of the free blocks in the first free block pool is allocated as a first copy destination block, and one of the blocks included in the first data block pool is allocated as a first copy destination block. and copying only valid data from one or more blocks in which valid data and invalid data are mixed to the first copy destination block, and copying the valid data to the first copy destination block to copy only the invalid data to the first copy destination block. performing an operation of returning the one or more blocks that have become free to the first free block pool;
In garbage collection of a group of blocks in one second data block pool of the plurality of second data block pools, garbage collection of blocks in the second free block pool shared by the plurality of second data block pools is performed. One of the free blocks is allocated as a second copy destination block, and only valid data is transferred from one or more blocks included in the one second data block pool and containing a mixture of valid data and invalid data to the second copy destination block. copying the valid data to the second copy destination block and returning the one or more blocks, which have become only invalid data by copying the valid data to the second copy destination block, to the second free block pool. 15. The control method according to claim 14, further comprising: The first die group includes a set of a plurality of first nonvolatile memory dies each connected to the plurality of channels, and the second die group includes a set of a plurality of first nonvolatile memory dies each connected to the plurality of channels. 14. The method of claim 13, comprising a set of two non-volatile memory dies. The first die group includes a set of first nonvolatile memory dies each connected to a first channel of the plurality of channels, and the second die group includes a set of first nonvolatile memory dies connected to a first channel of the plurality of channels. 14. The control method of claim 13, comprising a set of a plurality of second non-volatile memory dies each connected to a channel of the second non-volatile memory die.

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