JP2023157335A - Sealing resin composition, sheet material, semiconductor device, and manufacturing method of semiconductor device - Google Patents

Abstract

To provide a sealing resin composition less likely to create cavities in a sealing material when manufacturing the sealing material for sealing the gap between the base material and the semiconductor chip by using a sheet material manufactured from the sealing resin composition.SOLUTION: A sealing resin composition contains: a polyphenylene ether resin (A) that has a substituent that has radical polymerizability; tiallylisocyanurate (B); an inorganic filler (C); a radical polymerization initiator (D); and a thermoplastic elastomer (E). The percentage of the triallyl isocyanurate (B) is 5% by mass or more and 20% by mass or less based on the solid content of the sealing resin composition. The percentage of the thermoplastic elastomer (E) is 5% by mass or more and 18% by mass or less based on the solid content of the sealing resin composition.SELECTED DRAWING: Figure 1

Description

The present invention relates to a sealing resin composition, a sheet material, a semiconductor device, and a method for manufacturing a semiconductor device, and more specifically, the present invention relates to a sealing resin composition, a sheet material, a semiconductor device, and a method for manufacturing a semiconductor device. A sealing resin composition suitable for sealing, a sheet material produced from the sealing resin composition, a semiconductor device produced using the sealing resin composition, and a semiconductor device production using the sheet material. Regarding the method.

Patent Document 1 discloses that a sheet material made from a sealing acrylic composition is stacked on the surface of a semiconductor wafer having bump electrodes, and the semiconductor wafer is cut out from the semiconductor wafer by cutting the entire sheet material. A member is manufactured that includes a semiconductor chip cut out from the sheet material and individual sheets cut out from a sheet material, and the individual sheets are stacked on the surface of the base material having conductor wiring, and the individual sheets are stacked on the base material and the individual sheets. and semiconductor chips are stacked in this order, and the individual sheets are heated to melt and harden the individual sheets to create a sealing material and electrically connect the bump electrodes and conductor wiring. A method of manufacturing a semiconductor device is disclosed.

Japanese Patent Application Publication No. 2015-42754

When a sheet material is produced from a sealing resin composition and a sealing material made of a cured product of this sheet material is used to seal the gap between a semiconductor chip and a base material in a semiconductor device, the sheet material is Cavities may form in the encapsulant due to excessive material flow. This cavity reduces the reliability of the semiconductor device. According to the inventor's research, when the manufacturing process of a semiconductor device includes a step of stacking a sheet material on a semiconductor wafer as described in Patent Document 1, cavities are particularly likely to occur in the sealing material.

The problem of the present invention is that when producing an encapsulant that seals the gap between a base material and a semiconductor chip using a sheet material made from an encapsulant resin composition, cavities are created in the encapsulant. A encapsulating resin composition that is difficult to oxidize, a sheet material made from this encapsulating resin composition, a semiconductor device manufactured using the encapsulating resin composition, and a method for manufacturing a semiconductor device using the sheet material, It is to provide.

The encapsulating resin composition according to one embodiment of the present invention includes a polyphenylene ether resin (A) having a radically polymerizable substituent, triallylisocyanurate (B), an inorganic filler (C), and a radical polymerizable substituent. Contains a polymerization initiator (D) and a thermoplastic elastomer (E). The percentage of the triallyl isocyanurate (B) is 5% by mass or more and 20% by mass or less based on the solid content of the sealing resin composition. The percentage of the thermoplastic elastomer (E) is 5% by mass or more and 18% by mass or less based on the solid content of the encapsulating resin composition.

The sheet material according to one aspect of the present invention includes the encapsulating resin composition or a semi-cured product of the encapsulating resin composition.

A semiconductor device according to one aspect of the present invention includes a base material, a semiconductor chip mounted face down on the base material, and a sealing material that seals a gap between the base material and the semiconductor chip. Equipped with The sealing material is made of a cured product of the sealing resin composition.

A method for manufacturing a semiconductor device according to one aspect of the present invention includes stacking the sheet material on the surface of a semiconductor wafer including bump electrodes, and cutting the semiconductor wafer together with the sheet material. A chip member including a semiconductor chip cut out from a wafer and an individual sheet cut out from the sheet material is produced, and the individual sheet in the chip member is placed on the surface of a base material provided with conductor wiring on which the conductor wiring is located. The base material, the individual sheet, and the semiconductor chip are laminated in this order by stacking the base material, the individual sheet, and the semiconductor chip, and by heating the individual sheet, the individual sheet is melted and then hardened to produce a sealing material. and electrically connecting the bump electrode and the conductor wiring.

According to this embodiment, when producing an encapsulant that seals a gap between a base material and a semiconductor chip using a sheet material produced from an encapsulant resin composition, a cavity is formed in the encapsulant. It can be made less likely to occur.

FIG. 1 is a schematic cross-sectional view showing a semiconductor device according to an embodiment of the present invention. FIG. 2 is a schematic cross-sectional view showing a laminated sheet in one embodiment of the present invention. 3A, FIG. 3B, FIG. 3C, and FIG. 3D are schematic cross-sectional views showing a process of manufacturing a chip member from a semiconductor wafer and a sheet material in an embodiment of the present invention. 4A, 4B, 4C, and 4D are schematic cross-sectional views showing a process of mounting a semiconductor chip on a base material in an embodiment of the present invention.

The sealing resin composition according to the present embodiment (hereinafter also referred to as composition (X)) includes a polyphenylene ether resin (A) having a substituent having radical polymerizability, triallyl isocyanurate (B), It contains an inorganic filler (C), a radical polymerization initiator (D), and a thermoplastic elastomer (E). The percentage of triallylisocyanurate (B) is 5% by mass or more and 20% by mass or less based on the solid content of composition (X). The percentage of the thermoplastic elastomer (E) is 5% by mass or more and 18% by mass or less based on the solid content of the composition (X).

Sheet material 41 can be produced from composition (X). For example, the sheet material 41 can be produced by molding the composition (X) into a sheet shape and drying it as necessary, or by molding the composition (X) into a sheet shape and semi-curing it. That is, the sheet material 41 includes, for example, composition (X) or a semi-cured product of composition (X).

In addition, the solid content amount of the composition (X) is the amount of components that constitute a cured product when the composition (X) is cured, among the components in the composition (X). Among the components in X), this is the amount of the components excluding the solvent etc. that volatilize during the curing process of the composition (X).

According to this embodiment, the sealing material 4 that seals the gap between the base material 2 and the semiconductor chip 3 in the semiconductor device 1 can be produced from the sheet material 41 produced from the composition (X) (FIG. reference). Generally, the sealing material 4 that seals the gap between the base material 2 and the semiconductor chip 3 is called an underfill, and the sheet material 41 for making the underfill is NCF (non-conductive film). to be called.

In this embodiment, the composition (X) contains triallylisocyanurate (B), and the percentage of triallylisocyanurate (B) is 5% by mass or more and 20% by mass based on the solid content of the composition (X). % or less, the softening point of composition (X) may become low. Therefore, the softening point of the sheet material 41 made from the composition (X) may be low. Therefore, when stacking the sheet material 41 on the semiconductor chip 3, the heating temperature at which the sheet material 41 is heated can be lowered so that the bump electrodes 31 of the semiconductor chip 3 are buried in the sheet material 41. That is, even if the temperature at which the sheet material 41 is heated is low, the sheet material 41 can be softened and deformed, and the bump electrodes 31 can be easily buried in the sheet material 41.

Further, since the composition (X) contains the thermoplastic elastomer (E), and the percentage ratio of the thermoplastic elastomer (E) is 5% by mass or more and 18% by mass or less based on the solid content of the composition (X), Although the softening point of the composition (X) is low, the composition (X) does not easily flow excessively when the composition (X) is heated. Therefore, when producing the sealing material 4 from the sheet material 41 produced from the composition (X), if the sheet material 41 is heated while being interposed between the semiconductor chip 3 and the base material 2, the sheet material 41 is less likely to flow excessively, and therefore cavities are less likely to be formed within the sealing material 4. Therefore, deterioration in reliability of the semiconductor device 1 due to cavities in the sealing material 4 can be suppressed.

The components of composition (X) will be explained in detail.

The composition (X) contains a radically polymerizable compound, and the radically polymerizable compound contains a polyphenylene ether resin (A) having a radically polymerizable substituent and triallyl isocyanurate (B). do.

The polyphenylene ether resin (A) can increase the glass transition point of the cured product of the composition (X) and improve the heat resistance of the cured product. Thereby, the heat resistance reliability of the semiconductor device can be improved.

The polyphenylene ether resin (A) has, for example, a polyphenylene ether chain (a2) and a substituent (a1) bonded to the terminal of the polyphenylene ether chain (a2).

The structure of the substituent (a1) is not particularly limited as long as it has radical polymerizability. The substituent (a1) is preferably a group having a carbon-carbon double bond. In this case, the polyphenylene ether resin (A) can have good radical polymerizability.

The substituent (a1) has, for example, a structure shown in the following formula (1) or a structure shown in the following formula (2).

In formula (1), R is hydrogen or an alkyl group. When R is an alkyl group, this alkyl group is preferably a methyl group.

In formula (2), n is an integer from 0 to 10, for example, n=1. In formula (2), Z is an arylene group, and R ¹ to R ³ are each independently hydrogen or an alkyl group. In addition, when n in Formula (2) is 0, Z is directly bonded to the terminal of the polyphenylene ether chain (a1) in the polyphenylene ether resin (A).

It is particularly preferable that the substituent (a1) has a structure shown in formula (1).

The polyphenylene ether resin (A) contains, for example, a compound having the structure shown in the following formula (3).

In formula (3), Y is an alkylene group having 1 to 3 carbon atoms or a single bond. Y is, for example, a dimethylmethylene group. In formula (3), X is a substituent (a1), and is, for example, a group having the structure shown in formula (1) or a group having the structure shown in formula (2). It is particularly preferable that X is a group having the structure shown in formula (1). Further, in formula (3), s is a number greater than or equal to 0, t is a number greater than or equal to 0, and the sum of s and t is a number greater than or equal to 1. s is preferably a number from 0 to 20, t is preferably a number from 0 to 20, and the total value of s and t is preferably from 1 to 30.

As mentioned above, the composition (X) contains triallylisocyanurate (B), and the percentage of triallylisocyanurate (B) is 5% by mass or more and 20% by mass based on the solid content of the composition (X). % or less. When the composition (X) contains triallylisocyanurate (B) and the percentage thereof is 5% by mass or more, the softening point of the composition (X) and the sheet material is low, for example, the softening point is 80 ° C. It can be: Furthermore, since the percentage of triallylisocyanurate (B) is 20% by mass or less, the melt viscosity of the composition (X) and the sheet material is unlikely to decrease excessively. The percentage of triallylisocyanurate (B) is more preferably 8% by mass or more, and even more preferably 10% by mass or more. Further, the percentage of triallylisocyanurate (B) is more preferably 16% by mass or less, and even more preferably 12% by mass or less.

Moreover, it is preferable that the mass ratio of polyphenylene ether resin (A) and triallyl isocyanurate (B) is from 4:6 to 6:4. In this case, it becomes particularly easy to form the composition (X) into a sheet, and the sheet material made from the composition (X) can have good toughness.

It is preferable that the radically polymerizable compounds in the composition (X) are only the polyphenylene ether resin (A) and triallyl isocyanurate (B). Further, within a range that does not excessively impair the purpose of the present embodiment, the radically polymerizable compound in the composition (X) may be a compound other than the polyphenylene ether resin (A) and the triallyl isocyanurate (B) (hereinafter referred to as a compound). (F)) may further be contained. Compound (F) contains, for example, at least one selected from the group consisting of various vinyl compounds and (meth)acrylic compounds.

The inorganic filler (C) can improve the thermal conductivity of the cured product of the composition (X). Therefore, heat generated from the semiconductor chip 3 in the semiconductor device 1 can be efficiently released through the sealing material 4. Moreover, the inorganic filler (C) can lower the coefficient of thermal expansion of the cured product. Therefore, when the semiconductor device 1 including the encapsulant 4 is heated, the difference in dimensional change between the encapsulant 4, the semiconductor chip 3, the base material 2, etc. becomes small, and the semiconductor device 1 is warped and damaged. can be suppressed. Furthermore, the inorganic filler (C) can suppress the fluidity of the composition (X), and therefore the generation of cavities in the sealant 4 can be further suppressed.

Examples of the inorganic filler (C) include silica powder such as fused silica, synthetic silica, and crystalline silica; oxides such as alumina and titanium oxide; silicates such as talc, fired clay, unfired clay, mica, and glass; calcium carbonate, Carbonates such as magnesium carbonate and hydrotalcite; hydroxides such as aluminum hydroxide, magnesium hydroxide, and calcium hydroxide; sulfates or sulfites such as barium sulfate, calcium sulfate, and calcium sulfite; zinc borate, barium metaborate, boron It can contain one or more materials selected from the group consisting of borates such as aluminum oxide, calcium borate, and sodium borate; and nitrides such as aluminum nitride, boron nitride, and silicon nitride. The fused silica may be either fused spherical silica or fused crushed silica. In particular, it is preferable that the inorganic filler (C) contains at least one of silica and alumina.

The inorganic filler (C) may be any one of crushed, acicular, scaly, spherical, etc., and is not particularly limited. In order to improve the dispersibility of the inorganic filler (C) in the composition (X) and the cured product, and to control the viscosity of the composition (X), the inorganic filler (C) is preferably spherical.

It is preferable that the inorganic filler (C) has an average particle size smaller than the dimension between the base material 2 and the semiconductor chip 3. In order to improve the density of the inorganic filler (C) in the composition (X) and in the cured product, and to appropriately adjust the fluidity of the composition (X), it is necessary to adjust the average of the inorganic filler (C). The particle size is preferably 5 μm or less, more preferably 1 μm or less, even more preferably 0.5 μm or less, and particularly preferably 0.1 μm or more and 0.3 μm or less. The inorganic filler (C) may contain two or more components having mutually different average particle sizes. Note that the average particle diameter in this embodiment is a median diameter calculated from the results of particle size distribution measurement by laser light diffraction method.

The percentage ratio of the inorganic filler (C) to the solid content of the composition (X) is, for example, 55% by mass or more and 65% by mass or less.

The radical polymerization initiator (D) contains, for example, an organic peroxide. The 1-minute half-life temperature of the organic peroxide is preferably 100°C or more and 195°C or less, and more preferably 120°C or more and 180°C or less. In this case, the sheet material 41 can quickly thicken to the extent that the wettability between the bump electrode 31 and the conductor wiring 21 is not inhibited in the initial stage of the process of heating the sheet material 41 to produce the sealing material 4. Therefore, the generation of cavities within the sealing material 4 can be further suppressed. Furthermore, by curing the sheet material 41 progressing sufficiently quickly, peeling between the semiconductor chip 3 and the sealing material 4 can be suppressed.

Examples of organic peroxides include t-butyl peroxy-2-ethylhexyl monocarbonate (1 minute half-life temperature: 161.4°C), t-butyl peroxybenzoate (1 minute half-life temperature: 166.8°C), t- Butylcumyl peroxide (1 minute half-life temperature: 173.3°C), dicumyl peroxide (1 minute half-life temperature: 175.2°C), α,α'-di(t-butylperoxy)diisopropylbenzene (1 minute half-life temperature: 175.2°C) half-life temperature 175.4°C), 2,5-dimethyl-2,5-di(t-butylperoxy)hexane (1 minute half-life temperature 179.8°C), di-t-butyl peroxide (1 minute half-life temperature 179.8°C) At least one member selected from the group consisting of 2,5-dimethyl-2,5-bis(t-butylperoxy)hexyne (half-life temperature: 194.3°C), etc. Contains.

The percentage ratio of the radical polymerization initiator (D) to the total amount of radically polymerizable compounds in the composition (X) is, for example, 0.25% by mass or more and 2.0% by mass or less. It is more preferable that this percentage is 0.5% by mass or more. Moreover, it is more preferable that this percentage is 1.5% by mass or less.

As mentioned above, the composition (X) contains the thermoplastic elastomer (E), and the percentage of the thermoplastic elastomer (E) is 5% by mass or more and 18% by mass or less based on the solid content of the composition (X). It is. Since the composition (X) contains the thermoplastic elastomer (E) and the percentage thereof is 5% by mass or more, the flow of the composition (X) and the sheet material when heated is appropriately suppressed. Ru. Therefore, when the sealing material 4 is produced by heating the sheet material 41, the generation of cavities in the sealing material 4 can be suppressed. Further, since the percentage of the thermoplastic elastomer (E) is 18% by mass or less, the flow of the composition (X) and the sheet material 41 when heated is not excessively inhibited. The percentage of the thermoplastic elastomer (E) is more preferably 12% by mass or more, and even more preferably 14% by mass or more. Further, the percentage of the thermoplastic elastomer (E) is more preferably 17% by mass or less, and even more preferably 16% by mass or less.

The thermoplastic elastomer (E) contains, for example, at least one selected from the group consisting of styrene elastomer, acrylic elastomer, and urethane elastomer. Note that the components contained in the thermoplastic elastomer (E) are not limited to the above.

The thermoplastic elastomer (E) preferably contains a styrene elastomer. In this case, the fluidity of the composition (X) and the sheet material 41 when heated can be effectively suppressed. The styrenic elastomer contains, for example, styrene-ethylene/butylene-styrene block copolymer (SEBS).

Composition (X) may further contain appropriate components other than those listed above. Composition (X) can contain, as an optional component, at least one selected from the group consisting of flux, radical scavenger, coupling agent, antifoaming agent, leveling agent, low stress agent, pigment, and the like.

Composition (X) may contain a solvent for the purpose of adjusting moldability when producing sheet material 41 from composition (X). The solvent contains, for example, at least one selected from the group consisting of methanol, ethanol, ethylene glycol monomethyl ether, ethylene glycol monoethyl ether, ethylene glycol monobutyl ether, methyl ethyl ketone, acetone, isopropylacetone, toluene, and xylene. The amount of the solvent is adjusted so that the composition (X) has appropriate moldability, and for example, the percentage ratio of the solvent to the solid content of the composition (X) is 20% by mass or more and 80% by mass or less. In addition, when the composition (X) has appropriate moldability even without containing a solvent, the composition (X) does not need to contain a solvent.

Composition (X) is prepared, for example, by the following method.

First, among the raw materials for composition (X), raw materials other than the inorganic filler (C) are blended simultaneously or sequentially to obtain a mixture. This mixture is stirred and mixed while performing heating treatment and cooling treatment as necessary. Next, an inorganic filler (C) is added to this mixture, if necessary. Next, this mixture is stirred and mixed again while performing heating treatment and cooling treatment as necessary. Thereby, composition (X) can be obtained. For stirring the mixture, for example, a disper, a planetary mixer, a ball mill, a three-roll mill, a bead mill, etc. can be used in combination as necessary.

A sheet material 41 made from composition (X), a laminated sheet 7 including the sheet material 41, and a method for manufacturing the sheet material 41 and the laminated sheet 7 will be described.

The laminated sheet 7 includes a support sheet 71 and a sheet material 41 that overlaps the support sheet 71. When producing the sheet material 41 and the laminated sheet 7, for example, the support sheet 71 is first prepared. The support sheet 71 is, for example, a plastic sheet such as a polyethylene terephthalate sheet.

Composition (X) is applied onto one side of the support sheet 71. The sheet material 41 can be produced on the support sheet 71 by applying the composition (X) in this manner or by further drying the composition (X) by heating it. Thereby, a sheet material 41 containing the composition (X) is produced. Alternatively, the sheet material 41 may be produced on the support sheet 71 by applying the composition (X) and then heating the composition (X) to semi-cure it. Thereby, a sheet material 41 containing a semi-cured product of composition (X) is produced. When drying or semi-curing composition (X), the temperature at which composition (X) is heated is, for example, 60°C or more and 120°C or less, and the heating time is 5 minutes or more and 30 minutes or less, but the heating conditions is not limited to this.

The sheet material 41 and the laminated sheet 7 can be produced as described above.

The thickness of the sheet material 41 is, for example, 45 μm or more and 70 μm or less, but is not limited thereto, and may be any appropriate value depending on the thickness of the sealing material 4 in the semiconductor device 1.

The laminated sheet 7 may further include a protective film 72 that covers the sheet material 41. The material of the protective film 72 is not particularly limited.

The softening point of the sheet material 41 is preferably 80°C or lower. In this case, when stacking the sheet material 41 on the semiconductor chip 3, the heating temperature at which the sheet material 41 is heated can be lowered so that the bump electrodes 31 of the semiconductor chip 3 are buried in the sheet material 41. That is, even if the temperature at which the sheet material 41 is heated is low, the sheet material 41 can be softened and deformed, and the bump electrodes 31 can be easily buried in the sheet material 41. In this embodiment, as described above, the composition (X) contains triallylisocyanurate (B), and the percentage of triallylisocyanurate (B) is 5% by mass with respect to the solid content of the composition (X). Since the content is 20% by mass or less, the softening point of the sheet material 41 can be reduced, and it can be realized that the softening point of the sheet material 41 is 80° C. or less. The softening point of the sheet material 41 is more preferably 40°C or lower, and even more preferably 35°C or lower. Further, the softening point of the sheet material 41 is, for example, 30° C. or higher. Note that a specific method for measuring the softening point of the sheet material 41 will be explained in the Examples section below.

The minimum melt viscosity of the sheet material 41 is preferably 2000 Pa·s or more and 50000 Pa·s or less. If the minimum melt viscosity is 2000 Pa·s or more, when the encapsulant is produced from the sheet material 41, the heated sheet material 41 flows moderately, so that the encapsulant 4 can bond the semiconductor chip 3 and the base material. 2 can be sufficiently sealed. Furthermore, if the minimum melt viscosity is 50,000 Pa·s or less, when the sealing material 4 is produced from the sheet material 41, the heated sheet material 41 will be difficult to flow excessively, and therefore the sealing material 4 will have cavities. is less likely to occur. In this embodiment, as described above, the composition (X) contains the thermoplastic elastomer (E), and the percentage ratio of the thermoplastic elastomer (E) is 5% by mass or more with respect to the solid content of the composition (X). % by mass or less, excessive flow when the sheet material 41 is heated is suppressed, and therefore, the minimum melt viscosity of the sheet material 41 can be realized to be 2000 Pa·s or more and 50000 Pa·s or less. The minimum melt viscosity of the sheet material 41 is more preferably 10,000 Pa·s or more, and even more preferably 30,000 Pa·s or more. Moreover, the minimum melt viscosity of the sheet material 41 is more preferably 43,000 Pa·s or less, and even more preferably 38,000 Pa·s or less. Note that a specific method for measuring the minimum melt viscosity of the sheet material 41 will be explained in the Examples section below.

FIG. 1 shows an example of a semiconductor device 1. This semiconductor device 1 includes a base material 2, a semiconductor chip 3 mounted face down on the base material 2, and a sealing material 4 that seals a gap between the base material 2 and the semiconductor chip 3. . The sealing material 4 is made of a cured product of composition (X). The semiconductor chip 3 has bump electrodes 31 on the surface facing the base material 2, and the base material 2 has conductor wiring 21 on the surface facing the semiconductor chip 3. Bump electrode 31 and conductor wiring 21 are electrically connected. Bump electrode 31 and conductor wiring 21 are buried in sealing material 4.

A method for manufacturing the sealing material 4 and a method for manufacturing the semiconductor device 1 will be described with reference to FIGS. 3A to 3D and FIGS. 4A to 4D.

When producing the sealing material 4 and manufacturing the semiconductor device 1, for example, the sheet material 41 is stacked on the surface of the semiconductor wafer 32 provided with the bump electrodes 31, on which the bump electrodes 31 are located. By cutting the semiconductor wafer 32 along with the sheet material 41, a chip member including the semiconductor chip 3 cut out from the semiconductor wafer 32 and the individual sheets 42 cut out from the sheet material 41 is produced. The base material 2, the individual sheets 42, and the semiconductor chip 3 are laminated in this order by overlapping the individual sheets 42 of the chip member on the surface of the base material 2 having the conductor wires 21, on which the conductor wires 21 are located.

By heating the individual sheet 42, the individual sheet 42 is cured, the sealing material 4 is produced, and the bump electrode 31 and the conductor wiring 21 are electrically connected. In this way, the semiconductor device 1 is manufactured.

The method for manufacturing the sealing material 4 and the method for manufacturing the semiconductor device 1 will be described in more detail.

For example, first, the laminated sheet 7, the semiconductor wafer 32, the support frame, the dicing tape 8, and the base material 2 are prepared.

The base material 2 is, for example, a mother board, a package board, or an interposer board. For example, the base material 2 includes an insulating substrate made of glass epoxy, polyimide, polyester, ceramic, etc., and conductor wiring 21 made of a conductor such as copper formed on the surface thereof.

The semiconductor wafer 32 is, for example, a silicon wafer. A conductor wiring 21 is formed on the semiconductor wafer 32 by an appropriate method such as photolithography, and a bump electrode 31 connected to the conductor wiring 21 is provided on one surface of the semiconductor wafer 32.

The support frame is a frame-shaped jig for fixing the semiconductor wafer 32, and is generally also called a wafer ring, dicing ring, or dicing frame. As shown in FIG. 3A, the dicing tape 8 is stretched on the support frame, and the semiconductor wafer 32 is attached to the dicing tape 8 on the side opposite to the bump electrodes 31, thereby fixing the semiconductor wafer 32 to the support frame. be done.

The bump electrodes 31 on the semiconductor wafer 32 include, for example, solder bumps 6. Note that the conductor wiring 21 on the base material 2 instead of the bump electrode 31 may be provided with the solder bump 6, or the bump electrode 31 and the conductor wiring 21 may each be provided with the solder bump 6. That is, at least one of the bump electrodes 31 on the semiconductor wafer 32 and the conductor wiring 21 on the base material 2 may be provided with the solder bumps 6. The solder bumps 6 are preferably Sn-3.5Ag (melting point 221°C), Sn-2.5Ag-0.5Cu-1Bi (melting point 214°C), Sn-0.7Cu (melting point 227°C), Sn-3Ag- It is made of lead-free solder with a melting point of 210° C. or higher, such as 0.5Cu (melting point 217° C.).

The protective film 72 is peeled off from the sheet material 41 in the laminated sheet 7, and while the sheet material 41 remains overlapped with the support sheet 71, the bump electrodes 31 on the semiconductor wafer 32 fixed to the support frame are removed, as shown in FIG. 3B. Lay it on a certain surface. At this time, the sheet material 41 is layered on the semiconductor wafer 32 while being softened by heating. As a result, the sheet material 41 is laminated onto the semiconductor wafer 32 while the bump electrodes 31 are embedded in the softened sheet material 41.

Since the dicing tape 8 generally has low heat resistance, the heating temperature when heating the sheet material 41 is preferably adjusted to a temperature at which the dicing tape 8 does not deteriorate due to heat. In this case, the state in which the semiconductor wafer 32 is supported by the support frame is maintained. The heating temperature is, for example, 40°C or higher and 80°C or lower, preferably 60°C or higher and 80°C or lower. In this embodiment, even if the heating temperature is relatively low, the softening points of the composition (X) and the sheet material 41 can be low, so that the sheet material 41 is sufficiently softened and bumps are formed on the sheet material 41. Electrodes 31 may be embedded. Subsequently, as shown in FIG. 3C, the support sheet 71 is peeled off from the semiconductor wafer 32.

Next, while the semiconductor wafer 32 remains supported by the support frame, the semiconductor wafer 32 is cut together with the sheet material 41 using a cutting tool such as a dicing saw. As a result, as shown in FIG. 3D, a member (hereinafter also referred to as a chip member) including a semiconductor chip 3 cut out from a semiconductor wafer 32 and a divided sheet material 41 (hereinafter also referred to as an individual sheet 42) Create. This chip member is removed from the dicing tape 8. The semiconductor chip 3 in the chip member includes bump electrodes 31, and the individual sheet 42 overlaps the surface of the semiconductor chip 3 where the bump electrodes 31 are located.

Next, the semiconductor chip 3 is mounted face down on the base material 2 with the individual sheet 42 interposed between the base material 2 and the semiconductor chip 3. For this purpose, for example, as shown in FIG. 4A, a flip chip bonder 50 including a bonding head 51 and a stage 52 is used. In this embodiment, as will be described later, when mounting the semiconductor chip 3 on the base material 2, ultrasonic vibration may be applied to the bump electrodes 31. In this case, for example, at least one of the bonding head 51 and the stage 52 is configured to apply ultrasonic vibration to the bump electrode 31. A specific example of the flip chip bonder 50 is a device such as FCB3 manufactured by Panasonic Corporation.

As shown in FIG. 4A, the base material 2 is supported by a stage 52, and the semiconductor chip 3 is held by a bonding head 51. At this time, the conductor wiring 21 of the base material 2 and the bump electrodes 31 of the semiconductor chip 3 are made to face each other. As shown in FIG. 4B, the bonding head 51 is moved toward the stage 52. As a result, the semiconductor chip 3 is placed on the base material 2, and the individual sheet 42 is interposed between the base material 2 and the semiconductor chip 3. At this time, the semiconductor chip 3 and the base material 2 are aligned so that the bump electrodes 31 on the semiconductor chip 3 and the conductor wiring 21 on the base material 2 overlap.

By heating the individual sheets 42 and the bump electrodes 31 through the bonding head 51 and the stage 52, the bump electrodes 31 and the conductor wiring 21 are electrically connected while the individual sheets 42 are made to flow. The temperature at which the individual sheets 42 and the bump electrodes are heated is, for example, 100° C. or more and 150° C. or less. The individual sheets 42 are allowed to flow and then harden, thereby producing the sealing material 4 as shown in FIG. 4C.

In this embodiment, even if the sheet material 41 (individual sheets 42) is heated, the sheet material 41 (individual sheets 42) does not flow excessively. Therefore, even if the sheet material 41 (individual sheets 42) is heated, the generation of cavities within the sheet material 41 (individual sheets 42) and the sealing material 4 can be suppressed.

When heating the individual sheets 42 and the bump electrodes 31, ultrasonic vibrations may be simultaneously applied to the bump electrodes 31 from at least one of the bonding head 51 and the stage 52. In this case, since the electrical connection between the bump electrodes 31 and the conductive wiring 21 is promoted by ultrasonic vibration, it is possible to reduce the temperature and heating time for heating the individual sheet 42 and the bump electrodes 31. Conditions such as the time and frequency of applying the ultrasonic waves are set as appropriate; for example, the time is 0.1 seconds or more and 5.0 seconds or less, and the frequency is 10 kHz or more and 80 kHz or less.

Further, when heating the individual sheets 42 and the bump electrodes 31, compressive pressure may be applied to the base material 2, the semiconductor chip 3, and the individual sheets 42 from the bonding head 51 and the stage 52 at the same time. In this case, the electrical connection between the bump electrode 31 and the conductor wiring 21 is promoted by the compressive pressure. The compression pressure is, for example, 10N or more and 200N or less.

Subsequently, as shown in FIG. 4D, the bonding head 51 is moved upward and separated from the semiconductor chip 3.

After the set of the base material 2 and the chip member is removed from the stage 52, if necessary, the sealing material 4 is further heated to advance curing of the sealing material 4.

As a result, the semiconductor device 1 including the base material 2, the chip component, and the sealing material 4 is manufactured.

1. Preparation of Composition The raw materials shown in the composition column of Table 1 were prepared. Of these raw materials, a first mixture was prepared by adding a thermoplastic elastomer to toluene. To this first mixture, methyl ethyl ketone, triallyl isocyanurate and polyphenylene ether resin were added to prepare a second mixture. A coupling agent and a flux are added to this second mixture to prepare a third mixture, an inorganic filler is added to this third mixture, these are stirred with a disper, and then a polymerization initiator is further added. , and these were mixed in a bead mill. A composition was thus prepared. The total concentration of methyl ethyl ketone and toluene in the composition was adjusted to 30% by mass or more and 50% by mass or less.

The details of the raw materials shown in the composition column in the table are as follows.
- Polyphenylene ether resin: a modified polyphenylene ether resin having the structure shown in the above formula (3), in which X in the formula (3) is a group (R is a methyl group) having the structure shown in the above formula (1), Manufactured by SABIC, product number SA9000.
- Inorganic filler #1: Silica, manufactured by Tokuyama Co., Ltd., product number NMH-24D, average particle size 0.24 μm.
- Inorganic filler #2: Silica, manufactured by Admatex Co., Ltd., product number SO-C2, average particle size 0.5 μm.
- Radical polymerization initiator: dicumyl peroxide, manufactured by NOF Corporation, product name Percmil D.
- Thermoplastic elastomer: Styrene elastomer, manufactured by Asahi Kasei Corporation, product name Tuftec H1041.
- Silane coupling agent: polyfunctional silane, manufactured by Shin-Etsu Chemical Co., Ltd., product number X-12-1050.
-Flux: Glutaric acid.

2. Preparation of sheet material A polyethylene terephthalate film was prepared as a support sheet. The composition was applied onto this support sheet using a comma coater, and then first heated at 80°C for 50 seconds, then heated at 110°C for 35 seconds, and finally heated at 130°C for 35 seconds. As a result, a sheet material having a thickness within the range of 300 to 350 μm was produced on the support sheet.

3. Evaluation Test (1) Softening Point and Minimum Melt Viscosity A circular measurement sample with a diameter of 25 mm was prepared by punching out the sheet material. This measurement sample was measured using a rotary rheometer (model number HR-2, manufactured by TA Instruments) at a temperature range of 25°C to 200°C, a heating rate of 5°C/min, a strain of 0.2, and a frequency of 1Hz. Measured under the following conditions. Based on the results, the temperature dependence of the loss coefficient tan δ and the temperature dependence of the viscosity were determined. The temperature at which the loss coefficient tan δ reached the maximum value was defined as the softening point, and the minimum value of the viscosity was defined as the lowest melt viscosity.

(2) Lamination property on wafer Walts TEG CC80 (7.3 mm x 7.3 mm x 100 μm) manufactured by WALTS was prepared as a semiconductor wafer. Note that the semiconductor wafer includes 1048 bump electrodes each having a Cu pillar with a height of 30 μm and a solder bump with a height of 15 μm thereon, and the pitch between adjacent solder bumps is 80 μm.

With the semiconductor wafer fixed to the support frame by the dicing tape, the sheet material was stacked on the surface of the semiconductor wafer provided with bump electrodes while being supported by the support sheet. In this state, while heating the sheet material to 70° C., a pressure of 0.1 MPa toward the semiconductor wafer was applied to the sheet material.

Subsequently, the sheet material was cut and the cross section was observed under a microscope to confirm the presence or absence of a cavity at the root of the bump electrode. As a result, the case where no cavity was confirmed at the base of the bump electrode was evaluated as "A", and the case where a cavity was confirmed was evaluated as "C".

(3) Void evaluation Prepare the same semiconductor wafer as in the case of “(2) Lamability to wafer” above, and apply sheet material to this semiconductor wafer in the same manner as in “(2) Lamability to wafer” above. layered.

After peeling off the support sheet from the sheet material, the sheet material is diced together with the silicon wafer using a dicing saw made by DISCO (product name: DFD6341), thereby separating the semiconductor chip and the divided sheet material (individual sheets). A chip member with dimensions of 7.3 mm x 7.3 mm x 100 μm was cut out.

Walts TEG IP80 (10 mm x 10 mm x 300 μm) manufactured by WALTS was prepared as a base material, and model number FCB3 manufactured by Panasonic Corporation was prepared as a flip chip bonder. While the stage of the flip chip bonder was heated, the base material was fixed on the stage.

The chip member is held in the bonding head of the flip chip bonder, and while the bonding head is heated, the bonding head is brought close to the stage, and while aligning the bump electrodes of the semiconductor chip and the conductor wiring of the base material, the chip member is placed on the base material. The individual sheets of the chip member were stacked on top of each other. The temperature of the stage was set at 145°C, the temperature of the bonding head was set at 115°C, and thereby the temperature of the sheet material was adjusted to 130°C. In this state, the flip chip bonder applied pressure to the semiconductor chip and applied ultrasonic vibration while applying a load to the semiconductor chip toward the base material. The pressure applied to the semiconductor chip is maintained at 10N for 0.1 seconds from the start of pressurization, then increased to 50N at 0.2 seconds after the start of pressurization, and then 10N from the start of pressurization. The pressure was maintained at 50N until 0 seconds had elapsed. Ultrasonic waves were applied to the semiconductor chip 0.5 seconds after the start of pressurization. The output of the ultrasonic wave reached 3 W when 0.6 seconds had elapsed from the start of pressurization, and was then maintained at 3 W until 1.0 seconds had elapsed. When 1.0 seconds had elapsed from the start of the pressurization, the pressurization was released and the bonding head was moved away from the stage.

Next, the set of base material and chip component is removed from the flip chip bonder, and the sheet material (individual sheet) for the chip component is cured by heating at 150°C for 1 hour, and the sealing material (underfill) is cured. ) was created. As a result, a semiconductor device for testing was obtained. Voids in the encapsulant in this semiconductor device were investigated using an ultrasonic flaw detector (SAT). As a result, "A" indicates that no voids with a diameter of 20 μm or more are found, "B" indicates that voids with a diameter of 20 μm or more are found and the number of voids is less than 20, and voids with a diameter of 20 μm or more are found. , and the number was 20 or more, it was evaluated as "C".

(4) Continuity Reliability Continuity between the base material and the semiconductor chip in the test semiconductor device manufactured in "(3) Void evaluation" above was confirmed. As a result, the case where normal conduction was confirmed was evaluated as "A", and the case where poor conduction was observed was evaluated as "C".

1 Semiconductor device 2 Base material 21 Conductor wiring 3 Semiconductor chip 31 Bump electrode 32 Semiconductor wafer 4 Sealing material 41 Sheet material 42 Individual sheet

Claims (8)

A sealing resin composition,
A polyphenylene ether resin (A) having a radically polymerizable substituent,
triallylisocyanurate (B),
Inorganic filler (C);
A radical polymerization initiator (D),
Contains a thermoplastic elastomer (E),
The percentage of the triallylisocyanurate (B) is 5% by mass or more and 20% by mass or less based on the solid content of the sealing resin composition,
The percentage of the thermoplastic elastomer (E) is 5% by mass or more and 18% by mass or less based on the solid content of the encapsulating resin composition.
Sealing resin composition. The percentage ratio of the polyphenylene ether resin (A) is 2% by mass or more and 18% by mass or less based on the solid content of the encapsulating resin composition.
The sealing resin composition according to claim 1. The sealing resin composition according to claim 1 or 2, or a semi-cured product of the sealing resin composition,
sheet material. The softening point is 80°C or less,
The sheet material according to claim 3. The minimum melt viscosity is 2000 Pa·s or more and 50000 Pa·s or less,
The sheet material according to claim 3. The minimum melt viscosity is 2000 Pa·s or more and 50000 Pa·s or less,
The sheet material according to claim 4. base material and
a semiconductor chip mounted face down on the base material;
a sealing material that seals a gap between the base material and the semiconductor chip;
The sealing material is made of a cured product of the sealing resin composition according to claim 1 or 2.
Semiconductor equipment. Layering the sheet material according to claim 3 on the surface of a semiconductor wafer including bump electrodes, on which the bump electrodes are located,
By cutting the semiconductor wafer together with the sheet material, a chip member including a semiconductor chip cut out from the semiconductor wafer and an individual sheet cut out from the sheet material,
The base material, the individual sheets, and the semiconductor chip are laminated in this order by stacking the individual sheets of the chip member on the surface where the conductor wiring is of a base material provided with conductor wiring,
The method includes heating the individual sheets to melt and harden the individual sheets to produce a sealing material, and electrically connecting the bump electrodes and the conductor wiring.
A method for manufacturing a semiconductor device.

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