JP2023152651A - Formal verification device and formal verification method - Google Patents

Abstract

To make a verification of a circuit carrying out repetition processing efficient, comparing to a conventional verification.SOLUTION: A formal verification device comprises: a first formal verification unit 102 that performs a plurality of verifications of a logic circuit corresponding to a circuit carrying out repetition processing on the basis of a plurality of post-divided assertions divided based on the number of times of repetitions of the repetition processing in the circuit; a first acceptance determination unit 103 that determines whether all of a plurality of verifications by the first formal verification unit 102 is accepted; a second formal verification unit 104 that, when it is determined by the first acceptance determination unit 103 that all of the plurality of verifications is accepted, verifies that the number of times of repetitions of the repetition processing in the circuit is a desired number of times thereof; a second acceptance determination unit 105 that determines whether the verification by the second formal verification unit 104 is accepted; and a notification unit 106 that, when it is determined by the first acceptance determination unit 103 that all of the plurality of verifications is not accepted, or when it is determined by the second acceptance determination unit 105 that the verification is not accepted, notify the outside of the effect.SELECTED DRAWING: Figure 1

Description

The present disclosure relates to a formal verification device and a formal verification method that verify a circuit that undergoes repeated processing.

As circuits to be developed become larger and more complex, the proportion of the verification process in the development process for the circuits is not small. In other words, low verification efficiency in the verification process leads to delays in the development process.

This verification process uses dynamic verification or static verification.
Here, in static verification, formal verification is generally used to confirm the correctness of the circuit. Formal verification is a method of analyzing circuits mathematically and logically and comprehensively verifying them.

The problem with this formal verification is that when the mathematical complexity of the circuit is high, state explosion occurs and it takes an unrealistic execution time to obtain verification results. This problem significantly reduces verification efficiency.

In contrast, a formal verification device is known that suppresses the occurrence of pseudo errors that occur during formal verification (for example, see Patent Document 1). Note that a pseudo error is an error caused by an abnormal operation or a lack of preconditions.
This formal verification device prepares dynamic verification results in advance, extracts input and output conditions for the verification target from the results, and applies them as constraints in formal verification. As a result, in this formal verification device, pseudo errors are suppressed, errors to be analyzed in formal verification can be efficiently detected, and the verification process can be shortened.

JP 2016-9232 Publication

As described above, with the conventional formal verification device, it is possible to shorten the verification process by suppressing pseudo errors. However, with this formal verification device, it is not possible to suppress the verification execution time for a circuit with a high degree of mathematical complexity such as a circuit that performs repeated processing. In other words, when formal verification is used to verify a circuit that performs repetitive processing, it is important to prevent state explosions. Note that an example of a circuit that performs the above-described repetitive processing is a DMA (Direct Memory Access) controller.

The present disclosure has been made to solve the above-mentioned problems, and aims to provide a formal verification device that can more efficiently verify a circuit that undergoes repeated processing compared to the conventional technology.

A formal verification device according to the present disclosure includes a logic circuit corresponding to a circuit that performs repetitive processing, and a plurality of assertions for the circuit based on assertions divided into multiple pieces based on the number of repetitions of the repetitive processing in the circuit. A first formal verification unit that performs verification; a first pass determination unit that determines whether all the multiple verifications by the first formal verification unit are passed; and a first pass determination unit that determines whether all of the multiple verifications by the first formal verification unit are If it is determined to pass, a second formal verification unit verifies that the number of repetitions of the repetitive processing in the circuit is the desired number of times, and determines whether the verification by the second formal verification unit has passed. If the second pass determination unit and the first pass determination unit determine that all of the multiple verifications are not passed, or if the second pass determination unit determines that the verifications are not passed, The present invention is characterized by comprising a notification section that notifies the outside of this fact.

According to the present disclosure, with the configuration as described above, it is possible to more efficiently verify a circuit that performs repetitive processing than in the past.

1 is a diagram illustrating a configuration example of a formal verification device according to a first embodiment; FIG. 5 is a flowchart illustrating an example of the operation of the formal verification device according to the first embodiment. 2 is a flowchart illustrating an example of the operation of the formal verification apparatus according to the first embodiment, in a case where the circuit to be verified is a DMA controller. 4A and 4B are diagrams showing an example of the hardware configuration of the formal verification device according to the first embodiment.

Hereinafter, embodiments will be described in detail with reference to the drawings.
Embodiment 1.
FIG. 1 is a diagram showing a configuration example of a formal verification device 1 according to the first embodiment.
The formal verification device 1 is a device that performs formal verification on a circuit to be verified. This formal verification device 1 can be used as a support device in the verification of LSI (Large Scale Integration) development, for example.
Note that the circuit targeted for verification by the formal verification device 1 according to the first embodiment is a circuit that performs repeated processing. Examples of circuits that perform repetitive processing include a DMA controller and a product-sum calculation circuit. The DMA controller is a circuit that repeats read processing and write processing as its basic operation. The product-sum calculation circuit is a circuit that repeats multiplication processing and addition processing as its basic operation.

As shown in FIG. 1, this formal verification device 1 includes a recording section 101, a first formal verification section 102, a first pass judgment section 103, a second formal verification section 104, a second pass judgment section 105, It includes a notification section 106 and a modification completion reception section 107. Further, the recording unit 101 includes a logic circuit recording unit 1011, an assertion recording unit 1012, and a verification result recording unit 1013, as shown in FIG.

The recording unit 101 records various types of information handled by the formal verification device 1.
Note that the recording unit 101 includes, for example, RAM (Random Access Memory), ROM (Read Only Memory), flash memory, EPROM (Erasable Programmable ROM), and EEPROM (Electrical EPROM). ), non-volatile or volatile semiconductor memory, This includes a magnetic disk, flexible disk, optical disk, compact disk, mini disk, DVD (Digital Versatile Disc), and the like.

The logic circuit recording unit 1011 records information indicating a logic circuit. This logic circuit corresponds to a circuit to be verified (a circuit that performs repeated processing). Note that the information indicating the logic circuit recorded in the logic circuit recording section 1011 can be modified as appropriate by the user.

The assertion recording unit 1012 records information indicating a plurality of assertions for the logic circuit. Assertions are used to enable verification of a circuit to be verified. Note that the assertions used in the formal verification device 1 according to the first embodiment include assertions that are divided into a plurality of parts based on the number of repetitions of repetitive processing in the circuit to be verified (post-division assertions), and This is an assertion (pre-division assertion) for verifying that the number of repetitions of repetitive processing in the circuit is the desired number of times. Note that the information indicating the plurality of assertions recorded in the assertion recording unit 1012 can be modified as appropriate by the user.

Here, for example, if the circuit to be verified is a DMA controller, the assertion divided into multiple parts is the verification related to the operation before the number of repetitions of read processing and write processing reaches the desired number of times (first verification). ), assertions that enable verification of operations after the number of repetitions of read processing and write processing reaches a desired number (second verification), and number of repetitions of read processing and write processing. This is an assertion that enables verification (third verification) related to the operation when a desired number of times has been reached.

For example, if the circuit to be verified is a product-sum operation circuit, the assertion divided into multiple parts may be used for verification (first Assertion that enables verification (second verification) related to the operation after the number of repetitions of multiplication processing and addition processing reaches a desired number of times, and repetition of multiplication processing and addition processing This is an assertion that enables verification (third verification) related to the operation when the number of times reaches a desired number of times.

The verification result recording unit 1013 records information indicating the verification result by the first formal verification unit 102.

Further, FIG. 1 shows a case where the logic circuit recording section 1011, the assertion recording section 1012, and the verification result recording section 1013 are provided inside the formal verification device 1. However, the present invention is not limited thereto, and some or all of the logic circuit recording section 1011, the assertion recording section 1012, and the verification result recording section 1013 may be provided outside the formal verification device 1.

The first formal verification unit 102 performs verification based on the logic circuit indicated by the information recorded in the logic circuit recording unit 1011 and the plurality of assertions (post-division assertions) indicated by the information recorded in the assertion recording unit 1012. , multiple verifications are performed on the circuit to be verified. That is, the first formal verification unit 102 inputs a plurality of assertions into the logic circuit, respectively, thereby performing verification divided into a plurality of parts based on the number of repetitions of the repetition process in the circuit to be verified.
Information indicating the verification result by the first formal verification section 102 is recorded in the verification result recording section 1013.

The first formal verification unit 102 also receives a modification completion notification, which is a notification that the modification of the assertion has been completed, or a modification completion notification, which is a notification that the modification of the logic circuit has been completed, by the modification completion reception unit 107. If accepted, the above multiple verifications will be performed again.

Here, for example, if the circuit to be verified is a DMA controller, the first formal verification unit 102 performs verification divided into a plurality of parts based on the number of repetitions of read processing and write processing in this DMA controller. .
More specifically, the first formal verification unit 102 performs verification (first verification) related to the operation before the number of repetitions of read processing and write processing reaches a desired number of times, and the number of repetitions of read processing and write processing. Verification related to the operation after reaching the desired number of times (second verification), and verification related to the operation when the number of repetitions of read processing and write processing reaches the desired number of times (third verification) Do each.

For example, when the circuit to be verified is a product-sum calculation circuit, the first formal verification unit 102 performs verification divided into multiple parts based on the number of times the multiplication process and the addition process are repeated in this product-sum calculation circuit. Do each.
More specifically, the first formal verification unit 102 performs verification (first verification) related to the operation before the number of repetitions of multiplication processing and addition processing reaches a desired number of times, and the number of repetitions of multiplication processing and addition processing. Verification related to the operation after reaching the desired number of times (second verification), and verification related to the operation when the number of repetitions of multiplication processing and addition processing reaches the desired number of times (third verification) Do each.

In this case, as a first verification, the first formal verification unit 102 verifies that the series of read processing and write processing is continuous before the number of repetitions reaches a desired number of times.
Further, as a second verification, the first formal verification unit 102 verifies that a series of processes of read processing and write processing does not occur after the number of repetitions reaches a desired number of times.
In addition, as a third verification, the first formal verification unit 102 determines that when the number of repetitions reaches a desired number, the number of repetitions of read processing and write processing for ((desired number of repetitions - 1)) has occurred. When a read process and a write process occur next), only the last read process and write process are extracted and their validity is verified.

The first pass determination unit 103 determines whether all of the multiple verifications by the first formal verification unit 102 have passed.

When the first pass determination unit 103 determines that all of the multiple verifications have passed, the second formal verification unit 104 verifies that the number of repetitions of the repetitive process in the circuit to be verified is the desired number of times. Verify (fourth verification). At this time, the second formal verification unit 104 reads information indicating the verification result recorded in the verification result recording unit 1013 based on the assertion (pre-division assertion) indicated by the information recorded in the assertion recording unit 1012. The above verification is performed by reading.

Here, for example, when the circuit to be verified is a DMA controller, the second formal verification unit 104 performs a fourth verification to determine whether the number of repetitions of read processing and write processing in this DMA controller is a desired number of times. Verify that.

For example, when the circuit to be verified is a product-sum calculation circuit, the second formal verification unit 104 performs fourth verification to determine whether the number of repetitions of multiplication processing and addition processing in this product-sum calculation circuit is a desired number. Verify that it is the number of times.

The second pass determination unit 105 determines whether the verification by the second formal verification unit 104 is successful.

If the first pass determination unit 103 determines that all of the multiple verifications are not passed, or if the second pass determination unit 105 determines that the verifications are not passed, the notification unit 106 Notify the outside party.

Thereafter, the user who has received the notification from the notification unit 106 determines whether a problem has occurred in the assertion indicated by the information recorded in the assertion recording unit 1012.
Here, if the user determines that a problem has occurred in the assertion, the user corrects the assertion. Then, the assertion recording unit 1012 updates the recorded information indicating the assertion to information indicating the modified assertion.
On the other hand, if the user determines that there is no problem with the assertion, the user modifies the logic circuit. Then, the logic circuit recording unit 1011 updates the recorded information indicating the logic circuit to information indicating the corrected logic circuit.

The modification completion reception unit 107 receives from the user a modification completion notification that is a notification indicating that modification of an assertion is completed, or a modification completion notification that is a notification that indicates completion of modification of a logic circuit.

Next, an example of the operation of the formal verification device 1 according to the first embodiment shown in FIG. 1 will be described with reference to FIG. 2.
Note that the logic circuit recording unit 1011 records information indicating a logic circuit corresponding to the circuit to be verified. Furthermore, the assertion recording unit 1012 records a plurality of assertions for the logic circuit. The plurality of assertions indicated by the information recorded in the assertion recording unit 1012 are assertions divided into a plurality of parts based on the number of repetitions of the repetitive process in the circuit to be verified (split assertions), and assertions to be verified. This is an assertion (pre-division assertion) for verifying that the number of repetitions of repetitive processing in the circuit is the desired number of times.

In the operation example of the formal verification device 1 according to the first embodiment shown in FIG. 1, as shown in FIG. Based on the logic circuit and the plurality of assertions (post-division assertions) indicated by the information recorded in the assertion recording unit 1012, a plurality of verifications are performed on the circuit to be verified (step ST201). That is, the first formal verification unit 102 inputs a plurality of assertions into the logic circuit, respectively, thereby performing verification divided into a plurality of parts based on the number of repetitions of the repetition process in the circuit to be verified.

Note that the order of each verification in the first formal verification unit 102 is not critical, and may be performed in any order. Further, each verification in the first formal verification unit 102 may be performed independently or in parallel.

Note that information indicating the verification result by the first formal verification section 102 is recorded in the verification result recording section 1013. That is, the verification result recording unit 1013 records information indicating the results of a plurality of divided verifications.

Next, the first pass determination section 103 determines whether all of the plurality of verifications by the first formal verification section 102 are passed (step ST202).

In step ST202, when the first pass determination unit 103 determines that all of the multiple verifications have passed, the second formal verification unit 104 determines that the number of repetitions of the repetitive process in the circuit to be verified is a desired number of times. (Step ST203). At this time, the second formal verification unit 104 reads information indicating the verification result recorded in the verification result recording unit 1013 based on the assertion (pre-division assertion) indicated by the information recorded in the assertion recording unit 1012. The above verification is performed by reading.

In this way, the second formal verification unit 104 reads out the information indicating the verification results recorded in the verification result recording unit 1013 and performs the above verification, thereby reducing the mathematical complexity accordingly. It becomes possible.

Next, the second pass determination section 105 determines whether the verification by the second formal verification section 104 is passed (step ST204).

In this step ST204, when the second pass determination section 105 determines that the verification is passed, the sequence ends.

On the other hand, in step ST202, if the first pass determination section 103 determines that all of the multiple verifications are not passed, or in step ST204, the second pass determination section 105 determines that the verifications are not passed. If so, the notification unit 106 notifies the outside of that (step ST205).

Thereafter, the user who has received the notification from the notification unit 106 determines whether a problem has occurred in the assertion indicated by the information recorded in the assertion recording unit 1012.
Here, if the user determines that a problem has occurred in the assertion, the user corrects the assertion. Then, the assertion recording unit 1012 updates the recorded information indicating the assertion to information indicating the modified assertion.
On the other hand, if the user determines that there is no problem with the assertion, the user modifies the logic circuit. Then, the logic circuit recording unit 1011 updates the recorded information indicating the logic circuit to information indicating the corrected logic circuit.

Next, the modification completion reception unit 107 receives from the user a modification completion notification which is a notification indicating completion of modification of an assertion or a notification indicating completion of modification of a logic circuit (step ST206).
After that, the sequence returns to step ST201. Then, the first formal verification unit 102 performs the plurality of verifications described above again.

In this manner, the formal verification device 1 according to the first embodiment performs multiple verifications divided based on the number of repetitions of the repetitive processing in the circuit in formal verification of the circuit to be verified, and then Verify that the number is the desired number.
As a result, the formal verification device 1 according to the first embodiment can decompose and simplify the elements included in the circuit to be verified, and reduce the mathematical complexity, compared to the conventional method. As a result, the formal verification device 1 according to the first embodiment can suppress state explosion in formal verification and suppress verification execution time compared to the conventional method.

Next, an example of the operation of the formal verification apparatus 1 according to the first embodiment shown in FIG. 1 when the circuit to be verified is a DMA controller will be described with reference to FIG. 3.
Note that the logic circuit recording unit 1011 records information indicating a logic circuit corresponding to a DMA controller. Further, the assertion recording unit 1012 records information indicating a plurality of assertions. The plurality of assertions indicated by the information recorded in the assertion recording unit 1012 are assertions divided into three parts based on the number of repetitions of read processing and write processing in the DMA controller (post-division assertions), and assertions to be verified. This is an assertion (pre-division assertion) for verifying that the number of repetitions of repetitive processing in the circuit is the desired number of times.

In the operation example of the formal verification device 1 according to the first embodiment shown in FIG. 1 in the case where the circuit to be verified is a DMA controller, as shown in FIG. , based on the logic circuit indicated by the information recorded in the logic circuit recording section 1011 and the plurality of assertions (post-division assertions) indicated by the information recorded in the assertion recording section 1012. Verification (first verification, second verification, and third verification) is performed (step ST301). That is, the first formal verification unit 102 performs verification divided into three parts based on the number of repetitions of read processing and write processing in the DMA controller by respectively inputting three assertions to the logic circuit.

That is, as a first verification, the first formal verification unit 102 verifies that the series of read processing and write processing is continuous before the number of repetitions reaches a desired number of times.
Further, as a second verification, the first formal verification unit 102 verifies that a series of processes of read processing and write processing does not occur after the number of repetitions reaches a desired number of times.
In addition, as a third verification, the first formal verification unit 102 determines that when the number of repetitions reaches a desired number, the number of repetitions of read processing and write processing for ((desired number of repetitions - 1)) has occurred. When a read process and a write process occur next), only the last read process and write process are extracted and their validity is verified.

Note that the order of each verification in the first formal verification unit 102 is not critical, and may be performed in any order. Further, each verification in the first formal verification unit 102 may be performed independently or in parallel.

Then, information indicating the verification result by the first formal verification section 102 is recorded in the verification result recording section 1013. That is, the verification result recording unit 1013 stores information indicating the results of verification related to the operation before the number of repetitions reaches the desired number, and information indicating the results of verification related to the operation after the number of repetitions reaches the desired number. , and information indicating the result of verification related to the operation when the number of repetitions reaches a desired number of times are respectively recorded.

Next, the first pass determination section 103 determines whether all of the plurality of verifications by the first formal verification section 102 are passed (step ST302).

In this step ST302, when the first pass determination unit 103 determines that all of the plurality of verifications have passed, the second formal verification unit 104 determines that the number of repetitions of read processing and write processing in the DMA controller is a desired number of times. is verified (fourth verification) (step ST303). At this time, the second formal verification unit 104 reads information indicating the verification result recorded in the verification result recording unit 1013 based on the assertion (pre-division assertion) indicated by the information recorded in the assertion recording unit 1012. The above verification is performed by reading.

In this way, the second formal verification unit 104 reads out the information indicating the verification results recorded in the verification result recording unit 1013 and performs the above verification, thereby reducing the mathematical complexity accordingly. It becomes possible.

Next, the second pass determination section 105 determines whether the verification by the second formal verification section 104 is passed (step ST304).

In this step ST304, when the second pass determination section 105 determines that the verification is passed, the sequence ends.

On the other hand, in step ST302, if the first pass determination unit 103 determines that all of the multiple verifications are not passed, or in step ST304, the second pass determination unit 105 determines that the verifications are not passed. If so, the notification unit 106 notifies the outside to that effect (step ST305).

Thereafter, the user who has received the notification from the notification unit 106 determines whether a problem has occurred in the assertion indicated by the information recorded in the assertion recording unit 1012.
Here, if the user determines that a problem has occurred in the assertion, the user corrects the assertion. Then, the assertion recording unit 1012 updates the recorded information indicating the assertion to information indicating the modified assertion.
On the other hand, if the user determines that there is no problem with the assertion, the user modifies the logic circuit. Then, the logic circuit recording unit 1011 updates the recorded information indicating the logic circuit to information indicating the corrected logic circuit.

Next, the modification completion reception unit 107 receives from the user a modification completion notification which is a notification indicating completion of modification of an assertion or a notification indicating completion of modification of a logic circuit (step ST306).
After that, the sequence returns to step ST301. Then, the first formal verification unit 102 performs the plurality of verifications described above again.

In this way, in the formal verification device 1 according to the first embodiment, in formal verification of a DMA controller, a plurality of verifications (first verification, first verification, (second verification and third verification), and then verify that the number of repetitions is the desired number (fourth verification).
As a result, in the formal verification device 1 according to the first embodiment, the elements included in the DMA controller can be decomposed and simplified, and the mathematical complexity can be reduced compared to the conventional method. As a result, the formal verification device 1 according to the first embodiment can suppress state explosion in formal verification of a DMA controller, and can reduce verification execution time, compared to the conventional method.

Next, an example of the operation of the formal verification device 1 according to the first embodiment shown in FIG. 1 when the circuit to be verified is a product-sum operation circuit will be described with reference to FIG. 3.
Note that the logic circuit recording unit 1011 records information indicating a logic circuit corresponding to a product-sum operation circuit. Further, the assertion recording unit 1012 records information indicating a plurality of assertions. The plurality of assertions indicated by the information recorded in the assertion recording unit 1012 include assertions that are divided into three parts based on the number of repetitions of multiplication processing and addition processing in the product-sum operation circuit (split assertions), and verification target assertions. This is an assertion (pre-division assertion) for verifying that the number of repetitions of repetitive processing in a circuit is a desired number.

In the operation example of the formal verification device 1 according to the first embodiment shown in FIG. 1 when the circuit to be verified is a product-sum calculation circuit, as shown in FIG. 102 is a product-sum calculation circuit based on the logic circuit indicated by the information recorded in the logic circuit recording unit 1011 and the plurality of assertions (post-division assertions) indicated by the information recorded in the assertion recording unit 1012. A plurality of verifications (first verification, second verification, and third verification) are performed (step ST301). That is, the first formal verification unit 102 performs verification divided into three parts based on the number of repetitions of multiplication processing and addition processing in the product-sum calculation circuit by inputting three assertions into the logic circuit. .

That is, as a first verification, the first formal verification unit 102 verifies that the series of multiplication processing and addition processing is continuous before the number of repetitions reaches a desired number of times.
Furthermore, as a second verification, the first formal verification unit 102 verifies that the series of multiplication processing and addition processing does not occur after the number of repetitions reaches a desired number of times.
In addition, as a third verification, the first formal verification unit 102 determines that when the number of repetitions reaches a desired number of times, the number of repetitions of multiplication processing and addition processing for ((desired number of repetitions - 1)) has occurred. When a multiplication process and an addition process occur next), only the last multiplication process and addition process are extracted and their validity is verified.

Note that the order of each verification in the first formal verification unit 102 is not critical, and may be performed in any order. Further, each verification in the first formal verification unit 102 may be performed independently or in parallel.

Then, information indicating the verification result by the first formal verification section 102 is recorded in the verification result recording section 1013. That is, the verification result recording unit 1013 stores information indicating the results of verification related to the operation before the number of repetitions reaches the desired number, and information indicating the results of verification related to the operation after the number of repetitions reaches the desired number. , and information indicating the result of verification related to the operation when the number of repetitions reaches a desired number of times are respectively recorded.

Next, the first pass determination section 103 determines whether all of the plurality of verifications by the first formal verification section 102 are passed (step ST302).

In this step ST302, if the first pass determination section 103 determines that all of the plurality of verifications have passed, the second formal verification section 104 determines that the number of repetitions of the multiplication process and the addition process in the product-sum calculation circuit is the desired number. (fourth verification) (step ST303). At this time, the second formal verification unit 104 reads information indicating the verification result recorded in the verification result recording unit 1013 based on the assertion (pre-division assertion) indicated by the information recorded in the assertion recording unit 1012. The above verification is performed by reading.

In this way, the second formal verification unit 104 reads out the information indicating the verification results recorded in the verification result recording unit 1013 and performs the above verification, thereby reducing the mathematical complexity accordingly. It becomes possible.

Next, the second pass determination section 105 determines whether the verification by the second formal verification section 104 is passed (step ST304).

In this step ST304, when the second pass determination section 105 determines that the verification is passed, the sequence ends.

On the other hand, in step ST302, if the first pass determination unit 103 determines that all of the multiple verifications are not passed, or in step ST304, the second pass determination unit 105 determines that the verifications are not passed. If so, the notification unit 106 notifies the outside to that effect (step ST305).

Thereafter, the user who has received the notification from the notification unit 106 determines whether a problem has occurred in the assertion indicated by the information recorded in the assertion recording unit 1012.
Here, if the user determines that a problem has occurred in the assertion, the user corrects the assertion. Then, the assertion recording unit 1012 updates the recorded information indicating the assertion to information indicating the modified assertion.
On the other hand, if the user determines that there is no problem with the assertion, the user modifies the logic circuit. Then, the logic circuit recording unit 1011 updates the recorded information indicating the logic circuit to information indicating the corrected logic circuit.

Next, the modification completion reception unit 107 receives from the user a modification completion notification which is a notification indicating completion of modification of an assertion or a notification indicating completion of modification of a logic circuit (step ST306).
After that, the sequence returns to step ST301. Then, the first formal verification unit 102 performs the plurality of verifications described above again.

In this manner, the formal verification device 1 according to the first embodiment performs formal verification of a product-sum calculation circuit by performing multiple verifications (verifications) divided based on the number of times the multiplication process and addition process are repeated in the product-sum calculation circuit. 1, second verification, and third verification), and then verify that the number of repetitions is the desired number (fourth verification).
As a result, in the formal verification device 1 according to the first embodiment, the elements included in the product-sum calculation circuit can be decomposed and simplified, and the mathematical complexity can be reduced compared to the conventional method. As a result, the formal verification device 1 according to the first embodiment can suppress state explosion in formal verification of a product-sum operation circuit, and can reduce verification execution time, compared to the conventional method.

As described above, according to the first embodiment, the formal verification device 1 includes a logic circuit corresponding to a circuit that performs repetitive processing, and an assertion divided into a plurality of parts based on the number of repetitions of the repetitive processing in the circuit. a first formal verification unit 102 that performs multiple verifications on the circuit based on the above, and a first pass determination unit 103 that determines whether all of the multiple verifications by the first formal verification unit 102 are passed. and a second formal verification unit 104 that verifies that the number of repetitions of the repetitive processing in the circuit is a desired number of times when the first pass determination unit 103 determines that all of the plurality of verifications are passed; When the second pass determination unit 105 determines whether the verification by the second formal verification unit 104 passes, and the first pass determination unit 103 determines that all of the multiple verifications are not passed, or , and a notification unit 106 that notifies the outside when the second pass determination unit 105 determines that the verification is not passed. As a result, the formal verification device 1 according to the first embodiment can more efficiently verify a circuit that undergoes repeated processing than in the past. As a result, the formal verification apparatus 1 according to the first embodiment can shorten the verification process for a circuit to be verified compared to the conventional method.

Finally, with reference to FIG. 4, an example of the hardware configuration of the formal verification device 1 according to the first embodiment will be described.
Each of the first formal verification section 102, first pass judgment section 103, second formal verification section 104, second pass judgment section 105, notification section 106, and correction completion reception section 107 in the formal verification device 1 The functions are realized by processing circuit 501. The processing circuit 501 may be dedicated hardware as shown in FIG. 4A, or may be a CPU (Central Processing Unit) that executes a program stored in the memory 503, as shown in FIG. 4B. It may be a processing device, an arithmetic device, a microprocessor, a microcomputer, a processor, or a DSP (Digital Signal Processor)) 502.

When the processing circuit 501 is dedicated hardware, the processing circuit 501 is, for example, a single circuit, a composite circuit, a programmed processor, a parallel programmed processor, an ASIC (Application Specific Integrated Circuit), or an FPGA (Field Programmable Gate). Array), or a combination of these. Processes the functions of the first formal verification section 102, first pass judgment section 103, second formal verification section 104, second pass judgment section 105, notification section 106, and correction completion reception section 107, respectively. It may be realized by the circuit 501, or the functions of each part may be realized by the processing circuit 501.

When the processing circuit 501 is the CPU 502, the first formal verification section 102, the first pass judgment section 103, the second formal verification section 104, the second pass judgment section 105, the notification section 106, and the correction completion reception section. The functions of 107 are realized by software, firmware, or a combination of software and firmware. Software and firmware are written as programs and stored in memory 503. The processing circuit 501 realizes the functions of each section by reading and executing programs stored in the memory 503. That is, the formal verification device 1 includes a memory 503 for storing a program that, when executed by the processing circuit 501, results in each step shown in, for example, FIGS. 2 and 3 being executed. Additionally, these programs include a first formal verification section 102, a first pass judgment section 103, a second formal verification section 104, a second pass judgment section 105, a notification section 106, and a modification completion reception section 107. It can also be said that it allows a computer to execute the procedures and methods. Here, the memory 503 includes, for example, RAM (Random Access Memory), ROM (Read Only Memory), flash memory, EPROM (Erasable Programmable ROM), and EEPROM (Electrically EPROM). non-volatile or volatile semiconductor memory, such as This includes a magnetic disk, flexible disk, optical disk, compact disk, mini disk, DVD (Digital Versatile Disc), and the like.

Note that regarding each function of the first formal verification section 102, first pass judgment section 103, second formal verification section 104, second pass judgment section 105, notification section 106, and correction completion reception section 107, A portion may be realized by dedicated hardware, and a portion may be realized by software or firmware. For example, the function of the first formal verification section 102 is realized by a processing circuit 501 as dedicated hardware, and the first pass judgment section 103, the second formal verification section 104, and the second pass judgment section 105 , the notification unit 106, and the modification completion reception unit 107 can realize their functions by having the processing circuit 501 read and execute a program stored in the memory 503.

In this way, the processing circuit 501 can implement each of the above functions using hardware, software, firmware, or a combination thereof.

Note that it is possible to modify any component of the embodiment or omit any component of the embodiment.

1 formal verification device, 101 recording section, 102 first formal verification section, 103 first pass judgment section, 104 second formal verification section, 105 second pass judgment section, 106 notification section, 107 correction completion reception section , 501 processing circuit, 502 CPU, 503 memory, 1011 logic circuit recording section, 1012 assertion recording section, 1013 verification result recording section.

Claims (6)

A logic circuit corresponding to a circuit that performs repetitive processing, and a first formal verification unit that performs multiple verifications on the circuit based on assertions that are divided into multiple parts based on the number of repetitions of the repetitive processing in the circuit. and,
a first pass determination unit that determines whether all of the plurality of verifications by the first formal verification unit are passed;
a second formal verification unit that verifies that the number of repetitions of the repetitive processing in the circuit is a desired number of times when the first pass determination unit determines that all of the plurality of verifications are passed;
a second pass determination unit that determines whether the verification by the second formal verification unit is successful;
If the first pass determination unit determines that all of the multiple verifications are not passed, or if the second pass determination unit determines that the verification is not passed, notify external parties to that effect. A formal verification device with a notification section and . the circuit is a DMA controller;
The formal verification device according to claim 1, wherein the repeated processing in the circuit is read processing and write processing in the DMA controller. The first formal verification unit is concerned with verification related to operations before the number of repetitions of read processing and write processing reaches a desired number of times, and related to operations after the number of repetitions of read processing and write processing reaches a desired number of times. 3. The formal verification device according to claim 2, wherein the formal verification device performs verification and verification related to the operation when the number of repetitions of read processing and write processing reaches a desired number of times. The circuit is a product-sum calculation circuit,
The formal verification device according to claim 1, wherein the repetitive processing in the circuit is multiplication processing and addition processing in the product-sum calculation circuit. The first formal verification unit is concerned with verification related to operations before the number of repetitions of multiplication processing and addition processing reaches a desired number of times, and related to operations after the number of repetitions of multiplication processing and addition processing reaches a desired number of times. 5. The formal verification device according to claim 4, wherein the formal verification device performs verification and verification related to the operation when the number of repetitions of multiplication processing and addition processing reaches a desired number of times. The first formal verification unit performs multiple verifications on the circuit based on a logic circuit corresponding to a circuit that performs repetitive processing and assertions divided into multiple parts based on the number of repetitions of the repetitive processing in the circuit. and the steps to
a step in which a first pass determination unit determines whether all of the plurality of verifications by the first formal verification unit are passed;
a second formal verification section, when the first pass determination section determines that all of the plurality of verifications are passed, verifying that the number of repetitions of the repetitive processing in the circuit is a desired number; ,
a second pass determination unit determining whether the verification by the second formal verification unit is successful;
If the first pass determination unit determines that all of the multiple verifications are not passed, or if the second pass determination unit determines that the verifications are not passed, the notification unit shall notify the notification to that effect. A formal verification method comprising a step of notifying an external party.

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