JP2023152646A - Arithmetic processing unit and arithmetic processing method - Google Patents

Abstract

To reduce a circuit scale of an arithmetic processing unit that concurrently executes in turn from executable instructions of a plurality of instructions.SOLUTION: An arithmetic processing unit that concurrently executes in turn from executable instructions of a plurality of instructions comprises: a queue 105a that stores the plurality of instructions; a pipeline in which dependent source instructions of the plurality of instructions are executed; and a control section 105 that holds an index indicating an execution stage of the dependent source instruction in the pipeline, performs data dependent resolution of the dependent source instructions of the plurality of instructions and dependent destination instructions utilizing execution results of the dependent source instructions, and controls issue timing of the plurality of instructions.SELECTED DRAWING: Figure 9

Description

The present invention relates to an arithmetic processing device and an arithmetic processing method.

Improving the performance of the microarchitecture in the core of an arithmetic processing unit (processor core) means improving IPC (Instruction Per Cycle) in the same operating frequency band. Superscalar and out-of-order (OoO) execution are used as architectures for improving IPC.

A superscalar processor includes a plurality of pipelines including arithmetic units such as ALUs (Arithmetic Logic Units) and executes the number of instructions in one cycle.

Out-of-order execution is a method in which a processor executes executable instructions among a plurality of dispatched instructions in parallel (out-of-order). Executable instructions include, for example, instructions that have no dependence with other instructions or whose dependencies have been resolved, or instructions that can be assigned to the hardware to be used.

A processor capable of out-of-order execution includes a scheduler for detecting executable instructions and issuing the detected instructions to a pipeline. For example, the scheduler includes a comparator for each pipeline that determines whether or not the instruction dependency resolution timing is reached (whether or not the instruction is executable).

Japanese Patent Application Publication No. 10-078872 Japanese Patent Application Publication No. 2015-232902

In a processor that supports out-of-order execution, as the number of instructions that can be issued out-of-order (inflight instruction width) increases, the number of scheduler entries increases and the circuit scale of the comparator also increases. Furthermore, when the number of pipelines doubles, the number of comparators also doubles.

In this way, it may become difficult to simultaneously improve IPC by increasing the functionality of the processor core and reduce the circuit scale of the processor core (in other words, increase integration).

In one aspect, one of the objects of the present invention is to reduce the circuit scale of an arithmetic processing device that sequentially executes executable instructions among a plurality of instructions in parallel.

In one aspect, the arithmetic processing device is an arithmetic processing device that executes executable instructions among a plurality of instructions in parallel in order, and may include a queue and a control unit. The queue may store the plurality of instructions. The control unit retains an index indicating a pipeline in which a dependent instruction among the plurality of instructions is executed and an execution stage of the dependent instruction in the pipeline, and The issue timing of the plurality of instructions may be controlled by performing data dependency resolution between a dependent instruction and a dependent instruction that uses an execution result of the dependent instruction.

In one aspect, it is possible to reduce the circuit scale of an arithmetic processing device that sequentially executes executable instructions among a plurality of instructions in parallel.

1 is a block diagram illustrating a configuration example of a processor according to an embodiment. FIG. FIG. 2 is a block diagram illustrating a configuration example of a scheduler according to a comparative example. FIG. 3 is a diagram illustrating an example of pipeline stages and an example of data forwarding according to latency. FIG. 3 is a diagram illustrating a configuration example of a core of a processor according to a comparative example. FIG. 7 is a block diagram illustrating a configuration example of a dependency resolution determination unit according to a comparative example. FIG. 2 is a block diagram illustrating a configuration example of a scheduler according to an embodiment. It is a figure showing an example of pipeline stage information. FIG. 2 is a block diagram illustrating a configuration example of a dependency resolution determination unit according to an embodiment. FIG. 2 is a diagram illustrating a configuration example of a part of a core of a processor according to an embodiment. FIG. 9 is a diagram illustrating an example of a circuit configuration of a dependency resolution determining section illustrated in FIG. 8; FIG. 3 is a diagram for explaining an example of allocation of pipeline stage information. FIG. 7 is a diagram illustrating an example of forwarding timing determination according to a comparative example. FIG. 3 is a diagram illustrating an example of forwarding timing determination according to an embodiment. FIG. 7 is a diagram showing a determination example when there are two shortest forwarding timings according to a comparative example. FIG. 7 is a diagram illustrating an example of determination when there are two shortest forwarding timings according to an embodiment. FIG. 7 is a diagram illustrating a configuration example focusing on a process of canceling a subsequent instruction in a dependency chain dependent on a cache-missed load in a core configuration of a processor according to a comparative example. FIG. 7 is a diagram illustrating an example of determination in a process of canceling a subsequent instruction in a dependency chain that depends on a load that causes a cache miss according to a comparative example. FIG. 7 is a diagram showing an example of an arithmetic pipe advance load timing signal when there is one load pipe. FIG. 3 is a diagram for explaining an example of pipeline stage information allocation according to an embodiment. FIG. 3 is a diagram illustrating an example of a configuration for canceling a subsequent instruction in a dependency chain that depends on a cache-missed load in a core configuration of a processor according to an embodiment; FIG. 6 is a diagram illustrating an example of determination in a process of canceling a subsequent instruction in a dependency chain that depends on a load that has caused a cache miss according to an embodiment; FIG. 7 is a diagram illustrating a configuration example focusing on CF (Condition Flag) update control in a core configuration of a processor according to a comparative example. FIG. 7 is a diagram illustrating an example of determination of CF update control according to a comparative example. FIG. 2 is a diagram illustrating a configuration example focusing on CF update control in a core configuration of a processor according to an embodiment. FIG. 3 is a diagram illustrating an example of determination of CF update control according to an embodiment.

Embodiments of the present invention will be described below with reference to the drawings. However, the embodiments described below are merely examples, and there is no intention to exclude the application of various modifications and techniques not specified below. For example, this embodiment can be modified and implemented in various ways without departing from the spirit thereof. In the drawings used in the following description, parts with the same reference numerals represent the same or similar parts unless otherwise specified.

[1] One Embodiment [1-1] Configuration Example of Processor FIG. 1 is a block diagram showing a configuration example of a processor 1 according to one embodiment. For simplicity, FIG. 1 illustrates a part of the circuit configuration in the core of the processor 1. As shown in FIG.

The processor 1 is an example of an arithmetic processing device such as a CPU (Central Processing Unit) that executes executable instructions among a plurality of instructions in parallel. For example, the processor 1 may be a superscalar processor that supports out-of-order execution, which is an example of processing in which executable instructions among a plurality of instructions are executed in parallel.

As shown in FIG. 1, the processor 1 may include an instruction fetch control PC (Program Counter) 101, an instruction fetch unit 102, a decoder 103, an allocator 104, and a scheduler 105. Further, the processor 1 may include a plurality of arithmetic units 106, a load/store queue 107, and a register 108.

The instruction fetch control PC 101 is a program counter that stores the address (address of the main storage device, for example, the memory 100) where the next instruction to be executed is stored. The instruction fetch unit 102 fetches an instruction from the address indicated by the instruction fetch control PC 101. The decoder 103 decodes the instruction fetched by the instruction fetch unit 102. The allocator 104 allocates a resource for executing the decoded instruction, such as one of the plurality of arithmetic units 106, to the decoded instruction, and dispatches the instruction to the scheduler 105.

The scheduler 105 issues the instructions issued from the allocator 104 to the arithmetic units 106 allocated by the allocator 104. Note that the issuance of an instruction from the allocator 104 to the scheduler 105 may be referred to as a dispatch, and the issuance of an instruction from the scheduler 105 to the arithmetic unit 106 may be referred to as an issue.

The scheduler 105 includes, for example, a queue that receives and accumulates instructions issued from the allocator 104 in program order (in-order order). The scheduler 105 issues instructions with inter-instruction dependencies resolved from the queue to the arithmetic unit 106 out of order.

Each of the plurality of arithmetic units 106 executes the instruction issued to itself from the scheduler 105 and writes the execution result to the register 108. The plurality of computing units 106 may include computing units 106a to 106h. The arithmetic unit (BRCH) 106a is an arithmetic unit that executes a branch instruction. Arithmetic units (AGU) 106b and 106c are arithmetic units that execute address generation instructions. The computing device (STD) 106d is a computing device that executes transmission of store data. Arithmetic units (FXU) 106e and 106f are arithmetic units that execute fixed-point arithmetic instructions. Arithmetic units (FLU) 106g and 106h are arithmetic units that execute floating point arithmetic instructions.

The load/store queue 107 is a queue that stores data to be loaded or stored in the register 108 or the memory 100 during execution of instructions by the arithmetic units 106b to 106d.

The register 108 is used for execution of instructions by the plurality of arithmetic units 106. The memory 100 is, for example, a main storage device such as a DIMM (Dual Inline Memory Module).

In the processor 1, a plurality of calculation pipelines 109a and a plurality of load pipelines 109b are formed. Hereinafter, the calculation pipeline 109a and the load pipeline 109b may be simply referred to as the calculation pipe 109a and the load pipe 109b. One arithmetic pipe 109a includes an arrow from the scheduler 105 to the arithmetic unit 106, an arrow indicating a register read from the register 108 to the arithmetic unit 106 (corresponding to a register read port), an arithmetic unit 106, and an arrow from the arithmetic unit 106 to the register 108. Contains an arrow (corresponding to the register write port) indicating a register write to. The plurality of load pipes 109b are LDR0 and LDR1 in the example of FIG.

In FIG. 1, one register read port is connected to each arithmetic unit 106, but each arrow does not indicate one operand, but rather multiple operands, such as two or three operands, are connected to one operand. It is expressed as a book wire. In reality, a register read port may include at least a line with a bit width (64 bits for fixed point, SIMD width for floating point) x number of operands.

The scheduler 105 has the same number of issue ports as the calculation pipes 109a. Each computing unit 106 or each path from the issuing port of the scheduler 105 to each computing unit 106 may be referred to as a pipeline. In the processor 1, in order to enable simultaneous writing and execution, the same number of register write ports as the pipelines of the arithmetic pipe 109a and the load pipe 109b that perform register writing are prepared. In other words, the number of register write ports matches the number of pipelines of the calculation pipe 109a and the load pipe 109b.

[1-2] Configuration example of processor core according to comparative example FIG. 2 is a block diagram showing a configuration example of the scheduler 105 according to the comparative example. As illustrated in FIG. 2, the scheduler 105 according to the comparative example may include a payload data storage section 105a, a dependency resolution determination section 105b, a selection section 105c, and a selector 105d.

The payload data storage unit 105a stores payload data of instructions issued (instructions received) from the allocator 104. A storage unit that stores instructions, including the payload data storage unit 105a, is an example of a queue of the scheduler 105.

The dependency resolution determination unit 105b resolves the dependency relationship of the instructions issued by the allocator 104. The instruction dependency relationship is, for example, a relationship in which the operation result (data) of a first instruction is used in the operation of a second instruction. The first instruction may be referred to as a "dependent instruction" or a "predecessor instruction," and the second instruction may be referred to as a "dependent instruction" or a "successor instruction."

For example, the dependency resolution determination unit 105b determines whether or not the data dependence has been resolved, and when determining that the dependency has been resolved, issues to the selection unit 105c which instruction among the instructions for which the dependency relationship has been resolved. issue a notification (dependency resolution notification) indicating whether The notification may include, for example, information indicating the entry of the instruction in a queue of scheduler 105. Dependency or dependency relationship resolution may mean that the operation result of the dependent instruction can be used during the operation of the dependent instruction.

The selection unit 105c uses the selector 105d to arbitrate which instructions to issue among the instructions whose dependencies have been resolved, in response to the notification from the dependency resolution determination unit 105b. For example, the selection unit 105c may determine the entry to be issued based on the entry indicated by the dependency resolution notification and information on the program order of the instructions issued from the allocator 104. Further, the selection unit 105c may select an entry in the queue of the payload data storage unit 105a for the selector 105d.

For example, if there are multiple subsequent instructions that depend on the preceding instruction, dependency resolution notifications may be sent to multiple entries. The selection unit 105c determines which instruction is to be issued from the scheduler 105 among the plurality of instructions for which dependency resolution has been performed.

The selector 105d issues an instruction to the pipeline in response to selection (arbitration) by the selection unit 105c. The "instruction" also includes data used by the arithmetic unit 106, such as payload data stored in the payload data storage unit 105a. For example, the selector 105d issues the payload data of the entry selected by the selection unit 105c from the payload data storage unit 105a to the pipeline.

The scheduler 105 may include a payload data storage section 105a and a dependency resolution determination section 105b independently for each entry. Furthermore, the scheduler 105 may include dependency resolution determination units 105b for the number of operands (for example, "2", "3", or "4", etc.). In other words, one dependency resolution determining unit 105b may be provided for each entry and each operand.

Note that an associative method is used as the method (wakeup method) for determining the dependency resolution timing of instructions in the queue of the scheduler 105, but the method is not limited to this, and methods such as an indirect method and a direct method may also be used. may be used. Furthermore, since all of these methods utilize special circuits such as a multi-port small-capacity RAM (Random Access Memory) or a CAM (Content Addressable Memory), it is difficult to synthesize them using an automatic synthesis tool. For example, as these methods, a standard cell (stdcell) that can be synthesized using an automatic synthesis tool and consumes low power may be used.

Here, the dependency resolution determination unit 105b resolves data hazards between dependent instructions (a state in which the pipeline of a subsequent instruction cannot proceed without waiting for the calculation result of a preceding instruction) by forwarding control. Forwarding may also be referred to as bypass. Although not shown in FIG. 2, the scheduler 105 may include, for example, a forwarding unit 105e (see FIG. 4) that forwards data within the pipeline.

FIG. 3 is a diagram illustrating an example of pipeline stages and an example of data forwarding according to latency. Symbol A indicates an example of forwarding timing of an add instruction with a latency of 1 cycle, and symbol B indicates an example of forwarding timing of a mul instruction with a latency of 2 cycles. Symbol C indicates an example of the function of each stage. Note that the add instruction (for example, add: r0 <= r1 + r2) is an operation that writes the sum of the data in register r1 (data of operand 1) and the data in register r2 (data of operand 2) to register r0. It is a command. The mul instruction (for example, mul: r0 <= r1 * r2) is an arithmetic instruction that writes the product of the data of operand 1 in register r1 and the data of operand 2 in register r2 to register r0.

In symbols A and B, a stage preceding the P stage (hereinafter sometimes referred to as a "scheduler stage") indicates that an instruction exists in the scheduler 105. At this stage, the dependency resolution determination unit 105b determines whether the timing is such that the data of the preceding instruction can be used (wait for wakeup). For example, the dependency resolution determination unit 105b holds a wakeup bit (ready bit) for each operand (hereinafter sometimes referred to as "OP"). If all wakeup bits are on, it means that data for all operands is available. In this case, the dependency resolution determination unit 105b wakes up (ready) the subsequent instruction, for example, outputs a dependency resolution notification of the subsequent instruction to the selection unit 105c.

The P stage (see symbol C) is a stage in which the scheduler 105 selects and issues the instruction when data for all operands becomes available.

The B stage is the stage where the pipeline reads data from register 108.

The F stage is a stage in which the pipeline reads (obtains) forwarded data (operands).

The X (Xn; n is an integer greater than or equal to 1) stage is a stage in which the arithmetic unit 106 executes arithmetic operations using the data acquired in the B stage or F stage. There are stages for the number of cycles required.

The W stage is a stage in which the calculation result (data) of the Xn stage is written into the register 108.

Further, as a stage indicating a cycle, the LX (Last X) stage indicates the cycle of the last Xn stage. The Mm (or LXMm) stage is a stage m (m is an integer greater than or equal to 1) cycles before LX (LX minus m cycles). The Pp (or LXPp) stage is a stage p (p is an integer greater than or equal to 1) cycles after LX (LX plus p cycles).

The dependency resolution determination unit 105b forwards (bypasses) the operation result of the preceding instruction to a stage (for example, F stage) before the Xn stage of the subsequent instruction.

For example, in code A, the operation latency of instruction 1 (No. 1) is 1, so the dependency resolution determination unit 105b detects the dependence between instruction 1 and instruction 2 on OP1, and the add of instruction 1 is When it detects that it has entered the P stage, it uses this as an opportunity to wake up command 2 (No. 2). Thereby, the scheduler 105 can forward the operation result of the X1 stage (fourth cycle) of instruction 1 to OP1 of the F stage (immediately before the X1 stage) of instruction 2, which has a dependency relationship with instruction 1.

Further, in code B, since the operation latency of instruction 1 is 2, the dependency resolution determining unit 105b wakes up instruction 2 upon detecting that mul of instruction 1 has reached the B stage. Thereby, the scheduler 105 can forward the operation result of the X2 stage (fifth cycle) of the instruction 1 to the OP1 of the F stage (immediately before the X1 stage) of the instruction 2, which has a dependency relationship with the instruction 1.

In this manner, the dependency resolution determining unit 105b determines how many cycles before the LX stage the subsequent instruction should be woken up when performing forwarding control for multiple cycles of arithmetic latency. For example, in the examples of codes A and B, the dependency resolution determination unit 105b may wake up the subsequent instruction at LXM3 (two cycles before LX). In the example with code A, LXM3 of preceding instruction 1 with arithmetic latency 1 is in P stage, and in the example with code B, LXM3 of preceding instruction 1 with arithmetic latency 2 is in B stage, but in both examples, wakeup in LXM3 Forwarding is performed at the shortest timing.

In order for the dependency resolution determining unit 105b to determine such forwarding timing, the scheduler 105 performs, for example, a comparison process to compare the values of PRA (Physical Register Address) of each OP of the subsequent instruction at the timing of LXM3 of the preceding instruction. Prepare a container. The dependency resolution determining unit 105b wakes up the subsequent instruction when determining that the PRA in the comparator matches. The comparator here is for detecting a match between IDs that uniquely distinguish instructions to be speculatively executed. PRA is an example of the type of ID. Therefore, the comparison target does not have to be limited to PRA. In addition, a comparator determines a match in the form of an encoded ID, but it is also possible to detect a match between IDs by holding the ID in a decoded form and taking an and-or of each decoded signal line. good.

Note that since there is no queue for storing instructions between the scheduler 105 and the arithmetic unit 106, forwarding is executed before the arithmetic unit 106. This means that the scheduler 105 controls the timing of issuing an instruction and determines from which stage the instruction should be forwarded.

In the following description, the scheduler 105 will be described from the part of the scheduler 105 that outputs data from the queue (selector 105d in the example of FIG. 2) to the part that controls timing and determines the forwarding stage, including the comparator. shall be called.

FIG. 4 is a diagram illustrating an example of the configuration of the core of the processor 1 according to the comparative example. FIG. 4 shows an example of a core configuration focusing on forwarding of operation results to operands. In FIG. 4, an example is given in which the calculation latency is one cycle and the number of operands to be forwarded is one. Note that hereinafter, write address may be expressed as w address, and read address may be expressed as r address.

In FIG. 4, an example is shown in which an instruction is issued to one pipeline from one issue port of the selector 105d. Commands may be issued to the line.

As shown in FIG. 4, the write address 201 of the preceding instruction issued from the selector 105d branches from each stage of B, F, and X1, and is input to the comparator 105f corresponding to each stage. Further, the read address 202 (address of the operand waiting for forwarding in the F stage) of the subsequent instruction that has a dependency relationship with the preceding instruction is input to each comparator 105f. Note that, as shown in FIG. 4, an area (circuit) surrounded by a thick solid line including the comparator 105f may be referred to as a forwarding unit 105e.

The comparator 105f of each stage sends forwarding information, for example, a signal to select port 1, to the selector 205 of the corresponding stage when the write address 201 and the read address 202 match, for example, when the PRA matches. The selector 205 to which forwarding information has been input receives the operation result of the preceding instruction from the arithmetic unit 106 (an ALU as an example) from the X1/LX stage, W/LXP1 stage, LXP2 stage, etc., and converts it to the operand of the F stage of the subsequent instruction. Select the data to input. In this way, forwarding 206 is performed under switching control of selector 205.

Note that the operation result of the preceding instruction is written to the write address 201 of the register 108 by reg write 203 in the W/LXP1 stage of the preceding instruction. If forwarding 206 is not performed, the data is read by reg read 204 from read address 202 of register 108 in the B stage of the subsequent instruction. The selector selects port 0 and inputs the data to the arithmetic unit 106.

In the example shown in FIG. 4, the number of comparators 105f of the forwarding unit 105e increases according to the number of operands to be forwarded, for example, becomes an integral multiple (approximately 1 to 4 times; as an example, 3 times) of the number of operands. Furthermore, when the number of pipelines increases x times, the write address 201 that the comparator 105f compares with the read address 202 becomes x times as many, and the read address 202 itself also becomes x times, so the number of comparators 105f becomes x^2 times. Become.

Furthermore, the number of forwarding timings (the number of selectors 205) is the number of latency from reg read 204 to reg write 203 minus calculation latency (4-1==3 in FIG. 4). Therefore, when the pipeline becomes deeper, for example, when the latency from reg read 204 to reg write 203 increases from 4 to 7, the forwarding timing doubles and the number of comparators 105f also doubles.

Furthermore, when the inflight instruction width increases, the comparison width increases by log2, and therefore the circuit scale of each comparator 105f increases.

In this way, when improving the IPC by increasing the functionality of the core of the processor 1, the circuit scale of the forwarding unit 105e increases.

FIG. 5 is a block diagram illustrating a configuration example of the dependency resolution determination unit 105b according to the comparative example. FIG. 5 shows a configuration example of the dependency resolution determination unit 105b that performs wakeup for one entry and one operand in the scheduler 105.

As shown in FIG. 5, the dependency resolution determination unit 105b includes a shortest forward timing determination comparison circuit 301, cache miss timing determination comparison circuits 303 and 304, a cache miss determination circuit 305, and an AND circuit 306.

The shortest forward timing determination comparison circuit 301 is a comparison circuit that determines the shortest forward timing. The shortest forward timing determination comparison circuit 301 includes comparators for each pipeline, for example, the number of comparators corresponding to the number of calculation pipes 109a+the number of load pipes 109b.

A cache miss determination signal 302 from each load pipe 109b is input to the cache miss determination circuit 305. The cache miss determination signal 302 may be, for example, the LDR0 and LDR1 signals from the load/store queue 107 to the register 108 shown in FIG.

The scheduler 105 speculatively issues a cache miss-dependent load (load instruction (2) dependent from the load instruction (1) that caused the cache miss) before a cache miss occurs. An example of the load instruction (1) is a load instruction "load r1 <= [r0]" that writes data at the address written in the contents of the r0 register to the r1 register. Furthermore, an example of the load instruction (2) is the load instruction "load r2 <= [r1]".

The cache miss timing determination comparison circuit 303 is a comparison circuit for canceling a speculatively issued load. The cache miss timing judgment comparison circuit 304 is a comparison circuit for canceling an instruction (3) that depends on the operation result of an operation instruction (2) using the result of a speculatively issued load instruction (1) that misses the cache. be. Note that add is an example of an operation. An example of the load instruction (1) is “load r1 <= [r0]”. An example of the operation instruction (2) is an add instruction "add r2 <= r1 + r1" that adds the data in the r1 register and the data in the r1 register and writes the result to the r2 register. An example of the instruction (3) is the add instruction “add r3 <= r2 + r2”. Further, another example of the instruction (3) is the load instruction "load r3 <= [r2]".

The cache miss timing determination comparison circuit 303 is a circuit that determines the cache miss timing in the load pipe 109b for a directly dependent load or operation instruction from a load that has a cache miss, and performs a number of comparisons corresponding to the number of load pipes 109b. Prepare a container.

The cache miss timing determination comparison circuit 304 is a circuit that determines the cache miss timing in the arithmetic pipe 109a for the above-mentioned instruction (3), and includes a number of comparators corresponding to the number of arithmetic pipes 109a.

The cache miss determination circuit 305 is a circuit that determines the presence or absence of a cache miss based on the cache miss determination signal 302 and the outputs of the cache miss timing determination comparison circuits 303 and 304.

The AND circuit 306 outputs the result of ANDing the output of the shortest forward timing determination comparison circuit 301 and the inversion of the output of the cache miss determination circuit 305 as a dependency resolution notification signal 307. The signal 307 is a data dependency resolution bit (Q_xx_OPx_ready bit in the example of FIG. 5) of OPx in entry xx of the scheduler 105 (queue).

In the example shown in FIG. 5, when the number of entries in the queue increases by M times, the circuit size of the dependency resolution determination unit 105b also increases by M times. Further, the number of comparators in blocks 301, 303, and 304 in the dependency resolution determining unit 105b increases depending on the number of operands to be forwarded, for example, when the number of comparators is an integral multiple (approximately 1 to 4 times; as an example, 3 times) of the number of operands. Become. Furthermore, when the number of pipelines increases x times, the number of comparators also increases x times.

Furthermore, when the shortest forward timing increases from one to two, the number of comparators in the shortest forward timing determination comparison circuit 301 doubles.

Furthermore, as the inflight instruction width increases, the comparison width (id width) increases by log2, which increases the circuit scale of each comparator.

In this way, when improving the IPC by increasing the functionality of the core of the processor 1, the circuit scale of the dependency resolution determination unit 105b increases.

[1-3] Configuration example of processor core according to one embodiment The core of the processor 1 according to one embodiment will be described below. Note that in the following description of one embodiment, configurations, processes, and functions that are not particularly mentioned are the same as those in the comparative example.

FIG. 6 is a block diagram illustrating a configuration example of the scheduler 105 according to one embodiment. As illustrated in FIG. 6, the scheduler 105 according to one embodiment includes a dependency resolution determination unit 11 in place of the dependency resolution determination unit 105b, and outputs pipeline stage information, as compared to the comparative example illustrated in FIG. The difference is that a selector 105d is provided. The scheduler 105 retains an index indicating a pipeline in which a dependent instruction among a plurality of instructions is executed and an execution stage of the dependent instruction in the pipeline, and , is an example of a control unit that performs data dependency resolution with a dependent instruction using the execution result of a dependent source instruction and controls the issuance timing of a plurality of instructions.

The dependency resolution determination unit 11 outputs a dependency resolution notification to the selection unit 105c, and also selects a pipeline stage (hereinafter referred to as "PS") to the selector 105d (lower selector 105d in FIG. 6) selected by the entry selection signal. ) information 207 is output.

An entry selection signal is output from the selection section 105c. For example, an arrow that enters the selector 105d from the selection unit 105c is used to output information on the issued instruction including PS information 207 from the scheduler 105 to the pipeline, and an arrow that enters the dependency resolution determination unit 11 from the selection unit 105c is used for subsequent Used for resolving dependent instructions. The selector 105d on the upper side of FIG. 6 issues an instruction to the pipeline based on the entry selection signal. The lower selector 105d in FIG. 6 selects the PS information 207 (in the dependency resolution determination unit 11) held for each entry in the scheduler 105 using an entry selection signal, and selects the entry for which the command is issued from the upper selector 105d. PS information 207 is output.

Based on the PS information 207 and FIG. 5 (and FIG. 8, which will be described later), the dependency resolution determination unit 11 determines whether the dependent instruction among the plurality of instructions has a dependency relationship with the dependent instruction and the execution result of the dependent instruction. Controls the dependency resolution timing of dependent instructions that use . As one example, we will focus on FMA (Fused multiply-add) defined in IEEE754-2008, for example, a product-sum operation of x*y+z in which products are summed. For example, in the case of dependence on the FMA addition unit, the dependency resolution determining unit 11 sets “Q_xx_OPx_ready” based on the PS information 207 and performs wakeup using “Q_xx_OPx_ready”.

FIG. 7 is a diagram showing an example of the PS information 207. The PS information 207 is an example of an index indicating a pipeline in which a dependent instruction among a plurality of instructions is executed and an execution stage of the dependent instruction in the pipeline.

For example, the PS information 207 may include, for each operand in the entry of the scheduler 105, pipeline information and stage information of the preceding instruction of the operand. In the example of FIG. 7, the PS information 207 includes a stage ID 208 for each operand, and a pipeline ID 209 that is an example of identification information of the pipeline in which the dependent instruction was issued.

In the example of FIG. 7, the PS information 207 may be 6-bit information including a 3-bit pipeline ID 209 of [5:3] and a 3-bit stage ID 208 of [2:0]. Note that the number of bits of the stage ID 208 and pipeline ID 209 is not limited to these.

The stage ID 208 is, for example, a unique ID (stage_id) for each stage from the shortest forwarding timing to before data transfer via the register 108 where forwarding becomes unnecessary. In other words, the stage ID 208 transfers the execution result to the register 108 from the issuance timing (for example, P of instruction 2 in FIG. 13, which will be described later) at which the execution result (for example, operation result) can be transferred from the dependent instruction to the dependent instruction in the shortest possible time. This is an example of stage identification information that is uniquely assigned to each stage from the issuance timing (for example, from instruction 5 to the subsequent P in FIG. 13) at which the dependent instruction can read the execution result.

The stage ID 208 may indicate the stage of the preceding instruction when the subsequent instruction reaches the P stage (is issued).

For example, the stage ID 208 may be expressed as a counter that is set to a value other than the initial value (for example, 0) at the shortest forwarding timing LXMn, and is set (0-cleared) to the initial value (for example, 0) at LXPn. In other words, the stage ID 208 is a counter that is set a first predetermined number of cycles before the last cycle in which the dependent instruction is executed, and is reset in a second predetermined number of cycles after the last cycle. , the counter value is uniquely assigned to each stage.

The first predetermined number and the second predetermined number may have different values for different combinations of pipelines and forwarding types. Also, different stage IDs 208 may be assigned. These two reasons are because forward timing depends on the length of the pipeline and the read/write timing of register 108. The forwarding type is, for example, a fixed point register, a floating point register, a CF (Condition Flag), or the like.

The pipeline ID 209 is an example of identification information of the pipeline through which the dependent instruction is flowing, and a unique value may be set for each pipeline. The pipeline ID 209 is used to detect the timing at which the dependent instruction is input to the pipeline and the pipeline to which the dependent instruction is input.

FIG. 8 is a block diagram illustrating a configuration example of the dependency resolution determination unit 11 according to an embodiment. FIG. 8 shows a configuration example of the dependency resolution determination unit 11 that performs wakeup for one entry and one operand in the scheduler 105.

As shown in FIG. 8, compared to the comparative example shown in FIG. The difference is that a PS information update circuit 11b is provided.

The cache miss determination timing generation circuit 11a generates an arithmetic latency signal and an arithmetic pipe advance load timing signal. Note that the calculation latency signal and the calculation pipe advance load timing signal may be input from the control unit 105g (see FIG. 16). Incidentally, since the same PS information 207 is actually used in forwarding and cache miss determination, the forwarding section 12 shown in FIG. 9 and the control section 105g shown in FIG. 16 may be integrated.

The calculation latency signal is a signal generated when a pipeline has multiple latencies, and is generated for each pipeline. The arithmetic pipe advance load timing signal is a signal indicating the cache miss determination timing of a load instruction that is directly or indirectly (if another dependent instruction exists) dependent on the arithmetic instruction flowing through the arithmetic pipe 109a. In other words, the arithmetic pipe advance load timing signal indicates when the advance load instruction in the dependency chain has not yet reached the cache miss determination timing and will reach the cache miss determination timing, or whether it is now the cache miss determination timing. This signal indicates whether a cache miss has been confirmed after the cache miss determination timing has passed. In the case where there is indirect dependence on the arithmetic instruction flowing through the arithmetic pipe 109a, a plurality of arithmetic pipe advance load timing signals may rise for one operand.

The PS information update circuit 11b outputs a signal 11c based on the shortest forward timing determination comparison circuit 301, the cache miss determination circuit 305, and the PS information 207.

The signal 11c is a bit (Q_xx_OPx_igt [x:0] bit in the example of FIG. 8) that has the pipeline and stage information of the dependent instruction (preceding instruction) of the operand x in the entry xx of the scheduler 105 (queue), This is an example of updated PS information 207.

In this way, the PS information update circuit 11b generates PS information 207 regarding the dependent instruction for each queue entry and for each operand. Further, the PS information update circuit 11b performs data dependency resolution based on the PS information 207 held for each operand. Since the PS information update circuit 11b holds the PS information 207, it may be called a PS information holding unit. Note that the operand is a data source register provided immediately before the arithmetic unit, and is, for example, a register that holds the forwarding result performed in the F cycle and outputs it in the X1 cycle.

FIG. 9 is a diagram illustrating a partial configuration example of the core of the processor 1 according to an embodiment. As illustrated in FIG. 9, in one embodiment, the processor 1 (scheduler 105) includes a forwarding unit 12 instead of the forwarding unit 105e according to the comparative example shown in FIG.

The forwarding unit 12 includes an information generation unit 13 instead of the plurality of comparators 105f according to the comparative example shown in FIG.

The forwarding unit 12 executes control based on the PS information 207 to forward the operation result of the dependent instruction to the operand of the dependent instruction issued to the pipeline at a timing according to the control by the dependency resolution determining unit 11. This is an example of a control unit.

The information generation unit 13 generates forwarding information to be output to the selector 205 (forwarding 206) based on the stage ID 208 for each operand, which is generated and held by the dependency resolution determination unit 11 of the scheduler 105.

The stage ID 208 is uniquely assigned to each of the latency-calculation latency forwarding timings (forwarding mux; three timings in the example of FIG. 9) from reg read 204 to reg write 203. Each of the plurality of forwarding timings corresponds to the selector 205.

Note that even if the calculation latency is 2 cycles, the number of forwarding timings is 3, as the latency from reg read 204 to reg write 203 is 5 cycles, and the calculation latency is 2, which is the same as when the calculation latency is 1. .

The number of bits (stage_id width) of the stage ID 208 is log_2{4, from forwarding timing (three in the example of FIG. 9) + timing to read data via register (dependency undetected, for example, one) ==4 }==2.

In the pipeline shown in FIG. 9, the stage ID 208 is expressed by 2 bits, and for example, {1, 2, 3} is assigned to three forwarding timings. Forwarding timing {0} is assigned to register read (reading data via register 108).

The information generation unit 13 decodes the stage ID 208 input from the dependency resolution determination unit 11. The information generation unit 13 generates a forward instruction signal of 1hot0 when the stage ID 208 is one of 1, 2, and 3 assigned to the forwarding timing. For example, the information generation unit 13 generates a forward instruction signal with a value of 1 for the selector 205 corresponding to the stage ID 208, and generates a forward instruction signal with a value of 0 for all other selectors 205. do. The selector 205 to which the forward instruction signal with a value of 1 is input executes forwarding 206 similarly to the comparative example. The forward instruction signal is an example of forwarding information.

Note that when the stage ID 208 is a value (0) assigned to the timing of reading data via the register 108, the information generation unit 13 generates a forward instruction signal having a value of 0 for all selectors 205. In this case, the selector 205 selects reg read 204 as in the comparative example.

FIG. 10 is a diagram illustrating an example of the circuit configuration of the dependency resolution determination unit 11 illustrated in FIG. 8. The dependency resolution determination unit 11 is provided for each entry in the dependency resolution determination unit 105b and for each operand. As shown in FIG. 10, the dependency resolution determination unit 11 uses an ID (Q_xx_OPx_INST_ID) indicating a preceding dependent instruction held for each entry and each operand, and an ID of the preceding dependent instruction flowing through the calculation pipe 109a and the load pipe 109b. It has a shortest forward timing determination comparison circuit 301 (see FIG. 10) that detects the coincidence of .

The shortest forward timing determination comparison circuit 301 has comparators corresponding to the number of pipelines 109a and 109b through which preceding dependent instructions can flow. For example, the shortest forward timing determination comparison circuit 301 uses the INST_ID (LXM3_FXa_INST_ID) of the shortest forward timing LXM3 stage for the calculation pipe 109a and the INST_ID (L_LDX_INST_ID) of the shortest forward timing L stage of each load pipe 109b notified from the forwarding unit 12. , a match is detected with INST_ID (Q_xx_OPx_INST_ID) that indicates a preceding dependent instruction held for each entry and each operand. INST_ID (instruction_id) of the preceding dependent instruction is an ID unique to each instruction, and PRA or the like may be used. Then, the shortest forward timing determination comparison circuit 301 notifies the PS information update circuit 11b of detection information about which pipeline the directly dependent instruction flows through.

The PS information update circuit 11b generates a unique pipeline ID 209 for the calculation pipe 109a or the load pipe 109b by encoding detection information about which pipeline the directly dependent instruction flows through. Additionally, the PS information update circuit 11b permanently sets the stage ID 208 to 1. Furthermore, the PS information update circuit 11b refers to the stage ID 208 every cycle, and if the stage ID 208 is other than 0, increments the stage ID 208, and if it is a threshold value, sets the stage ID 208 to 0. Note that when the stage ID 208 is 0, the PS information update circuit 11b does not increment (update) the stage ID 208.

Note that when canceling a subsequent instruction in a dependency chain that depends on a load that has caused a cache miss, the PS information update circuit 11b may set the stage ID 208 to 0 (0-cleared). This is to prevent a dependent instruction whose dependence source is a load instruction from being erroneously issued in the issuance control of dependent instructions based on the stage ID 208.

The cache miss judgment timing generation circuit 11a generates the cache miss judgment timing of the indirectly dependent preceding load based on the latency information of the directly dependent preceding operation instruction and the PS information 207 having dependency information from the concerned operation instruction. identify. Further, the cache miss determination timing generation circuit 11a identifies the cache miss determination timing of the directly dependent preceding load based on the PS information 207.

Note that in FIG. 10, "F_" indicates the F stage when the stage of the calculation pipe 109a illustrated in FIG. 3 is included. “T_” indicates a T stage when the stage includes a load pipe 109b illustrated in FIG. 17, which will be described later, and “L_” indicates an L stage when the stage includes a load pipe 109b illustrated in FIG. 17, which will be discussed later.

The signals inputted from the cache miss determination timing generation circuit 11a to the cache miss determination circuit 305 have the following meanings in order from the top of FIG.
・Signal indicating that the preceding load is LDa and T timing.
・Signal indicating that the advance load is LDb and T timing.
- A signal indicating that the preceding load has exceeded the T timing and a cache miss has been confirmed.

In this way, the cache miss determination timing generation circuit 11a generates a signal indicating whether the directly dependent or indirectly dependent preceding loads have reached their respective cache miss determination timings, or whether the cache miss determination timing has passed and the cache miss has already been confirmed. Output.

FIG. 11 is a diagram for explaining an example of allocation of PS information 207. In FIG. 11, among the PS information 207 indicated by symbol A, an example of assignment of pipeline ID 209 (id[5:3]) is indicated by symbol B, and stage ID 208 (id[2:0]) (in case of calculation pipe 109a ) is shown in symbol C.

As shown in symbol B, the pipeline ID 209 is {0,1,2 ,3,4,5} are assigned.

As shown by symbol C, the stage ID 208 (in the case of the calculation pipe 109a) is assigned {0,1,2,3,0} to each stage before LXM3, LXM2, LXM1, LX, and after LXP1. Note that stage_id[2:0]==0 before LXM3 indicates that the stage ID 208 has not been issued (dependency undetected), and stage_id[2:0]==0 after LXP1 indicates the data via the register 108. Indicates that the data will be read.

For example, when forwarding timing is not detected, stage_id==0 (dependency not detected). When the shortest forward timing determination comparison circuit 301 detects the forwarding timing, the PS information update circuit 11b sets stage_id=1 in the OR circuit, and sets the pipeline ID 209 in the encoder (see "PS information encode" in FIG. 10). do.

In addition, the PS information update circuit 11b detects the current stage_id!=0 for the stage_id held by the PS information update circuit 11b after one cycle in the update unit (see "updater" in FIG. 10), and updates the PS information. The value of stage_id held by the circuit 11b is incremented and stage_id=2 is set. In the PS information update circuit 11b, the update unit detects the current stage_id!=0 after two cycles, increments the value, and sets stage_id=3. The PS information update circuit 11b detects the current stage_id==3 (==threshold) in the update section after three cycles, increments the value, and sets stage_id=0 (register read). After that, the PS information update circuit 11b detects the current stage_id==0 in the update unit and suppresses incrementing.

In the above example, the case where the stage ID 208 changes (is incremented) as ..., 0, 1, 2, 3, 0, ... is explained, but the stage ID 208 is not limited to this. ,3,2,0,1,3,... or...,0,1,3,2,0,... and so on.

In the comparative example shown in FIG. 5, the cache miss timing determination comparison circuits 303 and 304 include comparators corresponding to the number of load pipes 109b and calculation pipes 109a. Furthermore, in the comparative example shown in FIG. 4, the forwarding section 105e includes three comparators 105f.

On the other hand, as shown in FIG. 10, the dependency resolution determination unit 11 according to the embodiment has a stage ID 208 that can uniquely determine a total of four factors: the forward timing of the comparator and the timing of reading data via the register. PS information 207 containing the information is generated. Furthermore, the dependency resolution determining unit 11 can determine cache miss timing based on information such as LDa, LDb, and PS information 207. Therefore, the dependency resolution determination unit 11 can omit a comparator for cache mistiming determination (cache mistiming determination comparison circuits 303 and 304).

Further, as shown in FIG. 9, the forwarding unit 12 includes an information generating unit 13 that generates information indicating forwarding timing based on the stage ID 208, thereby making it possible to omit the comparator 105f.

As described above, according to one embodiment, by reducing the comparative cost (for example, mounting area) of the wakeup logic in the dependency resolution determining unit 11 of the scheduler 105, executable instructions among a plurality of instructions are executed in parallel in order. The circuit scale of the processor 1 can be reduced. Thereby, the number of usable entries of the scheduler 105 can be increased, and the performance of the processor 1 can be improved.

[1-4] Forwarding Timing Determination Example Next, a forwarding timing determination example according to an embodiment will be described in comparison with a comparative example.

FIG. 12 is a diagram illustrating an example of forwarding timing determination according to a comparative example, and FIG. 13 is a diagram illustrating an example of forwarding timing determination according to an embodiment. Symbol A indicates an example of the forwarding timing of an add instruction with a latency of one cycle, and symbol B indicates an example of the function of each stage.

In FIGS. 12 and 13, instruction 1 (No. 1) indicates a dependent instruction, and instruction 2-5 (No. 2-5) indicates a dependent instruction. Instruction 2-4 is an instruction in which forwarding (see arrows from instruction 1 to each instruction 2-4) is executed, and instruction 5 is an instruction in which register 108 is referenced.

As shown in FIG. 12, among the comparators 105f (see FIG. 4) according to the comparative example, the comparator 105f corresponding to the B stage compares the B stage of instruction 1 and the P stage of instruction 2 (“< ->” (see below). If they match, the comparator 105f outputs forwarding information for forwarding data from the LX stage of instruction 1 to OP1 of the F stage of instruction 2 (see broken line).

The comparator 105f corresponding to the F stage compares the F stage of instruction 1 and the P stage of instruction 3, and if they match, forwards the data from the P1 stage of instruction 1 to OP1 of the F stage of instruction 3 (one point outputs forwarding information for (see dashed line).

The comparator 105f corresponding to the X1 stage compares the X1 stage of instruction 1 and the P stage of instruction 4, and if they match, forwards the data from the P2 stage of instruction 1 to OP1 of the F stage of instruction 4 (dotted line output forwarding information for reference).

Note that for instruction 5, the operation result of instruction 1 is written to the register 108 at the B stage (fifth cycle). Therefore, the processor 1 can read data from the register 108 at the B stage (sixth cycle) of instruction 5.

In this way, the comparator 105f of the forwarding unit 105e compares {B,F,X1}_[preceding instruction pipeline] and P_[dependent instruction pipeline].

In the forwarding timing determination according to the comparative example described above, the forwarding unit 105e includes three comparators 105f. Therefore, as the number of pipelines for preceding instructions and the number of pipelines for dependent instructions increases, the depth of the pipeline increases and the number of comparators 105f increases. For example, the number of comparators 105f can be calculated by multiplying the depth of the pipeline, the number of forwardable pipelines, the number of pipelines, and the number of operands. When the number of comparators 105f increases, the amount of material in the scheduler 105 increases, so the performance of the processor 1 is not achieved, a delay occurs, and the entries of the scheduler 105 are limited.

In the example of FIG. 13, the dependency resolution determination unit 11 compares LXM3 of instruction 1 in the entry of the scheduler 105 and instruction 2-5.

The stage ID 208 indicates the stage of instruction 1, which is the dependent instruction. If stage_id of instruction 2==1, it indicates that dependent instruction 1 is in the LXM2 stage. Since the PS information 207 is selected from the scheduler 105 in the P stage, the meaning is the same in the scheduler 105 even if the instruction 2 is in the P stage. When the operation latency of instruction 1 is 1, the LXM2 stage becomes the B stage. The same applies to the explanation of FIG. When the information generation unit 13 detects stage_id==1 of instruction 2, it outputs forwarding information for forwarding data from the LX stage of instruction 1 to OP1 of the F stage of instruction 2 (see broken line).

If stage_id of instruction 3 is 2, it indicates that dependent instruction 1 is in LXM1 stage. When the information generation unit 13 detects stage_id==2 of instruction 3, it generates forwarding information for forwarding data from the LXP1 (LastX plus 1) stage of instruction 1 to OP1 of the F stage of instruction 3 (see the dashed line). Output.

If stage_id of instruction 4 is 3, it indicates that dependent instruction 1 is in the LX stage. When the information generation unit 13 detects stage_id==3 of instruction 4, it outputs forwarding information for forwarding data from the LXP2 (LastX plus 2) stage of instruction 1 to OP1 of the F stage of instruction 4 (see dotted line). do.

Note that for instruction 5, since stage_id==0, the information generation unit 13 does not generate forwarding information. In this case, processor 1 can read data from register 108 at the B stage (sixth cycle) of instruction 5.

In this way, according to the forwarding unit 12 according to one embodiment, the forwarding timing can be determined by using the stage ID 208 in a configuration in which the comparator 105f is omitted.

In one embodiment, an example is given in which the timing at which the dependent instruction receives data from the dependent instruction is at the F stage of the dependent instruction; however, this is not limited to this, and the timing at which data is received may be It may be a stage before the F stage of the previous instruction.

In the above description, the case where there is one shortest forwarding timing is taken as an example, but there may be two or more shortest forwarding timings.

For example, IEEE754-2008 defines FMA (Fused multiply-add) that performs a multiply-add operation of x*y+z. The sum part in FMA (fma) performs summation on products, so the calculation latency is small. That is, in the case of FMA, the latency is determined not only by the operation latency of the preceding instruction but also by the FMA operand type.

In the examples of FIGS. 12 and 13, it is assumed that the subsequent instruction uses data forwarded to OP1 from the X1 stage of the preceding instruction. In the following explanation, it is assumed that FMA takes a total of 4 cycles, 2 cycles for the "product" operation and 2 cycles for the "sum" operation.

The xy product portion of the subsequent instruction uses data from the X1 stage of the preceding instruction, and the z sum portion of the subsequent instruction uses data from the X3 stage of the preceding instruction. In this case, the wakeup timing is LXM3 for the product of xy, but is LXM5 for the sum of z. In other words, the scheduler 105 compares the two shortest forward timings of LXM3 and LXM5.

FIG. 14 is a diagram illustrating a determination example when there are two shortest forwarding timings according to a comparative example, and FIG. 15 is a diagram illustrating a determination example when there are two shortest forwarding timings according to an embodiment. Symbol A indicates an example of the forwarding timing of an fma instruction with a latency of 2 cycles, symbol B indicates an example of the function of each stage, and symbol C indicates an example of the fma function.

In FIGS. 14 and 15, instruction 1 (No. 1) and instruction 2 (No. 2) each indicate a dependent instruction, and instruction 3 (No. 3; FIG. 14) or instruction 3-7 (No. -7; FIG. 15) indicates the dependent instruction on which forwarding (see the arrow from instruction 1 or 2 to instruction 3-7) is executed. Instruction 8 shown in FIG. 15 is a dependent instruction that refers to register 108.

In addition, in FIGS. 14 and 15, the forwarding timing of the sum operation portion of instruction 2 to the operand of instruction 3 only needs to be in time for the execution of the sum operation, and does not need to be performed during the product operation. For example, in forwarding from instruction 1 to instruction 3, data is forwarded from the LX stage of instruction 1 to OP1 and OP2 of the F stage of instruction 3. Note that illustration and description of forwarding to OP2 will be omitted. In forwarding from instruction 2 to instruction 3, data is forwarded from the LX stage of instruction 2 to OP3 of the X2 stage of instruction 3. This makes it possible to hide the two-cycle latency of multiply (product operation).

In the comparative example, as shown in FIG. 14, LXM3 of instruction 1 in the entry of the scheduler 105 and instruction 3 (OP1) are compared in the fourth cycle (three cycles before LX of instruction 1). In addition, in order to issue the fastest instruction in accumulate (see X3, Detect and resolve dependencies.

For this reason, the cost for detecting dependence in the dependency resolution determination unit 105b, for example, the cost for comparing the instruction-specific ID and register number (for example, the mounting area) increases. Further, the number of comparators 105f in the pipeline also increases compared to the example shown in FIG. 12.

On the other hand, in the example of FIG. 15, the PS information update circuit 11b of the dependency resolution determination unit 11 generates the PS information 207 corresponding to the pipeline of instruction 1 based on the comparison in LXM3 described above, as well as generates the PS information 207 in LXM5. PS information 207 corresponding to the pipeline of instruction 2 is generated based on the comparison. For example, the PS information update circuit 11b updates the stage ID 208 of each PS information 207 at each timing of LXM3 and LXM5 for each pipeline ID 209 specified by the output from the shortest forward timing determination comparison circuit 301.

In the example of FIG. 15, the stage ID 208 (PS information 207) corresponding to OP1 of subsequent instruction 3 indicates stage_id in the pipeline of preceding instruction 1, and the stage ID 208 corresponding to OP3 of subsequent instruction 3 indicates the preceding instruction. Shows stage_id in pipeline 2.

(Forwarding from instruction 1)
When the information generation unit 13 detects stage_id==1 corresponding to OP1 in the P cycle of instruction 3, it outputs forwarding information for forwarding data from the LX stage of instruction 1 to OP1 of the F stage of instruction 3.

When the information generation unit 13 detects stage_id==2 corresponding to OP1 in the P cycle of instruction 4, it outputs forwarding information for forwarding data from the LXP1 stage of instruction 1 to OP1 of the F stage of instruction 4.

When the information generation unit 13 detects stage_id==3 corresponding to OP1 in the P cycle of instruction 5, it outputs forwarding information for forwarding data from the LXP2 stage of instruction 1 to OP1 of the F stage of instruction 5.

Note that for instructions after instruction 6, the stage_id corresponding to OP1 is 0, so the information generation unit 13 does not generate forwarding information for OP1. In this case, the processor 1 reads data from the register 108 in the B stage (sixth cycle) after instruction 6.

(Forwarding from instruction 2)
When the information generation unit 13 detects stage_id==1 corresponding to OP3 in the P cycle of instruction 3, it outputs forwarding information for forwarding data from the LX stage of instruction 2 to OP3 of the X2 stage of instruction 3.

When the information generation unit 13 detects stage_id==2 corresponding to OP3 in the P cycle of instruction 4, it outputs forwarding information for forwarding data from the LXP1 stage of instruction 2 to OP3 of the X2 stage of instruction 4.

When the information generation unit 13 detects stage_id==3 corresponding to OP3 in the P cycle of instruction 5, it outputs forwarding information for forwarding data from the LX stage of instruction 2 to OP3 of the F stage of instruction 5.

When the information generation unit 13 detects stage_id==4 corresponding to OP3 in the P cycle of instruction 6, it outputs forwarding information for forwarding data from the LXP1 stage of instruction 2 to OP3 of the F stage of instruction 6.

When the information generation unit 13 detects stage_id==5 corresponding to OP3 in the P cycle of instruction 7, it outputs forwarding information for forwarding data from the LXP2 stage of instruction 2 to OP3 of the F stage of instruction 7.

Note that for instructions after instruction 8, since stage_id==0 corresponding to OP3, the information generation unit 13 does not generate forwarding information for OP3. In this case, the processor 1 reads data from the register 108 in the B stage (11th cycle) after instruction 8.

This makes it possible to eliminate the need for the comparator 105f in the pipeline even in processing where a plurality of shortest forward timings exist, such as in FMA.

Note that, for example, if the instruction does not have Accumulate forwarding (forwarding to X2 instead of F; see OP3 in instructions 3 and 4), the dependency resolution determination unit 11 sets the wakeup ready bit when op3_stage_id==2, The command may be controlled to be issued after stage_id==3 of P stage.

[1-5] Configuration example for canceling a subsequent instruction in a dependency chain that depends on a cache-missed load Up to this point, a configuration example for determining forwarding timing has been described. The method using can also be applied to cancel subsequent instructions in a dependency chain that depend on a load that misses the cache.

FIG. 16 shows a configuration focusing on a process of canceling a subsequent instruction in a dependency chain that depends on a cache-missed load (hereinafter sometimes referred to as "cache-miss cancellation") in the core configuration of processor 1 according to a comparative example. It is a figure which shows an example. In FIG. 16, an example is given in which the calculation latency is one cycle and the number of target operands is one.

"Cancellation" may mean erasing an instruction that has been issued by the scheduler 105 from the pipeline, and making the instruction remaining in the scheduler 105 unissued.

In FIG. 16, a broken line indicates a process for canceling an operation-dependent instruction from a load that misses the cache, a chain line indicates a process for canceling an operation-dependent instruction from an operation that depends on a load, and a dotted line indicates a process for the corresponding scheduler 105. This shows the cancellation process in the entry.

As shown in FIG. 16, the core of the processor 1 (for example, the scheduler 105) may include a control unit 105g. The control unit 105g outputs a cache miss signal based on a forwarding unit 105e including a comparator 105f, a plurality of comparators 105h, and an arithmetic pipe advance load timing signal (sometimes referred to as "cancel_code" from FIG. 16 onwards). A generation circuit 105i that generates the information may be provided. Further, the core of the processor 1 may include a cancellation circuit 211 that cancels the forwarding 206 of the dependent instruction based on the cache miss signal and the valid signal.

FIG. 17 is a diagram illustrating an example of determination in a process of canceling a subsequent instruction in a dependency chain that depends on a load that has caused a cache miss according to a comparative example. Symbol A in FIG. 17 indicates an example of the timing of cache miss cancellation of an add instruction with a latency of one cycle, and symbol B indicates an example of the function of each stage.

As shown by reference numeral B in FIG. 17, the L stage indicates a stage where a load instruction depending on a cache miss is issued to the pipeline. The R stage indicates a stage in which data is read from the RAM. M stage indicates the stage where tag matching and selection are performed. The T stage indicates the stage where data arrives or misses. Cache misses are discovered at the T stage. The W stage indicates a stage in which data is written to the register 108.

Hereinafter, with reference to FIGS. 16 and 17, an example of a process for canceling a dependent instruction at the time of a cache miss according to a comparative example will be described.

As shown in FIG. 17, instructions 2-5 have a direct dependency on instruction 1. Therefore, the scheduler 105 compares the T stage of instruction 1 with each instruction 2-5, and cancels the issuance of each instruction 2-5 if a cache miss is determined at the T stage. Note that no instructions are issued from the scheduler 105 after the timing of issuing instructions 5 and 8.

Instruction 2-5 has issue timing information from instruction 1 to its own instruction, and an arithmetic pipe advance load timing signal that is miss confirmation information for instruction 1, and identifies the T stage (cycle) of instruction 1.

The arithmetic pipe advance load timing signal is a code generated by the control unit 105g shown in FIG. 16, for example, the comparator 105h. The operation pipe preload timing signal is used to perform dependent preload ( This signal notifies the cache miss determination timing (T stage of instruction 1) of instruction 1) and cancels the above instruction. The arithmetic pipe advance load timing signal of the F stage of the arithmetic pipeline 109a matches the arithmetic pipe advance load timing signal notified to the arithmetic pipe cache miss timing determination comparator 304 in FIG. 5 and the cache miss timing generation circuit 11a in FIG. do.

For example, the compute pipe preload timing signal may indicate any of the following:

- The cache miss determination timing of the load pipe 109b of the load instruction that is directly or indirectly dependent and preceding occurs after N cycles.
- The comparison timing of the calculation pipe 109a matches the cache miss timing of the load pipe 109b (refer to the cache miss determination signal).
- The cache miss timing has already passed (the cache miss has been determined by referring to the cache miss determination signal previously).

For example, at the issuance timing of instruction 2, the control unit 105g compares the R stage (write address 210) of instruction 1 and the P stage (read address 202) of instruction 2 in the second cycle. At the timing of issuing instruction 3, the control unit 105g compares the M stage of instruction 1 and the P stage of instruction 3 in the third cycle. At the timing of issuing instruction 4, the control unit 105g compares the T stage of instruction 1 and the P stage of instruction 4 in the fourth cycle. At the timing after instruction 5, the in-scheduler comparator 303 is used to identify the cache miss determination timing (T stage) of the dependent advance load, and the cache miss determination signal is used to perform cache miss cancellation. Therefore, at the timing after instruction 5, the scheduler does not issue any directly dependent instructions from the load.

The control unit 105g sets bit 1 in cancel_code[1] according to the comparison result between the R stage and the P stage by the comparator 105h. Further, the control unit 105g sets bit 1 in cancel_code[2] according to the comparison result between the M stage and the P stage by the comparator 105h. Further, bit 1 is set in cancel_code[3] according to the comparison result between the T stage and the P stage by the comparator 105h.

Note that instructions 6-8 are instructions that have no direct dependency relationship with instruction 1 and depend on instruction 2, which instruction 1 depends on. Therefore, the control unit 105g cancels each instruction 6-8 based on the comparison between instruction 2 and each instruction 6-8 and the arithmetic pipe advance load timing signal of instruction 2.

For example, for instructions (instructions 6-7) that are not directly dependent on the dependent preload (instruction 1), the arithmetic pipe preload timing signal is inherited from the instruction (instruction 2) that is directly dependent on the corresponding instruction (Figure 16 B stage cancel_code[2:0] or multiple paths that loopback from F stage cancel_code[1:0] to B stage cancel_code[2:0] The determination timing (T stage of instruction 1) is identified, and the cache miss is canceled by the cache miss determination signal.

In addition, the instructions after instruction 8 are determined by the cache miss timing judgment comparison circuit 304 in the scheduler 105 based on the ID match of the F stage of the arithmetic pipeline 109a and the arithmetic pipe advance load timing signal of the F stage of the arithmetic pipeline 109a. The cache miss judgment timing (T stage) of the preceding load (instruction 1) is identified from the latency (=1) of the preceding operation instruction (instruction 2), and the cache miss of instruction 8 is canceled from the cache miss judgment signal of instruction 1. Therefore, the scheduler 105 does not issue it.

The arithmetic pipe advance load timing signal includes relative position information between a dependent load (instruction 1) and a certain instruction (instruction 2). As a result, each instruction 6-8 can identify the T stage of the dependent load instruction 1 using the following two pieces of information.

- Relative position between each instruction 6-8 and instruction 2 by comparing each instruction 6-8 and instruction 2.
- Relative position between instruction 2 and instruction 1 based on the arithmetic pipe preload timing signal.

For instruction 6-8, the control unit 105g obtains the arithmetic pipe advance load timing signal of the F stage of instruction 2, which is a direct dependency source, and compares the F stage of instruction 2 with each instruction 6-8, and compares the F stage of instruction 2 with each instruction 6-8. Each instruction 6-8 is canceled based on the cache miss determination signal of 1.

For example, the issue timing of instruction 6 is the B stage of instruction 2 in the third cycle==P stage of instruction 6 (see n4 in FIG. 16). B_cancel_code[1] (see n5) of instruction 2 indicates that B stage of instruction 2 = M stage of instruction 1. The control unit 105g sets B_cancel_code[2] of the instruction 6 because the M stage of the instruction 1 is the P stage of the instruction 6.

The issue timing of instruction 7 is the F stage of instruction 2 == P stage of instruction 7 (see n6) in the 4th cycle, or the B stage of instruction 3 == P stage of instruction 7 (when there is a dependency) ( (see n4). F_cancel_code[1] (see n8) of instruction 2 indicates that F stage of instruction 2 == T stage of instruction 1. Since the T stage of instruction 1 == the P stage of instruction 7, the control unit 105g cancels instruction 7 with the cache miss signal (see g1). B_cancel_code[2] (see n7) of instruction 3 indicates that B stage of instruction 3 ==T stage of instruction 1. Since the T stage of instruction 1 == the P stage of instruction 7, the control unit 105g cancels instruction 7 with the cache miss signal (see g1).

For example, the control unit 105g issues to the cancellation circuit 211 a cache miss signal that is an AND of the T stage miss detect signal and the arithmetic pipe advance load timing signal. The cancel circuit 211 drops the P stage valid signal of the subsequent instruction input to the selector 205 in response to the cache miss signal. This causes the subsequent instruction to be canceled.

Instructions 5 and 8 are not issued at subsequent timings. For example, in the F stage of the instruction 2 in the fourth cycle==the comparator in the scheduler 105, the control unit 105g refers to the cache miss signal in the F_cancel_code[1]==1 of the instruction 2.

Each instruction continues to have an arithmetic pipe advance load timing signal (cancellation information) from the P stage to the F stage in order to cancel the instruction following the own instruction. At the F stage, each instruction is compared with subsequent instructions within the scheduler 105. Furthermore, in the issuance timing of instruction 6 described above, the arithmetic pipe advance load timing signal is inherited from the arithmetic pipe advance load timing signal of instruction 2 to the arithmetic pipe advance load timing signal of instruction 6 in the third cycle.

FIG. 18 is a diagram illustrating an example of the arithmetic pipe advance load timing signal (cancel_code) when there is one load pipe 109b. Each value of the arithmetic pipe advance load timing signal may indicate the following states, for example. Note that n1-n3 and g1-g3 in parentheses correspond to signals or configurations with the same symbols in FIG. 16, respectively.

For P stage[3:1].
[3]: P==dependent load (instruction 1) T timing → cancel with cache miss signal (g1) → B stage[0] after 1 cycle
[2]: P==dependent load (instruction 1) M timing (B==T)
→B stage[2](n1) after 1 cycle
[1]: P==dependent load (instruction 1) R timing (F==T)
→B stage[1](n2) after 1 cycle
[0]: P is dependent load (instruction 1) later than T timing, error confirmed (unnecessary as it is not issued by scheduler 105)

For B stage[2:0].
[2]: B==dependent load (instruction 1) T timing → cancel with cache miss signal (g2) → F stage[0] after 1 cycle
[1]: B==dependent load (instruction 1) M timing (F==T)
[0]: B is dependent load (instruction 1) later than T timing, mistake confirmed → 1 cycle later, F stage[0](n3)

For F stage[1:0].
[1]: F==dependent load (instruction 1) T timing → cancel with cache miss signal (g3)
[0]: F is dependent load (instruction 1) later than T timing, error confirmed

In this way, for example, code [3] of the 3-bit P stage cancel_code [3:1] indicates the T timing of the P stage dependent load (instruction 1). In the examples of FIGS. 17 and 18, the scheduler 105 uses the cache miss confirmation information of instruction 1 (arithmetic pipe advance load timing signal) to issue instruction 2 at a timing that overlaps with the T stage of loading in the F stage, and Comparison is performed at the cycle. For example, for instructions 6-8, the scheduler 105 waits for the arithmetic pipe advance load timing signal of the F stage of dependent instruction 2, the timing of the F cycle of instruction 2, and the cache miss determination signal of instruction 1, and then cancels the instructions. Do the following.

In this way, the dependency resolution determination unit 105b according to the comparative example has timing comparators for the T stage and F stage in the cache miss timing determination comparison circuits 303 and 304, a timing comparator for the T-R stage and the P stage in the control unit 105g, Equipped with timing comparators for B-F stage and P stage. The comparison cost (eg, implementation area) of these comparators increases as the number of pipelines increases.

FIG. 19 is a diagram for explaining an example of allocation of PS information 207 according to one embodiment. In FIG. 19, in addition to an example of assignment of the stage ID 208 for the calculation pipe 109a, which is indicated by the symbol C in FIG. 11, an example of assignment of the stage ID 208 for the load pipe 109b is indicated by the symbol D.

As shown by reference numeral D in FIG. 19, the stage ID 208 according to one embodiment is {0,1,2,3,0 for each stage before L, R, M, T, and after W for the load pipe 109b. } is assigned. Note that stage_id[2:0]==0 before L indicates the dependency is unresolved (dependency undetected), and stage_id[2:0]==0 after W indicates that the data is transferred via register 108. Indicates that reading is to be performed. Also, if an instruction is canceled due to a cache miss in the dependency chain of the preceding instruction, or if a pipeline flush occurs, set stage ID 208 stage_id[2:0]=0, which indicates that the dependency is in an unresolved state. Good too.

FIG. 20 is a diagram illustrating a configuration example for canceling a subsequent instruction in a dependency chain that depends on a cache-missed load in the core configuration of the processor 1 according to an embodiment. FIG. 21 is a diagram illustrating a determination example of processing for canceling a subsequent instruction in a dependency chain that depends on a load that has caused a cache miss, according to an embodiment. Note that the value of the arithmetic pipe advance load timing signal, instruction issue or cancellation timing, etc. are the same as in the comparative example.

As shown in FIG. 20, the core of the processor 1 (for example, the scheduler 105) may include the control unit 14. The control unit 14 may include a forwarding unit 12 including the information generation unit 13, an information generation unit 15, and a generation circuit 105i. Further, the core of the processor 1 may include a cancellation circuit 211.

Since the pipeline stage shown in FIG. 20 is for loading, the PS information 207 input to the pipeline stage is used for cache miss cancellation. For example, the PS information 207 is used to specify the T cycle.

As shown in FIG. 21, the dependency resolution determining unit 11 determines whether to cancel the dependency of the T cycle based on stage_id==3 & pipeline_id == load & T_cache_miss. In addition, the dependency resolution determination unit 11 performs dependency cancellation of F cycle {(stage_id==2 & f_latency==1) | (stage_id==1 & f_latency==2)} & {(F_cancel_code[1]&T_cache_miss)| Determine with F_cancel_code[0]} & pipeline_id==exec.

In the information generation unit 15, the control unit 14 acquires the PS information 207 as the determination result in the dependency resolution determination unit 11, identifies the load pipe 109b from the pipeline ID 209, and generates a calculation pipe advance load timing signal from the stage ID 208. . The control unit 14 identifies the timing of the T cycle based on the arithmetic pipe advance load timing signal and the subsequent PS information 207. Then, the control unit 14 causes the cancel circuit 211 to cancel the subsequent instruction based on the determination signal indicating the presence or absence of a cache miss in the T cycle.

In this way, when there is a pre-load instruction in the dependency chain of the dependent source instruction and the pre-load instruction causes a cache miss, the control unit 14 controls all instructions in the dependency chain following the pre-load instruction (the subsequent series This is an example of a cancel control unit that cancels the following chain command. Cancellation includes setting a value indicating failure (for example, dropping opX_ready bit) to information indicating success or failure of data dependency resolution (for example, opX_ready bit) for all instructions in the dependency chain following the preload instruction. It's fine.

In addition, in the issuance control, the dependency resolution determination unit 11 sets information (for example, 0 in the stage ID 208) to suppress the issuance of the dependent instruction in the PS information 207 related to the dependent instruction, so that the dependent instruction is incorrectly issued. You can suppress being controlled.

As described above, according to one embodiment, the dependency resolution determination unit 11 replaces the cache miss timing determination comparison circuits 303 and 304 with the cache miss determination timing generation circuit 11a including the decoder, ) (see FIGS. 8 and 10). In this way, the number of comparators in the scheduler 105 can be reduced by replacing the comparator in the dependency resolution determination unit 105b with a decoder for the stage ID 208 and controlling cancellation based on the stage ID 208. Furthermore, in the pipeline, the comparator 105h can be omitted in addition to the comparator 105f.

[1-6] Configuration example for Inflight Condition Flag update control
CF (Condition Flag) is renamed similarly to register 108. CF as an architectural register is updated after commit (reorder).

The core of processor 1 holds the CF in the Rename stage and updates it each time. CFs after the Rename stage are called Inflight CFs. The core has a bit indicating whether or not to update the CF in the scheduler 105 or later when the value of Rename stage is incorrect while speculatively executing a CF update instruction, and controls the update of the CF.

The instruction refers to the CF in the Rename stage, and if the CF update instruction has been executed, the value is posted. If the CF update instruction has not been executed, the core determines the pipeline and timing of the CF update instruction in the scheduler 105 or pipeline, and captures and forwards the CF value.

FIG. 22 is a diagram illustrating a configuration example focusing on CF update control in the core configuration of the processor 1 according to the comparative example. In FIG. 22, an example is given in which the calculation latency is one cycle and the number of target operands is one.

As shown in FIG. 22, the core of the processor 1 (for example, the scheduler 105) may include a CF update timing determination section 105j and a capture section 105m. The CF update timing determination unit 105j includes a comparator 105k that compares the instruction ID 212 and the read instruction ID. The capture unit 105m includes a comparator 105l. The core also includes a selector 213 that selects the CF from the capture unit 105m or the calculation result of the calculation unit 106 based on the forwarding timing information from the comparator 105k.

In the CF update timing determination unit 105j, a dotted line indicates forwarding from LX to X stage, a broken line indicates forwarding from LXP1 to F stage, and a dashed line indicates forwarding from LXP2 to F stage. The solid line indicates forwarding from LXP3 to F stage.

FIG. 23 is a diagram illustrating a determination example of CF update control according to a comparative example. Symbol A in FIG. 23 indicates an example of the timing of an addeq instruction with a latency of one cycle, and symbol B indicates an example of the function of each stage.

As shown by reference numeral B in FIG. 23, the C stage indicates the stage at which the inflight CF is read. Other stages are similar to those in FIG. 12.

cmp: r0, r1 indicated by symbol A compares the values of r0 and r1, and outputs CF indicating equal if they match, and not equal if they do not match. The core does not write the result to the register 108 with the cmp instruction, but only updates the CF held by the scheduler 105. The inflight CF and the CF of the inflight CF field of the subsequent CF read dependent instruction in the scheduler 105 are also updated. CF as an Architectural register is updated after commit. Furthermore, the Inflight resources held by the scheduler 105 are updated with LXP1. For example, the scheduler 105 controls the CF using Inflight resources, such as register renaming.

Since the cmp instruction is an instruction to update the CF, and the addeq instruction is an instruction to read the CF, there is a dependency between the cmp and addeq instructions.

In the example of FIG. 23, forwarding 214 is performed at the timing from instruction 1 (cmp instruction) to instruction 2-5 (addeq instruction) via the comparator 105k and selector 213 path. After the timing from instruction 1 to instruction 7 (addeq instruction), Inflight CF is read out via the capture unit 105m. For example, comparator 105l is provided to capture the LXP1 timing of instruction 1 and update the Inflight CF.

In this way, in the comparative example, in order to capture the write timing, the comparator 105k for identifying the timing is used.

Furthermore, since the dependence of the CF is different from the lifetime of the register 108, the capture unit 105m has a dedicated control bit and manages whether or not the CF is forwarded from the pipeline. In order to have this information, the capture unit 105m uses a comparator 105l dedicated to checking timing.

In the above-mentioned CF update control, when the number of pipelines, the number of pipeline stages, etc. increases, the process for determining the pipeline and timing of the CF update instruction is performed in the queue of the scheduler 105 and in the pipeline (forwarding unit 105e). The number of comparators increases.

FIG. 24 is a diagram illustrating a configuration example focusing on CF update control in the core configuration of the processor 1 according to an embodiment. In FIG. 24, an example is given in which the calculation latency is one cycle and the number of target operands is one.

As shown in FIG. 24, the core of the processor 1 (for example, the scheduler 105) may include a CF update timing determination section 16 and a capture section 18. The CF update timing determination unit 16 includes an information generation unit 17 that generates forwarding information based on the stage ID 208. The capture unit 18 includes an input of the stage ID 208 instead of the comparator 105l. The core also includes a selector 213 that selects the CF from the capture unit 18 or the calculation result of the calculation unit 106 based on the forwarding timing information from the information generation unit 17.

In the CF update timing determination unit 16, a dotted line indicates forwarding from LX to X stage, a broken line indicates forwarding from LXP1 to F stage, and a dashed line indicates forwarding from LXP2 to F stage. The solid line indicates forwarding from LXP3 to F stage.

FIG. 25 is a diagram illustrating an example of determination of CF update control according to an embodiment. Symbol A in FIG. 25 indicates an example of the timing of an addeq instruction with a latency of one cycle, and symbol B indicates an example of the function of each stage.

In the example of FIG. 25, forwarding 214 is performed at the timing from instruction 1 (cmp instruction) to instruction 2-5 (addeq instruction) through the information generation unit 17 and selector 213 path. The timing from instruction 1 (cmp instruction) to instruction 6 (addeq instruction) is the P stage after the update of the CF in the scheduler 105, and after the capture unit 18 captures (reads) the CF, instruction 6 is issued. Therefore, forwarding 214 becomes unnecessary. After the timing from instruction 1 to instruction 7 (addeq instruction), Inflight CF is read out via the capture unit 18.

In this way, the CF update timing determination unit 16 is an example of an update control unit that controls updating of the Flight Condition Flag based on the PS information 207.

As described above, in addition to forwarding, the PS information 207 can also be applied to one or both of the following instructions in the dependency chain that depends on the cache miss load, and CF update control. In this case, the comparator can be omitted.

[2] Others The technique according to the embodiment described above can be modified and changed as follows.

In one embodiment, the scheduler 105 performs the comparison at the P stage, but the invention is not limited to this, and the comparison may be performed by the forwarding timing.

Furthermore, although the information generating units 13 and 17 generate forwarding information based on the PS information 207 at the P stage, the present invention is not limited to this, and the generation timing may be determined at any stage that is in time for the forwarding or capture timing. But that's fine.

Furthermore, the various comparators illustrated as comparative examples are the same even if they are CAMs.

Furthermore, although the stage ID 208 of the preceding instruction assigned to each operand or CF is a counter that counts up, the stage ID 208 is not limited to this, and may be a counter that counts down. Alternatively, the stage ID 208 may be information in various forms as long as the pipeline and stage can be identified.

[3] Additional notes Regarding the above embodiments, the following additional notes are further disclosed.

(Additional note 1)
An arithmetic processing unit that executes executable instructions among a plurality of instructions in parallel,
a queue storing the plurality of instructions;
holding an index indicating a pipeline in which a dependent instruction among the plurality of instructions is executed and an execution stage of the dependent instruction in the pipeline; a control unit that performs data dependency resolution with a dependent instruction using an execution result of the dependent source instruction and controls issuance timing of the plurality of instructions;
An arithmetic processing device comprising:

(Additional note 2)
The said index is
Identification information of the pipeline in which the dependent instruction was issued;
Uniquely for each stage from the issue timing at which the execution result can be transferred from the dependent source instruction to the dependent instruction in the shortest time to the issuing timing at which the execution result can be stored in a register and the dependent instruction can read the execution result. an assigned stage identification information;
The arithmetic processing device according to supplementary note 1.

(Additional note 3)
The control unit generates the index regarding each dependent instruction for each entry in the queue and for each operand of each of the plurality of instructions.
The arithmetic processing device according to supplementary note 2.

(Additional note 4)
The stage identification information is set in a cycle a first predetermined number of times before the last cycle in which the dependent source instruction is executed, is reset in a second predetermined number of cycles after the last cycle, and each of the one or more cycles between the reset cycle and the reset cycle is assigned a unique identifier;
The arithmetic processing device according to appendix 3.

(Appendix 5)
The control unit performs the data dependency resolution based on the index held in the operand.
The arithmetic processing device according to appendix 4.

(Appendix 6)
forwarding control that executes control based on the index to forward the execution result of the dependent instruction to an operand of the dependent instruction issued to a pipeline in which the dependent instruction is executed at a timing according to the control; equipped with a department;
The arithmetic processing device according to any one of Supplementary notes 1 to 5.

(Appendix 7)
Based on the index, if a preceding load instruction exists in the dependency chain of the dependent source instruction and the preceding load instruction causes a cache miss, cancel control cancels all instructions in the dependency chain subsequent to the preceding load instruction. equipped with a department;
The arithmetic processing device according to any one of Supplementary notes 1 to 6.

(Appendix 8)
In the cancellation, the cancellation control unit sets a value indicating failure in information indicating success or failure of data dependency resolution for all instructions in a dependency chain subsequent to the preceding load instruction.
The arithmetic processing device according to appendix 7.

(Appendix 9)
The arithmetic processing device according to any one of Supplementary Notes 1 to 8, comprising an update control unit that controls updating of the Flight Condition Flag based on the index.

(Appendix 10)
An arithmetic processing method in an arithmetic processing device that executes executable instructions among a plurality of instructions in parallel,
A scheduler included in the arithmetic processing device,
storing the plurality of received instructions in a queue;
It holds an index indicating a pipeline in which a dependent instruction among the plurality of instructions stored in the queue is executed and an execution stage of the dependent instruction in the pipeline; performing data dependency resolution between the dependent instruction and a dependent instruction that uses the execution result of the dependent instruction, and controlling the issuance timing of the plurality of instructions;
An arithmetic processing method that performs processing.

(Appendix 11)
The said index is
Identification information of the pipeline in which the dependent instruction was issued;
Uniquely for each stage from the issue timing at which the execution result can be transferred from the dependent source instruction to the dependent instruction in the shortest time to the issuing timing at which the execution result can be stored in a register and the dependent instruction can read the execution result. an assigned stage identification information;
The arithmetic processing method according to appendix 10.

(Appendix 12)
the scheduler generates the index for each dependent instruction for each entry in the queue and for each operand of each of the plurality of instructions;
The arithmetic processing method described in Appendix 11.

(Appendix 13)
The stage identification information is set in a cycle a first predetermined number of times before the last cycle in which the dependent source instruction is executed, is reset in a second predetermined number of cycles after the last cycle, and each of the one or more cycles between the reset cycle and the reset cycle is assigned a unique identifier;
The arithmetic processing method according to appendix 12.

(Appendix 14)
the scheduler performs the data dependency resolution based on the index held in the operand;
The arithmetic processing method according to appendix 13, which performs the processing.

(Appendix 15)
The scheduler controls, based on the index, forwarding the execution result of the dependent instruction to the operand of the dependent instruction issued to a pipeline in which the dependent instruction is executed at a timing according to the control. Execute,
The arithmetic processing method according to any one of Supplementary Notes 10 to 14, which performs the processing.

(Appendix 16)
Based on the index, if a preload instruction exists in the dependency chain of the dependent instruction and the preload instruction causes a cache miss, the scheduler executes all instructions in the dependency chain subsequent to the preload instruction. Cancel,
The arithmetic processing method according to any one of Supplementary Notes 10 to 15, which performs the processing.

(Appendix 17)
In the cancellation, the scheduler sets a value indicating failure in information indicating success or failure of data dependency resolution for all instructions in a dependency chain subsequent to the advance load instruction.
The arithmetic processing method according to appendix 16, which performs the processing.

(Appendix 18)
the scheduler controls updating of the Inflight Condition Flag based on the indicator;
The arithmetic processing method according to any one of Supplementary Notes 10 to 17, which performs the processing.

1 Processor 11 Dependency resolution determination unit 11a Cache miss determination timing generation circuit 11b PS information update circuit 11c, 307 Signal 12 Forwarding unit 13, 15, 17 Information generation unit 14 Control unit 16 CF update timing determination unit 18 Capture unit 100 Memory 101 Instruction Fetch control PC
102 Instruction fetch section 103 Decoder 104 Allocator 105 Scheduler 105a Payload data storage section 105c Selection section 105d, 205, 213 Selector 104i Generation circuit 106 Arithmetic unit 107 Load/store queue 108 Register 109a Arithmetic pipe 109b Load pipe 207 PS information 20 8 Stage ID
209 Pipeline ID
211 Cancellation circuit 301 Shortest forward timing determination comparison circuit 302 Cache miss determination signal 305 Cache miss determination circuit 306 AND circuit

Claims (10)

An arithmetic processing unit that executes executable instructions among a plurality of instructions in parallel,
a queue storing the plurality of instructions;
holding an index indicating a pipeline in which a dependent instruction among the plurality of instructions is executed and an execution stage of the dependent instruction in the pipeline; a control unit that performs data dependency resolution with a dependent instruction using an execution result of the dependent source instruction and controls issuance timing of the plurality of instructions;
An arithmetic processing device comprising: The said index is
Identification information of the pipeline in which the dependent instruction was issued;
Uniquely for each stage from the issue timing at which the execution result can be transferred from the dependent source instruction to the dependent instruction in the shortest time to the issuing timing at which the execution result can be stored in a register and the dependent instruction can read the execution result. an assigned stage identification information;
The arithmetic processing device according to claim 1. The control unit generates the index regarding each dependent instruction for each entry in the queue and for each operand of each of the plurality of instructions.
The arithmetic processing device according to claim 2. The stage identification information is set in a cycle a first predetermined number of times before the last cycle in which the dependent source instruction is executed, is reset in a second predetermined number of cycles after the last cycle, and each of the one or more cycles between the reset cycle and the reset cycle is assigned a unique identifier;
The arithmetic processing device according to claim 3. The control unit performs the data dependency resolution based on the index held in the operand.
The arithmetic processing device according to claim 4. forwarding control that executes control based on the index to forward the execution result of the dependent instruction to an operand of the dependent instruction issued to a pipeline in which the dependent instruction is executed at a timing according to the control; equipped with a department;
The arithmetic processing device according to any one of claims 1 to 5. Based on the index, if a preceding load instruction exists in the dependency chain of the dependent source instruction and the preceding load instruction causes a cache miss, cancel control cancels all instructions in the dependency chain subsequent to the preceding load instruction. equipped with a department;
The arithmetic processing device according to any one of claims 1 to 5. In the cancellation, the cancellation control unit sets a value indicating failure in information indicating success or failure of data dependency resolution for all instructions in a dependency chain subsequent to the preceding load instruction.
The arithmetic processing device according to claim 7. The arithmetic processing device according to any one of claims 1 to 5, further comprising an update control unit that controls updating of the Flight Condition Flag based on the index. An arithmetic processing method in an arithmetic processing device that executes executable instructions among a plurality of instructions in parallel,
A scheduler included in the arithmetic processing device,
storing the plurality of received instructions in a queue;
It holds an index indicating a pipeline in which a dependent instruction among the plurality of instructions stored in the queue is executed and an execution stage of the dependent instruction in the pipeline; performing data dependency resolution between the dependent instruction and a dependent instruction using the execution result of the dependent instruction, and controlling the issuance timing of the plurality of instructions;
An arithmetic processing method that performs processing.

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