JP2023147174A - Voltage detection circuit, charge control circuit, charging and discharge control circuit, and semiconductor device - Google Patents

Abstract

To provide a voltage detection circuit in which an increase of an area of the voltage detection circuit connected with a multi-cell secondary battery can be suppressed, a charge control circuit, a charging and discharge control circuit, and a semiconductor device.SOLUTION: A voltage detection circuit 50 comprises: a gate (hereinbelow, G) to which a voltage detected is applied; an enhancement type transistor (hereinbelow, ETr) containing a source (hereinbelow, S) connected to a power supply terminal 9; an ETr 54 containing the G connected to the G of the ETr 51, D connected to a drain (hereinbelow, D) of the ETr 51, the S connected to the G of the ETr 51 and the G of itself, and a back gate connected to the power supply terminal 9; a depression type transistor (hereinbelow, DTr) 52 containing a first end connected to the ETr 51 and a second end connected to an output terminal P3; a DTr 53 containing the D and G of the ETr 51, connected to a power supply terminal 8, and the S connected to the G itself; and an ETr 63 vertically connected to the DTr 53.SELECTED DRAWING: Figure 2

Description

The present invention relates to a voltage detection circuit, a charging control circuit, a charging/discharging control circuit, and a semiconductor device.

From the viewpoint of obtaining higher voltage, a battery device incorporating a secondary battery having a plurality of battery cells connected in series (hereinafter referred to as "multi-cell") is sometimes applied. In a circuit to which multi-cell secondary batteries are connected, in a voltage detection circuit that detects the voltage between intermediate terminals, if the intermediate terminal is short-circuited to the power supply terminal or ground terminal, that is, short-circuited to the power source or ground, one battery A voltage higher than that of a battery device incorporating a cell (hereinafter referred to as a "single cell") secondary battery is applied to the intermediate terminal. BACKGROUND ART A charging/discharging control circuit is known that includes a voltage detection circuit having a comparator to detect a power supply fault or a ground fault of an intermediate terminal as an abnormality during charging/discharging (see, for example, Patent Document 1). Note that from the viewpoint of simplifying the configuration of the voltage detection circuit, it is also possible to replace the comparator with a simpler voltage detection circuit.

FIG. 8 schematically shows the main configuration of a charge/discharge control circuit 100, which is an example of a conventional charge/discharge control circuit, including a conventional voltage detection circuit 30 that is a simpler configuration of the comparator described in Patent Document 1. FIG. Here, if n is a natural number greater than or equal to 2 and is the number of battery cells connected in series in a secondary battery having a multi-cell configuration, then the charge/discharge control circuit 100 controls a secondary battery having n battery cells connected in series. It is configured so that it can be connected to. FIG. 8 shows the final stage voltage detection circuit 30 and level shifter 40 connected to the last battery cell from the positive electrode side to the negative electrode side of the secondary battery.

In FIG. 8, the charge/discharge control circuit 100 includes a voltage detection circuit 30, a level shifter 40, an overvoltage determination circuit 12, and a control circuit 15. The voltage detection circuit 30 and the level shifter 40 are configured using a MOS transistor, which is an example of a field effect transistor (hereinafter referred to as "FET"). The voltage detection circuit 30 includes an enhancement type NMOS transistor 31 and a depletion type NMOS transistor 32. The level shifter 40 includes an enhancement type PMOS transistor 41 and a constant current source 42.

The NMOS transistor 31 has a drain and a connection point P_(n-1) between a resistor 21_(n-1) and a resistor 22_(n-1) connected in series between the positive electrode and the negative electrode of one battery cell. It includes a gate connected to it, and a source connected to the negative power supply input terminal VSS. The negative power supply input terminal VSS is connected to a power supply terminal 9 to which a voltage Vss, which is a power supply voltage, is supplied. The NMOS transistor 32 has a drain connected to a power supply terminal 8 to which a voltage Vdd, which is a power supply voltage different from the voltage Vss, is supplied, a source connected to the drain of the NMOS transistor 31, and a gate shorted to its own source. Contains. Further, a connection point between the drain of the NMOS transistor 31 and the source of the NMOS transistor 32 is connected to the gate of the PMOS transistor 41.

PMOS transistor 41 includes a source connected to power supply terminal 8, a gate connected to the drain of NMOS transistor 31 and the source of NMOS transistor 32, and a drain. Constant current source 42 includes a first end connected to the drain of PMOS transistor 41 and a second end connected to negative power input terminal VSS. A second end of the constant current source 42 and a connection point between the drain of the PMOS transistor 41 and the first end of the constant current source 42 are connected to the overvoltage determination circuit 12 at the subsequent stage.

The overvoltage determination circuit 12 has a function of determining whether each cell 2_1, . . . , 2_n is overvoltage based on the input voltages at both ends. When the voltage of the negative power supply input terminal VSS and the voltage of the drain of the PMOS transistor 41 are input to the overvoltage determination circuit 12, it is determined whether each cell 2_1, . . . , 2_n is at an overvoltage. The determination result by the overvoltage determination circuit 12 is transmitted from the overvoltage determination circuit 12 to the control circuit 15.

The control circuit 15 outputs a charging control signal output terminal CO in response to signals input from other circuits including circuits other than the overvoltage determination circuit 12 such as an overdischarge detection circuit and an overcharge detection circuit (not shown). Alternatively, it is configured to be able to output a control signal for switching the transistor on and off to the discharge control signal output terminal DO.

Japanese Patent Application Publication No. 2020-10536

In a conventional circuit to which a multi-cell secondary battery is connected, such as the charge/discharge control circuit 100 illustrated in FIG. The signal level at the drain of is inverted from a high (hereinafter referred to as "H") level to a low (hereinafter referred to as "L") level. That is, the voltage detection circuit 30 can detect the presence or absence of short-to-power based on the signal level of the drain of the NMOS transistor 31. The withstand voltage of the element receiving the voltage of the cell connection terminal VC(n-1), which is an intermediate terminal of the voltage detection circuit 30, is determined in consideration of the voltage of the secondary battery. This means that if the path connecting the positive terminals of n battery cells and the cell connection terminal VC(n-1) is shorted to power (short circuited to the power supply terminal 8), the gate of the NMOS transistor 31 is connected to the This is because a voltage obtained by connecting battery cells in series is applied.

The breakdown voltage of the NMOS transistor 31 and the NMOS transistor 32 is determined by considering the voltage level of the secondary battery, that is, the size of n, and the breakdown voltage becomes higher as the number of battery cells increases. A semiconductor element such as the NMOS transistor 31 has a disadvantage that the higher the breakdown voltage, the larger the element area, and therefore the larger the number of battery cells, the larger the area of the voltage detection circuit. Furthermore, in order to achieve low power consumption while ensuring breakdown voltage, it is necessary to increase the channel length (L length), so the tendency for the area of the circuit to increase becomes noticeable.

The present invention has been made in view of the above-mentioned circumstances, and provides a voltage detection circuit, a charge control circuit, a charge/discharge control circuit, and a semiconductor capable of suppressing an increase in the area of a voltage detection circuit connected to a multi-cell secondary battery. The purpose is to provide equipment.

A voltage detection circuit according to an embodiment of the present invention includes an input transistor including a gate to which a voltage to be detected is applied, a source connected to a first power supply terminal, and a drain, and an input transistor connected to the gate of the input transistor. a drain connected to the drain of the input transistor, a source connected to the gate of the input transistor and its own gate, and a back gate connected to the first power supply terminal; , a first transistor including a first end connected to the input transistor and a second end connected to an output end from which a signal indicating a voltage detection result is output; and a second power supply terminal. It is characterized by comprising a second transistor including a drain, a gate, and a source connected to its own gate, and a third transistor connected in cascade with the second transistor.

According to the present invention, it is possible to suppress an increase in area of a voltage detection circuit connected to a multi-cell secondary battery as the number of cells increases.

1 is a schematic diagram showing a configuration example of a charge/discharge control circuit and a semiconductor device according to a first embodiment of the present invention. 1 is a circuit diagram schematically showing the main configuration of a voltage detection circuit according to a first embodiment of the present invention and a charge/discharge control circuit according to a first embodiment including the voltage detection circuit; FIG. FIG. 2 is a circuit diagram schematically showing the main configuration of a voltage detection circuit according to a second embodiment of the present invention. FIG. 2 is a circuit diagram schematically showing the main configuration of another configuration example (first modification) of the voltage detection circuit according to the embodiment of the present invention. FIG. 2 is a circuit diagram schematically showing the main configuration of another configuration example (second modification) of the voltage detection circuit according to the embodiment of the present invention. FIG. 3 is a circuit diagram schematically showing the main configuration of another configuration example (third modification) of the voltage detection circuit according to the embodiment of the present invention. FIG. 7 is a schematic diagram showing another configuration example (fourth modification) of the charging control circuit according to the embodiment of the present invention and the semiconductor device according to the embodiment of the present invention. FIG. 2 is a circuit diagram schematically showing the main components of a conventional charge/discharge control circuit, including a conventional voltage detection circuit.

EMBODIMENT OF THE INVENTION Hereinafter, a voltage detection circuit, a charge control circuit, a charge/discharge control circuit, and a semiconductor device according to embodiments of the present invention will be described with reference to the drawings. In the following description, components that are not substantially different from the charge/discharge control circuit 100 shown in FIG. 8 as an example of a conventional charge/discharge control circuit will be designated by the same reference numerals and the explanation thereof will be omitted.

[First embodiment]
FIG. 1 is a block diagram showing a circuit configuration of a battery device 1, which is an example of a semiconductor device according to a first embodiment of the present invention.

The battery device 1 includes a semiconductor integrated circuit formed on a semiconductor substrate by a semiconductor process, specifically an IC chip including a charge/discharge control circuit 10 that controls charging and discharging of the secondary battery 2.

The battery device 1 and the charge/discharge control circuit 10 are examples of the semiconductor device and the charge/discharge control circuit according to the first embodiment, respectively. The battery device 1 includes a secondary battery 2 including a so-called multi-cell assembled battery, an external positive terminal P+, an external negative terminal P-, a discharge control FET (Field Effect Transistor) 3, a charging control FET 4, and a secondary A charging/discharging control circuit 10 for controlling charging/discharging of the battery 2 is provided.

The secondary battery 2 is a so-called multi-cell battery including an assembled battery in which n battery cells (hereinafter simply referred to as "cells") 2_1 to 2_n are connected in series, where "n" is the number of cells connected in series. It is a cell battery. In the case of a multi-cell battery, n is a natural number of 2 or more, ie, a plurality. The n cells 2_1, ..., 2_n are connected in series in this order from the positive electrode 2a of the secondary battery 2 to the negative electrode 2b of the secondary battery 2.

The charge/discharge control device 20 includes an external positive terminal P+, an external negative terminal P−, a discharge control FET 3, a charge control FET 4, and a charge/discharge control circuit 10. That is, the charge/discharge control device 20 as a semiconductor device is a device obtained by omitting the secondary battery 2 from the battery device 1.

The external positive terminal P+ and the external negative terminal P- are terminals for connecting to external devices (not shown) such as a charger and a load, for example. In the battery device 1, the path connecting the external positive terminal P+ and the external negative terminal P- (hereinafter referred to as the "path between external terminals") includes, for example, the secondary battery 2 in order from the external positive terminal P+ side. , an overcurrent detection resistor 5, a discharge control FET 3, and a charge control FET 4 are connected.

The battery device 1 and the charge/discharge control device 20 include a discharge control FET 3 and a charge control FET 4 on the external negative terminal P- side, that is, on the low side. The discharge control FET3 and the charge control FET4 are both NMOS transistors, and their drains are connected to each other.

The discharge control FET 3 has a gate connected to the discharge control signal output terminal DO, a drain as one end connected to the drain of the charge control FET 4, and a source as the other end connected to one end of the overcurrent detection resistor 5. Contains.

The charging control FET 4 has a gate connected to the charging control signal output terminal CO, a source as one end connected to the external negative terminal P-, and a drain as the other end connected to the drain of the discharge control FET 3. Contains.

The charge/discharge control circuit 10 includes a positive power supply input terminal VDD, a negative power supply input terminal VSS, cell connection terminals VC1, ..., VC(n-1), a charge control signal output terminal CO, a discharge control signal output terminal DO, and an external It includes a negative voltage input terminal VM and an overcurrent detection terminal VINI.

A positive power input terminal VDD serving as a first power input terminal is connected to the positive electrode 2a via a resistor R1, and is supplied with voltage from the positive electrode 2a of the secondary battery 2. A negative power input terminal VSS serving as a second power input terminal is connected to the negative electrode 2b, and is supplied with voltage from the negative electrode 2b.

The cell connection terminal VC1 is connected to the contact point of the first cell 2_1 and the second cell 2_2, that is, the negative terminal of the first cell 2_1 and the positive terminal of the second cell 2_2, via a resistor R2. Hereinafter, in the same manner as the cell connection terminal VC1, the cell connection terminals VC2, ..., VC(n-1) are connected to the negative terminal and the negative terminal of the second cell 2_2 through the resistors R3, ..., Rn, respectively. The positive terminal of the third cell 2_3, . . . , is connected to the negative terminal of the (n−1)th cell 2_(n−1) and the positive terminal of the nth cell 2_n.

Here, the ends of the resistors R1, ..., Rn connected to the first cell 2_1 to the nth cell 2_n (the left end in FIG. 1) are referred to as the first ends, and the positive power input terminal VDD and the cell connection terminal The end connected to VC1, .

A capacitor C1 for suppressing voltage fluctuations is connected between a contact point between the second end of the resistor R1 and the positive power input terminal VDD, and a contact point between the negative electrode 2b and the negative power input terminal VSS. Hereinafter, in the same way as the capacitor C1, the capacitors C2, ..., Cn are connected to the second ends of the resistors R2, ..., Rn and the cell connection terminals VC1, ..., VC(n-1), respectively. and a contact between the negative electrode 2b and the negative power input terminal VSS.

The charging control signal output terminal CO is a terminal that outputs a charging control signal generated within the charging and discharging control circuit 10 that controls stopping and permission of charging of the secondary battery 2 to the outside of the charging and discharging control circuit 10. The charging control signal output terminal CO is connected to the gate of the charging control FET4.

The discharge control signal output terminal DO is a terminal that outputs, to the outside of the charge and discharge control circuit 10, a discharge control signal that controls stopping and permission of discharging of the secondary battery 2 generated within the charge and discharge control circuit 10. The discharge control signal output terminal DO is connected to the gate of the discharge control FET3.

The external negative voltage input terminal VM is connected to the external negative terminal P- and the source of the charge control FET 4 via a resistor 6.

The overcurrent detection terminal VINI is connected to one end of the overcurrent detection resistor 5 and the source of the discharge control FET 3.

FIG. 2 is a circuit diagram schematically showing the main configuration of the charge/discharge control circuit 10, which is an example of the charge/discharge control circuit according to the present embodiment.

The charge/discharge control circuit 10 is different from the charge/discharge control circuit 100 (see FIG. 8) in that it includes a voltage detection circuit 50 instead of the voltage detection circuit 30 (see FIG. 8), but is substantially the same in other respects. There is no difference. Therefore, in the description of the charge/discharge control circuit 10, the voltage detection circuit 50 will be mainly explained, and components such as the level shifter 40 (see FIG. 8), which are not substantially different, will be given the same reference numerals and the description will be simplified or simplified. Omitted.

The charge/discharge control circuit 10 includes a voltage detection circuit 50 that is an example of a voltage detection circuit according to this embodiment, a level shifter 40, an overvoltage determination circuit 12, and a control circuit 15. The voltage detection circuit 50 differs from the voltage detection circuit 30 in that it includes an enhancement type NMOS transistor 51 instead of the NMOS transistor 31, a protection circuit 60 instead of the NMOS transistor 32, and a depletion type NMOS transistor. 52, a depletion type NMOS transistor 53, and an enhancement type NMOS transistor 54.

The NMOS transistor 51 as an input transistor is connected in the same way as the NMOS transistor 31, but its withstand voltage is lower than that of the NMOS transistor 31, and is a relatively low withstand voltage FET. That is, the NMOS transistor 51 has a smaller area than the NMOS transistor 31. The NMOS transistor 51 is set to have a gate breakdown voltage that is at least higher than the voltage applied to the gate in a normal state where no supply fault or ground fault occurs, specifically, higher than the voltage of one cell.

The NMOS transistor 52, which is an example of a FET, is a so-called cascode transistor, and is connected to ensure the drain-source voltage VDS of the NMOS transistor 51 to some extent. NMOS transistor 52 includes a source as a first end connected to the drain of NMOS transistor 51. A connection point between the source of the NMOS transistor 52 and the drain of the NMOS transistor 51 constitutes a node P2. Further, the NMOS transistor 52 includes a gate connected to the gate of the NMOS transistor 51 and a drain serving as a second end connected to the output terminal P3 of the voltage detection circuit 50. That is, the drain of the NMOS transistor 52 is connected to the level shifter 40 (more specifically, the gate of the PMOS transistor 41) in the circuit subsequent to the voltage detection circuit 50.

The NMOS transistor 54 as a bypass transistor has a gate connected to the gate of the NMOS transistor 51 and the gate of the NMOS transistor 52, a source connected to the gate of the NMOS transistor 51 and its own gate, and a drain of the NMOS transistor 51 and the NMOS transistor 54. It includes a drain connected to the source of the transistor 52 and a back gate connected to the source of the NMOS transistor 51 and the power supply terminal 9. A connection point between the drain of the NMOS transistor 54, the drain of the NMOS transistor 51, and the source of the NMOS transistor 52 constitutes a node P2. Like the NMOS transistor 51, the NMOS transistor 54 is a relatively low-voltage FET that is lower than the withstand voltage of the NMOS transistor 31.

NMOS transistor 53 includes a drain connected to power supply terminal 8, a gate, and a source connected to its own gate, and operates as a constant current source. The connection point between the NMOS transistor 53 and the protection circuit 60 constitutes a node P1. Since the NMOS transistor 53 can be protected against voltage by the protection circuit 60, a relatively low voltage FET can be used.

The protection circuit 60 includes, for example, PMOS transistors 61, 62, and 63, which are examples of FETs, and a constant current source 65.

The PMOS transistor 61 includes a source connected to the power supply terminal 8, a gate, and a drain connected to its own gate. The PMOS transistor 62 includes a source connected to the drain of the PMOS transistor 61, a gate, and a drain connected to its own gate. The PMOS transistor 63 has a source connected to the gate and source of the NMOS transistor 53, a gate connected to the gate and drain of the PMOS transistor 62, and a drain connected to the drain of the NMOS transistor 52 and the gate of the PMOS transistor 41. , contains.

Constant current source 65 includes a first end connected to the gate and drain of PMOS transistor 62 and the gate of PMOS transistor 63, and a second end connected to power supply terminal 9.

In the protection circuit 60, two cascade-connected PMOS transistors 61 and 62 and a constant current source 65 that supplies drain current to the PMOS transistors 61 and 62 constitute a clamp circuit. The PMOS transistor 63 constitutes an output transistor of the protection circuit 60 whose gate receives the output voltage from the clamp circuit. The PMOS transistors 61, 62, and 63 have a breakdown voltage comparable to that of the NMOS transistor 32.

The overvoltage determination circuit 12 has a function of determining whether or not each cell 2_1, ..., 2_n is overvoltage based on the input voltage at both ends, and determines whether or not each cell 2_1, ..., 2_n is overvoltage. It is configured so that it can be determined. The control circuit 15 generates a charging control signal in response to signals input from other circuits including circuits other than the overvoltage determination circuit 12 including at least one of an overdischarge detection circuit and an overcharge detection circuit (not shown). It is configured such that a control signal for switching the transistor on and off can be supplied to the output terminal CO or the discharge control signal output terminal DO.

Next, an example of a case where the highest voltage is applied to the voltage detection circuit 50, specifically a case where the cell connection terminal VC (n-1) is shorted to power (shorted to the power supply terminal 8) will be given as an example. The operation of the voltage detection circuit 50 will be explained.

In the normal state before the cell connection terminal VC(n-1) is shorted to power, the NMOS transistor 51 and the NMOS transistor 54 are off. The voltage at node P2 is voltage Vdd. The voltage at the output terminal P3 of the voltage detection circuit 50 corresponds to a signal indicating the voltage detection result, and is at H level in a normal state.

When the cell connection terminal VC(n-1) is shorted to power, the voltage Vdd of the power supply terminal 8, that is, the voltage corresponding to the voltage of the secondary battery 2 is applied to the gate of the NMOS transistor 51. After the cell connection terminal VC(n-1) is shorted to power, the voltage at the gate of the NMOS transistor 51 gradually increases, and eventually exceeds the threshold voltage of the NMOS transistor 51. When the voltage at the gate of the NMOS transistor 51 exceeds the threshold voltage of the NMOS transistor 51, the NMOS transistor 51 turns on and becomes conductive.

When the NMOS transistor 51 becomes conductive, the voltage at the node P2 decreases to "the voltage at the gate of the NMOS transistor 51 - the threshold voltage of the NMOS transistor 52". As the voltage at node P2 decreases, the voltage at output terminal P3 also decreases, making a transition from H level to L level. That is, a signal indicating that a short-to-power supply of the cell connection terminal VC(n-1) has been detected is output from the output terminal P3 to the level shifter 40. The voltage at the node P2 is higher than the voltage at the gate of the NMOS transistor 51 because the threshold voltage of the NMOS transistor 52 is negative. Even after the NMOS transistor 51 becomes conductive, the NMOS transistor 54 remains off until the voltage at the gate of the NMOS transistor 51 reaches the reference voltage Vref. While the NMOS transistor 54 remains off, the voltage at the node P2 is maintained higher than the voltage at the gate of the NMOS transistor 51.

Furthermore, when the voltage at the gate of the NMOS transistor 51 increases and becomes equal to or higher than the reference voltage Vref, the NMOS transistor 54 turns on and becomes conductive. When the NMOS transistor 54 is turned on and conductive, the voltage at the node P2 decreases to "voltage at the gate of the NMOS transistor 51 - threshold voltage of the NMOS transistor 51 - overdrive voltage of the NMOS transistor 51".

Here, the voltage at the same node as the gate of the NMOS transistor 51 is higher than the voltage at the node P2 due to the relationship between the threshold voltage and the overdrive voltage of the NMOS transistor 51. Therefore, a bypass current flows from the drain to the source of the NMOS transistor 51 via the NMOS transistor 54 so that the voltage at the gate of the NMOS transistor 51 is clamped to the reference voltage Vref. As a result, the voltage rise at the gate of the NMOS transistor 51 is suppressed to around the reference voltage Vref.

The protection circuit 60 protects the NMOS transistor 53 from overvoltage by clamping the source voltage of the NMOS transistor 53 that operates as a constant current source, that is, the voltage of the node P1, to a predetermined voltage. The predetermined voltage is set in consideration of the voltage Vdd of the power supply terminal 8, the source-drain voltage of the NMOS transistor 53 when it is conductive, and the withstand voltage of the NMOS transistor 53. For example, if the PMOS transistors 61, 62, and 63 are all FETs having the same threshold voltage |Vthp|, the voltage at the node P1 is clamped to the voltage (Vdd-|Vthp|).

The signal processing subsequent to the voltage detection circuit 50 is the same as that of the conventional charge/discharge control circuit 100 and the charge/discharge control device and battery device including the charge/discharge control circuit 100. That is, in the example of FIG. 2, the overvoltage determination circuit 12 determines whether the cell 2_n is overvoltage based on the voltage input from the voltage detection circuit 50 via the level shifter 40, and responds to the determination result. A signal is transmitted to the control circuit 15. Based on the signal corresponding to the received determination result, the control circuit 15 supplies a control signal for switching the charge control FET 4 between on and off to the charge control signal output terminal CO, while switching the discharge control FET 3 between on and off. A control signal is supplied to the discharge control signal output terminal DO.

According to the voltage detection circuit 50, the charge/discharge control circuit 10, the charge/discharge control device 20, and the battery device 1 including the voltage detection circuit 50, the NMOS transistor 51 includes a gate to which the voltage input to the voltage detection circuit 50 is applied. The input voltage to can be suppressed lower than before. Since the input voltage to the NMOS transistor 51 can be suppressed lower than before, the breakdown voltage of the NMOS transistor 51 can be suppressed lower than the breakdown voltage of the NMOS transistor 31 of the conventional voltage detection circuit 30 (see FIG. 8).

Further, the breakdown voltages of the NMOS transistor 53 and the NMOS transistor 54 can be suppressed to the same level as the NMOS transistor 51 (relatively low breakdown voltage). Furthermore, due to the difference in function between the NMOS transistor 53 and the NMOS transistor 54, it is possible to apply a channel length (L length) that is sufficiently short (about 1 to 2 orders of magnitude smaller) than that of the NMOS transistor 51. can. On the other hand, the NMOS transistor 52 and the PMOS transistors 61, 62, and 63 require the same breakdown voltage as the NMOS transistor 31 and the NMOS transistor 32, but due to the difference in their functions, the channel length (L length) is shorter. It can be made shorter (about 1 to 2 orders of magnitude smaller).

Therefore, although the voltage detection circuit 50 has an increased number of elements compared to the voltage detection circuit 30, the area of each individual element is smaller than the NMOS transistor 31 and the NMOS transistor 32. The area of the voltage detection circuit 50 can be kept small compared to the area of the circuit 30. Further, although the area of each circuit of the voltage detection circuit 50 and the voltage detection circuit 30 increases, the voltage detection circuit 50, the charge/discharge control circuit 10, the charge/discharge control device 20, and the battery device 1 including the voltage detection circuit 50 For example, even if n, which is the number of cells 2_1 to 2_n connected in series, is large and the voltage of the secondary battery 2 is high, the increase in area of the voltage detection circuit 50 is equal to the increase in area of the voltage detection circuit 30. can be kept smaller than.

According to the voltage detection circuit 50, the charge/discharge control circuit 10, the charge/discharge control device 20, and the battery device 1 including the voltage detection circuit 50, the input voltage of the NMOS transistor 51 can be suppressed lower than before, so that the PBTI( Positive Bias Temperature Instability) can be suppressed more than before. Furthermore, since PBTI can be suppressed more than before, the threshold voltage shift of the N-type transistor can be suppressed, and the detection voltage shift after a long-term reliability test can be suppressed more than before.

Further, since the voltage detection circuit 50 includes the NMOS transistor 52 connected in cascade with the NMOS transistor 51, the drain-source voltage VDS of the NMOS transistor 51 can be kept constant. That is, the drain-source voltage VDS of the NMOS transistor 51 can be made to be a voltage that is not dependent on the voltage Vdd.

Although the voltage detection circuit 50 described above has a clamp circuit in the protection circuit 60, this may be used as long as the PMOS transistor 63 has a configuration that can receive a clamped voltage at its gate. Not limited. For example, if a clamp circuit is provided outside the voltage detection circuit 50 and the output voltage of the clamp circuit can be used, the PMOS transistor 63 including the gate to which the output voltage of the clamp circuit is applied is connected to the protection circuit 60. You can also use it as

[Second embodiment]
FIG. 3 is a circuit diagram schematically showing the main configuration of a voltage detection circuit 50A, which is an example of a voltage detection circuit according to the second embodiment.

The semiconductor device, charge/discharge control circuit, and voltage detection circuit according to the second embodiment differ from the semiconductor device, charge/discharge control circuit, and voltage detection circuit according to the first embodiment in the configuration of the voltage detection circuit. However, there are no substantial differences in other respects. Therefore, in the description of this embodiment, the voltage detection circuit 50A that is different from the voltage detection circuit 50 will be mainly explained, and other components that are not substantially different from each other will be given the same reference numerals and redundant explanations will be given. Omitted.

The charge/discharge control circuit 10A differs from the charge/discharge control circuit 10 in that it includes a voltage detection circuit 50A instead of the voltage detection circuit 50, but there is no substantial difference in other respects. The voltage detection circuit 50A is different from the voltage detection circuit 30 in that it includes an NMOS transistor 51 instead of the NMOS transistor 31, and further includes an NMOS transistor 52, an NMOS transistor 53, and an NMOS transistor 54. , there are no other substantial differences. Further, the voltage detection circuit 50A differs from the voltage detection circuit 50 in that it includes an NMOS transistor 32 instead of the protection circuit 60, but there is no substantial difference in other respects.

In the NMOS transistor 53 in the voltage detection circuit 50A, an NMOS transistor 32 is connected between the drain and the power supply terminal 8 to protect the NMOS transistor 53 from overvoltage. That is, the NMOS transistor 32 serving as the third transistor is connected in cascade with the NMOS transistor 53 (more specifically, the gate and source). Further, the NMOS transistor 53 has its own gate and source connected, and is also connected to the gate of the NMOS transistor 32 , the drain of the NMOS transistor 52 , and the gate of the PMOS transistor 41 . The gate and source of the NMOS transistor 53 are the output terminal P3 in the voltage detection circuit 50A.

Next, we will explain the operation of the voltage detection circuit 50A using an example where the highest voltage is applied to the voltage detection circuit 50A, specifically a case where the cell connection terminal VC (n-1) is shorted to power. explain.

The voltage detection circuit 50A is different from the voltage detection circuit 50, which protects the NMOS transistor 53 with withstand voltage using the protection circuit 60, in that the NMOS transistor 53 is protected withstand voltage using the NMOS transistor 32, but includes a protection operation for the NMOS transistor 51. Overall circuit operation is not substantially different. A description of the circuit operation of the voltage detection circuit 50A will be omitted with a description of the circuit operation of the voltage detection circuit 50.

According to the voltage detection circuit, charge/discharge control circuit, charge/discharge control device, and battery device according to the second embodiment, the voltage detection circuit, charge/discharge control circuit, charge/discharge control device, and battery device according to the first embodiment You can get the same effect as .

Further, in the voltage detection circuit 50A, the number of FETs having a relatively high breakdown voltage can be further reduced compared to the voltage detection circuit 50, so that the circuit area can be further reduced. Therefore, even if n, which is the number of cells 2_1 to 2_n connected in series, is large and the voltage of the secondary battery 2 is high, the increase in the area of the voltage detection circuit 50A is compensated for by the voltage detection circuit 30 and the voltage detection circuit This can be suppressed to less than the area increase of 50.

It should be noted that the present invention is not limited to the above-mentioned embodiments as they are, and at the implementation stage, it is possible to implement them in various forms other than the above-mentioned embodiments, and within the scope of the gist of the invention, Various omissions, additions, substitutions, or changes may be made. Therefore, some modifications of the present invention will be described with reference to some examples.

(First modification)
FIG. 4 is a schematic diagram showing the configuration of a voltage detection circuit 50B, which is another configuration example (first modification) of the voltage detection circuit according to the embodiment of the present invention.

The voltage detection circuit 50B differs from the voltage detection circuit 50A in that it includes an enhancement type NMOS transistor 72 instead of the depletion type NMOS transistor 52, but is substantially the same in other respects. Note that since the NMOS transistor 72 has a positive threshold voltage, its gate is not at the connection point P_(n-1) but rather than the connection point P_(n-1), such as the connection point P_(n-2). Although it differs from the NMOS transistor 52 in that it is connected to a high voltage connection point, its operation and function are essentially the same as the NMOS transistor 52.

The voltage detection circuit 50B configured in this manner operates in the same manner as the voltage detection circuit 50A, and can obtain similar effects. Therefore, in the voltage detection circuit according to the embodiment of the present invention, the charge/discharge control circuit, the charge/discharge control device, and the battery device including the voltage detection circuit, the voltage detection circuit 50B may be applied instead of the voltage detection circuit 50A. good. In other words, in the charge/discharge control circuit 10B, the charge/discharge control device 20, and the battery device 1 in which the voltage detection circuit 50A is replaced with the voltage detection circuit 50B, the charge/discharge control circuit 10A, the charge/discharge control device 20, and the charge/discharge control circuit 10A including the voltage detection circuit 50A, It functions in the same manner as the battery device 1 and can obtain similar effects.

(Second modification)
FIG. 5 is a schematic diagram showing the configuration of a voltage detection circuit 50C which is another configuration example (second modification) of the voltage detection circuit according to the embodiment of the present invention.

The voltage detection circuit 50C is different from the voltage detection circuit 50A in that it further includes a current mirror circuit 56 having two PMOS transistors 561 and 562, and in the arrangement of the NMOS transistors 32 and 56. , there are no other substantial differences. Therefore, in the description of the voltage detection circuit 50C, substantially the same components such as the NMOS transistor 51 are given the same reference numerals, and the description thereof will be omitted.

The voltage detection circuit 50C includes an NMOS transistor 32, an NMOS transistor 51, an NMOS transistor 52, an NMOS transistor 53, an NMOS transistor 54, and a current mirror circuit 56. In the current mirror circuit 56, the PMOS transistor 561 includes a source connected to the power supply terminal 8, a gate connected to the gate of the PMOS transistor 562, and a drain. Further, the PMOS transistor 562 includes a source connected to the power supply terminal 8, a gate connected to the gate of the PMOS transistor 561, and a drain connected to the gate of itself (PMOS transistor 562). The current flowing through the drain of PMOS transistor 561 is configured to be equal to the current flowing through the drain of PMOS transistor 562.

The drain of the PMOS transistor 561 is connected to the output terminal P3 of the voltage detection circuit 50C and the drain of the NMOS transistor 52. On the other hand, the NMOS transistor 32 and the NMOS transistor 53 in the voltage detection circuit 50A are connected between the drain of the PMOS transistor 562 and the power supply terminal 9. Specifically, the source of the NMOS transistor 32 and the drain of the NMOS transistor 53 are connected. The gate of the NMOS transistor 53 is connected to the gate of the NMOS transistor 32 and the source of the NMOS transistor 53. A connection point between the gate of the NMOS transistor 32, the gate of the NMOS transistor 53, and the source of the NMOS transistor 53 is connected to the power supply terminal 9.

The voltage detection circuit 50C configured in this manner operates in the same manner as the voltage detection circuits 50A and 50B, and can obtain similar effects. In other words, in the charging/discharging control circuit 10C, the charging/discharging control device 20, and the battery device 1 in which the voltage detecting circuit 50A is replaced with the voltage detecting circuit 50C, the charging/discharging control circuit 10A, the charging/discharging control device 20, and the charging/discharging control circuit 10A including the voltage detecting circuit 50A, It functions in the same manner as the battery device 1 and can obtain similar effects.

(Third modification)
FIG. 6 is a schematic diagram showing the configuration of a voltage detection circuit 50D which is another configuration example (third modification) of the voltage detection circuit according to the embodiment of the present invention.

Voltage detection circuit 50D is different from voltage detection circuit 50C in that it includes an enhancement type NMOS transistor 72 instead of depletion type NMOS transistor 52, but is not substantially different in other respects. In other words, the voltage detection circuit 50D is a circuit to which the modification contents of the first modification are applied to the voltage detection circuit 50C.

The voltage detection circuit 50D configured in this manner operates in the same manner as the voltage detection circuits 50A, 50B, and 50C, and can obtain the same effects. In other words, even in the charge/discharge control circuit 10D, the charge/discharge control device 20, and the battery device 1 in which the voltage detection circuit 50A is replaced with the voltage detection circuit 50D, the charge/discharge control circuit 10A, the charge/discharge control device 20, and the charge/discharge control circuit 10A including the voltage detection circuit 50A, It functions in the same manner as the battery device 1 and can obtain similar effects.

(Fourth modification)
FIG. 7 schematically shows the configurations of a charging control circuit 210, a charging control device 220, and a battery device 201, which is another configuration example (fourth modification) of the charging control circuit and semiconductor device according to the embodiment of the present invention. It is a diagram.

The charging control device 220 is a so-called fuse-protected charging control device, and includes an open circuit 80 including a fuse 81 and a fuse 82, and a charging control circuit 210. Fuse 81 and fuse 82 are connected in series with each other. Specifically, one end of the fuse 82 is connected to the EB+ terminal. The other end of the fuse 82 is connected to one end of the fuse 81. The other end of the fuse 81 is connected to the + pole of the first cell 2_1. The charging control circuit 210 is a circuit that is different from the charging and discharging control circuit 10 (see FIG. 2) in that the discharge control terminal DO and the signal path connected to the discharge control terminal DO are omitted, and other parts are substantially the same. The circuit is no different from the above.

The charge control FET 4 is, for example, an N-channel field effect transistor having a gate, a source, and a drain. The gate is connected to the CO terminal of charging control circuit 210. The source is connected to the EB- terminal. The drain is connected to one end of the resistor 85. The charge control FET 4 performs on/off control between the source terminal and the drain terminal based on a signal output from the CO terminal. The other end of the resistor 85 is connected to the connection between the fuse 81 and the fuse 82 . The resistor 85 functions as a heater element that blows out the fuse 81 and the fuse 82 when the charging control FET 4 is on.

Like the charge control device 220 and battery device 201 described above, a semiconductor device having a configuration different from that of the charge/discharge control device 20 and the battery device 1 may be employed as the semiconductor device according to the embodiment of the present invention. According to the charge control device circuit 210, the charge control device 220, and the battery device 201, the same effects as the charge and discharge control circuit 10, the charge and discharge control device 20, and the battery device 1 can be obtained.

Note that the above-mentioned MOS transistor is shown as an example of a FET, and any type of FET may be used. For example, a type of FET different from a MOSFET, such as a junction FET (JFET) or a metal-insulating-film-semiconductor FET (MISFET), may be applied.

These embodiments and their modifications are included within the scope and gist of the invention, as well as within the scope of the invention described in the claims and its equivalents.

1,201 Battery device (semiconductor device)
2 Secondary battery 3 Discharge control FET
4 Charge control FET
8 Power supply terminal 9 Power supply terminal 10, 10A, 10B, 10C, 10D Charge/discharge control circuit 210 Charge control circuit 12 Overvoltage determination circuit 15 Control circuit 20 Charge/discharge control device (semiconductor device)
220 Charging control circuit (semiconductor device)
50, 50A, 50B, 50C, 50D Voltage detection circuit 32 Depletion type NMOS transistor (third transistor)
51 Enhancement type NMOS transistor (input transistor)
52 Depletion type NMOS transistor (first transistor)
53 Depletion type NMOS transistor (second transistor)
54 Enhancement type NMOS transistor (bypass transistor)
63 Enhancement type PMOS transistor (third transistor)
80 Open circuit 81, 82 Fuse CO Charge control signal output terminal DO Discharge control signal output terminal

Claims (9)

an input transistor including a gate to which a voltage to be detected is applied, a source connected to a first power supply terminal, and a drain;
a gate connected to the gate of the input transistor; a drain connected to the drain of the input transistor; a source connected to the gate of the input transistor and its own gate; and a source connected to the first power supply terminal. a bypass transistor including a back gate;
a first transistor including a first end connected to the input transistor and a second end connected to an output end from which a signal indicating a voltage detection result is output;
a second transistor including a drain connected to a second power supply terminal, a gate, and a source connected to its own gate;
a third transistor connected in cascade with the second transistor;
A voltage detection circuit comprising: The third transistor has a drain connected to the second power supply terminal, a gate connected to the gate and source of the second transistor, and a source connected to the drain of the second transistor. 2. The voltage detection circuit according to claim 1, wherein the voltage detection circuit is a depletion type transistor. The third transistor is an enhancement type transistor including a source connected to the gate and source of the second transistor, a drain connected to a second end of the first transistor, and a gate. The voltage detection circuit according to item 1. The voltage detection circuit according to any one of claims 1 to 3,
a first power input terminal and a second power input terminal;
a charging control signal output terminal connected to a gate of a charging control FET that controls charging of a secondary battery including an assembled battery in which a plurality of battery cells are connected in series;
an overvoltage determination circuit that can determine whether or not the secondary battery is overvoltage based on the voltage output from the voltage detection circuit;
a control circuit capable of supplying a control signal for switching the charge control FET between on and off to the charge control signal output terminal in accordance with a signal input from another circuit including the overvoltage determination circuit;
A charging control circuit comprising: The voltage detection circuit according to any one of claims 1 to 3,
a first power input terminal and a second power input terminal;
a charging control signal output terminal connected to a gate of a charging control FET that controls charging of a secondary battery including an assembled battery in which a plurality of battery cells are connected in series;
a discharge control signal output terminal connected to a gate of a discharge control FET that controls discharge of the secondary battery;
an external negative voltage input into which the voltage of the external negative terminal is input, among an external positive terminal and an external negative terminal to which either a charger for charging the secondary battery or a load for discharging the secondary battery is connected; terminal and
an overvoltage determination circuit that can determine whether or not the secondary battery is overvoltage based on the voltage output from the voltage detection circuit;
A control signal for switching the charge control FET on and off is supplied to the charge control signal output terminal in accordance with a signal input from another circuit including the overvoltage determination circuit, and a control signal for switching the charge control FET on and off is supplied to the charge control signal output terminal, while the discharge control FET is turned on and off. a control circuit capable of supplying a control signal for switching between off and off to the discharge control signal output terminal;
A charge/discharge control circuit comprising: A charging control circuit according to claim 4,
an external positive terminal and an external negative terminal to which either a charger for charging the secondary battery or a load for discharging the secondary battery are connected;
the charge control FET whose gate is connected to a charge control signal output terminal;
an open circuit including a fuse connected to the charge control FET;
A semiconductor device comprising: The semiconductor device according to claim 6, further comprising the secondary battery. A charge/discharge control circuit according to claim 5;
the external positive terminal and the external negative terminal;
the discharge control FET, whose drain and source are connected in series with a path connecting the external positive terminal and the external negative terminal, and whose gate is connected to a discharge control signal output terminal;
the charge control FET, whose drain and source are connected in series with a path connecting the external positive terminal and the external negative terminal, and whose gate is connected to a charge control signal output terminal;
A semiconductor device comprising: The semiconductor device according to claim 8, further comprising the secondary battery.

Images