JP2023146779A - Manufacturing method of multilayer ceramic electronic component, multilayer ceramic electronic component, and circuit board - Google Patents

Abstract

To provide a manufacturing method of a multilayer ceramic electronic component capable of suppressing fusion of an external electrode, the multilayer ceramic electronic component, and a circuit board.SOLUTION: A manufacturing method of a multilayer ceramic electronic component includes: a step of preparing an element assembly including a first end face which includes a plurality of dielectric layers and a plurality of internal electrode layers laminated via the plurality of dielectric layers and in which ends of partial internal electrode layers in the plurality of internal electrode layers are exposed, and a second end face in which ends of the other partial internal electrode layers in the plurality of internal electrode layers are exposed and which is opposed with the first end face; a first external electrode forming step of seizing and forming a first external electrode on the first end face; and a second external electrode forming step is seizing and forming a second external electrode, of which the composition is different from that of the first external electrode, on the second end face at a temperature lower than that in the first external electrode forming step by 50°C or more.SELECTED DRAWING: Figure 6

Description

The present invention relates to a method for manufacturing a laminated ceramic electronic component, a laminated ceramic electronic component, and a circuit board.

In multilayer ceramic electronic components such as multilayer ceramic capacitors, external electrodes are formed by applying a metal paste to a fired element body and baking it.

Japanese Patent Application Publication No. 8-306580 Japanese Patent Application Publication No. 8-22930

During this baking process, one of the issues is the fusion of the laminated ceramic electronic component and the jig. Such fusion causes a decrease in yield. Therefore, it is required to bake the external electrodes in a state where no fusion is caused.

As countermeasures against this problem, various efforts have been made so far. For example, it has been disclosed that baking treatment is performed by sprinkling ceramic powder for mold release (for example, see Patent Document 1). However, the ceramic powder itself may also be fused to the external electrode. Therefore, it has been disclosed that a process of producing a conductive paste containing metal powder having various particle shapes, and of forming a baked electrode layer by coating and baking the conductive paste on the outer surface of an element body ( For example, see Patent Document 1). Furthermore, it is disclosed that an adhesive layer is provided on the surface of the pod, and after the external electrodes are applied, a plurality of ceramic electronic components are individually and adhesively held in the adhesive layer, and then the external electrodes are baked. (For example, see Patent Document 2).

However, in the methods of Patent Documents 1 and 2, since the metal paste portion to be baked is in contact with the jig, it is difficult to prevent fusion.

The present invention has been made in view of the above problems, and aims to provide a method for manufacturing a multilayer ceramic electronic component, a multilayer ceramic electronic component, and a circuit board that can suppress fusion of external electrodes.

The method for manufacturing a laminated ceramic electronic component according to the present invention includes a plurality of dielectric layers and a plurality of internal electrode layers laminated via the plurality of dielectric layers, and one of the plurality of internal electrode layers is a first end surface in which end portions of some of the internal electrode layers are exposed; and a second end surface that faces the first end surface and in which end portions of other internal electrode layers among the plurality of internal electrode layers are exposed; a step of forming a first external electrode by baking a first external electrode on the first end surface; a second external electrode having a composition different from that of the first external electrode on the second end surface; and a second external electrode forming step in which the electrodes are baked at a temperature lower than the first external electrode forming step by 50° C. or more.

In the above manufacturing method, baking may be performed in the second external electrode forming step at a temperature lower than the first external electrode forming step by 70° C. or more.

In the above manufacturing method, the first external electrode and the second external electrode may contain boron, and the second external electrode may have a higher boron content than the first external electrode.

In the above manufacturing method, the second external electrode may have a boron content greater than 2 wt% in terms of oxide than the first external electrode.

In the above manufacturing method, the first external electrode and the second external electrode may contain silicon, and the second external electrode may have a lower silicon content than the first external electrode.

In the above manufacturing method, the first external electrode and the second external electrode may contain copper as a main component.

In the above manufacturing method, the first external electrode may have nickel as a main component, and the second external electrode may have copper as a main component.

In the above manufacturing method, the first external electrode and the second external electrode may contain at least one of aluminum, calcium, strontium, lithium, sodium, and phosphorus as an additive.

Another method for manufacturing a laminated ceramic electronic component includes a plurality of ceramic green sheets and a plurality of internal electrode patterns laminated via the plurality of ceramic green sheets, and a part of the plurality of internal electrode patterns. a first end surface in which ends of internal electrode patterns of the plurality of internal electrode patterns are exposed; and a second end surface that faces the first end surface and in which ends of other internal electrode patterns among the plurality of internal electrode patterns are exposed. a step of preparing a ceramic laminate; a step of applying a metal paste to the first end surface; a firing step of simultaneously firing the ceramic laminate and the metal paste to obtain an element body from the ceramic laminate; The method includes a baking step of applying a metal paste to the second end surface of the element body and baking it at a temperature 50° C. or more lower than that of the baking step.

A multilayer ceramic electronic component according to the present invention includes a plurality of dielectric layers and a plurality of internal electrode layers laminated via the plurality of dielectric layers, and a part of the plurality of internal electrode layers is provided. an element body having a first end surface in which an end portion of an internal electrode layer is exposed; a second end surface in which an end portion of another part of the internal electrode layers among the plurality of internal electrode layers is exposed; and the first end surface. and a second external electrode provided on the second end surface and having a different composition from the first external electrode.

In the multilayer ceramic electronic component, the first external electrode and the second external electrode may contain boron, and the second external electrode may have a higher boron content than the first external electrode.

In the multilayer ceramic electronic component, the second external electrode may have a boron content greater than 2 wt% in terms of oxide than the first external electrode.

In the multilayer ceramic electronic component, the first external electrode and the second external electrode may contain silicon, and the second external electrode may have a lower silicon content than the first external electrode.

In the multilayer ceramic electronic component, the first external electrode and the second external electrode may have copper as a main component.

In the multilayer ceramic electronic component, the first external electrode may have nickel as a main component, and the second external electrode may have copper as a main component.

In the multilayer ceramic electronic component, the first external electrode and the second external electrode may contain at least one of aluminum, calcium, strontium, lithium, sodium, and phosphorus as an additive.

A circuit board according to the present invention is a circuit board provided with any of the above-mentioned multilayer ceramic electronic components.

According to the present invention, it is possible to provide a method for manufacturing a multilayer ceramic electronic component, a multilayer ceramic electronic component, and a circuit board that can suppress fusion of external electrodes.

FIG. 2 is a partial cross-sectional perspective view of a multilayer ceramic capacitor. FIG. 2 is a cross-sectional view taken along line AA in FIG. 1. 2 is a sectional view taken along line BB in FIG. 1. FIG. FIG. 2 is a diagram illustrating a state in which a multilayer ceramic capacitor is mounted on a circuit board. (a) and (b) are diagrams illustrating a plating layer. FIG. 3 is a diagram illustrating a flow of a method for manufacturing a multilayer ceramic capacitor. (a) and (b) are diagrams illustrating a lamination process. (a) and (b) are diagrams illustrating a first coating step. (a) and (b) are diagrams illustrating the second coating step. FIG. 3 is a diagram illustrating a flow of another method for manufacturing a multilayer ceramic capacitor. (a) and (b) are diagrams illustrating a first coating step. (a) and (b) are diagrams illustrating the second coating step.

Hereinafter, embodiments will be described with reference to the drawings.

FIG. 1 is a partially cross-sectional perspective view of a multilayer ceramic capacitor 100 according to an embodiment. FIG. 2 is a cross-sectional view taken along line AA in FIG. FIG. 3 is a sectional view taken along line BB in FIG. As illustrated in FIGS. 1 to 3, the multilayer ceramic capacitor 100 includes an element body 10 having a substantially rectangular parallelepiped shape, a first external electrode 20a provided on any two opposing end surfaces of the element body 10, and and a second external electrode 20b. Note that, of the four surfaces of the element body 10 other than the two end surfaces, two surfaces other than the upper surface and the lower surface in the stacking direction are referred to as side surfaces. The first external electrode 20a and the second external electrode 20b extend on the top surface, bottom surface, and two side surfaces of the element body 10 in the stacking direction. However, the first external electrode 20a and the second external electrode 20b are spaced apart from each other.

The element body 10 has a structure in which dielectric layers 11 containing a ceramic material functioning as a dielectric and internal electrode layers 12 mainly composed of metal are laminated alternately. In other words, the element body 10 includes a plurality of internal electrode layers 12 facing each other and dielectric layers 11 each sandwiched between the plurality of internal electrode layers 12. The edges in the extending direction of each internal electrode layer 12 are exposed alternately at the end surface where the first external electrode 20a of the element body 10 is provided and the end surface where the second external electrode 20b is provided. There is. Thereby, each internal electrode layer 12 is alternately electrically connected to the first external electrode 20a and the second external electrode 20b. As a result, multilayer ceramic capacitor 100 has a structure in which a plurality of dielectric layers 11 are stacked with internal electrode layers 12 in between. Further, in the laminate of the dielectric layer 11 and the internal electrode layer 12, the internal electrode layer 12 is disposed as the outermost layer in the stacking direction, and the top and bottom surfaces of the laminate are covered with a cover layer 13. The cover layer 13 has a ceramic material as its main component. For example, the cover layer 13 may have the same composition as the dielectric layer 11 or may have a different composition.

The size of the multilayer ceramic capacitor 100 is, for example, 0.25 mm long, 0.125 mm wide, and 0.125 mm high, or 0.4 mm long, 0.2 mm wide, 0.2 mm high, or long. 0.6mm, width 0.3mm, height 0.3mm, or length 0.6mm, width 0.3mm, height 0.110mm, or length 1.0mm, width 0.5mm, height The length is 0.5 mm, or the length is 1.0 mm, the width is 0.5 mm, and the height is 0.1 mm; or the length is 3.2 mm, the width is 1.6 mm, and the height is 1.6 mm; The size is 4.5 mm, the width is 3.2 mm, and the height is 2.5 mm, but the size is not limited to these.

The dielectric layer 11 has, for example, a ceramic material having a perovskite structure represented by the general formula _ABO3 as a main phase. Note that the perovskite structure includes ABO _3-α that deviates from the stoichiometric composition. For example, the ceramic materials include barium titanate (BaTiO ₃ ), calcium zirconate (CaZrO ₃ ), calcium titanate (CaTiO ₃ ), strontium titanate (SrTiO ₃ ), magnesium titanate (MgTiO ₃ ), and perovskite structures. Select and use at least one of Ba _1-x-y Ca _x Sry _{Ti 1-z} Zr _z O ₃ (0≦x≦1, 0≦y≦1, 0≦z≦1) to form. be able to. Ba _1-x-y Ca _{x Sry} Ti _1-z Zr _z O ₃ is barium strontium titanate, barium calcium titanate, barium zirconate, barium zirconate titanate, calcium zirconate titanate, and zirconate titanate. Barium calcium, etc.

An additive may be added to the dielectric layer 11. As additives to the dielectric layer 11, magnesium (Mg), manganese (Mn), molybdenum (Mo), vanadium (V), chromium (Cr), rare earth elements (yttrium (Y), samarium (Sm), europium ( Cobalt (Co), nickel (Ni), lithium (Li), boron (B), sodium (Na), potassium (K) or silicon (Si), or containing cobalt, nickel, lithium, boron, sodium, potassium or silicon Glass is an example.

The internal electrode layer 12 mainly contains a base metal such as nickel (Ni), copper (Cu), and tin (Sn). As the internal electrode layer 12, noble metals such as platinum (Pt), palladium (Pd), silver (Ag), and gold (Au), or alloys containing these metals may be used.

As illustrated in FIG. 2, the region where the internal electrode layer 12 connected to the first external electrode 20a and the internal electrode layer 12 connected to the second external electrode 20b face each other has a capacitance in the multilayer ceramic capacitor 100. This is the area where this occurs. Therefore, the region where the capacitance occurs is referred to as a capacitor section 14. That is, the capacitive portion 14 is a region where adjacent internal electrode layers 12 connected to different external electrodes face each other.

A region where the internal electrode layers 12 connected to the first external electrode 20a face each other without interposing the internal electrode layer 12 connected to the second external electrode 20b is referred to as an end margin 15. Further, the end margin 15 is also a region where the internal electrode layers 12 connected to the second external electrode 20b face each other without interposing the internal electrode layer 12 connected to the first external electrode 20a. That is, the end margin 15 is a region where internal electrode layers 12 connected to the same external electrode face each other without interposing the internal electrode layers 12 connected to a different external electrode. The end margin 15 is an area where no capacitance occurs. The end margin 15 may have the same composition as the dielectric layer 11 of the capacitive section 14, or may have a different composition.

As illustrated in FIG. 3, in the element body 10, a region from two side surfaces of the element body 10 to the internal electrode layer 12 is referred to as a side margin 16. That is, the side margin 16 is a region provided so as to cover the ends of the plurality of stacked internal electrode layers 12 extending toward the two side surfaces in the stacked structure. The side margin 16 is also an area where no electrostatic capacitance occurs. The side margin 16 may have the same composition as the dielectric layer 11 of the capacitive portion 14, or may have a different composition.

The first external electrode 20a and the second external electrode 20b have different compositions. Thereby, the appropriate temperature for forming the first external electrode 20a and the appropriate temperature for forming the second external electrode 20b can be made different. Therefore, the temperature at which one external electrode is formed can be lower than the temperature at which the other external electrode is formed. For example, the temperature at which the second external electrode 20b is formed can be lower than the temperature at which the first external electrode 20a is formed. In this case, the second external electrode 20b can be formed after forming the first external electrode 20a. If the vicinity of the first external electrode 20a is not held with a jig when forming the first external electrode 20a, it is possible to suppress fusion between the first external electrode 20a and the jig. Even if the vicinity of the first external electrode 20a is held with a jig when forming the second external electrode 20b, the temperature when forming the second external electrode 20b will be low, so the jig and the first external electrode Fusion with the electrode 20a can be suppressed. Even when firing is performed without using a jig and without aligning the element bodies 10, the glass component of the first external electrode 20a can be reduced by lowering the temperature at which the second external electrode 20b is formed after baking the first external electrode 20a The glass component of the second external electrode 20b does not react with the glass component of the second external electrode 20b, and it is possible to suppress fusion between the first external electrode 20a and the second external electrode 20b.

Further, since the composition of the first external electrode 20a and the composition of the second external electrode 20b are different, the natural frequency generated in the first external electrode 20a and the natural frequency generated in the second external electrode 20b are different. , resonance of the multilayer ceramic capacitor 100 is suppressed. As a result, the occurrence of noise can be suppressed.

For example, the first external electrode 20a and the second external electrode 20b may have the same main component metal, but may have different compositions of additives such as glass. For example, the boron content contained in the second external electrode 20b is made greater than the boron content contained in the first external electrode 20a. Thereby, the temperature at which the second external electrode 20b is formed can be lower than the temperature at which the first external electrode 20a is formed. Note that the boron content can also be expressed as wt % of boron in terms of oxide, assuming that the weight of the main component metal in terms of oxide is 100 wt %. For example, the boron content in the second external electrode 20b is preferably 2 wt% or more greater than the boron content in the first external electrode 20a, preferably 3 wt% or more, and 5 wt% or more. is more preferable, and it is even more preferable to increase the amount by 8 wt% or more.

Alternatively, the silicon content contained in the second external electrode 20b is made greater than the silicon content contained in the first external electrode 20a. Thereby, the temperature at which the second external electrode 20b is formed can be lower than the temperature at which the first external electrode 20a is formed. Note that the silicon content can also be expressed as wt % of silicon in terms of oxide, assuming that the weight of the main component metal in terms of oxide is 100 wt %. For example, the silicon content in the second external electrode 20b is preferably 2 wt% or more greater than the silicon content in the first external electrode 20a, more preferably 4 wt% or more, and 6 wt% or more. It is even more preferable.

Alternatively, the temperature at which the second external electrode 20b is formed can be adjusted to the temperature at which the second external electrode 20a is formed by adjusting the content of each component contained in the additive glass to create a difference in the temperature at which the glass becomes liquid phase. The temperature may be lower than that at which . For example, the content of at least one of aluminum, calcium, strontium, lithium, sodium, and phosphorus may be adjusted. The content in this case can also be expressed as wt % in terms of oxide, assuming that the weight of the main component metal in terms of oxide is 100 wt %.

FIG. 4 is a diagram illustrating a state in which the multilayer ceramic capacitor 100 is mounted on the circuit board 201. As illustrated in FIG. 4, the lower surface in the stacking direction is arranged to face the land 203 on the circuit board 201. The first external electrode 20a and the second external electrode 20b are each independently electrically connected to the circuit board 201 via the solder 202 to the land 203 on the circuit board 201.

As illustrated in FIGS. 5(a) and 5(b), a plating layer may be provided on the first external electrode 20a, and a plating layer may be provided on the second external electrode 20b. . During the plating process, the first external electrode 20a and the second external electrode 20b function as a base layer. The plating layer mainly contains metals such as copper, nickel, aluminum, zinc, and tin, or alloys of two or more of these metals. The plating layer may be a plating layer of a single metal component, or may be a plurality of plating layers of mutually different metal components. For example, the plating layer has a structure in which a first plating layer 21, a second plating layer 22, and a third plating layer 23 are formed in order from the base layer side. The first plating layer 21 is, for example, a copper plating layer. The second plating layer 22 is, for example, a nickel plating layer. The third plating layer 23 is, for example, a tin plating layer.

Next, a method for manufacturing the multilayer ceramic capacitor 100 will be described. FIG. 6 is a diagram illustrating a flow of a method for manufacturing the multilayer ceramic capacitor 100.

(Raw material powder production process)
First, a dielectric material for forming the dielectric layer 11 is prepared. The A-site element and the B-site element contained in the dielectric layer 11 are usually contained in the dielectric layer 11 in the form of a sintered body of ABO ₃ particles. For example, BaTiO ₃ is a tetragonal compound having a perovskite structure and exhibits a high dielectric constant. This BaTiO ₃ can generally be obtained by reacting a titanium raw material such as titanium dioxide with a barium raw material such as barium carbonate to synthesize barium titanate. Various methods are conventionally known for synthesizing the main component ceramic of the dielectric layer 11, such as a solid phase method, a sol-gel method, a hydrothermal method, and the like. In this embodiment, any of these can be adopted.

A predetermined additive compound is added to the obtained ceramic powder depending on the purpose. Additive compounds include magnesium (Mg), manganese (Mn), molybdenum (Mo), vanadium (V), chromium (Cr), rare earth elements (yttrium (Y), samarium (Sm), europium (Eu), gadolinium ( Cobalt (Co), Nickel (Ni), Lithium (Li), boron (B), sodium (Na), potassium (K), or silicon (Si), or glass containing cobalt, nickel, lithium, boron, sodium, potassium, or silicon. Among these, SiO ₂ mainly functions as a sintering aid.

For example, a ceramic material is prepared by wet-mixing a compound containing an additive compound with a ceramic raw material powder, drying and pulverizing the mixture. For example, the ceramic material obtained as described above may be pulverized to adjust the particle size, if necessary, or may be combined with a classification process to adjust the particle size. Through the above steps, a dielectric material is obtained.

(Coating process)
Next, a binder such as polyvinyl butyral (PVB) resin, an organic solvent such as ethanol or toluene, and a plasticizer are added to the obtained dielectric material and wet-mixed. Using the obtained slurry, a ceramic green sheet 52 is coated on the base material 51 by, for example, a die coater method or a doctor blade method, and then dried. The base material 51 is, for example, a polyethylene terephthalate (PET) film.

(Internal electrode formation process)
Next, as illustrated in FIG. 7A, an internal electrode pattern 53 is formed on the ceramic green sheet 52. In FIG. 7A, as an example, four layers of internal electrode patterns 53 are formed on a ceramic green sheet 52 at predetermined intervals. The ceramic green sheet 52 on which the internal electrode pattern 53 is formed is a laminated unit. For the internal electrode pattern 53, a metal paste of the main component metal of the internal electrode layer 12 is used. The film forming method may be printing, sputtering, vapor deposition, or the like.

(crimping process)
Next, while peeling off the ceramic green sheet 52 from the base material 51, the laminated units are laminated as illustrated in FIG. 7(b). Next, a predetermined number (for example, 2 to 10 layers) of cover sheets 54 are stacked on top and bottom of the laminate obtained by stacking the laminate units, and the cover sheets 54 are bonded by thermocompression to a predetermined chip size (for example, 1.0 mm×0. .5mm). In the example of FIG. 7(b), the cut is made along the dotted line. The cover sheet 54 may have the same components as the ceramic green sheet 52, or may have different additives.

(Firing process)
Thereafter, it is fired at 1100° C. to 1300° C. for 10 minutes to 2 hours in a reducing atmosphere with an oxygen partial pressure of 10 ⁻⁵ to 10 ⁻⁸ atm. In this way, the element body 10 can be obtained.

(Re-oxidation treatment process)
Thereafter, reoxidation treatment may be performed at 600° C. to 1000° C. in an N ₂ gas atmosphere.

(1st coating process)
Next, as illustrated in FIG. 8(a), the plurality of element bodies 10 are held with a jig 60. In this case, the vicinity of the first end face of the element body 10 is not held, but the second end face side is held. In this state, as illustrated in FIG. 8(b), with the first end surface side of the element body 10 facing downward, a first A metal paste 55a is applied using a dipping method or the like.

(First external electrode formation step)
Next, the first external electrode 20a is formed by baking the first metal paste 55a at a temperature of about 700° C. to 900° C.

(Second coating process)
Next, as illustrated in FIG. 9A, a jig 60 holds the plurality of element bodies 10 on which the first external electrodes 20a are formed. In this case, the vicinity of the second end face of the element body 10 is not held, but the first end face side is held. In this case, the jig 60 may be in contact with the first external electrode 20a. In this state, as illustrated in FIG. 9(b), a second metal paste 55b, which will become the second external electrode 20b, is applied to the second end surface of the element body 10 by a dipping method or the like.

(Second external electrode formation process)
Next, the second external electrode 20b is formed by baking the second metal paste 55b at a temperature lower than the temperature in the first external electrode forming step.

(Plating process)
Thereafter, a metal coating such as copper, nickel, tin, etc. may be applied to the first external electrode 20a and the second external electrode 20b by plating.

According to the manufacturing method according to the present embodiment, since the first metal paste 55a and the jig 60 are not in contact when baking the first metal paste 55a, the first external electrode 20a and the jig 60 are fused. No wear will occur. Next, the temperature at which the second metal paste 55b is baked is lower than the temperature at which the first metal paste 55a is baked. In this case, even if the jig 60 is in contact with the first external electrode 20a, since the temperature is low, fusion between the first external electrode 20a and the jig 60 can be suppressed. Furthermore, even when firing is performed without using the jig 60 and without aligning the element bodies 10, the temperature at which the second external electrodes 20b are formed after baking the first external electrodes 20a becomes lower, so that the first external electrodes 20a The glass component of the second external electrode 20b does not react with the glass component of the second external electrode 20b, and it is possible to suppress fusion between the first external electrode 20a and the second external electrode 20b.

In order to make the temperature at which the second metal paste 55b is baked lower than the temperature at which the first metal paste 55a is baked, the composition of the first metal paste 55a and the composition of the second metal paste 55b are made different.

For example, the first metal paste 55a and the second metal paste 55b may have the same main component metal, but may have different compositions of additives such as glass. For example, the boron content contained in the second metal paste 55b is made greater than the boron content contained in the first metal paste 55a. Thereby, the temperature at which the second metal paste 55b is baked can be lower than the temperature at which the first metal paste 55a is baked. Note that the boron content can also be expressed as wt % of boron in terms of oxide, assuming that the weight of the main component metal in terms of oxide is 100 wt %. For example, the boron content in the second metal paste 55b is preferably 2 wt% or more greater than the boron content in the first metal paste 55a, more preferably 5 wt% or more, and 8 wt% or more. It is even more preferable.

Alternatively, the silicon content contained in the second metal paste 55b is made larger than the silicon content contained in the first metal paste 55a. Thereby, the temperature at which the second metal paste 55b is baked can be lower than the temperature at which the first metal paste 55a is baked. Note that the silicon content can also be expressed as wt % of silicon in terms of oxide, assuming that the weight of the main component metal in terms of oxide is 100 wt %. For example, the silicon content in the second metal paste 55b is preferably 2 wt% or more greater than the silicon content in the first metal paste 55a, more preferably 4 wt% or more, and 6 wt% or more. It is even more preferable.

Alternatively, by adjusting the content of each component contained in the additive glass, by creating a difference in the temperature at which the glass becomes liquid phase, the temperature at which the second metal paste 55b is baked is different from that of the first metal paste 55a. The temperature may be lower than the baking temperature. For example, the content of at least one of aluminum, calcium, strontium, lithium, sodium, and phosphorus may be adjusted. The content in this case can also be expressed as wt % in terms of oxide, assuming that the weight of the main component metal in terms of oxide is 100 wt %.

By setting the baking temperature in the second external electrode forming step to be as low as possible than the baking temperature in forming the first external electrode, it is possible to suppress fusion between the jig 60 and the first external electrode 20a. For example, the baking temperature in the second external electrode forming step is preferably lower than the baking temperature in the first external electrode forming step by 50°C or more, preferably by 70°C or more, and preferably by 100°C or more lower. More preferred.

Furthermore, the baking temperature (maximum temperature of the baking process) in the second external electrode forming step is preferably in the range of 750°C or more and 840°C or less, preferably in the range of 750°C or more and 800°C or less, and 750°C or more. Preferably, the temperature is in the range of 780°C or less.

Next, another method of manufacturing the multilayer ceramic capacitor 100 will be described. FIG. 10 is a diagram illustrating the flow of another method for manufacturing the multilayer ceramic capacitor 100. The process from the raw material powder preparation process to the compression bonding process is the same as the flowchart in FIG. Thereby, a ceramic laminate is obtained.

(1st coating process)
Next, as illustrated in FIG. 11(a), a plurality of ceramic laminates 70 are held with a jig 60. In this case, the vicinity of the first end face of the ceramic laminate 70 is not held, but the second end face side is held. In this state, as illustrated in FIG. 11(b), the first external electrode 20a is formed on the first end surface of the ceramic laminate 70 with the first end surface side of the ceramic laminate 70 facing down. The first metal paste 55a is applied by a dipping method or the like.

(Firing process)
Thereafter, it is fired at 1100° C. to 1300° C. for 10 minutes to 2 hours in a reducing atmosphere with an oxygen partial pressure of 10 ⁻⁵ to 10 ⁻⁸ atm. In this way, the element body 10 on which the first external electrode 20a is formed can be obtained.

(Re-oxidation treatment process)
Thereafter, reoxidation treatment may be performed at 600° C. to 1000° C. in an N ₂ gas atmosphere.

(Second coating process)
Next, as illustrated in FIG. 12A, a jig 60 holds the plurality of element bodies 10 on which the first external electrodes 20a are formed. In this case, the vicinity of the second end face of the element body 10 is not held, but the first end face side is held. In this case, the jig 60 may be in contact with the first external electrode 20a. In this state, as illustrated in FIG. 12(b), a second metal paste 55b, which will become the second external electrode 20b, is applied to the second end surface of the element body 10 by a dipping method or the like.

(Second external electrode formation process)
Next, the second external electrode 20b is formed by baking the second metal paste 55b at a temperature lower than that of the baking process.

(Plating process)
Thereafter, a metal coating such as copper, nickel, tin, etc. may be applied to the first external electrode 20a and the second external electrode 20b by plating.

According to the manufacturing method according to the present embodiment, since the first metal paste 55a and the jig 60 are not in contact when firing the first metal paste 55a, the first external electrode 20a and the jig 60 are not in contact with each other. No fusion occurs. Next, the temperature at which the second metal paste 55b is baked is lower than the temperature at which the first metal paste 55a is baked. In this case, even if the jig 60 is in contact with the first external electrode 20a, since the temperature is low, fusion between the first external electrode 20a and the jig 60 can be suppressed.

The composition of the first metal paste 55a and the composition of the second metal paste 55b are made different from the viewpoint of making the temperature at which the second metal paste 55b is baked lower than the temperature at which the first metal paste 55a is baked.

For example, a co-material of ceramic particles is added to the first metal paste 55a without adding glass. Glass is added to the second metal paste 55b without adding any common material. Thereby, the baking temperature of the second metal paste 55b can be lower than the baking temperature of the first metal paste 55a.

Alternatively, the main component metals in the first metal paste 55a and the second metal paste 55b may be different. For example, the main component of the first metal paste 55a is nickel, and the main component of the second metal paste 55b is copper. Thereby, the baking temperature of the second metal paste 55b can be lower than the baking temperature of the first metal paste 55a.

By setting the baking temperature in the second external electrode forming step to be as low as possible than the firing temperature in the firing step, it is possible to suppress fusion between the jig 60 and the first external electrode 20a. For example, the baking temperature in the second external electrode forming step is preferably lower than the firing temperature in the firing step by 50° C. or more, preferably by 70° C. or more, and more preferably by 100° C. or more.

Furthermore, the baking temperature (maximum temperature of the baking process) in the second external electrode forming step is preferably in the range of 750°C or more and 840°C or less, preferably in the range of 750°C or more and 800°C or less, and 750°C or more. Preferably, the temperature is in the range of 780°C or less.

Note that in each of the above embodiments, a multilayer ceramic capacitor has been described as an example of a ceramic electronic component, but the present invention is not limited thereto. For example, the configurations of the above embodiments can also be applied to other multilayer ceramic electronic components such as varistors and thermistors.

Hereinafter, a multilayer ceramic capacitor according to an embodiment was manufactured and its characteristics were investigated.

(Examples 1 to 3 and Comparative Examples 1 to 3)
An element body was prepared in which a plurality of dielectric layers and a plurality of internal electrode layers were alternately laminated. In the element body, a plurality of internal electrode layers are alternately exposed on the first end surface and the second end surface.

Five types of metal pastes A to E were prepared as metal pastes for forming external electrodes. In all of the metal pastes A to E, copper powder is the main metal component, and glass is added. Metal pastes A to E have different compositions of glass components. Table 1 shows the composition of each of the glass components added to metal pastes A to E. The glass components added to metal paste A include 42 wt% barium oxide (BaO), 20 wt% zinc oxide (ZnO), 6 wt% silicon oxide (SiO ₂ ), and 24 wt% boron oxide (B ₂ O ₃ ). , and other components were included at 8 wt%. The glass components added to metal paste B include 42 wt% barium oxide (BaO), 20 wt% zinc oxide (ZnO), 8 wt% silicon oxide (SiO ₂ ), and 20 wt% boron oxide (B ₂ O ₃ ). , and other components were included at 10 wt%. The glass components added to metal paste C include 42 wt% barium oxide (BaO), 20 wt% zinc oxide (ZnO), 8 wt% silicon oxide (SiO ₂ ), and 18 wt% boron oxide (B ₂ O ₃ ). , and other components were included at 12 wt%. The glass components added to metal paste D include 38 wt% barium oxide (BaO), 18 wt% zinc oxide (ZnO), 12 wt% silicon oxide (SiO ₂ ), and 12 wt% boron oxide (B ₂ O ₃ ). , and other components were included at 20 wt%. The glass components added to metal paste E include 35 wt% barium oxide (BaO), 17 wt% zinc oxide (ZnO), 16 wt% silicon oxide (SiO ₂ ), and 9 wt% boron oxide (B ₂ O ₃ ). , and other components were included at 23 wt%.

In any of the metal pastes A to E, the amount of the glass component added was 8 wt % when the copper powder was 100 wt %. The recommended baking temperature for metal paste A is 750°C. The recommended baking temperature for metal paste B is 800°C. The recommended baking temperature for metal paste C is 840°C. The recommended baking temperature for metal paste D is 870°C. The recommended baking temperature for metal paste E is 900°C.

Next, as explained in FIG. 8(a), the jig does not hold the vicinity of the first end face of the element body, but holds the second end face side, and the first end face of the element body is held with the jig. A metal paste was applied by a dipping method or the like, and baked at the recommended baking temperature for the first metal paste used. In Example 1, metal paste C was used as the first metal paste. In Example 2, metal paste D was used as the first metal paste. In Example 3, metal paste E was used as the first metal paste. In Comparative Example 1, metal paste B was used as the first metal paste. In Comparative Example 2, metal paste C was used as the first metal paste. In Comparative Example 3, metal paste E was used as the first metal paste.

Next, as explained in FIG. 9(a), the jig is used to hold the first end surface side of the element body, without holding the vicinity of the second end face of the element body on which the first external electrode is formed. A second metal paste was applied to the two end faces by a dipping method or the like, and baked at the recommended baking temperature for the second metal paste used. In Example 1, metal paste A was used as the second metal paste. In Example 2, metal paste B was used as the second metal paste. In Example 3, metal paste A was used as the second metal paste. In Comparative Example 1, metal paste B was used as the second metal paste. In Comparative Example 2, metal paste B was used as the second metal paste. In Comparative Example 3, metal paste D was used as the second metal paste.

In Example 1, the baking temperature of the second metal paste was 90° C. lower than the baking temperature of the first metal paste. In Example 2, the baking temperature of the second metal paste was 70° C. lower than the baking temperature of the first metal paste. In Example 3, the baking temperature of the second metal paste was 150° C. lower than the baking temperature of the first metal paste. In Comparative Example 1, the baking temperature of the second metal paste was the same as that of the first metal paste. In Comparative Example 2, the baking temperature of the second metal paste was 40° C. lower than the baking temperature of the first metal paste. In Comparative Example 3, the baking temperature of the second metal paste was 30° C. lower than the baking temperature of the first metal paste.

For each of Examples 1 to 3 and Comparative Examples 1 to 3, the ratio of samples in which fusion occurred between the first external electrode and the jig (fusion rate) was investigated for 1000 samples. . The results are shown in Table 2. As shown in Table 2, the fusion rate was 0% in all of Examples 1 to 3. This is considered to be because the baking temperature of the second metal paste was set lower than the baking temperature of the first metal paste. On the other hand, in Comparative Example 1, the fusion rate was 100%. This is thought to be because the baking temperature of the first metal paste and the baking temperature of the second metal paste were the same, and the baking temperature of the second metal paste was higher. From the results of Examples 1 to 3 and Comparative Examples 1 to 3, it is considered that if the temperature difference is 50° C. or more, the fusion rate will be 0%.

Although the embodiments of the present invention have been described in detail above, the present invention is not limited to these specific embodiments, and various modifications and variations can be made within the scope of the gist of the present invention as described in the claims. Changes are possible.

10 Element body 11 Dielectric layer 12 Internal electrode layer 13 Cover layer 14 Capacitive part 15 End margin 16 Side margin 20a First external electrode 20b Second external electrode 51 Base material 60 Jig 70 Ceramic laminate 52 Ceramic green sheet 53 Internal electrode Pattern 100 Multilayer Ceramic Capacitor

Claims (17)

A first electrode comprising a plurality of dielectric layers and a plurality of internal electrode layers stacked via the plurality of dielectric layers, the ends of some of the internal electrode layers being exposed among the plurality of internal electrode layers. preparing an element body having one end surface and a second end surface facing the first end surface and exposing the ends of some of the other internal electrode layers among the plurality of internal electrode layers;
a first external electrode forming step of baking and forming a first external electrode on the first end surface;
a second external electrode forming step of forming a second external electrode having a different composition from the first external electrode on the second end surface at a temperature lower than the first external electrode forming step by 50° C. or more; Method of manufacturing ceramic electronic components. 2. The method for manufacturing a multilayer ceramic electronic component according to claim 1, wherein the second external electrode forming step is performed at a temperature that is 70° C. or more lower than the first external electrode forming step. The multilayer ceramic electronic component according to claim 1 or 2, wherein the first external electrode and the second external electrode contain boron, and the second external electrode has a higher boron content than the first external electrode. manufacturing method. 4. The method for manufacturing a multilayer ceramic electronic component according to claim 3, wherein the second external electrode has a boron content greater than 2 wt% in terms of oxide than the first external electrode. the first external electrode and the second external electrode contain silicon,
The method for manufacturing a multilayer ceramic electronic component according to any one of claims 1 to 4, wherein the second external electrode has a lower silicon content than the first external electrode. The method for manufacturing a multilayer ceramic electronic component according to any one of claims 1 to 5, wherein the first external electrode and the second external electrode contain copper as a main component. The first external electrode mainly contains nickel,
The method for manufacturing a multilayer ceramic electronic component according to any one of claims 1 to 5, wherein the second external electrode contains copper as a main component. The laminate according to any one of claims 1 to 7, wherein the first external electrode and the second external electrode contain at least one of aluminum, calcium, strontium, lithium, sodium, and phosphorus as an additive. Method of manufacturing ceramic electronic components. A first electrode comprising a plurality of ceramic green sheets and a plurality of internal electrode patterns laminated via the plurality of ceramic green sheets, the ends of some of the internal electrode patterns being exposed among the plurality of internal electrode patterns. preparing a ceramic laminate having one end surface and a second end surface facing the first end surface and exposing the ends of some of the other internal electrode patterns among the plurality of internal electrode patterns;
applying a metal paste to the first end surface;
a firing step of simultaneously firing the ceramic laminate and the metal paste to obtain an element body from the ceramic laminate;
A method for manufacturing a multilayer ceramic electronic component, comprising a baking step of applying a metal paste to the second end surface of the element body and baking at a temperature 50° C. or more lower than that of the baking step. A first electrode comprising a plurality of dielectric layers and a plurality of internal electrode layers stacked via the plurality of dielectric layers, the ends of some of the internal electrode layers being exposed among the plurality of internal electrode layers. an element body having one end face and a second end face where ends of other part of the internal electrode layers among the plurality of internal electrode layers are exposed;
a first external electrode provided on the first end surface;
A multilayer ceramic electronic component comprising: a second external electrode provided on the second end surface and having a composition different from that of the first external electrode. The first external electrode and the second external electrode contain boron,
The multilayer ceramic electronic component according to claim 10, wherein the second external electrode has a higher boron content than the first external electrode. 12. The multilayer ceramic electronic component according to claim 11, wherein the second external electrode has a boron content greater than 2 wt% in terms of oxide than the first external electrode. the first external electrode and the second external electrode contain silicon,
The multilayer ceramic electronic component according to any one of claims 10 to 12, wherein the second external electrode has a lower silicon content than the first external electrode. The multilayer ceramic electronic component according to any one of claims 10 to 13, wherein the first external electrode and the second external electrode contain copper as a main component. The first external electrode mainly contains nickel,
The multilayer ceramic electronic component according to any one of claims 10 to 13, wherein the second external electrode contains copper as a main component. The laminate according to any one of claims 10 to 15, wherein the first external electrode and the second external electrode contain at least one of aluminum, calcium, strontium, lithium, sodium, and phosphorus as an additive. Ceramic electronic components. A circuit board provided with the multilayer ceramic electronic component according to any one of claims 10 to 16.

Images