JP2023135913A - Drive circuit, control method, and program - Google Patents

Abstract

To provide a drive circuit capable of reducing the possibility of deviation from a normal operation range.SOLUTION: A drive circuit comprises: a differential amplifier; a first circuit that feeds a voltage applied to a load back to an inversion terminal of the differential amplifier when a current flows in the load; and a second circuit that feeds a voltage different from the voltage applied to the load back to the inversion terminal when no current flows in the load.SELECTED DRAWING: Figure 4

Description

The present disclosure relates to a drive circuit, a control method executed by the drive circuit, and a program.

In recent years, LEDs (Light Emitting Diodes) have been used in various fields. Patent Document 1 discloses, as a related technique, a technique related to a circuit that drives an LED.

Japanese Patent Application Publication No. 2012-164746

By the way, generally, when a differential amplifier is operated without applying negative feedback, the output voltage of the differential amplifier is fixed at an upper limit or a lower limit, and the differential amplifier deviates from a normal operating range. For example, in the drive circuit shown in FIG. 1 of Patent Document 1, when the LED is off, the transistor MN1 is turned off, the input voltage Vs of the operational amplifier 1 is reduced, and no feedback is applied. In this drive circuit, the current detector 2, the switch SW2, and the current source I2 accelerate the rise of the gate voltage of the transistor MN1, thereby shortening the time required for the transition from turning off to turning on. However, the time required for the operating point of the operational amplifier 1 to return from outside the normal operating range to within the normal operating range due to feedback is not shortened. That is, in the invention described in Patent Document 1, since there is a state outside the normal operation range, it takes a long time for the LED to transition (switch) from the off state to the on state.

Therefore, there is a need for a technique that can reduce the possibility that the drive circuit will deviate from the normal operating range.

One of the objectives of each aspect of the present disclosure is to provide a drive circuit, a control method executed by the drive circuit, and a program that can solve the above problems.

In order to achieve the above object, according to one aspect of the present disclosure, a drive circuit includes a differential amplifier, and when current is flowing through the load, a voltage applied to the load is transferred to an inverting terminal of the differential amplifier. and a second circuit that feeds back a voltage different from the voltage applied to the load to the inverting terminal when no current is flowing through the load.

In order to achieve the above object, according to another aspect of the present disclosure, a control method executed by a drive circuit includes a control method executed by a drive circuit including a differential amplifier, a first circuit, and a second circuit. The method comprises: feeding back the voltage applied to the load to an inverting terminal of the differential amplifier when current is flowing through the load; and returning the voltage applied to the load when no current is flowing through the load. and feeding back a voltage different from the voltage applied to the inverting terminal to the inverting terminal.

In order to achieve the above object, according to another aspect of the present disclosure, a program includes a differential amplifier, and when a current is flowing through the load, a voltage applied to the load is set to an inverting terminal of the differential amplifier. a first circuit having a first switch and a second circuit configured to feed back a voltage different from the voltage applied to the load to the inverting terminal when no current is flowing through the load and having a second switch; a circuit, the first switch is turned on when the current flows through the load, and the first switch is turned off when the current is not flowed through the load; The second switch is turned off when current is flowing through the load, and the second switch is turned on when current is not passed through the load.

According to each aspect of the present disclosure, the possibility of deviating from the normal operation range can be reduced.

FIG. 1 is a diagram illustrating an example of a configuration of a drive circuit according to an embodiment of the present disclosure. FIG. 3 is a diagram illustrating a first example of a processing flow of a drive circuit according to an embodiment of the present disclosure. FIG. 7 is a diagram illustrating a second example of the processing flow of the drive circuit according to an embodiment of the present disclosure. 1 is a diagram showing the minimum configuration of a drive circuit 1 according to an embodiment of the present disclosure. FIG. 2 is a diagram illustrating an example of a processing flow of a drive circuit 1 with a minimum configuration according to an embodiment of the present disclosure. FIG. 1 is a schematic block diagram showing the configuration of a computer according to at least one embodiment.

Hereinafter, embodiments will be described in detail with reference to the drawings.
<Embodiment>
FIG. 1 is a diagram showing an example of the configuration of a drive circuit 1 according to an embodiment of the present disclosure. As shown in FIG. 1, the drive circuit 1 includes a differential amplifier 10, a load circuit 20 (an example of a load), a current mirror 30, an LED (Light Emitting Diode) 100, a first circuit 120, and a second circuit 130. . The drive circuit 1 is a circuit that causes the LED 100 to emit light, and is a circuit that can reduce the possibility of deviating from the normal operation range.

The first circuit 120 feeds back the voltage applied to the load circuit 20 to the inverting terminal of the differential amplifier 10 when current is flowing through the load circuit 20 . The first circuit 120 includes a switch 40 (an example of a first switch), an output circuit 60, and an inversion circuit 90, as shown in FIG.

The second circuit 130 feeds back a voltage different from the voltage applied to the load circuit 20 to the inverting terminal of the differential amplifier 10 when no current flows through the load circuit 20 . The second circuit 130 includes a switch 50 (an example of a second switch), an output circuit 70, and an impedance circuit 110, as shown in FIG.

As shown in FIG. 1, the differential amplifier 10 includes N (negative) channel MOSFETs (Metal Oxide Semiconductor Field Effect Transistor) 101, 102, 103, and P (positive) channel MOSFETs 104, 105 Equipped with Hereinafter, the N-channel MOSFET will be referred to as an NMOS transistor, and the P-channel MOSFET will be referred to as a PMOS transistor.

A reference voltage Vref is applied to the gate of the NMOS transistor 101. The source of NMOS transistor 101 is connected to the source of NMOS transistor 102 and the source of NMOS transistor 103. The drain of NMOS transistor 101 is connected to the drain of PMOS transistor 104, the gate of PMOS transistor 104, and the gate of PMOS transistor 105. The drain of NMOS transistor 102 is connected to the drain of NMOS transistor 103 and the drain of PMOS transistor 105. The source of PMOS transistor 104 is connected to the source of PMOS transistor 105. A voltage VDD is applied to the source of the PMOS transistor 104. Note that the drain of the NMOS transistor 102 is the output of the differential amplifier 10. The output voltage of this differential amplifier 10 is assumed to be Vo. Note that in the differential amplifier 10, the PMOS transistors 104 and 105 constitute an active load. Therefore, the differential amplifier 10 has a very high gain (for example, 100,000 times).

The load circuit 20 is, for example, a resistor having a resistance value R2. A first terminal of the load circuit 20 is connected to ground GND. A second terminal of load circuit 20 is connected to the gate of NMOS transistor 102. As will be described later, the voltage at the gate of the NMOS transistor 102 when the switch 40 is turned on and current Iload flows through the load circuit 20 is assumed to be Vs2.

The current mirror 30 includes an NMOS transistor 301 and an NMOS transistor 302, as shown in FIG. As shown in FIG. 1, the source of NMOS transistor 301 is connected to ground GND and the source of NMOS transistor 302. Further, the gate of the NMOS transistor 301 is connected to the drain of the NMOS transistor 301 and the gate of the NMOS transistor 302. Further, the drain of the NMOS transistor 302 is connected to the source of the NMOS transistor 101. When the channel length L1 of the NMOS transistor 301 and the channel length L2 of the NMOS transistor 302 are equal, the NMOS transistor 301 and the NMOS transistor 302 of the current mirror 30 have a channel width W1 of the NMOS transistor 301 and a channel width W2 of the NMOS transistor 302. A current flows according to the ratio. Specifically, the current flowing through the NMOS transistor 302 is (W2/W1) times the current flowing through the NMOS transistor 301. The current flowing through this NMOS transistor 302 becomes the tail current of the differential amplifier 10.

The on state and off state of the switch 40 are controlled by a signal obtained by inverting the signal Sig by an inverting circuit 90. The signal Sig is a high level signal or a low level signal. The switch 40 is, for example, an NMOS transistor. If switch 40 is an NMOS transistor, the drain of switch 40 is connected to the source of PMOS transistor 104. Note that the current flowing through the switch 40 when the switch 40 is in the on state is Iload.

The on state and off state of the switch 50 are controlled by a signal Sig. The switch 50 is, for example, an NMOS transistor.

The output circuit 60 includes an NMOS transistor 601 and a capacitor 602, as shown in FIG. The NMOS transistor 601 is a buffer circuit and increases the ability to supply current from the differential amplifier 10 to the load circuit 20. Capacitor 602 compensates the phase of drive circuit 1 . As shown in FIG. 1, the source of NMOS transistor 601 is connected to the first terminal of capacitor 602 and the gate of NMOS transistor 102. Further, the gate of the NMOS transistor 601 is connected to the second terminal of the capacitor 602 and the drain of the NMOS transistor 102. Further, the drain of the NMOS transistor 601 is connected to the source of the switch 40.

The output circuit 70 includes an NMOS transistor 701 and a capacitor 702, as shown in FIG. The NMOS transistor 701 is a buffer circuit and increases the ability to supply current from the differential amplifier 10 to the impedance circuit 110. Capacitor 702 compensates for the phase of drive circuit 1 . As shown in FIG. 1, the source of NMOS transistor 701 is connected to the first terminal of capacitor 702 and the gate of NMOS transistor 103. Further, the gate of the NMOS transistor 701 is connected to the second terminal of the capacitor 702 and the drain of the NMOS transistor 102. Further, the drain of the NMOS transistor 701 is connected to the source of the switch 50.

Current source 80 supplies a constant current Iref. Current source 80 is, for example, a resistor. As shown in FIG. 1, a first terminal of current source 80 is connected to the source of PMOS transistor 104. Further, the second terminal of the current source 80 is connected to the drain of the NMOS transistor 301.

The inversion circuit 90 generates a signal by inverting the signal Sig, and outputs the generated signal. The inverting circuit 90 is an inverter made of, for example, a complementary MOS transistor in which the drain of an NMOS transistor and the drain of a PMOS transistor are connected. As shown in FIG. 1, the first terminal of the inverting circuit 90 is connected to the gate of the switch 50. Further, the second terminal of the inverting circuit 90 is connected to the gate of the switch 40. A signal Sig is applied to a first terminal of the inverting circuit 90.

The LED 100 emits light when a voltage is applied in the forward direction. As shown in FIG. 1, the anode of LED 100 is connected to a power source. Further, the cathode of the LED is connected to the drain of the switch 50. For example, when the switch 50 is in the on state, the LED 100 causes a current Iled to flow in the forward direction and emits light. Further, for example, when the switch 50 is in the off state, the LED 100 does not pass current in the forward direction and does not emit light.

Impedance circuit 110 is implemented so that negative feedback is applied to differential amplifier 10 during operation. The impedance circuit 110 is, for example, a resistor having a resistance value R1. Note that when the impedance of the impedance circuit 110 is larger than the impedance of the load circuit 20, the power consumption per unit time while the impedance circuit 110 is operating is calculated as the power consumption per unit time while the load circuit 20 is operating. It can be reduced more than the power consumption. As shown in FIG. 1, the first terminal of impedance circuit 110 is connected to the source of NMOS transistor 301. Further, the second terminal of the impedance circuit 110 is connected to the gate of the NMOS transistor 103. Note that the gate voltage of the NMOS transistor 103 when the switch 50 is turned on and the current Iled flows through the impedance circuit 110 is assumed to be Vs1.

Note that the capacitor 602 and capacitor 702 described above are not always necessary. The above connection connects the gate of the NMOS transistor 102, the second terminal of the load circuit 20, the source of the NMOS transistor 601, and the first terminal of the capacitor 602. Among them, only the gate of the NMOS transistor 102 is removed from the above connection, the gate of the NMOS transistor 102 is used as an input, and the second terminal of the load circuit 20, the source of the NMOS transistor 601, and the first terminal of the capacitor 602 are used as the output. The capacitance of the capacitor 602 can be determined by verifying the gain margin and phase margin in the open loop in the case of the above. Furthermore, the above connection connects the gate of the NMOS transistor 102, the second terminal of the impedance circuit 110, the source of the NMOS transistor 701, and the first terminal of the capacitor 702. Among them, only the gate of the NMOS transistor 102 is removed from the above connection, and the gate of the NMOS transistor 102 is used as an input, and the second terminal of the impedance circuit 110, the source of the NMOS transistor 701, and the first terminal of the capacitor 702 are used as the output. The capacitance of the capacitor 702 can be determined by verifying the gain margin and phase margin in the open loop in the case of the above. Therefore, if the above-described gain margin and phase margin are sufficient, capacitor 602 and capacitor 702 are unnecessary.

Further, the on state and off state of each of the switches 40 and 50 may be controlled by the computer 5, which the drive circuit 1 includes, which will be described later.

Next, processing performed by the drive circuit 1 according to an embodiment of the present disclosure will be described. FIG. 2 is a diagram showing a first example of the processing flow of the drive circuit 1 according to an embodiment of the present disclosure. FIG. 3 is a diagram illustrating a second example of the processing flow of the drive circuit 1 according to an embodiment of the present disclosure. Here, a process for controlling lighting and extinguishing of the LED 100 using the signal Sig in the drive circuit 1 shown in FIG. 1 will be described.

(When signal Sig is a high level signal)
First, with reference to FIG. 2, the process of lighting the LED 100 performed by the drive circuit 1 will be described. When the signal Sig is a high level signal, the switch 40 is turned off and the switch 50 is turned on (step S1). Therefore, the current Iled flows through the LED 100, and the LED 100 lights up (step S2). Current Iled is converted into voltage Vs1 by impedance circuit 110. The voltage Vs1 is then input to the gate of the NMOS transistor 103, which is the inverting input terminal of the differential amplifier 10. Further, since the switch 40 is in the off state, no current flows through the load circuit 20. Therefore, 0 volt (that is, a voltage at the GND level) is input to the gate of the NMOS transistor 102, which is another inverting input terminal of the differential amplifier 10. As a result, since the differential amplifier 10 has a very high gain, virtual grounding is established between the gate of the NMOS transistor 101 and the gate of the NMOS transistor 103 in the differential amplifier 10. That is, in this state, negative feedback is applied to the differential amplifier 10, and the gate voltage Vs1 of the NMOS transistor 103 is controlled to be equal to the gate voltage Vref of the NMOS transistor 101 (step S3).

Therefore, as described above, when the signal Sig is a High level signal, the LED 100 lights up and the current Iled flowing through the impedance circuit 110 is calculated by dividing the gate voltage Vref of the NMOS transistor 101 by the impedance circuit 110, for example, by formula (1 ).

Note that the resistance value R1 in equation (1) is an example of the impedance of the impedance circuit 110.

Further, the gate of the NMOS transistor 102 is at 0 volts. That is, the voltage Vs2 applied to the load circuit 20 is 0 volts. Therefore, the current Iload becomes 0 ampere by dividing the voltage Vs2 by the impedance of the load circuit 20.

(When signal Sig is a low level signal)
Next, with reference to FIG. 3, the process of turning off the LED 100 performed by the drive circuit 1 will be described. When the signal Sig is a low level signal, the switch 40 is turned on and the switch 50 is turned off (step S11). Therefore, the current Iled does not flow through the LED 100, and the LED 100 is turned off (step S12). Further, in this case, no current flows through the impedance circuit 110. Therefore, 0 volt is input to the gate of the NMOS transistor 103, which is the inverting input terminal of the differential amplifier 10. Further, since the switch 40 is in the on state, a current Iload flows through the load circuit 20. As a result, since the differential amplifier 10 has a very high gain, virtual grounding is established between the gate of the NMOS transistor 101 and the gate of the NMOS transistor 102 in the differential amplifier 10. That is, in this state, negative feedback is applied to the differential amplifier 10, and the gate voltage Vs2 of the NMOS transistor 102 is controlled to be equal to the gate voltage Vref of the NMOS transistor 102 (step S13).

Therefore, as described above, when the signal Sig is a Low level signal, the LED 100 is turned off and the current Iload flowing through the load circuit 20 is calculated by dividing the gate voltage Vref of the NMOS transistor 102 by the impedance of the load circuit 20, for example, using the equation It is expressed as (2).

Note that the resistance value R2 in equation (2) is an example of the impedance of the load circuit 20.

Further, the gate of the NMOS transistor 103 is at 0 volts. That is, the voltage Vs1 applied to the impedance circuit 110 is 0 volts. Therefore, the current Iled becomes 0 ampere by dividing the voltage Vs1 by the impedance of the impedance circuit 110.

(advantage)
As described above, in the drive circuit 1, even when the signal Sig is a High level signal, that is, the LED 100 is turned on, when the signal Sig is a Low level signal, that is, the LED 100 is turned off. Even in this case, negative feedback is applied to one of the inverting input terminals of the differential amplifier 10. Therefore, in the drive circuit 1, it is possible to avoid a situation where negative feedback is not applied. In other words, the drive circuit 1 can reduce the possibility of deviating from the normal operation range.

FIG. 4 is a diagram showing the minimum configuration of the drive circuit 1 according to the embodiment of the present disclosure. The drive circuit 1 includes a differential amplifier 10, a first circuit 120, and a second circuit 130, as shown in FIG. The first circuit 120 feeds back the voltage applied to the load to the inverting terminal of the differential amplifier 10 when current is flowing through the load. The second circuit 130 feeds back a voltage different from the voltage applied to the load to the inverting terminal when no current is flowing through the load.

FIG. 5 is a diagram illustrating an example of a processing flow of the drive circuit 1 with the minimum configuration according to the embodiment of the present disclosure. Next, processing of the drive circuit 1 with the minimum configuration according to the embodiment of the present disclosure will be described with reference to FIG. 5.

When current is flowing through the load, the first circuit 120 feeds back the voltage applied to the load to the inverting terminal of the differential amplifier 10 (step S101). When no current is flowing through the load, the second circuit 130 feeds back a voltage different from the voltage applied to the load to the inverting terminal (step S102).

The drive circuit 1 with the minimum configuration according to the embodiment of the present disclosure has been described above. This drive circuit 1 can reduce the possibility of deviating from the normal operation range.

Note that the order of the processing in the embodiment of the present disclosure may be changed as long as appropriate processing is performed.

Although the embodiment of the present disclosure has been described, the above-described drive circuit 1 and other control devices may include a computer system therein. The above-described processing steps are stored in a computer-readable recording medium in the form of a program, and the above-mentioned processing is performed by reading and executing this program by the computer. A specific example of a computer is shown below.
FIG. 6 is a schematic block diagram showing the configuration of a computer according to at least one embodiment.
The computer 5 includes a CPU 6, a main memory 7, a storage 8, and an interface 9, as shown in FIG.
For example, each of the above-described drive circuit 1 and other control devices is implemented in the computer 5. The operations of each processing section described above are stored in the storage 8 in the form of a program. The CPU 6 reads the program from the storage 8, expands it to the main memory 7, and executes the above processing according to the program. Further, the CPU 6 reserves storage areas corresponding to each of the above-mentioned storage units in the main memory 7 according to the program.

Examples of the storage 8 include HDD (Hard Disk Drive), SSD (Solid State Drive), magnetic disk, magneto-optical disk, CD-ROM (Compact Disc Read Only Memory), and DVD-ROM (Digital Versatile). (Disc Read Only Memory) , semiconductor memory, etc. Storage 8 may be an internal medium directly connected to the bus of computer 5, or may be an external medium connected to computer 5 via interface 9 or a communication line. Furthermore, when this program is distributed to the computer 5 via a communication line, the computer 5 that receives the program may develop the program in the main memory 7 and execute the above processing. In at least one embodiment, storage 8 is a non-transitory tangible storage medium.

Further, the program may realize some of the functions described above. Furthermore, the program may be a file that can realize the above-described functions in combination with a program already recorded in the computer system, a so-called difference file (difference program).

Although several embodiments of the disclosure have been described, these embodiments are examples and do not limit the scope of the disclosure. Various additions, omissions, substitutions, and changes may be made to these embodiments without departing from the spirit of the disclosure.

1... Drive circuit 5... Computer 6... CPU
7... Main memory 8... Storage 9... Interface 10... Differential amplifier 20... Load circuit 30... Current mirrors 40, 50... Switches 60, 70... Output circuit 80... Current source 90... Inverting circuit 100... LED
101, 102, 103, 301, 302...NMOS transistor 104, 105...PMOS transistor 110...Impedance circuit 120...First circuit 130...Second circuit 601, 701...Buffer circuit

The present disclosure relates to a drive circuit , a control method, and a program.

One of the objectives of each aspect of the present disclosure is to provide a drive circuit , a control method, and a program that can solve the above problems.

In order to achieve the above object, according to one aspect of the present disclosure, a drive circuit includes a differential amplifier, and when current is flowing through the load, a voltage applied to the load is transferred to an inverting terminal of the differential amplifier. a first circuit that feeds back a voltage to the inverting terminal; and a second circuit that feeds back a voltage different from a voltage applied to the load to the inverting terminal when no current is flowing through the load. The device includes a first switch that is turned on when current is passed through the load and turned off when no current is passed through the load.
In order to achieve the above object, according to another aspect of the present disclosure, a drive circuit includes a differential amplifier, and when a current is flowing through the load, a voltage applied to the load is inverted from the differential amplifier. a first circuit that feeds back a voltage to the inverting terminal; and a second circuit that feeds back a voltage different from a voltage applied to the load to the inverting terminal when no current is flowing through the load. , a second switch that is turned off when current flows through the load and turned on when no current is flowed through the load.

In order to achieve the above object, according to another aspect of the present disclosure, a control method includes a control method performed by a drive circuit including a differential amplifier, a first circuit including a first switch, and a second circuit. The method comprises: feeding back the voltage applied to the load to an inverting terminal of the differential amplifier when current is flowing through the load; and returning the voltage applied to the load when no current is flowing through the load. and feeding back a voltage different from a voltage to the inverting terminal to the inverting terminal, the first switch being in an on state when current is flowing through the load, and being in an off state when no current is flowing through the load. Become.
In order to achieve the above object, according to another aspect of the present disclosure, a control method includes a control method performed by a drive circuit including a differential amplifier, a first circuit, and a second circuit including a second switch. The method comprises: feeding back the voltage applied to the load to an inverting terminal of the differential amplifier when current is flowing through the load; and returning the voltage applied to the load when no current is flowing through the load. and feeding back a voltage different from a voltage to the inverting terminal to the inverting terminal, and the second switch is in an on state when current is flowing through the load and is in an off state when no current is flowing through the load. Become.

In order to achieve the above object, according to another aspect of the present disclosure, a program includes a differential amplifier, and when a current is flowing through the load, a voltage applied to the load is set to an inverting terminal of the differential amplifier. a first circuit having a first switch and a second circuit configured to feed back a voltage different from the voltage applied to the load to the inverting terminal when no current is flowing through the load and having a second switch; A drive circuit including a circuit is configured to turn on the first switch when current is flowing through the load, and turn off the first switch when no current is flowing through the load.
In order to achieve the above object, according to another aspect of the present disclosure, a program includes a differential amplifier, and when a current is flowing through the load, a voltage applied to the load is set to an inverting terminal of the differential amplifier. a first circuit having a first switch and a second circuit configured to feed back a voltage different from the voltage applied to the load to the inverting terminal when no current is flowing through the load and having a second switch; A drive circuit including a circuit is configured to turn the second switch off when a current is flowing through the load, and turn the second switch on when a current is not flowing through the load.

Claims (6)

a differential amplifier;
a first circuit that feeds back the voltage applied to the load to an inverting terminal of the differential amplifier when current is flowing through the load;
a second circuit that feeds back a voltage different from the voltage applied to the load to the inverting terminal when no current is flowing through the load;
A drive circuit comprising: The first circuit is
comprising a first switch that is turned on when current is flowing through the load and turned off when no current is flowed through the load;
The drive circuit according to claim 1. The second circuit is
a second switch that is in an off state when current is flowing through the load and is in an on state when no current is flowing through the load;
The drive circuit according to claim 1 or claim 2. The second circuit is
comprising an impedance circuit having an impedance, and feeding back the voltage applied to the impedance circuit to the inverting terminal;
The drive circuit according to any one of claims 1 to 3. A control method executed by a drive circuit including a differential amplifier, a first circuit, and a second circuit, the method comprising:
When current is flowing through the load, feeding back the voltage applied to the load to the inverting terminal of the differential amplifier;
When no current is flowing through the load, feeding back a voltage different from the voltage applied to the load to the inverting terminal;
A control method executed by a drive circuit including: a differential amplifier; and a first circuit having a first switch; a first circuit configured to feed back a voltage applied to the load to an inverting terminal of the differential amplifier when current is flowing through the load; and a first circuit having a first switch; If not, a second circuit configured to feed back a voltage different from the voltage applied to the load to the inverting terminal and include a second switch;
turning the first switch on when a current is flowing through the load, and turning the first switch off when a current is not flowing through the load;
Turning the second switch into an OFF state when a current is flowing through the load, and turning the second switch into an ON state when a current is not flowing through the load;
A program to run.

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