JP2023135845A - Laminated electronic component - Google Patents

Abstract

To achieve a laminated electronic component capable of lowering the height thereof.SOLUTION: An electronic component 1 includes a ground conductor layer 611, inductors L11, L12, capacitors C11, C12, and a laminate 50. The inductor L11 and the capacitor C11 and the inductor L12 and the capacitor C12 are used to configure LC resonators 11, 12, respectively. In a lamination direction T, the LC resonators 11, 12 each exist between a bottom face 50A of the laminate 50 and the ground conductor layer 611, but do not exist between a top face 50B of the laminate 50 and the ground conductor layer 611. In the lamination direction T, the inductors L11, L12 are disposed between the bottom face 50A and the capacitor C11 and between the bottom face 50A and the capacitor C12, respectively.SELECTED DRAWING: Figure 7

Description

The present invention relates to a multilayer electronic component including a grounding conductor layer covering an LC resonator.

In recent years, small mobile communication devices such as mobile phones and smartphones have become more multi-functional and smaller, and as a result, the density of electronic components has been increased. As a result, in small mobile communication devices, the intervals between multiple electronic components mounted on a mounting board are becoming smaller.

When the distance between the plurality of electronic components becomes smaller, electromagnetic interference between the plurality of electronic components is more likely to occur. On the other hand, for example, Patent Document 1 discloses a bandpass filter that blocks external noise by providing a ground electrode on the upper surface side. The bandpass filter disclosed in Patent Document 1 includes an LC resonator in which a line electrode of an inductor faces a ground electrode.

Japanese Patent Application Publication No. 2013-128232

Electronic components used in small mobile communication devices are also required to be smaller and lower in profile. Here, when reducing the height of an electronic component that has a structure in which an inductor conductor layer that constitutes an inductor faces a ground conductor layer that is connected to the ground, such as the bandpass filter disclosed in Patent Document 1, think about. In this case, if the distance between the inductor conductor layer and the ground conductor layer is reduced, stray capacitance will occur between the inductor conductor layer and the ground conductor layer, and there is a risk that desired characteristics may not be obtained. Therefore, in the electronic component having the above structure, it is difficult to reduce the distance between the inductor conductor layer and the ground conductor layer, and as a result, it is difficult to reduce the height of the electronic component.

The present invention has been made in view of these problems, and its purpose is to provide a multilayer electronic component that is equipped with a grounding conductor layer that covers an LC resonator, and that can be made low in profile. It's about doing.

The multilayer electronic component of the present invention includes a grounding conductor layer connected to the ground, at least one inductor, a plurality of capacitors, and a laminate. The laminate includes a plurality of stacked dielectric layers, and has a first surface facing the mounted object and a second surface opposite to the first surface. The laminate is for integrating a grounding conductor layer, at least one inductor, and a plurality of capacitors. At least one inductor and multiple capacitors are used to configure at least one LC resonator. At least one LC resonator exists between the first surface and the grounding conductor layer in the stacking direction of the plurality of dielectric layers, but between the second surface and the grounding conductor layer. not exist. At least one inductor is disposed between the first surface and the plurality of capacitors in the stacking direction.

In the multilayer electronic component of the present invention, the grounding conductor layer may be located closer to the second surface than the first surface in the multilayer body.

Furthermore, the multilayer electronic component of the present invention may further include a plurality of capacitor conductor layers, each of which is integrated into the multilayer body and faces the ground conductor layer. In this case, the plurality of dielectric layers may include at least one dielectric layer interposed between the ground conductor layer and the plurality of capacitor conductor layers. The plurality of capacitors may include a ground conductor layer, a plurality of capacitor conductor layers, and at least one dielectric layer.

Furthermore, in the multilayer electronic component of the present invention, the at least one LC resonator may be a plurality of LC resonators. In this case, the at least one inductor may be a plurality of inductors. Further, in this case, each of the plurality of LC resonators may include at least one inductor among the plurality of inductors and at least one capacitor among the plurality of capacitors.

Furthermore, in the multilayer electronic component of the present invention, the at least one inductor connects the first through hole row, the second through hole row, and the first through hole row and the second through hole row. The conductor layer for an inductor may also be included. Each of the first through hole row and the second through hole row may be configured by two or more through holes connected in series. In this case, the inductor conductor layer may be arranged between the first surface and the first and second through-hole rows in the stacking direction. Further, in this case, the inductor conductor layer may include a portion extending non-parallel to both the lateral direction and the longitudinal direction of each of the plurality of dielectric layers. Further, the inductor conductor layer includes a portion extending in a first direction perpendicular to the lamination direction and a portion extending in a second direction perpendicular to the lamination direction and intersecting the first direction. You can stay there.

Furthermore, the multilayer electronic component of the present invention may further include a ground terminal disposed on the first surface and a plurality of through holes connecting the ground conductor layer and the ground within the multilayer body.

Furthermore, in the multilayer electronic component of the present invention, there may be no capacitor connected to the at least one inductor between the first surface and the at least one inductor.

In the multilayer electronic component of the present invention, at least one LC resonator exists between the first surface and the grounding conductor layer in the stacking direction of the plurality of dielectric layers, but between the second surface and the grounding conductor layer. It does not exist between it and the ground conductor layer. At least one inductor is disposed between the first surface and the plurality of capacitors in the stacking direction. As a result, according to the present invention, it is possible to realize a multilayer electronic component that can be made low in height.

FIG. 1 is a circuit diagram showing a circuit configuration of a multilayer electronic component according to an embodiment of the present invention. FIG. 1 is a perspective view showing the appearance of a laminated electronic component according to an embodiment of the present invention. FIG. 2 is an explanatory diagram showing pattern-formed surfaces of first to third dielectric layers in a laminate of a laminate type electronic component according to an embodiment of the present invention. FIG. 6 is an explanatory diagram showing pattern-formed surfaces of fourth to sixth dielectric layers in a laminate of a multilayer electronic component according to an embodiment of the present invention. FIG. 6 is an explanatory diagram showing pattern-formed surfaces of the seventh to ninth dielectric layers in the laminate of the multilayer electronic component according to an embodiment of the present invention. FIG. 3 is an explanatory diagram showing pattern-formed surfaces of the tenth to twelfth dielectric layers in the laminate of the multilayer electronic component according to an embodiment of the present invention. FIG. 1 is a perspective view showing the inside of a laminate of a laminate type electronic component according to an embodiment of the present invention. FIG. 3 is an explanatory diagram showing pattern-formed surfaces of first to third dielectric layers in a laminate of a laminate electronic component of a comparative example. FIG. 7 is an explanatory diagram showing pattern-formed surfaces of fourth to sixth dielectric layers in a laminate of a laminate type electronic component of a comparative example. FIG. 7 is an explanatory diagram showing pattern-formed surfaces of the seventh to ninth dielectric layers in a laminate of a laminated electronic component of a comparative example. FIG. 6 is an explanatory diagram showing pattern-formed surfaces of the 10th to 12th dielectric layers in a laminate of a laminate type electronic component of a comparative example. FIG. 3 is a perspective view showing the inside of a laminate of a laminate type electronic component of a comparative example. FIG. 7 is a characteristic diagram showing transmission attenuation characteristics and reflection attenuation characteristics of a model of a comparative example. It is a characteristic diagram showing the transmission attenuation characteristic and the reflection attenuation characteristic of the model of the example.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. First, with reference to FIG. 1, an outline of the configuration of a laminated electronic component (hereinafter simply referred to as electronic component) 1 according to an embodiment of the present invention will be described. FIG. 1 shows a bandpass filter as an example of the electronic component 1. Electronic component 1 includes at least one inductor and multiple capacitors. At least one inductor and multiple capacitors are used to configure at least one LC resonator.

The at least one LC resonator may be multiple LC resonators. In this case, the at least one inductor is a plurality of inductors. Each of the plurality of LC resonators is configured by at least one inductor among the plurality of inductors and at least one capacitor among the plurality of capacitors.

In particular, in this embodiment, the electronic component 1 includes a first port 2, a second port 3, and two LC resonances provided between the first port 2 and the second port 3 due to the circuit configuration. It is equipped with containers 11 and 12. The two LC resonators 11 and 12 are configured to be electromagnetically coupled. Each of the first and ports 2 and 3 is a port for inputting or outputting a signal. Note that in this application, the expression "on the circuit configuration" is used to refer to the layout on the circuit diagram rather than the layout in the physical configuration.

The electronic component 1 includes two inductors L11 and L12 as at least one inductor. Further, the electronic component 1 includes two capacitors C11 and C12 as a plurality of capacitors. Capacitors C11 and C12 are connected to inductors L11 and L12, respectively. The LC resonator 11 is composed of an inductor L11 and a capacitor C11. The LC resonator 12 is composed of an inductor L12 and a capacitor C12.

Inductors L11 and L12 are magnetically coupled to each other. The electronic component 1 further includes a capacitor C10 that capacitively couples the inductor L11 and the inductor L12.

Hereinafter, an example of another circuit configuration of the electronic component 1 will be described with reference to FIG. 1. The electronic component 1 further includes inductors L1, L2, L3, L4 and capacitors C1, C2, C3. One end of the inductor L1 is connected to the first port 2. One end of the capacitor C1 is connected to the other end of the inductor L1. One end of capacitor C10 is connected to the other end of capacitor C1.

One end of capacitor C2 is connected to the other end of capacitor C10. One end of inductor L2 is connected to the other end of capacitor C2. The other end of the inductor L2 is connected to the second port 3.

One end of the capacitor C3 is connected to the first port 2. The other end of capacitor C3 is connected to second port 3.

One end of each of the inductor L11 and the capacitor C11 is connected to the connection point between the capacitor C1 and the capacitor C10. One end of each of the inductor L12 and the capacitor C12 is connected to the connection point between the capacitor C2 and the capacitor C10. The other ends of the inductors L11 and L12 are connected to one end of the inductor L3. The other ends of the capacitors C11 and C12 are connected to one end of the inductor L4. The other ends of the inductors L3 and L4 are connected to ground.

Note that the inductor L1 and capacitor C1 may be connected in the opposite order from the example shown in FIG. 1. That is, one end of the capacitor C1 may be connected to the first port 2, one end of the inductor L1 may be connected to the other end of the capacitor C1, and one end of the capacitor C10 may be connected to the other end of the inductor L1. In this case as well, the same characteristics as the configuration shown in FIG. 1 can be obtained.

Similarly, the inductor L2 and capacitor C2 may be connected in the opposite order from the example shown in FIG. That is, one end of the inductor L2 may be connected to the other end of the capacitor C10, one end of the capacitor C2 may be connected to the other end of the inductor L2, and the other end of the capacitor C2 may be connected to the second port 3. In this case as well, the same characteristics as the configuration shown in FIG. 1 can be obtained.

Next, other configurations of the electronic component 1 will be described with reference to FIG. 2. FIG. 2 is a perspective view showing the external appearance of the electronic component 1.

The electronic component 1 further includes a laminate 50 including a plurality of stacked dielectric layers and a plurality of conductor layers. The first port 2, the second port 3, the LC resonators 11 and 12, the inductors L1 to L4, and the capacitors C1 to C3 and C10 are integrated into the laminate 50.

The laminate 50 has a bottom surface 50A and a top surface 50B located at both ends in the stacking direction T of the plurality of dielectric layers, and four side surfaces 50C to 50F connecting the bottom surface 50A and the top surface 50B. The side surfaces 50C and 50D face oppositely to each other, and the side faces 50E and 50F also face oppositely to each other. The side surfaces 50C to 50F are perpendicular to the top surface 50B and the bottom surface 50A.

Here, as shown in FIG. 2, the X direction, Y direction, and Z direction are defined. The X direction, Y direction, and Z direction are orthogonal to each other. In this embodiment, one direction parallel to the stacking direction T is defined as the Z direction. Further, the direction opposite to the X direction is defined as the -X direction, the direction opposite to the Y direction is defined as the -Y direction, and the direction opposite to the Z direction is defined as the -Z direction.

As shown in FIG. 2, the bottom surface 50A is located at the end of the laminate 50 in the −Z direction. The upper surface 50B is located at the end of the laminate 50 in the Z direction. Each of the bottom surface 50A and the top surface 50B has a rectangular shape that is long in the X direction. The side surface 50C is located at the end of the laminate 50 in the −X direction. The side surface 50D is located at the end of the laminate 50 in the X direction. The side surface 50E is located at the end of the stacked body 50 in the −Y direction. The side surface 50F is located at the end of the stacked body 50 in the Y direction.

The bottom surface 50A faces an unillustrated mounting object such as a board. The bottom surface 50A corresponds to the "first surface" in the present invention. In the laminate 50, the top surface 50B is located on the opposite side from the bottom surface 50A. The upper surface 50B corresponds to the "second surface" in the present invention.

The electronic component 1 further includes terminals 111, 112, 113, 114, 115, and 116 provided on the bottom surface 50A of the laminate 50. The terminals 111, 112, and 113 are arranged in this order in the X direction at a position closer to the side surface 50E than the side surface 50F. The terminals 114, 115, and 116 are arranged in this order in the −X direction at a position closer to the side surface 50F than the side surface 50E.

Terminal 114 corresponds to second port 3, and terminal 116 corresponds to first port 2. Therefore, the first and second ports 2 and 3 are provided on the bottom surface 50A of the stacked body 50. Each of terminals 111-113, 115 is connected to ground. Each of the terminals 111 to 113, 115 corresponds to a "ground terminal" in the present invention.

The electronic component 1 further includes a grounding conductor layer 611 that is integrated with the laminate 50 and connected to the ground. The grounding conductor layer 611 is placed closer to the top surface 50B than the bottom surface 50A. As described later, the LC resonators 11 and 12 exist between the bottom surface 50A and the ground conductor layer 611 in the stacking direction T, but do not exist between the top surface 50B and the ground conductor layer 611. .

Next, an example of a plurality of dielectric layers and a plurality of conductor layers that constitute the laminate 50 will be described with reference to FIGS. 3(a) to 6(c). In this example, the laminate 50 has 12 stacked dielectric layers. Hereinafter, these 12 dielectric layers will be referred to as 1st to 12th dielectric layers in order from the bottom. Further, the first to twelfth dielectric layers are represented by numerals 51 to 62.

In FIGS. 3(a) to 6(a), multiple circles represent multiple through holes. A plurality of through holes are formed in each of the dielectric layers 51 to 60. Each of the plurality of through holes is formed by filling a hole for the through hole with a conductive paste. Each of the plurality of through holes is connected to a terminal, a conductive layer, or another through hole.

FIG. 3(a) shows the patterned surface of the first dielectric layer 51. Terminals 111 to 116 are formed on the patterned surface of the dielectric layer 51. Further, in FIG. 3A, a specific through hole connected to the terminal 114 is indicated by a reference numeral 51T7, and a specific through hole connected to the terminal 116 is indicated by a reference numeral 51T6.

FIG. 3(b) shows the patterned surface of the second dielectric layer 52. Conductive layers 521 and 522 are formed on the patterned surface of the dielectric layer 52. Further, in FIG. 3(b), two specific through holes connected to two specific through holes 51T6 and 51T7 formed in the dielectric layer 51 are indicated by symbols 52T6 and 52T7, respectively.

FIG. 3C shows the patterned surface of the third dielectric layer 53. Conductive layers 531 and 532 are formed on the patterned surface of the dielectric layer 53. A specific through hole 52T6 formed in the dielectric layer 52 is connected to the conductor layer 531. A specific through hole 52T7 formed in the dielectric layer 52 is connected to the conductor layer 532.

Further, in FIG. 3(c), two specific through holes connected to the conductor layer 531 are indicated by the reference numeral 53T6, and two specific through holes connected to the conductor layer 532 are indicated by the reference numeral 53T7.

FIG. 4A shows the patterned surface of the fourth dielectric layer 54. FIG. In FIG. 4A, two specific through holes connected to two specific through holes 53T6 formed in the dielectric layer 53 are indicated by reference numerals 54T6, and two specific through holes formed in the dielectric layer 53 are shown as 54T6. Two specific through-holes connected to the through-hole 53T7 are indicated by reference numeral 54T7.

FIG. 4(b) shows the patterned surface of the fifth dielectric layer 55. Inductor conductor layers 551 and 552 are formed on the patterned surface of the dielectric layer 55. Each of the conductor layers 551, 552 has a first end and a second end located opposite to each other.

Further, in FIG. 4(b), a specific through hole connected to the first end of the conductive layer 551 is indicated by the symbol 55T1, and a specific through hole connected to the second end of the conductive layer 551 is indicated by the symbol 55T2. , a specific through hole connected to the first end of the conductive layer 552 is designated by the reference numeral 55T3, and a specific through hole connected to the second end of the conductor layer 552 is designated by the reference numeral 55T4. Further, two specific through holes connected to two specific through holes 54T6 formed in the dielectric layer 54 are indicated by reference numeral 55T6, and are connected to two specific through holes 54T7 formed in the dielectric layer 54. Two specific through-holes are designated 55T7.

FIG. 4C shows the patterned surface of the sixth dielectric layer 56. In FIG. 4(c), four specific through holes connected to four specific through holes 55T1, 55T2, 55T3, and 55T4 formed in the dielectric layer 55 are designated by symbols 56T1, 56T2, 56T3, and 56T4, respectively. It shows. Further, two specific through holes connected to two specific through holes 55T6 formed in the dielectric layer 55 are indicated by reference numeral 56T6, and are connected to two specific through holes 55T7 formed in the dielectric layer 55. Two specific through-holes are designated 56T7.

FIG. 5A shows the patterned surface of the seventh dielectric layer 57. A conductor layer 571 is formed on the patterned surface of the dielectric layer 57. Specific through holes 56T2 and 56T4 formed in dielectric layer 56 are connected to conductor layer 571.

Further, in FIG. 5A, two specific through holes connected to two specific through holes 56T1 and 56T3 formed in the dielectric layer 56 are indicated by symbols 57T1 and 57T3, respectively. Further, a specific through hole connected to the conductor layer 571 is indicated by the reference numeral 57T5. Further, two specific through holes connected to two specific through holes 56T6 formed in the dielectric layer 56 are indicated by reference numeral 57T6, and are connected to two specific through holes 56T7 formed in the dielectric layer 56. Two specific through-holes are designated 57T7.

FIG. 5(b) shows the patterned surface of the eighth dielectric layer 58. Conductive layers 581 and 582 are formed on the patterned surface of the dielectric layer 58. Two specific through holes 57T6 formed in dielectric layer 57 are connected to conductor layer 581. Two specific through holes 57T7 formed in dielectric layer 57 are connected to conductor layer 582.

In addition, in FIG. 5(b), three specific through holes connected to the three specific through holes 57T1, 57T3, and 57T5 formed in the dielectric layer 57 are indicated by symbols 58T1, 58T3, and 58T5, respectively. There is. Further, a specific through hole connected to the conductor layer 581 is indicated by the reference numeral 58T6, and a specific through hole connected to the conductor layer 582 is indicated by the reference numeral 58T7.

FIG. 5C shows the patterned surface of the ninth dielectric layer 59. On the patterned surface of the dielectric layer 59, capacitor conductor layers 591, 592, 593 and conductor layers 594, 595 are formed. Two specific through holes 58T1 and 58T3 formed in dielectric layer 58 are connected to conductor layers 594 and 595, respectively. Two specific through holes 58T6 and 58T7 formed in dielectric layer 58 are connected to conductor layers 591 and 592, respectively.

Further, in FIG. 5(c), a specific through hole connected to the conductor layer 594 is indicated by a reference numeral 59T1, a specific through hole connected to the conductor layer 595 is indicated by a reference numeral 59T3, and a specific through hole connected to the conductor layer 594 is indicated by a reference numeral 59T3. A specific through hole connected to the specific through hole 58T5 is indicated by a reference numeral 59T5.

FIG. 6A shows the patterned surface of the tenth dielectric layer 60. Capacitor conductor layers 601 and 602 are formed on the patterned surface of the dielectric layer 60. Two specific through holes 59T1 and 59T3 formed in dielectric layer 59 are connected to conductor layers 601 and 602, respectively. Further, in FIG. 6A, a specific through hole connected to a specific through hole 59T5 formed in the dielectric layer 59 is indicated by a reference numeral 60T5.

FIG. 6(b) shows the patterned surface of the eleventh dielectric layer 61. A grounding conductor layer 611 is formed on the patterned surface of the dielectric layer 61. A specific through hole 60T5 formed in the dielectric layer 60 is connected to a grounding conductor layer 611.

FIG. 6(c) shows the patterned surface of the twelfth dielectric layer 62. Marks 621 made of a conductive layer are formed on the patterned surface of the dielectric layer 62.

In the stacked body 50 shown in FIG. 2, the patterned surface of the first dielectric layer 51 is the bottom surface 50A of the stacked body 50, and the surface opposite to the patterned surface of the twelfth dielectric layer 62. The first to twelfth dielectric layers 51 to 62 are stacked so that the top surface 50B of the stacked body 50 is formed.

Each of the plurality of through holes shown in FIGS. 3(a) to 6(a), excluding the plurality of specific through holes with reference numerals, is formed by laminating the first to twelfth dielectric layers 51 to 62. At this time, it is connected to a conductor layer that overlaps in the stacking direction T or to another through hole that overlaps in the stacking direction T. Furthermore, among the plurality of through holes shown in FIGS. 3(a) to 6(a) excluding the plurality of specific through holes, the through holes located in the terminal or the conductor layer are It is connected to the.

FIG. 7 shows the inside of a stacked body 50 configured by stacking first to twelfth dielectric layers 51 to 62. As shown in FIG. 7, inside the laminate 50, a plurality of conductor layers and a plurality of through holes shown in FIGS. 3(a) to 6(c) are stacked. Note that in FIG. 7, the mark 621 is omitted.

Hereinafter, the correspondence between the circuit components of the electronic component 1 shown in FIG. 1 and the internal components of the laminate 50 shown in FIGS. 3(a) to 6(c) will be explained. The inductor L11 of the LC resonator 11 includes an inductor conductor layer 551 and specific through holes 55T1, 55T2, 56T1, 56T2, 57T1, and 58T1. The capacitor C11 of the LC resonator 11 includes a capacitor conductor layer 601, a ground conductor layer 611, and a dielectric layer 60 between these conductor layers. The capacitor conductor layer 601 is connected to a specific through hole 58T1 constituting the inductor L11 via the conductor layer 594 and a specific through hole 59T1.

The inductor L12 of the LC resonator 12 includes an inductor conductor layer 552 and specific through holes 55T3, 55T4, 56T3, 56T4, 57T3, and 58T3. The capacitor C12 of the LC resonator 11 includes a capacitor conductor layer 602, a ground conductor layer 611, and a dielectric layer 60 between these conductor layers. The capacitor conductor layer 602 is connected to a specific through hole 58T3 that constitutes the inductor L12 via the conductor layer 595 and a specific through hole 59T3.

The capacitor C10 is composed of capacitor conductor layers 593, 601, 602 and a dielectric layer 59 between these conductor layers.

Inductor L1 is configured by specific through holes 53T6, 54T6, 55T6, 56T6, and 57T6. Inductor L2 is configured by specific through holes 53T7, 54T7, 55T7, 56T7, and 57T7.

The capacitor C1 is composed of capacitor conductor layers 591 and 601 and a dielectric layer 59 between these conductor layers. The capacitor C2 is composed of capacitor conductor layers 592, 602 and a dielectric layer 59 between these conductor layers. Capacitor C3 is composed of conductor layers 521, 531, 532 and a dielectric layer 52 between these conductor layers.

Next, with reference to FIGS. 2 to 7, structural features of the electronic component 1 according to the present embodiment will be described. The LC resonators 11 and 12 exist between the bottom surface 50A and the ground conductor layer 611 in the stacking direction T, but do not exist between the top surface 50B and the ground conductor layer 611. That is, the inductors L11, L12 and the capacitors C11, C12 exist between the bottom surface 50A and the ground conductor layer 611 in the stacking direction T, but do not exist between the top surface 50B and the ground conductor layer 611. . When the laminate 50 is viewed from a position ahead of the laminate 50 in the Z direction, the grounding conductor layer 611 covers the LC resonators 11 and 12.

The inductors L11 and L12 are arranged in the stacking direction T between the bottom surface 50A and the capacitors C11 and C12. That is, the inductors L11 and L12 are arranged ahead of the capacitors C11 and C12 in the −Z direction. The −Z direction is also the direction from the grounding conductor layer 611 toward the bottom surface 50A.

Capacitors C1, C2, and C10 are arranged in the stacking direction T between inductors L11 and L12 and capacitors C11 and C12.

Between the bottom surface 50A and the inductors L11, L12, there is a capacitor C3 not connected to the inductors L11, L12, but there is no capacitor connected to the inductors L11, L12.

The capacitor conductor layer 601 faces the ground conductor layer 611. The dielectric layer 60 is interposed between the capacitor conductor layer 601 and the ground conductor layer 611. As described above, the capacitor C11 includes the capacitor conductor layer 601, the ground conductor layer 611, and the dielectric layer 60.

The capacitor conductor layer 602 faces the ground conductor layer 611. The dielectric layer 60 is interposed between the capacitor conductor layer 602 and the ground conductor layer 611. As described above, the capacitor C12 includes the capacitor conductor layer 602, the ground conductor layer 611, and the dielectric layer 60.

The grounding conductor layer 611 is connected to the terminal 115 through a portion of a plurality of through holes excluding a plurality of specific through holes with reference numerals, and is connected to a plurality of through holes excluding a plurality of specific through holes. It is connected to the terminals 111 to 113 via the other part of the hole and the conductor layer 522. In this embodiment, a conductor layer for connecting the ground conductor layer 611 and the terminals 111 to 113, 115 is not provided on the side surfaces 50C to 50F of the laminate 50.

Here, a structure formed by connecting two or more through holes in series is referred to as a through hole array. The laminate 50 includes a through hole row T1 made up of through holes 55T1, 56T1, 57T1, 58T1, a through hole row T2 made up of through holes 55T2, 56T2, and a through hole 55T3, 56T3, 57T3, 58T3. The through-hole row T3 includes a through-hole row T3 made up of a plurality of through-holes, and a through-hole row T4 made up of through-holes 55T4 and 56T4. The through-hole rows T1 and T3 correspond to the "first through-hole row" in the present invention, and the through-hole rows T2 and T4 correspond to the "second through-hole row" in the present invention.

The inductor conductor layer 551 connects the through hole row T1 and the through hole row T2. The inductor conductor layer 551 is arranged in the stacking direction T between the bottom surface 50A and the through hole rows T1 and T2. Inductor L11 includes through-hole rows T1 and T2 and an inductor conductor layer 551.

The inductor conductor layer 551 is formed in the lateral direction of each of the plurality of dielectric layers 51 to 62 (same as the lateral direction of the bottom surface 50A and the top surface 50B) and in the longitudinal direction of each of the plurality of dielectric layers 51 to 62 (the bottom surface 50A and the upper surface 50B). The inductor conductor layer 551 further includes a portion 551B extending in the lateral direction of each of the plurality of dielectric layers 51 to 62 (same as the lateral direction of the bottom surface 50A and the top surface 50B). Particularly in this embodiment, the portion 551A extends in a direction parallel to the direction inclined from the Y direction toward the −X direction. Portion 551B extends in a direction parallel to the Y direction.

The inductor conductor layer 552 connects the through hole row T3 and the through hole row T4. The inductor conductor layer 552 is arranged in the stacking direction T between the bottom surface 50A and the through-hole rows T3 and T4. Inductor L12 includes through-hole rows T3 and T4 and an inductor conductor layer 552.

The inductor conductor layer 552 is formed in the lateral direction of each of the plurality of dielectric layers 51 to 62 (same as the lateral direction of the bottom surface 50A and the top surface 50B) and the longitudinal direction of each of the plurality of dielectric layers 51 to 62 (the bottom surface 50A and the upper surface 50B). The inductor conductor layer 552 further includes a portion 552B extending in the lateral direction of each of the plurality of dielectric layers 51 to 62 (same as the lateral direction of the bottom surface 50A and the top surface 50B). Particularly in this embodiment, the portion 552A extends in a direction parallel to the direction inclined from the Y direction toward the X direction. Portion 552B extends in a direction parallel to the Y direction.

Next, the functions and effects of the electronic component 1 according to the present embodiment will be explained. In this embodiment, the grounding conductor layer 611 covers the LC resonators 11 and 12, that is, the inductors L11 and L12 and the capacitors C11 and C12. If the inductor is placed between the capacitor and the grounding conductor layer in the stacking direction T, if the distance between the inductor and the grounding conductor layer becomes small, there will be a stray capacitance between the inductor and the grounding conductor layer. may occur, making it impossible to obtain desired characteristics. In order to prevent this, it is necessary to intentionally increase the distance between the inductor and the grounding conductor layer.

In contrast, in the present embodiment, inductors L11 and L12 are arranged between bottom surface 50A and capacitors C11 and C12 in stacking direction T. As a result, according to the present embodiment, the distance between the grounding conductor layer 611 and the inductors L11 and L12 can be increased compared to the above case. As a result, according to the present embodiment, it is not necessary to intentionally increase the distance between the grounding conductor layer 611 and the inductors L11 and L12. As a result, according to this embodiment, the height of the electronic component 1 can be reduced.

Furthermore, in this embodiment, there are no circuit components of the electronic component 1, not only the LC resonators 11 and 12, between the upper surface 50B and the grounding conductor layer 611. Therefore, in this embodiment, there is no through hole in the dielectric layer 61 on which the grounding conductor layer 611 is formed. As a result, according to the present embodiment, the area of the grounding conductor layer 611 can be increased compared to the case where the grounding conductor layer 611 is formed in another dielectric layer in which a through hole is present. .

Further, in this embodiment, capacitors C11 and C12 are configured by having capacitor conductor layers 601 and 602 facing ground conductor layer 611. As described above, since the area of the ground conductor layer 611 can be increased, the area of each of the capacitor conductor layers 601 and 602 can also be increased. As a result, according to the present embodiment, the range of capacitances of the capacitors C11 and C12 that can be designed can be increased, and the degree of freedom in designing the electronic component 1 can be increased.

Furthermore, as in the electronic component of a comparative example described later, three or more capacitor conductor layers arranged at different positions in the stacking direction T may be provided in order to increase the capacitance. In contrast, in the present embodiment, by increasing the area of the capacitor conductor layers 601 and 602, the range in which the capacitance of the capacitors C11 and C12 can be increased is larger than that of the conventional case. According to this embodiment, the height of the electronic component 1 can also be reduced by this.

Furthermore, in this embodiment, the inductor conductor layer 551 of the inductor L11 and the inductor conductor layer 552 of the inductor L12 are arranged at a relatively distant position from the ground conductor layer 611. Stray capacitance is less likely to occur between the Therefore, according to this embodiment, the width and length of the inductor conductor layers 551 and 552 can be increased without causing stray capacitance or increasing the stray capacitance. In this manner, according to the present embodiment, the degree of freedom in designing the inductors L11 and L12 can be increased. For example, by lengthening the inductor conductor layer 551, the space surrounded by the inductor conductor layer 551, the through-hole rows T1, and the through-hole rows T2, that is, the opening of the inductor L11 can be increased. Similarly, by lengthening the inductor conductor layer 552, the space surrounded by the inductor conductor layer 552, the through-hole rows T3, and the through-hole rows T4, that is, the opening of the inductor L12 can be increased.

Particularly in this embodiment, each of the inductor conductor layers 551 and 552 includes a portion extending in a direction inclined from the Y direction. As a result, according to the present embodiment, compared to the case where each of the inductor conductor layers 551 and 552 consists of only a portion extending in a direction parallel to the Y direction (the lateral direction of the dielectric layer 55), The length of the inductor conductor layers 551 and 552 can be increased.

Next, the effects of this embodiment will be described with reference to simulation results. In the simulation, a model of the example and a model of the comparative example were used. The model of the example is a model of the electronic component 1 according to the present embodiment. The comparative example model is a model of an electronic component of the comparative example. The circuit configuration of the electronic component of the comparative example is the same as the circuit configuration of the electronic component 1 according to the present embodiment shown in FIG.

First, the configuration of an electronic component 101 as a comparative example will be described with reference to FIGS. 8(a) to 12. The electronic component 101 includes a stacked body 70 that includes stacked first to twelfth dielectric layers 71 to 82. The circuit components of the electronic component 101 are integrated into the laminate 70. In FIGS. 8(a) to 11(a), multiple circles represent multiple through holes. A plurality of through holes are formed in each of the dielectric layers 71-80.

FIG. 8A shows the patterned surface of the first dielectric layer 71. Terminals 211, 212, 213, 214, 215, and 216 are formed on the patterned surface of the dielectric layer 71. Terminal 214 corresponds to second port 3 and terminal 216 corresponds to first port 2.

FIG. 8(b) shows the patterned surface of the second dielectric layer 72. Capacitor conductor layers 721 and 722 are formed on the patterned surface of the dielectric layer 72. FIG. 8C shows the patterned surface of the third dielectric layer 73. Capacitor conductor layers 731 and 732 are formed on the patterned surface of the dielectric layer 73.

FIG. 9A shows the patterned surface of the fourth dielectric layer 74. Capacitor conductor layers 741 and 742 are formed on the patterned surface of the dielectric layer 74. FIG. 9(b) shows the patterned surface of the fifth dielectric layer 75. On the patterned surface of the dielectric layer 75, capacitor conductor layers 751, 752, 753 and conductor layers 754, 755, 756, 757 are formed. FIG. 9C shows the patterned surface of the sixth dielectric layer 76. A capacitor conductor layer 761 is formed on the patterned surface of the dielectric layer 76 .

FIG. 10A shows the patterned surface of the seventh dielectric layer 77. A conductor layer 771 is formed on the patterned surface of the dielectric layer 77. FIG. 10(b) shows the patterned surface of the eighth dielectric layer 78. No conductor layer is formed on the patterned surface of the dielectric layer 78.

FIG. 10C shows the patterned surface of the ninth dielectric layer 79. Inductor conductor layers 791 and 792 are formed on the patterned surface of the dielectric layer 79. The shape of each of the inductor conductor layers 791 and 792 is substantially the same as the shape of each of the inductor conductor layers 551 and 552 in this embodiment.

FIG. 11A shows the patterned surface of the tenth dielectric layer 80. No conductor layer is formed on the patterned surface of the dielectric layer 80. FIG. 11(b) shows the patterned surface of the eleventh dielectric layer 81. A ground conductor layer 811 is formed on the patterned surface of the dielectric layer 81 . FIG. 11C shows the patterned surface of the 12th dielectric layer 82. Marks 821 made of a conductive layer are formed on the patterned surface of the dielectric layer 82 .

In the laminate 70 of the electronic component 101 of the comparative example, the pattern-formed surface of the first dielectric layer 71 is the bottom surface of the laminate 70, and the pattern-formed surface of the twelfth dielectric layer 82 is the opposite side to the pattern-formed surface of the twelfth dielectric layer 82. The first to twelfth dielectric layers 71 to 82 are stacked so that their surfaces become the upper surface of the laminate 70.

Each of the plurality of through holes is connected to a conductor layer that overlaps in the stacking direction T or another through hole that overlaps in the stacking direction T when the first to twelfth dielectric layers 71 to 82 are stacked. . Further, among the plurality of through holes, a through hole located within the terminal or within the conductor layer is connected to the terminal or the conductor layer.

FIG. 12 shows the inside of a stacked body 70 configured by stacking first to twelfth dielectric layers 71 to 82. As shown in FIG. 12, inside the laminate 70, a plurality of conductor layers and a plurality of through holes shown in FIGS. 8(a) to 11(c) are stacked. Note that in FIG. 12, the mark 821 is omitted.

Hereinafter, the circuit components of the electronic component 101 (same as the circuit components of the electronic component 1 shown in FIG. 1) and the internal configuration of the laminate 70 shown in FIGS. 8(a) to 11(c) will be described. The correspondence with elements will be explained. The inductor L11 of the LC resonator 11 includes an inductor conductor layer 791, a plurality of through holes connecting the inductor conductor layer 791 and the conductor layer 756, and a plurality of through holes connecting the inductor conductor layer 791 and the conductor layer 771. It consists of a through hole. The capacitor C11 of the LC resonator 11 is composed of capacitor conductor layers 721, 731, 741 and dielectric layers 72, 73 between these conductor layers.

The inductor L12 of the LC resonator 12 includes an inductor conductor layer 792, a plurality of through holes connecting the inductor conductor layer 792 and the conductor layer 757, and a plurality of through holes connecting the inductor conductor layer 792 and the conductor layer 771. It consists of a through hole. The capacitor C12 of the LC resonator 11 is composed of capacitor conductor layers 722, 732, 742 and dielectric layers 72, 73 between these conductor layers.

The capacitor C10 is composed of capacitor conductor layers 741, 742, 753 and a dielectric layer 74 between these conductor layers.

The inductor L1 is composed of a plurality of through holes that connect the terminal 216 and the capacitor conductor layer 751. The inductor L2 is composed of a plurality of through holes that connect the terminal 214 and the capacitor conductor layer 752.

The capacitor C1 is composed of capacitor conductor layers 741 and 751 and a dielectric layer 74 between these conductor layers. The capacitor C2 is composed of capacitor conductor layers 742 and 752 and a dielectric layer 74 between these conductor layers. The capacitor C3 is composed of capacitor conductor layers 751, 752, 761 and a dielectric layer 75 between these conductor layers.

In the electronic component 101 of the comparative example, the inductors L11 and L12 are arranged in the stacking direction T between the capacitors C11 and C12 and the grounding conductor layer 811. Further, the inductor conductor layers 791 and 792 face the ground conductor layer 811. No capacitor is present between the inductor conductor layers 791 and 792 and the ground conductor layer 811.

Next, the results of the simulation will be explained. In the simulation, the passbands of the electronic component 1 and the electronic component 101 are almost the same, and the attenuation characteristics in the lower frequency region of the passband of the electronic component 1 and the electronic component 101 are almost the same. An example model and a comparative example model were designed.

FIG. 13 is a characteristic diagram showing the transmission attenuation characteristics and reflection attenuation characteristics of a model of a comparative example. In FIG. 13, the horizontal axis shows the frequency, and the vertical axis shows the amount of attenuation. Further, in FIG. 13, a curve with reference numeral 91 indicates the transmission attenuation characteristic of the electronic component 101. Further, a curve labeled 92 shows the return loss characteristic at the first port 2 of the electronic component 101.

FIG. 14 is a characteristic diagram showing the transmission attenuation characteristics and reflection attenuation characteristics of the model of the comparative example. In FIG. 14, the horizontal axis shows the frequency, and the vertical axis shows the amount of attenuation. Moreover, in FIG. 14, a curve with reference numeral 93 indicates the transmission attenuation characteristic of the electronic component 1. Further, a curve labeled 94 shows the return loss characteristic at the first port 2 of the electronic component 1.

In a bandpass filter, it is sometimes required to increase the amount of pass attenuation expressed by the absolute value of the amount of attenuation in the frequency region on the high side of the pass band. It can be seen from FIGS. 13 and 14 that in the model of the example, the amount of pass attenuation is larger in a wide frequency region higher than the pass band, compared to the model of the comparative example. As understood from the simulation results, according to the present embodiment, by arranging the inductors L11 and L12 between the bottom surface 50A and the capacitors C11 and C12, a wide frequency range higher than the passband can be achieved. In this case, the amount of passing attenuation can be increased.

Note that the present invention is not limited to the above embodiments, and various modifications are possible. For example, the electronic component of the present invention may include only one LC resonator, or may include three or more LC resonators.

1...Electronic component, 2...First port, 3...Second port, 11, 12...Resonator, 50...Laminated body, 50A...Bottom surface, 50B...Top surface, 50C to 50F...Side surface, 611...For grounding Conductor layer, C1 to C3, C10 to C12...capacitor, L1 to L4, L11, L12...inductor.

Claims (11)

a grounding conductor layer connected to the ground;
at least one inductor;
multiple capacitors,
It includes a plurality of laminated dielectric layers, has a first surface facing the mounted object, and a second surface opposite to the first surface, the grounding conductor layer, the at least one a laminate for integrating one inductor and the plurality of capacitors,
The at least one inductor and the plurality of capacitors are used to configure at least one LC resonator,
The at least one LC resonator exists between the first surface and the grounding conductor layer in the stacking direction of the plurality of dielectric layers, but between the second surface and the grounding conductor layer. It does not exist between layers,
The multilayer electronic component, wherein the at least one inductor is disposed between the first surface and the plurality of capacitors in the stacking direction. 2. The multilayer electronic component according to claim 1, wherein the grounding conductor layer is located closer to the second surface than the first surface in the multilayer body. Further, a plurality of capacitor conductor layers each integrated with the laminate and facing the ground conductor layer,
The plurality of dielectric layers include at least one dielectric layer interposed between the ground conductor layer and the plurality of capacitor conductor layers,
3. The multilayer electronic component according to claim 1, wherein the plurality of capacitors are constituted by the ground conductor layer, the plurality of capacitor conductor layers, and the at least one dielectric layer. the at least one LC resonator is a plurality of LC resonators;
4. The multilayer electronic component according to claim 1, wherein the at least one inductor is a plurality of inductors. 5. The LC resonator according to claim 4, wherein each of the plurality of LC resonators is configured by at least one inductor among the plurality of inductors and at least one capacitor among the plurality of capacitors. Laminated electronic components. The at least one inductor includes a first through hole row, a second through hole row, and an inductor conductor layer connecting the first through hole row and the second through hole row,
6. Each of the first through hole row and the second through hole row is configured by two or more through holes connected in series. The laminated electronic component described in . 7. The multilayer electronic component according to claim 6, wherein the inductor conductor layer is disposed between the first surface and the first and second through hole rows in the stacking direction. . The laminate according to claim 6 or 7, wherein the inductor conductor layer includes a portion extending non-parallel to both the lateral direction and the longitudinal direction of each of the plurality of dielectric layers. type electronic components. The inductor conductor layer has a portion extending in a first direction perpendicular to the lamination direction, and a portion extending in a second direction perpendicular to the lamination direction and intersecting the first direction. 9. The laminated electronic component according to claim 8, further comprising a laminate type electronic component. Further, a ground terminal disposed on the first surface;
10. The multilayer electronic component according to claim 1, further comprising a plurality of through holes connecting the ground conductor layer and the ground in the multilayer body. 11. The multilayer electronic component according to claim 1, wherein there is no capacitor connected to the at least one inductor between the first surface and the at least one inductor. .

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