JP2023126858A - Wiring board and element - Google Patents

Abstract

To provide a wiring board in which cracking of a grass substrate at a mounting of a functional chip is suppressed, and a functional element using the wiring board.SOLUTION: A wiring board 10 includes: a glass substrate 1; a wiring layer 2 arranged on one surface side of the glass substrate 1; an isolation layer 3 that includes an open part H arranged on a surface side on the wiring layer 2 side of the glass substrate 1; and a connection convex part 4 that is arranged on the open part H of the isolation layer 3 and is electrically connected to the wiring layer 2. The wiring board is provided with a connection convex part group having the two or more connection convex parts 4 including the reference convex part in a region of a radial diameter of 100 μm from a center of a reference convex part when one connection convex part 4 is the reference convex part. A stress buffer layer 5 is arranged between at least one or more connection convex parts 4 of the connection convex part group and the glass substrate 1.SELECTED DRAWING: Figure 1

Description

The present disclosure relates to a wiring board and an element using the same.

For example, functional chips such as semiconductor chips and wiring boards for mounting the functional chips are used in various electronic devices. The wiring board has, for example, a laminated structure in which a support substrate, a wiring layer, and an insulating layer having an opening are laminated in this order, and the opening of the insulating layer has a connection electrically connected to the wiring layer. It has a configuration in which a convex portion is provided for use. The connection convex portion is, for example, a portion electrically connected to a terminal of a functional chip, and is formed of, for example, a solder bump or the like.

For example, Patent Document 1 discloses, as a method for manufacturing a wiring board, a step of measuring the height of the second conductor layer in at least one product region among a plurality of product regions; If the layer height is less than the threshold, a first chemical solution that selectively etches the first conductor layer is used to remove the portion of the first conductor layer exposed by removing the resin layer and the second conductor layer. Etching is performed on a portion located directly below the outer edge of the layer, and when the height of the second conductor layer is equal to or higher than a threshold value, a second chemical solution is applied to etch the first conductor layer and the second conductor layer. A manufacturing method is disclosed that includes a step of etching a portion of the first conductor layer exposed by removing the resin layer and a part of the second conductor layer. The purpose is to reduce defects caused by variations in the height of solder bumps.

Japanese Patent Application Publication No. 2015-23045

In recent years, with the miniaturization and higher performance of electronic devices, there has been a demand for narrower pitches, such as mounting functional chips on the wiring board at narrower pitches. Furthermore, in order to successfully mount a functional chip on a wiring board, it is required that the height variation of the connecting convex portions arranged on the wiring board be small. However, in narrow-pitch wiring boards, because the distance between adjacent connection protrusions is short, it is difficult to make the heights of adjacent connection protrusions the same while suppressing contact in the surface direction. .

In addition, resin substrates and glass epoxy substrates have traditionally been used as support substrates for wiring boards, but these substrates have low heat resistance, so they are difficult to use during the heat treatment process when mounting functional chips. Distortion may occur. Therefore, from the viewpoint of heat resistance, consideration has been given to using a glass substrate as a support substrate constituting a wiring board.

However, as mentioned above, in narrow pitch wiring boards, it is difficult to sufficiently suppress variations in the height of the connection protrusions, and furthermore, when a glass substrate is used as a support substrate, functional chips Pushing during mounting causes local stress concentration on the wiring board, which may cause the glass substrate to break.

The present disclosure has been made in view of the above-mentioned circumstances, and its main purpose is to provide a wiring board in which cracking of the glass substrate is suppressed when a functional chip is mounted, and a functional element using the wiring board. shall be.

In order to achieve the above object, the present disclosure includes a glass substrate, a wiring layer disposed on one side of the glass substrate, and an opening disposed on the side of the wiring layer side of the glass substrate. and a connecting convex portion disposed in an opening of the insulating layer and electrically connected to the wiring layer, wherein one of the connecting convex portions is used as a reference convex portion. In this case, a connecting convex group having two or more of the connecting convex parts including the reference convex part is provided in an area with a radius of 100 μm from the center of the reference convex part, and at least one of the connecting convex groups includes A wiring board is provided, in which a stress buffer layer is disposed between one or more of the connection convex portions and the glass substrate.

According to the present disclosure, a stress buffer layer is disposed between at least one of the connection convex portions of the connection convex portion group and the glass substrate, so that when a functional chip is mounted, It is possible to obtain a wiring board in which cracking of the glass substrate is suppressed.

In the above disclosure, when the surface of the glass substrate on the wiring layer side of the group of connection convex parts is used as a reference plane, from the top of one of the connection convex parts on which the stress buffer layer is disposed, The height to the reference surface is the height from the top of the connection protrusion on which the stress buffer layer is arranged, which is thinner than one of the connection protrusions, to the reference plane, or the stress buffer layer. It is preferable that the height is higher than the height from the top of the connecting convex portion on which the connecting convex portion is not disposed to the reference plane. This is because cracking of the glass substrate can be suitably suppressed during mounting of functional chips.

In the above disclosure, when the surface of the glass substrate on the wiring layer side of the group of connection protrusions is used as a reference plane, the height from the top of the connection protrusion to the reference plane is the highest. It is preferable that the connecting convex portion is arranged at a position corresponding to the outermost terminal of the functional chip to be mounted. This is because it is possible to obtain a wiring board on which functional chips can be better mounted.

In the above disclosure, when the surface of the glass substrate on the wiring layer side of the group of connection convex portions is taken as a reference plane, from the top of the connection convex portion on which the stress buffer layer is disposed, to the reference plane. It is preferable that the ratio of the thickness of the stress buffer layer to the height of the connection protrusion having the highest height is 10% or more. This is because a stress buffer layer that can easily suppress stress concentration during mounting of functional chips can be obtained.

In the above disclosure, it is preferable that the connection convex portion is a plating layer. This is because connection convex portions can be formed satisfactorily on narrow-pitch wiring boards.

In the above disclosure, it is preferable that the stress buffer layer is a resin layer. This is because a stress buffer layer that can easily suppress stress concentration during mounting of functional chips can be obtained.

The present disclosure provides an element that includes the above-mentioned wiring board and a functional chip electrically connected to the connection protrusion of the connection protrusion group.

According to the present disclosure, by having the above-mentioned wiring board, it is possible to provide an element in which a functional chip is satisfactorily mounted.

The wiring board of the present disclosure has the effect of being able to suppress cracking of the glass substrate during mounting of functional chips.

FIG. 1 is a schematic plan view and a schematic cross-sectional view illustrating a wiring board of the present disclosure. It is a schematic plan view explaining the convex part group for connection in this indication. 1 is a schematic cross-sectional view illustrating a wiring board of the present disclosure. FIG. 1 is a schematic plan view illustrating a functional chip according to the present disclosure. FIG. 2 is an explanatory diagram of a wiring board according to the present disclosure. FIG. 2 is an explanatory diagram of a wiring board according to the present disclosure. FIG. 1 is a schematic plan view and a schematic cross-sectional view illustrating an element of the present disclosure.

Embodiments of the present disclosure will be described below with reference to the drawings and the like. However, the present disclosure can be implemented in many different ways, and should not be construed as being limited to the description of the embodiments exemplified below. Further, in order to make the explanation clearer, the drawings may schematically represent the width, thickness, shape, etc. of each part compared to the actual form, but this is just an example and does not limit the interpretation of the present disclosure. It's not something you do. In addition, in this specification and each figure, the same elements as those described above with respect to the previously shown figures are denoted by the same reference numerals, and detailed explanations may be omitted as appropriate.

In this specification, when expressing a mode in which another member is placed on top of a certain member, when it is simply written as "above" or "below", unless otherwise specified, it means that it is in contact with a certain member. This includes both cases in which another member is placed directly above or below a certain member, and cases in which another member is placed above or below a certain member via another member.

Similarly, in this specification, when the phrase "on the side of a certain member" is used, unless otherwise specified, there are cases in which another member is placed directly in contact with the surface of a certain member, and cases in which another member is placed directly in contact with the surface of a certain member. This includes both the case where another member is placed on the surface of the object via another member.

The present disclosure relates to a wiring board and an element using the same.
As described above, there is a demand for narrower pitches in wiring boards, such as mounting functional chips at narrower pitches. Furthermore, in order to successfully mount a functional chip on a wiring board, it is required that the height variation of the connecting convex portions arranged on the wiring board be small. As a method of adjusting the height variation of the connection convex portion, for example, a method of adjusting the amount of solder placed in the opening of the insulating layer and adjusting the size of the solder bump can be considered. As another example, a method of forming the connecting convex portion by a plating method is also being considered. When forming the connecting protrusions using a plating method, the thickness of the plating layer can be kept constant by performing the plating process until it reaches a saturated state, thereby suppressing variations in the height of the connecting protrusions. It is thought that it can be done.
However, in a wiring board with a narrow pitch, the distance between adjacent connection protrusions is short, so the above-mentioned method suppresses contact between adjacent connection protrusions in the surface direction while increasing the height. It is difficult to arrange.

Further, from the viewpoint of heat resistance, the use of a glass substrate as a support substrate for the wiring layer is being considered. However, in narrow-pitch wiring boards, it is difficult to sufficiently suppress variations in the height of the connection convex parts, and furthermore, when a glass substrate is used as a support substrate, it is difficult to sufficiently suppress the height variation of the connection protrusions. As a result, local stress concentration occurs on the wiring board, and the glass substrate may break.

To solve the above problem, for example, it is being considered to reduce the height difference of the connection convex part by forming the insulating layer used in the wiring board with an inorganic material layer. It is difficult to sufficiently suppress cracking.
The wiring board of the present disclosure and an element using the same are inventions made to solve the above problems.

A. Wiring Board The wiring board of the present disclosure includes a glass substrate, a wiring layer disposed on one side of the glass substrate, and an insulating layer disposed on the wiring layer side of the glass substrate and having an opening. , a wiring board having a connection protrusion disposed in the opening of the insulating layer and electrically connected to the wiring layer, wherein one of the connection protrusions is taken as a reference protrusion; A connection protrusion group having two or more of the connection protrusions including the reference protrusion is provided in an area with a radius of 100 μm from the center of the protrusion, and at least one of the connection protrusion groups is provided. A stress buffer layer is disposed between the connection convex portion and the glass substrate.

The wiring board of the present disclosure will be explained using figures. FIG. 1(a) is a schematic plan view showing an example of the wiring board of the present disclosure, FIG. 1(b) is an enlarged view of portion A in FIG. 1(a), and FIG. It is a sectional view taken along the line BB of FIG. The wiring board 10 shown in FIGS. 1A to 1C includes a glass substrate 1, a wiring layer 2 disposed on one side of the glass substrate 1, and a wiring layer 2 disposed on the side of the wiring layer 2 of the glass substrate 1. The insulating layer 3 is disposed in the insulating layer 3 and has an opening H, and the connecting convex part 4 is disposed in the opening of the insulating layer 3 and is electrically connected to the wiring layer 2.

Further, as shown in FIGS. 1(b) and 1(c), when one connection protrusion 4 is a reference protrusion 4S, the wiring board 10 is arranged in an area of a predetermined radius R1 from the center of the reference protrusion 4S. A connection protrusion group 4G having two or more connection protrusions 4 including a reference protrusion 4S is provided. The radius R1 is, for example, 100 μm. In FIGS. 1(b) and 1(c), when the connecting convex portion 4e is taken as the reference convex portion 4S, nine connections including the connecting convex portion 4e are located in an area of radius R1 from the center of the connecting convex portion 4e. An example is shown in which a connection protrusion group 4G having connection protrusions 4a to 4i is provided. Further, as shown in FIG. 1(c), in the wiring board 10, a stress buffer layer 5 is disposed between at least one connection protrusion 4 among the connection protrusion group 4G and the glass substrate 1. has been done.

FIG. 1C shows an example in which the connecting convex portion 4 is made of two plating layers, a plating layer 41 and a plating layer 42. Further, the wiring board 10 has a first wiring layer 2a disposed as the wiring layer 2 on the surface side of the stress buffer layer 5 on the glass substrate 1 side, and a first wiring layer 2a disposed on the surface side of the stress buffer layer 5 on the connection convex portion side. An example is shown in which the second wiring layer 2b is formed. Further, an example in which a conductive layer 6 is provided between the first wiring layer 2a and the second wiring layer 2b is shown.

According to the present disclosure, a stress buffer layer is disposed between at least one of the connection convex portions of the connection convex portion group and the glass substrate, so that when a functional chip is mounted, It is possible to obtain a wiring board in which cracking of the glass substrate is suppressed.

Hereinafter, each configuration of the wiring board of the present disclosure will be explained.

1. Connection Protrusion Group The wiring board of the present disclosure includes a connection protrusion group composed of a plurality of connection protrusions. The connection protrusion group includes two or more connection protrusions including the reference protrusion in an area of a predetermined radius from the center of the reference protrusion, when one connection protrusion is taken as a reference protrusion. have

"Center of the reference protrusion (center of the connection protrusion)" refers to the center or center of gravity of the planar view shape of the reference protrusion (connection protrusion); for example, if the planar view shape of the reference protrusion is If the reference convex part has a circular or elliptical shape, it refers to its center; if the reference convex part has a polygonal shape in plan view, it refers to its center of gravity.

"When the one connection protrusion is taken as a reference protrusion, having two or more connection protrusions including the reference protrusion in an area of a predetermined radius from the center of the reference protrusion" means This means that the connecting convex portion adjacent to an area within a predetermined radius from the center of the reference convex portion is located so as to overlap with the area within the predetermined radius in plan view.

In the case where "when the one connection convex part is taken as a reference convex part, there are two or more connection convex parts including the reference convex part in an area of a predetermined radius from the center of the reference convex part" Specifically, as shown in FIG. 1(b), when the connection convex part 4e is the reference convex part 4S, the connection convex part adjacent to the area of a predetermined radius R1 from the center of the reference convex part 4S This refers to the case where 4a, 4b, 4c, 4d, 4f, 4g, 4h, and 4i are located so as to overlap a region with a predetermined radius R1 in a plan view. In other words, in the connection protrusion group, adjacent connection terminals are arranged within a predetermined distance from the center of the reference protrusion.

The reference protrusion is set to define the relative positional relationship between two or more connection protrusions. In the present disclosure, any connection convex portion of the wiring board can be set as the reference convex portion. For example, in FIG. 1(b), the case where the connecting convex portion 4e is set as the reference convex portion 4S is explained as an example, but for example, any of the other connecting convex portions 4a to 4d, 4f to 4h It is also possible to set this as the reference convex portion. Which of the plurality of connection convex portions on the wiring board is to be used as the reference convex portion can be appropriately set, for example, depending on the arrangement of the connection convex portions.

The connection projection group has two or more connection projections including the reference projection in an area within a predetermined radius from the center of the reference projection. The region at a predetermined radius from the center of the reference convex portion is a region with a radius of 100 μm, but for example, it may be a region with a radius of 100 μm or less, a region with a radius of 80 μm or less, or a region with a radius of 60 μm or less. . Further, the region at a predetermined radius from the center of the reference convex portion may be, for example, a region with a radius of 5 μm or more, a region with a radius of 8 μm or more, or a region with a radius of 10 μm or more.
By setting the area at a predetermined radius from the center of the reference convex portion to the above range, a wiring board on which functional chips can be arranged at a relatively narrow pitch can be obtained. Further, since the height of the connecting convex portion tends to vary, the effect of providing the stress buffer layer can be highly exhibited.

In the connection projection group, the pitch width between adjacent connection projections may be such that it is possible to have two or more connection projections including the reference projection in the above-mentioned predetermined radius area. It is not particularly limited, and is appropriately selected depending on the pitch width of the terminals of the functional chip to be mounted. The width of the pitch between adjacent connection convex portions may be larger than the radius mentioned above, may be the same, or may be smaller. The pitch width may be, for example, 10 μm or more, 20 μm or more, or 30 μm or more. Further, the pitch width may be, for example, 60 μm or less, 50 μm or less, or 40 μm or less. Note that the pitch width between adjacent connecting convex portions refers to the distance from the center of one connecting convex portion to the center of the other connecting convex portion.

The external shape of the connection protrusion group in plan view is appropriately selected depending on the arrangement of the terminals of the functional chip to be mounted. The external shape of the connection protrusion group in plan view is, for example, circular (FIG. 2(a)), elliptical (not shown), triangular (FIG. 2(b)), or rectangular (FIG. 2(c)). , n-gon shape (n is a real number of 5 or more, not shown), and the like. The outer shape of the connection protrusion group in plan view refers to the shape of the area in which the plurality of connection protrusions constituting the connection protrusion group are arranged in plan view.

In the connection protrusion group, the individual connection protrusions are arranged corresponding to the arrangement of the terminals of the functional chip to be mounted. In the connection protrusion group, the individual connection protrusions may be arranged, for example, in a predetermined pattern such as a line, or may be arranged randomly.

The number of connection protrusions constituting the connection protrusion group is at least two or more. The number of the connecting convex portions is appropriately adjusted according to the number of terminals of the functional chip to be mounted.

The size of the connection protrusion group is appropriately selected depending on the size of the functional chip to be mounted. An example of the size of the connection protrusion group is 40 μm or more and 20000 μm or less, but is not limited thereto. The size of the connection protrusion group refers to the longest distance among the planar external shapes of the connection protrusion group described above.

The distance (radius) from the center of the reference convex portion and the pitch width described above can be measured, for example, by observing the wiring board using a scanning electron microscope (SEM).

In the present disclosure, a stress buffer layer is disposed between at least one connection protrusion of the connection protrusion group and the glass substrate. In other words, the connection protrusions that make up the connection protrusion group include not only those on which the stress buffer layer is disposed on the surface facing the glass substrate, but also those on which no stress buffer layer is disposed. You can stay there. Further, when stress buffer layers are arranged on the glass substrate side surfaces of the plurality of connection projections, the thickness of the stress buffer layers arranged on each connection projection may be the same, It's okay to be different.

The wiring board of the present disclosure usually has height variations in the connection protrusions in the connection protrusion group. Specifically, in the connection projection group, there is variation in the height from the top of the connection projection to the reference plane when the wiring layer side surface of the glass substrate is used as the reference plane. In addition, in the following explanation, the "height from the top of the connection protrusion to the reference surface when the surface on the wiring layer side of the glass substrate is the reference plane" is referred to as the "height of the connection protrusion". May be explained.

In the present disclosure, when the surface of the wiring layer side of the glass substrate among the group of connection convex parts is used as a reference plane, the height from the top of one connection convex part on which the stress buffer layer is arranged to the reference plane is the height from the top of a connection convex part on which a stress buffer layer thinner than one connection convex part is arranged to the reference surface, or the top of a connection convex part without a stress buffer layer arranged on it. It is preferable that the height is higher than the height from to the reference plane.

The relationship between the heights of the above-mentioned connecting convex portions will be explained with reference to the drawings. FIG. 3 is a schematic cross-sectional view showing another example of the wiring board of the present disclosure. In the wiring board 10 shown in FIG. 3, a group of connection convex parts 4G includes a connection convex part 4j on which a stress buffer layer 5a is disposed, a connection convex part 4k on which a stress buffer layer is not disposed, and a stress buffer group 4G. The connecting convex portion 4l is arranged on the stress buffering layer 5b which is thinner than the layer 5a. In such a wiring board 10, it is preferable that the height T1 of the connection protrusion 4j is higher than the height T2 of the connection protrusion 4k or the height T3 of the connection protrusion 4l. During pushing when a functional chip is mounted on a wiring board, stress concentration tends to occur in a portion of a group of connection projections where a connection projection with a higher height is arranged. Therefore, the height of the connection protrusion on which the stress buffer layer is arranged is higher than the height of the connection protrusion on which the stress buffer layer is not arranged, so that stress caused by pushing during mounting can be appropriately alleviated. This is because cracking of the glass substrate can be suitably suppressed. Moreover, the stress buffering layer tends to be more effective in buffering stress as it becomes thicker. Therefore, the height of the connecting convex part on which the thicker stress buffering layer is placed can suitably relieve the stress caused by pushing during mounting, and suitably suppress cracking of the glass substrate. This is because it can be done. In the present disclosure, as shown in FIG. 3, the height T1 of the connection projection 4j is preferably higher than the height T2 of the connection projection 4k and the height T3 of the connection projection 4l. .

In addition, in the present disclosure, when the surface on the wiring layer side of the glass substrate is the reference plane among the group of connection protrusions, the connection protrusion has the highest height from the top of the connection protrusion to the reference plane. is preferably arranged at a position corresponding to the outermost terminal of the functional chip to be mounted.

The relationship between the heights of the connecting convex portions will be explained with reference to the drawings. For example, as shown in FIG. 1B, for a connection projection group 4G having connection projections 4a to 4i, as shown in FIG. Consider the case of implementing . It is assumed that the connection protrusions 4a to 4i are arranged at positions corresponding to the terminals 22a to 22i, respectively. For example, as shown in FIG. 5A, when the height of the connection protrusion 4e corresponding to the central terminal 22e of the functional chip among the connection protrusion group 4G is the highest height T4, As shown in FIG. 5(b), when mounting the functional chip 20, although the connection protrusions 4e and the terminals 22e can be brought into good contact, other connection protrusions (for example, connection protrusions) It may be difficult to bring the portions 4d, 4f) into contact with other terminals (for example, the terminals 22d, 22f). In this case, for example, by tilting the functional chip, it is possible to bring the other connecting protrusions into contact with the other terminals. It may be difficult to tilt the functional chip in a specific direction starting from the contact point. Furthermore, there is a concern that the stability of the functional chip may be low, such as wobbling during and after mounting.

On the other hand, as shown in FIG. 6(a), the height of the connection protrusion 4d corresponding to the outermost terminal 22d of the functional chip among the connection protrusion group 4G is the highest height T4. In some cases, as shown in FIG. 6(b), when mounting the functional chip 20, the connection protrusion 4d and the terminal 22d can be brought into good contact; For example, by tilting the functional chip starting from the point of contact with the terminal 22f, such that the end of the functional chip on the terminal 22f side is lower than the end of the functional chip on the terminal 22d side. It becomes possible to bring the connecting convex portions (for example, the connecting convex portions 4d and 4f) into contact with other terminals (for example, the terminals 22d and 22f). Furthermore, since the inclination of the functional chip can be adjusted in a fixed direction, the stability of the functional chip during and after mounting can be improved.

In the present disclosure, it is more preferable that the connection protrusion disposed at a position corresponding to the outermost terminal of the functional chip to be mounted is a connection protrusion on which a stress buffer layer is disposed. This is because stress concentration in the portion where the connecting convex portion is arranged can be suppressed.

Note that the "height from the top of the connection convex part to the reference plane when the surface on the wiring layer side of the glass substrate is the reference plane", that is, the height of the connection convex part, can be measured using, for example, a scanning electron microscope ( It can be measured by observing a vertical cross section using SEM).

Examples of the method for adjusting the height of the connection protrusion include a method of adjusting the thickness of a layer located between the glass substrate and the connection protrusion, such as a stress buffer layer, a wiring layer, an insulating layer, etc. .

The height of the connecting convex portion is appropriately selected depending on the form of the wiring board and is not particularly limited, but for example, it is preferably 5 μm or more, more preferably 8 μm or more, and preferably 10 μm or more. preferable. Further, the height of the connecting convex portion is preferably, for example, 200 μm or less, preferably 180 μm or less, and particularly preferably 100 μm or less.

2. Connection Protrusion The connection protrusion is a member disposed in the opening of the insulating layer and electrically connected to the wiring layer. The connecting convex portion is a member used for electrically connecting to the terminal portion of the functional chip.

The thickness of the connection protrusion is usually thicker than the thickness of the insulating layer from the wiring layer side surface of the connection protrusion. The ratio of the thickness of the connection protrusion to the thickness of the above-mentioned insulating layer is, for example, 1.01 or more, may be 1.5 or more, or may be 2 or more. Further, the ratio may be, for example, 10 or less, 8 or less, or 5 or less. This is because if the thickness of the connection protrusion is too thin, it may be difficult to electrically connect with the functional chip, and if the connection protrusion is too thick, the connection protrusion may This is because it may be difficult to form.

Note that the "thickness of the connection protrusion" refers to the distance in the vertical direction from the wiring layer side surface of the connection protrusion to the top, and for example, the distance represented by t1 in FIG. 1(c). say. In addition, "thickness of the insulating layer from the wiring layer side surface of the connection protrusion" is the vertical direction from the wiring layer side surface of the connection protrusion to the surface of the insulating layer opposite to the wiring layer side. For example, it refers to the distance represented by t2 in FIG. 1(c). The "thickness of the connection protrusion" and the "thickness of the insulating layer from the surface of the connection protrusion on the wiring layer side" can be determined by, for example, observing a vertical cross section using a scanning electron microscope (SEM). can be measured.

The thickness of the connecting convex portion is appropriately selected depending on the use, size, etc. of the wiring board, and is not particularly limited, but is preferably, for example, 2 μm or more and 15 μm or less. Although it depends on the number of connection protrusions arranged on the wiring board, if there are at least 10 connection protrusions, the average thickness of the 10 connection protrusions falls within the above range. It is preferable that it be within.

The external shape of the connecting convex portion in plan view is appropriately selected depending on the shape of the opening of the insulating layer. Examples of the external shape of the connecting convex portion in plan view include a circular shape, an elliptical shape, and a rectangular shape. Further, the size of the connecting convex portion may be, for example, 10 μm or more and 150 μm or less, or 20 μm or more and 100 μm or less. The size of the connecting convex portion refers to the longest distance among the external shapes of the above-mentioned connecting convex portions in plan view. The size of the connection protrusion can be measured, for example, by observing the wiring board using a scanning electron microscope (SEM).

The material of the connecting convex part is not particularly limited as long as it is a conductive material, and any conductive material used for general wiring can be used. selected.

Specific examples of the material of the connecting convex portion include metals such as copper, gold, silver, platinum, palladium, rhodium, tin, aluminum, nickel, and chromium, or alloys containing these metals. . Furthermore, solder can also be used as the material for the connecting convex portion. The connecting convex portion may be a single layer, or may be a multilayer in which a plurality of layers are laminated.

Further, the connection convex portion may be, for example, a plating layer formed by a plating method, or a vapor deposition layer formed by a vapor deposition method. Further, the connection convex portion may be a solder bump formed using solder, for example. In the present disclosure, it is particularly preferable that the connecting convex portion is a plating layer. This is because connection convex portions can be formed satisfactorily on narrow-pitch wiring boards. When the connecting convex portion is a plating layer, it is preferable to have a laminated structure in which a nickel plating layer and a gold plating layer are laminated in this order on the wiring layer, for example. This is because deterioration of the nickel plating layer can be suppressed. Further, for example, when the wiring layer contains copper, deterioration of the wiring layer can be suppressed by using a nickel plating layer.

The method for forming the connection protrusion is not particularly limited, and examples include PVD methods such as vapor deposition and sputtering, CVD, and plating methods.

3. Stress Buffer Layer The stress buffer layer is a member disposed between at least one connection convex part of the connection convex part group and the glass substrate. The stress buffering layer has a function of buffering stress generated in the wiring board due to pushing during mounting of the functional chip, that is, a stress buffering function.

The material of the stress buffer layer is not particularly limited as long as it can provide a stress buffer function, and may be an organic material or an inorganic material, but an organic material is preferable. This is because the stress buffering layer can be made into a soft layer and a stress buffering function can be satisfactorily imparted.

The organic material used for the stress buffer layer is not particularly limited, and examples thereof include polyimide resin, acrylic resin, epoxy resin, polyethylene terephthalate resin, and novolak resin. By including these materials, a better buffering effect can be obtained.

The thickness of the stress buffer layer is not particularly limited as long as it can have the desired stress buffer function. It is preferable that the ratio of the thickness of the stress buffer layer to the height of the highest connection protrusion on which the stress buffer layer is disposed is a predetermined ratio. Specifically, the ratio of the thickness of the stress buffer layer to the height of the connecting convex portion is preferably 10% or more, more preferably 15% or more, and 20% or more. is even more preferable. This is because if the above ratio is too small, it may be difficult to fully exhibit the stress buffering function. Further, from the viewpoint of reducing the thickness and weight of the wiring board, the above ratio is, for example, 80% or less, may be 70% or less, or may be 60% or less.

"Thickness of the stress buffer layer" refers to the distance in the vertical direction from one surface to the other surface of the stress buffer layer. The "thickness of the stress buffer layer" can be measured, for example, by observing a vertical cross section using a scanning electron microscope (SEM). Further, the above ratio can be expressed as t3/T1 in FIG. 3, for example.

The specific thickness of the stress buffer layer can be appropriately selected depending on the size of the wiring board, etc., and is not particularly limited. The thickness of the stress buffer layer may be, for example, 1 μm or more, 3 μm or more, or 5 μm or more. Moreover, the thickness of the stress buffer layer may be, for example, 20 μm or less, 15 μm or less, or 10 μm or less.
Furthermore, the stress buffer layer may be a layered structure of a plurality of layers. The number of laminated layers is generally about 2 to 4 layers.
This is because when the thickness of the stress buffer layer is within the above range, it is possible to suitably suppress stress concentration on the wiring board during mounting of the functional chip. In addition, when the stress buffer layer has a laminated structure in which a plurality of layers are laminated, it is preferable that the total of each layer becomes a value within the above-mentioned numerical range.

The maximum thickness of the stress buffer layer refers to the thickness at the thickest part of the stress buffer layer, and is represented by t3 among the distances represented by t3 and t4 in FIG. 1(c), for example. Refers to distance.

The stress buffer layer may also serve as an insulating layer. For example, when the wiring layers are arranged on both sides of the stress buffer layer, the stress buffer layer may also serve as an insulating layer for insulating the wiring layers from each other. As a specific example, as shown in FIGS. 1(c), 5(a), (b), and 6(a), (b), the wiring layer 2 is formed on the surface of the stress buffer layer 5 on the glass substrate 1 side. When the stress buffer layer 5 has the first wiring layer 2a disposed on the side and the second interconnect layer 2b disposed on the surface side of the connection convex portion of the stress buffer layer 5, the stress buffer layer 5 It may also serve as an insulating layer for insulating the wiring layer 2a and the second wiring layer 2b.

Further, when the stress buffer layer 5 also serves as an insulating layer, the stress buffer layer 5 may have an opening, as shown in FIG. 1(c). In this case, it is preferable that the opening of the stress buffering layer 5 is arranged at a position overlapping the opening of the insulating layer 3 in plan view. The shape, size, etc. of the opening provided in the stress buffer layer can be appropriately selected depending on the layer structure of the wiring board.

In addition, there may be at least one stress buffer layer between the connection convex portion and the glass substrate, and there may be a plurality of stress buffer layers.

4. Wiring Layer The wiring layer is a member placed on one side of the glass substrate. Further, the wiring layer is a member that is electrically connected to the connecting convex portion.

The wiring layer only needs to be placed on one side of the glass substrate, and may be placed directly on one side of the glass substrate, or may be placed with an insulating layer interposed therebetween. Further, in the present disclosure, a plurality of wiring layers may be arranged with an insulating layer or a stress buffer layer interposed therebetween.

The wiring layer usually has at least a linear wiring portion. The line width of the linear wiring portion can be appropriately selected depending on the use of the wiring board, and is not particularly limited. Further, the wiring layer may have a pad portion for connection to the connecting convex portion. The pad portion is a portion having a wider pattern than the linear wiring portion. The shape of the pad portion in plan view can be, for example, circular, elliptical, or rectangular. The thickness of the wiring layer, the line width of the linear wiring part, and the size of the pad part are based on the thickness of the wiring layer, the line width of the linear wiring part, and the size of the pad part used in general wiring boards. The explanation here will be omitted since it can be done in the same way as the above.

The material of the wiring layer is not particularly limited as long as it is a conductive material, and may be the same as the conductive material used for the wiring layer of a general wiring board. Examples of conductive materials used in the wiring layer include titanium (Ti), molybdenum (Mo), tungsten (W), tantalum (Ta), nickel (Ni), chromium (Cr), aluminum (Al), and copper ( Cu) These metals or compounds, or alloys thereof, and conductive oxides such as indium tin oxide (ITO) and indium zinc oxide (IZO) can be used.

As the method for forming the wiring layer, a general method for forming wiring can be used, and is appropriately selected depending on the form of the wiring layer and the like. Examples of methods for forming the wiring layer include PVD methods such as vapor deposition and sputtering methods, CVD methods, and plating methods. Further, the plating method is preferably an electrolytic plating method.

5. Insulating Layer The insulating layer is a member disposed on the wiring layer side of the glass substrate and having an opening. The insulating layer is usually arranged to cover the wiring layer.

The insulating layer usually has an opening at a position that overlaps a part of the wiring layer in a plan view. It is preferable that the opening of the insulating layer is provided so as to overlap the pad of the wiring layer in plan view. The size of the opening in the insulating layer is appropriately selected depending on the form of the wiring board and is not particularly limited. Note that "the size of the opening in the insulating layer" refers to the longest distance in the plan view of the opening in the insulating layer.

The material used for the insulating layer is not particularly limited as long as it has insulating properties, and may be the same as the material used for the insulating layer of general wiring boards. Further, as the material used for the insulating layer, the materials described in the above-mentioned section "3. Stress buffer layer" can also be used.

The thickness of the insulating layer can be appropriately selected depending on the form of the wiring layer. Further, in the present disclosure, it is sufficient that the insulating layer has at least one layer on at least one surface of the glass substrate, and may have multiple layers.

6. Glass Substrate The glass substrate is a member that supports the wiring layer, the insulating layer, the stress buffer layer, and the connection protrusion. Glass substrates are preferred because they have high flatness and high heat resistance. Examples of the glass used for the glass substrate include soda lime glass, alkali-free glass, and quartz glass.

The thickness of the glass substrate is not particularly limited as long as it can support each layer described above, and can be appropriately selected depending on the use of the wiring board. The thickness of the glass substrate is, for example, preferably 10 μm or more and 1000 μm or less, more preferably 100 μm or more and 700 μm or less, and particularly preferably 300 μm or more and 500 μm or less.

7. Conductive Layer The wiring board of the present disclosure may further include a conductive layer for connecting a plurality of wiring layers. The conductive layer is disposed within the opening of the insulating layer or the stress buffering layer, and functions as a via layer. The material used for the conductive layer can be the same as the conductive material described in the section of the wiring layer above. Further, the conductive layer is not limited to this, but for example, a conductive paste or the like can also be used. The method for forming the conductive layer can be, for example, the same as the method for forming the wiring layer described above. Further, the wiring layer can also be formed simultaneously with a plating method.

8. Wiring Board The wiring board of the present disclosure is not particularly limited as long as it has the above-mentioned layers, and other configurations can be added as appropriate.

The wiring board of the present disclosure is usually used together with a functional chip, and constitutes an element described in the section "B. Element" below.

B. Element The element of the present disclosure includes the above-described wiring board and a functional chip electrically connected to the connection protrusion of the connection protrusion group.

The device of the present disclosure will be explained using figures. FIG. 7(a) is a schematic plan view showing an example of the element of the present disclosure, and FIG. 7(b) is an enlarged view showing a part of the cross section taken along line BB in FIG. 7(a). The element 100 shown in FIG. 7 includes a wiring board 10 and a functional chip 2 electrically connected to the connection protrusion 4 of the connection protrusion group 4G. Since the wiring board 10 has been described with reference to FIGS. 1(a) to 1(c) and the functional chip 20 with reference to FIG. 4, detailed description thereof will be omitted.

According to the present disclosure, by having the above-mentioned wiring board, it is possible to provide an element in which a functional chip is satisfactorily mounted.

Hereinafter, the elements of the present disclosure will be explained for each configuration.

1. Wiring Board The wiring board in the present disclosure is the same as that described in the section "A. Wiring Board" above, so the description here will be omitted.

2. Functional Chip The functional chip in the present disclosure is a member that is electrically connected to the connection protrusion of the connection protrusion group. A functional chip includes, for example, a chip body and a terminal. Specific functional chips include dynamic random access memory (DRAM), NAND flash memory, SAW devices, power amplifier ICs, display driver ICs, image sensors, acceleration sensors, angle sensors, etc. can be mentioned.

3. Element The element of the present disclosure is not particularly limited as long as it has the wiring board and functional chip described above, and other necessary configurations can be selected and added as appropriate.

The device of the present disclosure can be used in, for example , smartphones, displays, cars, and the like.

Note that the present disclosure is not limited to the above embodiments. The above-mentioned embodiments are illustrative, and any embodiment that has substantially the same configuration as the technical idea stated in the claims of the present disclosure and provides similar effects is the present invention. within the technical scope of the disclosure.

DESCRIPTION OF SYMBOLS 1... Glass substrate 2... Wiring layer 3... Glass substrate 4... Connection convex part 5... Stress buffer layer 10... Wiring board 20... Functional chip 100... Element

Claims (1)

a glass substrate, a wiring layer disposed on one surface of the glass substrate, an insulating layer disposed on the wiring layer side of the glass substrate and having an opening, and disposed in the opening of the insulating layer. A wiring board having a connecting convex portion electrically connected to the wiring layer,
When one of the connection protrusions is taken as a reference protrusion, a connection protrusion group having two or more of the connection protrusions including the reference protrusion in an area with a radius of 100 μm from the center of the reference protrusion. A wiring board, comprising: a stress buffering layer disposed between at least one of the connection protrusions in the group of connection protrusions and the glass substrate.

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