JP2023126145A - Motor driver circuit, positioning device using the same, hard disk device, motor driving method - Google Patents

Abstract

To improve current detection accuracy.SOLUTION: A mask generation circuit 280 is asserted by transition start of a first output voltage VOUTA of a first output terminal AOUT as trigger, and generates a mask signal MSKB negated after completion of the transition. An error detection amplifier 230 generates an analog error signal VERR based on error between a current feedback signal VFB according to voltage drop across a current sense resistor Rs and a reference signal VDAC. An A/D converter 290 converts the analog error signal VERR to a digital error signal DERR. A digital compensator 224 loads the digital error signal DERR in a period during which the mask signal MSKB is negated, and generates a voltage command value DCTRL according to the digital error signal DERR. A pulse width modulator 240 generates a first pulse PWMA and a second pulse PWMB having complementary duty cycles according to the voltage command value DCTRL.SELECTED DRAWING: Figure 18

Description

The present disclosure relates to a motor driver circuit.

Linear motors (linear actuators) are used in various electronic devices and industrial machines to position objects. A voice coil motor is one type of linear motor, and can control the position of a movable element according to a supplied drive current. The voice coil motor drive circuit feedback-controls the current flowing through the voice coil motor so that it approaches a target current that defines a target position.

Japanese Patent Application Publication No. 2008-43171

There are two types of driver circuits for constant current driven motors: analog type and digital type. Analog driver circuits are difficult to design because they require phase compensation for the error amplifier. On the other hand, in the digital system, phase compensation is easy by employing a PI controller or a PID controller.

Digital methods require converting the current flowing through the motor into a digital signal. FIG. 1 is a diagram illustrating current detection.

A sense resistor Rs and a current sense amplifier AMP1 are provided for current detection. The sense resistor Rs is connected in series with the motor M between the A-phase output terminal (AOUT) and the B-phase output terminal (BOUT) of the motor driver circuit. A voltage drop Vs proportional to the drive current _IDRV occurs in the sense resistor Rs. The current sense amplifier AMP1 amplifies the voltage drop V _CS of the sense resistor Rs and generates a current feedback signal V _FB .

As a result of studying current detection using the sense resistor Rs, the inventor has come to recognize the following problems.

In a system that performs PWM driving, the voltage at the AOUT terminal and the voltage at the BOUT terminal switch (transition) independently. The in-phase components of the two input voltages Va and Vb of the current sense amplifier AMP1 are relatively less influenced by transitions at the BOUT terminal, and more influenced by transitions at the AOUT terminal.

In other words, the AC CMRR (Common Mode Rejection Ratio) of the current sense amplifier AMP1 is different during a voltage transition at the AOUT terminal and during a voltage transition at the BOUT terminal. An error will occur.

The present disclosure has been made in view of the above problems, and one exemplary objective of a certain aspect thereof is to provide a driver circuit with improved current detection accuracy.

Certain aspects of the present disclosure relate to motor driver circuits. The motor driver circuit includes a first output terminal to be connected to a first end of a motor to be driven via a current sense resistor, a second output terminal to be connected to a second end of the motor, and a first output terminal. a mask generation circuit that generates a mask signal that is asserted using the start of transition of the first output voltage as a trigger and is negated after the transition is completed; and a mask generation circuit that generates a mask signal that is triggered by the start of transition of the first output voltage of It has an error detector that generates an analog error signal, a feedback controller that generates a voltage command value based on the analog error signal generated during the period when the mask signal is negated, and a complementary duty cycle according to the voltage command value. a pulse width modulator that generates a first pulse and a second pulse; a first driver that generates a first output voltage at a first output terminal according to the first pulse; and a first driver that generates a second output voltage that corresponds to the second pulse. a second driver that generates a signal at a second output terminal.

Another aspect of the disclosure is also a motor driver circuit. This motor driver circuit includes a first output terminal to be connected to a first end of a motor to be driven via a current sense resistor, a second output terminal to be connected to a second end of the motor, and a first output terminal to be connected to a second end of the motor to be driven. a mask generation circuit that generates a mask signal that is asserted using the start of transition of the first output voltage of the terminal as a trigger and is negated after the transition is completed; and a current detection circuit that generates a current feedback signal based on the voltage drop of the current sense resistor. , a feedback controller that generates a voltage command value such that the current feedback signal approaches a reference signal, and a pulse width modulator that generates first and second pulses having complementary duty cycles according to the voltage command value. The device includes a first driver that generates a first output voltage corresponding to the first pulse at a first output terminal, and a second driver that generates a second output voltage corresponding to the second pulse at a second output terminal. The feedback controller is configured, at least in part, of a digital circuit, and the digital circuit is configured to convert an analog signal into a digital signal and capture the digital signal while the mask signal is negated.

Yet another aspect of the present disclosure is a method of driving a motor. The driving method includes connecting a current sense resistor in series with the motor at the first end of the motor, generating a current feedback signal based on the voltage drop across the current sense resistor, and generating a current feedback signal applied to the current sense resistor. a step of asserting a mask signal using the start of transition of the first output voltage as a trigger; a step of negating the mask signal using the completion of the transition of the first output voltage as a trigger; a step of negating the mask signal when the transition is completed; A step of generating an analog error signal according to the error between the feedback signal and the reference signal, a step of converting the analog error signal into a digital error signal and importing it during the period when the mask signal is negated, and a step of generating a voltage command according to the digital error signal. applying a first output voltage responsive to a first pulse having a duty cycle responsive to a voltage command value to a first end of the motor via a current sensing resistor; applying a second output voltage responsive to the complementary second pulse to the second end of the motor.

Another aspect of the present disclosure is also a method of driving a motor. The driving method includes the steps of connecting a current sense resistor in series with the first end of the motor, generating a current feedback signal based on the voltage drop of the current sense resistor, and generating a first output applied to the current sense resistor. A step of asserting a mask signal using the start of a voltage transition as a trigger, a step of negating the mask signal using the completion of a transition of the first output voltage as a trigger, and a step of generating a voltage command value so that the current feedback signal approaches a reference signal. generating a first pulse and a second pulse having complementary duty cycles in response to a voltage command value; and applying a second output voltage corresponding to the second pulse to the second end of the motor. The step of generating the voltage command value includes the step of converting the analog signal into a digital signal and capturing the digital signal while the mask signal is negated.

Note that arbitrary combinations of the above components, and mutual substitution of components and expressions among methods, devices, systems, etc., are also effective as aspects of the present invention or the present disclosure. Furthermore, the description in this section (Means for Solving the Problems) does not describe all essential features of the present invention, and therefore, subcombinations of the described features may also constitute the present invention. .

According to an aspect of the present disclosure, current can be detected at appropriate timing.

FIG. 1 is a diagram illustrating current detection. FIG. 2 is a block diagram of a positioning device including a motor driver circuit according to the first embodiment. FIG. 3 is a diagram showing input/output characteristics of the motor driver circuit of FIG. 2. FIG. 4 is an operational waveform diagram of the motor driver circuit. FIG. 5 is a circuit diagram showing a part of the motor driver circuit according to the first embodiment. FIG. 6 is an operational waveform diagram of the motor driver circuit of FIG. 5. FIG. 7 is a circuit diagram showing a part of the motor driver circuit according to the second embodiment. FIG. 8 is an operational waveform diagram of the motor driver circuit of FIG. 7. FIG. 9 is a circuit diagram showing a part of the motor driver circuit according to the third embodiment. FIG. 10 is an operational waveform diagram of the motor driver circuit of FIG. 9. FIG. 11 is a circuit diagram showing a part of the motor driver circuit according to the fourth embodiment. FIG. 12 is a circuit diagram showing a configuration example of the A/D converter shown in FIG. 11. FIG. 13 is an operational waveform diagram of the motor driver circuit of FIG. 11. FIG. 14 is a diagram showing spectra obtained in the motor driver circuit of FIG. 2 and the motor driver circuit of FIG. 11. FIG. 15 is a circuit diagram showing a configuration example of a current sense amplifier and an error detection amplifier. FIG. 16 is a circuit diagram of a motor driver circuit according to the fifth embodiment. FIG. 17 is a circuit diagram of a motor driver circuit according to another embodiment. FIG. 18 is a block diagram of a positioning device including a motor driver circuit according to the second embodiment. FIG. 19 is a circuit diagram showing a configuration example of a sample and hold circuit. FIG. 20 is a diagram showing a hard disk device including a motor driver circuit.

(Summary of embodiment)
1 provides an overview of some exemplary embodiments of the present disclosure. This Summary is intended to provide a simplified description of some concepts of one or more embodiments in order to provide a basic understanding of the embodiments and as a prelude to the more detailed description that is presented later. It does not limit the size. This summary is not an exhaustive overview of all possible embodiments and is not intended to identify key elements of all embodiments or to delineate the scope of any or all aspects. For convenience, "one embodiment" may be used to refer to one embodiment (example or modification) or multiple embodiments (examples or modifications) disclosed in this specification.

A motor driver circuit according to an embodiment includes a first output terminal to be connected to a first end of a motor to be driven via a current sense resistor, and a second output terminal to be connected to a second end of the motor. , a mask generation circuit that generates a mask signal that is asserted using the start of transition of the first output voltage of the first output terminal as a trigger and is negated after the transition is completed; and a current feedback signal and a reference signal based on the voltage drop of the current sense resistor. an error detector that generates an analog error signal based on the error between the mask signal and the feedback controller; a pulse width modulator that generates a first pulse and a second pulse having a duty cycle; a first driver that generates a first output voltage at a first output terminal responsive to the first pulse; and a first driver that generates a first output voltage responsive to the first pulse; a second driver that generates a second output voltage at a second output terminal.

The inventors have recognized that current detection accuracy decreases during voltage transitions at the output terminal connected to the current sense resistor. Therefore, current detection accuracy can be improved by masking current detection during transition.

In one embodiment, the feedback controller includes an A/D converter that converts an analog error signal into a digital error signal, and a feedback controller that captures the digital error signal during a period in which the mask signal is negated and generates a voltage command value according to the digital error signal. A compensator may also be included.

In one embodiment, the feedback controller includes a sample and hold circuit that holds the analog error signal, an A/D converter that converts the output of the sample and hold circuit to a digital error signal, and an A/D converter that converts the output of the sample and hold circuit to a digital error signal during the period when the mask signal is asserted. A compensator that generates a corresponding voltage command value may also be included.

In one embodiment, the mask generation circuit may trigger the transition of the first pulse to assert the mask signal. In one embodiment, the mask generation circuit may assert the mask signal when the first output voltage crosses a predetermined threshold voltage.

In one embodiment, the first driver may include a high-side transistor and a low-side transistor. Regarding the mask signal corresponding to the rising edge of the first output voltage, the mask generation circuit negates the mask signal when the gate-source voltage of the high-side transistor exceeds the first threshold voltage. good.

In one embodiment, the first driver may include a high-side transistor and a low-side transistor. With respect to the mask signal corresponding to the rising edge of the first output voltage, the mask generation circuit generates a mask signal corresponding to the rising edge of the first output voltage, after the gate-source voltage of the high-side transistor exceeds the first threshold voltage. The mask signal may be negated later.

In one embodiment, for a mask period corresponding to a fall edge of the first output voltage, the mask generation circuit negates the mask signal when the first output voltage becomes less than a second threshold voltage after assertion of the mask signal. It's okay.

In one embodiment, with respect to a mask period corresponding to a falling edge of the first output voltage, the mask generation circuit is configured to perform a predetermined second period of time after the first output voltage becomes lower than a second threshold voltage after assertion of the mask signal. The mask signal may be negated after .

In one embodiment, with respect to a mask signal corresponding to a rising edge of the first output voltage, the mask generation circuit negates the mask signal when the first output voltage exceeds a third threshold voltage after assertion of the mask signal. It's okay.

In one embodiment, with respect to a mask signal corresponding to a rising edge of the first output voltage, the mask generation circuit is configured to perform a predetermined first period of time after the first output voltage exceeds a third threshold voltage after assertion of the mask signal. The mask signal may be negated after .

In one embodiment, the predetermined first time period may be externally settable. In one embodiment, the predetermined second time period may be externally settable.

In one embodiment, the A/D converter may restart the sample and hold timing signal using negation of the mask signal as a trigger. The present inventor recognized that when the timing signal, which is the operating clock of the A/D converter, is asynchronous with the mask signal, the output of the A/D converter includes a frequency lower than the PWM frequency. According to this configuration, by synchronizing the timing signal with the mask signal, frequencies lower than the PWM frequency included in the output of the A/D converter can be reduced or removed.

A motor driver circuit according to an embodiment includes a first output terminal to be connected to a first end of a motor to be driven via a current sense resistor, and a second output terminal to be connected to a second end of the motor. , a mask generation circuit that generates a mask signal that is asserted using the start of transition of the first output voltage of the first output terminal as a trigger and is negated after the transition is completed, and generates a current feedback signal based on the voltage drop of the current sense resistor. a current detection circuit; a feedback controller that generates a voltage command value such that the current feedback signal approaches a reference signal; and a pulse width that generates first and second pulses having complementary duty cycles according to the voltage command value. a modulator; a first driver that generates a first output voltage at a first output terminal according to the first pulse; and a second driver that generates a second output voltage at a second output terminal according to the second pulse; Equipped with The feedback controller is configured, at least in part, of a digital circuit, and the digital circuit is configured to convert an analog signal into a digital signal and capture the digital signal while the mask signal is negated.

In one embodiment, the feedback controller may convert an error signal based on the error between the current feedback signal and the reference signal into a digital signal.

In one embodiment, the feedback controller may convert the current feedback signal to a digital signal.

In one embodiment, the motor may be a linear motor. In one embodiment, the linear motor may be a voice coil motor.

In one embodiment, the motor driver circuit may be monolithically integrated on one semiconductor substrate. "More integration" includes cases where all of the circuit components are formed on a semiconductor substrate, and cases where the main components of the circuit are integrated, and some resistors are used to adjust the circuit constants. or a capacitor may be provided outside the semiconductor substrate. By integrating circuits on one chip, the circuit area can be reduced and the characteristics of circuit elements can be kept uniform.

A positioning device according to one embodiment includes a linear motor and any of the above-mentioned motor driver circuits that drive the linear motor.

A hard disk device according to one embodiment includes the above-described positioning device.

(Embodiment)
Hereinafter, preferred embodiments will be described with reference to the drawings. Identical or equivalent components, members, and processes shown in each drawing are designated by the same reference numerals, and redundant explanations will be omitted as appropriate. Furthermore, the embodiments are illustrative rather than limiting the disclosure and invention, and all features and combinations thereof described in the embodiments are not necessarily essential to the disclosure and invention.

In this specification, "a state in which member A is connected to member B" refers to a case where member A and member B are physically directly connected, or when member A and member B are electrically connected. This also includes cases in which they are indirectly connected through other members that do not substantially affect the connection state or impair the functions and effects achieved by their combination.

Similarly, "a state in which member C is provided between member A and member B" refers to the case where member A and member C or member B and member C are directly connected, This also includes cases in which they are indirectly connected via other members that do not substantially affect the connection state or impair the functions and effects achieved by their combination.

Furthermore, the vertical and horizontal axes of the waveform diagrams and time charts shown in this specification have been enlarged or reduced as appropriate for ease of understanding, and each waveform shown has also been simplified for ease of understanding. has been made into

(Embodiment 1)
FIG. 2 is a block diagram of the positioning device 100 including the motor driver circuit 200 according to the first embodiment. The positioning device 100 includes a linear motor 102, a host controller 104, a motor driver circuit 200, and a current sense resistor (hereinafter also simply referred to as a sense resistor) Rs.

The upper controller 104 integrally controls the positioning device 100. The host controller 104 generates position control data POS indicating the target position of the linear motor 102 and transmits the position control data POS to the motor driver circuit 200. The upper controller 104 is composed of, for example, a microcontroller, an FPGA (Field Programmable Gate Array), and an ASIC (Application Specific Integrated Circuit).

The motor driver circuit 200 receives the position control data POS and supplies the linear motor 102 with a drive current _IDRV of an amount corresponding to the position control data POS. The linear motor 102 is, for example, a voice coil motor, and its movable element is displaced by an amount corresponding to a drive current _IDRV flowing through the linear motor 102.

Next, the configuration of the motor driver circuit 200 will be explained. The motor driver circuit 200 includes a current command generation section 210, a feedback controller 220, a pulse width modulator 240, a current detection circuit 250, a mask generation circuit 280, a first driver 260, and a second driver 270, and is integrated on one semiconductor substrate. It is a functional IC (Integrated Circuit).

The motor driver circuit 200 includes a first output terminal (A phase output) AOUT, a second output terminal (B phase output) BOUT, and a current detection terminal ISNS. One end of the linear motor 102 is connected to the AOUT terminal via a sense resistor Rs. The other end of the linear motor 102 is connected to the BOUT terminal. The ISNS terminal is connected to one end of the linear motor 102.

The current command generation unit 210 generates an analog command signal V _DAC indicating a target value of the drive current _IDRV to be supplied to the linear motor 102 . For example, current command generation section 210 includes an interface circuit 212, a logic circuit 214, and a D/A converter 216. The interface circuit 212 is connected to the host controller 104 and receives various control data including position control data POS. The interface circuit 212 may be, for example, an I ² C (Inter IC) interface or an SPI (Serial Peripheral Interface). For example, the control data from the interface circuit 212 includes a code indicating the target position of the mover of the linear motor 102. Logic circuit 214 outputs a control code based on the received code to D/A converter 216. The control code may be the same as the code received from the host controller 104, or may be another code obtained by calculating the received code. D/A converter 216 converts the control code generated by logic circuit 214 into an analog command signal V _DAC .

Note that the configuration of the current command generation section 210 is not limited to this, and may be configured to directly receive the analog command signal V _DAC from the outside.

The current detection circuit 250 is connected to the AOUT terminal and the ISNS terminal, and generates a current feedback signal V _FB indicating the drive current _IDRV flowing through the linear motor 102 based on the voltage drop across the sense resistor Rs. For example, the current feedback signal V _FB is expressed by the following equation (1). k, V _CMREF are arbitrary constants.
V _FB =k×I _DRV +V _CMREF …(1)

Feedback controller 220 is a servo controller, and generates voltage command value V _CTRL by feedback so that current feedback signal V _FB approaches analog command signal V _DAC , which is a reference signal.

Feedback controller 220 includes an error detection amplifier 230, an A/D converter 290, a digital compensator 224, and a D/A converter 226. The error detection amplifier 230 is an error detector that receives the current feedback signal V _FB and the analog command signal V _DAC and generates an analog error signal V _ERR indicating the error between the drive current _IDRV and its target amount I _REF .
V _ERR = (I _REF - I _DRV ) x g
g is a finite gain.

The A/D converter 290 converts the analog error signal V _ERR generated by the error detection amplifier 230 into a digital error signal D _ERR . The analog error signal V _ERR is a signal indicating the drive current _IDRV , and specifically, a signal indicating the error between the drive current _IDRV and its target amount.

The digital compensator 224 generates _{a digital control amount D CTRL based} on the digital error signal DERR output from the A/D converter 290. The digital compensator 224 includes a PI (proportional integral) compensator and a PID (proportional integral differential) compensator. The PI compensator multiplies the digital error signal _DERR by the proportional gain _KP , multiplies the integral value of the digital error signal _DERR by the integral gain _KI , and adds them to generate the digital control amount _DCTRL. .

The PID compensator multiplies the digital error signal _DERR by a proportional gain _KP , multiplies the integral value of the digital error signal _DERR by an integral gain KI, and _multiplies the differential value of the digital error signal _DERR by a differential gain _KD . The digital control amount D _CTRL is generated by multiplying and adding them. A PI compensator or a PID compensator is also called a PI controller or a PID controller. The PI compensator and PID compensator may be selected depending on the characteristics of the controlled object.

The D/A converter 226 converts the digital control amount D _CTRL into an analog control signal V _CTRL . The analog control signal V _CTRL is a command value of the voltage to be applied between both ends of the linear motor 102, and is also referred to as a voltage command value.

The pulse width modulator 240 generates a first pulse (A-phase PWM pulse) PWMA and a second pulse (B-phase PWM pulse) PWMB having a duty cycle according to the voltage command value V _CTRL . The duty cycle of the PWMA signal may have a positive correlation to the voltage command value V _CTRL , and the duty cycle of the PWMB signal may have a negative correlation to the voltage command value V _CTRL .

The configuration of pulse width modulator 240 is not particularly limited, and can be configured using known techniques. For example, the pulse width modulator 240 may generate a PWMA signal and a PWMB signal by generating a triangular or sawtooth periodic signal and comparing the voltage command value V _CTRL with the periodic signals TRIA and TRIB. As the periodic signals TRIA and TRIB, triangular waves with opposite phases can be used. Hereinafter, the TRIA signal and the TRIB signal will also be referred to as triangular wave signals.

The first driver 260 generates a pulsed drive voltage V _OUTA according to the PWMA signal at the AOUT terminal, and supplies it to one end of the linear motor 102 via the sense resistor Rs. The second driver 270 generates a pulsed drive voltage V _OUTB in accordance with the PWMB signal at the BOUT terminal, and supplies it to the other end of the linear motor 102 .

The mask generation circuit 280 generates a mask signal MSKB based on the state of the AOUT terminal, that is, the first output voltage V _OUTA , and supplies it to the A/D converter 290 of the feedback controller 220. Specifically, the mask generation circuit 280 asserts the mask signal MSKB using the start of the transition of the output voltage V _OUTA as a trigger, and negates the mask signal MSKB after the transition is completed. In this embodiment, mask signal MSKB is asserted low and negated high.

The feedback controller 220 generates the voltage command value V _CTRL based on the analog error signal V _ERR generated during the period when the mask signal MSKB is negated, that is, during the non-transition period of the output voltage V _OUTA . In other words, the analog error signal V _ERR is not used for feedback control during the period when the mask signal MSKB is asserted, that is, during the transition of the output voltage V _OUTA .

The A/D converter 290 converts the analog error signal V _ERR into a digital error signal D _ERR in accordance with a sample and hold timing signal S/H (not shown in FIG. 2), which is an internal signal thereof. A synchronizing signal SYNC is supplied to the A/D converter 290 from the pulse width modulator 240. The synchronization signal SYNC is synchronized with the TRIA signal and the TRIB signal, and indicates, for example, the peak and bottom timings of TRIA and TRIB. The sample and hold timing of the A/D converter 290 is synchronized with the synchronization signal SYNC. For example, the A/D converter 290 is configured to be able to retime the internal timing signal S/H using the synchronization signal SYNC.

The digital compensator 224 takes in the digital error signal _DERR output from the A/D converter 290 during the period when the mask signal MSKB is negated. Digital compensator 224 generates voltage command value D _CTRL according to digital error signal D _ERR .

Note that the A/D converter 290 may stop operating during the period when the mask signal MSK is asserted, or may continue to operate during the period when the mask signal MSK is asserted.

The above is the configuration of the motor driver circuit 200. Next, its operation will be explained.

The above is the configuration of the positioning device 100. Next, its operation will be explained. FIG. 3 is a diagram showing input/output characteristics of the motor driver circuit 200 of FIG. 2. Feedback control by the digital compensator 224 applies feedback so that the error between the feedback signal V _FB and the analog command signal V _DAC becomes closer. Therefore, when the feedback is stable, equation (2) holds true.
V _FB =k×I _DRV +V _CMREF =V _DAC …(2)
In a steady state where equation (2) holds true, drive current I _DRV is stabilized at the target level I _REF expressed by equation (3).
I _REF = (V _DAC - V _CMREF )/k...(3)

The above is the operation of the motor driver circuit 200. According to the motor driver circuit 200, an analog phase compensation circuit is not required, compared to the case of an analog system, and therefore the design is easier.

FIG. 4 is an operational waveform diagram of the motor driver circuit 200. In the pulse width modulator 240, the voltage command value V _CTRL is compared with the triangular wave signals TRIA and TRIB to generate a PWMA signal and a PWMB signal.

The first driver 260 generates a pulsed A-phase drive voltage V _OUTA in response to the PWMA signal. Due to the delay of the first driver 260, the A-phase drive voltage V _OUTA lags behind the PWMA signal. The second driver 270 generates a pulsed B-phase drive voltage V _OUTB in response to the PWMB signal. Due to the delay of the second driver 270, the B-phase drive voltage V _OUTB lags behind the PWMB signal.

Mask signal MSKB is generated by mask generation circuit 280. The mask signal MSKB is asserted (high) during the transition period of the A-phase drive voltage V _OUT , and is negated (low) while the A-phase drive voltage V _OUT is stable.

While the mask signal MSK is negated, the A/D converter 290 converts the analog error signal V _ERR into a digital error signal D _ERR based on the timing signal (sample hold signal) S/H, which is its internal signal.

In the waveform diagram of FIG. 4, the S/H signal is synchronized with the triangular wave signals TRIA and TRIB. Specifically, the S/H signal is retimed (forced synchronized) at the peak and bottom timings of the triangular wave signals TRIA and TRIB.

At the bottom of FIG. 4, the digital error signal _DERR taken into the digital compensator 224 is shown. The digital compensator 224 generates a digital control amount D _CTRL based on the captured digital error signal D _ERR . This digital control amount D _CTRL is converted by the D/A converter 226 into an analog voltage command value V _CTRL .

The above is the operation of the motor driver circuit 200. As described above, the inventor of the present invention recognized that the current detection accuracy decreases during the transition of the voltage (A-phase drive voltage) V _OUTA of the output terminal AOUT connected to the current sense resistor Rs. Therefore, current detection accuracy can be improved by masking current detection during the transition of the A-phase drive voltage V _OUTA .

The present disclosure extends to various devices and methods that can be understood as the block diagram or circuit diagram of FIG. 2 or derived from the above description, and is not limited to a particular configuration. More specific configuration examples and examples will be described below, not to narrow the scope of the present disclosure, but to help understand and clarify the essence and operation of the present disclosure and the present invention.

(Example 1)
FIG. 5 is a circuit diagram showing a portion of the motor driver circuit 200A according to the first embodiment. The first driver 260 includes a high side transistor MH, a low side transistor ML, a high side predriver 262, a low side predriver 264, and a bootstrap diode D1.

High-side transistor MH is an N-channel MOSFET, and is connected between a power supply terminal VCC receiving input voltage _VCC and an OUTA terminal. Low-side transistor ML is connected between the OUTA terminal and ground. The input voltage V _CC is, for example, 12V to 60V.

A bootstrap capacitor _CBS is externally connected between the bootstrap terminal BS and the AOUT terminal. The power supply voltage V _DD is input to the anode of the diode D1, and the cathode of the diode D1 is connected to the BS terminal.

High-side pre-driver 262 and low-side pre-driver 264 complementarily drive high-side transistor MH and low-side transistor ML according to the PWMA signal. When the PWMA signal is high, the high-side pre-driver 262 applies a high voltage, specifically a voltage _VBS generated at the BS terminal, to the gate of the high-side transistor MH, thereby turning on the high-side transistor MH. Furthermore, when the PWMA signal is low, the high-side pre-driver 262 applies a low voltage, specifically a voltage V _OUTA generated at the OUTA terminal, to the gate of the high-side transistor MH, thereby turning off the high-side transistor MH.

When the PWMA signal is low, the low-side pre-driver 264 applies a high voltage, specifically, a power supply voltage V _DD , to the gate of the low-side transistor ML to turn on the low-side transistor ML. Furthermore, when the PWMA signal is high, the low-side pre-driver 264 applies a low voltage, specifically, a ground voltage of 0 V, to the gate of the low-side transistor ML to turn off the low-side transistor ML.

The mask generation circuit 280A includes an edge detection circuit 282, a first comparator 284, a second comparator 286, and a logic circuit 288.

Edge detection circuit 282 detects positive edges and negative edges of the PWMA signal and generates edge detection signal EDGE. Edge detection signal EDGE indicates the start of transition of A-phase drive voltage V _OUTA . Logic circuit 288 asserts (low) mask signal MSKB in response to edge detection signal EDGE.

The first comparator 284 compares the gate-source voltage V _GS of the high-side transistor MH with the first threshold voltage V _TH1 and asserts the high transition completion signal H_DET when V _GS >V _TH1 . Assertion of the H_DET signal indicates the completion of the low-to-high transition of the A-phase drive voltage V _OUTA .

The second comparator 286 compares the A-phase drive voltage V _OUTA with the second threshold voltage V _TH2 . The second threshold voltage V _TH2 is set, for example, between 0 and 1V. The second comparator 286 asserts the low transition completion signal L_DET when V _OUTA <V _TH2 . Assertion of the L_DET signal indicates the completion of the high-to-low transition of the A-phase drive voltage V _OUTA .

Logic circuit 288 negates mask signal MSKB (high) in response to assertion of the H_DET signal and assertion of the L_DET signal.

The above is the configuration of the motor driver circuit 200A. Next, its operation will be explained.

FIG. 6 is an operational waveform diagram of the motor driver circuit 200A of FIG. 5. When the PWMA signal becomes high at time _t0 , the edge detection signal EDGE is asserted, and the mask signal MSKB becomes asserted (low).

When the PWMA signal becomes high, the gate capacitance of the high-side transistor MH is charged by the high-side predriver 262, and the gate-source voltage _VGS of the high-side transistor MH increases. When the gate-source voltage V _GS exceeds the first threshold voltage V _TH1 at time t ₁ , the H_DET signal is asserted. As a result, the mask signal MSKB is negated (high).

The above is the generation of the mask signal MSKB regarding the rising edge of the A-phase drive voltage V _OUTA .

At time _t2 , when the PWMA signal transitions to low, the edge detection signal EDGE is asserted and the mask signal MSKB is asserted (low).

When the PWMA signal becomes low, the gate capacitance of the high-side transistor MH is discharged by the high-side predriver 262, the gate-source voltage _VGS of the high-side transistor MH decreases, and the high-side transistor MH is turned off. Furthermore, the low-side predriver 264 turns on the low-side transistor ML. As a result, the A-phase drive voltage V _OUTA decreases.

At time _t3 , when the A-phase drive voltage V _OUTA becomes lower than the second threshold voltage V _TH2 , the L_DET signal is asserted. As a result, the mask signal MSKB is negated (high).

The above is the generation of the mask signal MSKB regarding the fall edge of the A-phase drive voltage V _OUTA .

According to the mask generation circuit 280A of FIG. 5, the mask signal MSKB can be asserted during the rise edge and fall edge sections of the A-phase drive voltage V _OUTA .

(Example 2)
FIG. 7 is a circuit diagram showing a part of the motor driver circuit 200B according to the second embodiment. The configuration of the first driver 260 is similar to that in FIG. 5.

The mask generation circuit 280B includes a delay circuit 289 in addition to an edge detection circuit 282, a first comparator 284, a second comparator 286, and a logic circuit 288.

The delay circuit 289 delays the H_DET signal by a first time τ ₁ and delays the L_DET signal by a second time τ ₂ . Logic circuit 288 negates mask signal MSKB in response to the delayed H_DET signal and the delayed L_DET signal.

The first time τ ₁ and the second time τ ₂ may be equal or different. For example, the first time τ ₁ and the second time τ ₂ can be 0.2 μs. These delay times τ ₁ and τ ₂ may be externally settable using a register or the like. In this case, it may be possible to set the time in the range of 0 to 1 μs.

FIG. 8 is an operational waveform diagram of the motor driver circuit 200B of FIG. 7. When the PWMA signal becomes high at time _t0 , the edge detection signal EDGE is asserted, and the mask signal MSKB becomes asserted (low).

When the PWMA signal becomes high, the gate capacitance of the high-side transistor MH is charged by the high-side predriver 262, and the gate-source voltage _VGS of the high-side transistor MH increases. When the gate-source voltage V _GS exceeds the first threshold voltage V _TH1 at time t ₁ , the H_DET signal is asserted. The mask signal MSKB is negated at time t _{1 ′} after a first time τ _{1 has elapsed from time t 1} .

The above is the generation of the mask signal MSKB regarding the rising edge of the A-phase drive voltage V _OUTA .

At time _t2 , when the PWMA signal transitions to low, the edge detection signal EDGE is asserted and the mask signal MSKB is asserted (low).

When the PWMA signal becomes low, the gate capacitance of the high-side transistor MH is discharged by the high-side predriver 262, the gate-source voltage _VGS of the high-side transistor MH decreases, and the high-side transistor MH is turned off. Furthermore, the low-side predriver 264 turns on the low-side transistor ML. As a result, the A-phase drive voltage V _OUTA decreases.

At time _t3 , when the A-phase drive voltage V _OUTA becomes lower than the second threshold voltage V _TH2 , the L_DET signal is asserted. The mask signal MSKB is negated at time t _{3 ′} after a second time τ _{2 has elapsed from time t 3} .

The above is the generation of the mask signal MSKB regarding the fall edge of the A-phase drive voltage V _OUTA .

The transition time of the A-phase drive voltage V _OUTA depends on the type of motor and the voltage level of the power supply voltage V _CC . According to the mask generation circuit 280B of FIG. 7, the mask time can be extended according to the first time τ ₁ and the second time τ ₂ , and the mask time can be optimized according to the transition time of the A-phase drive voltage V _OUTA . can be converted into

(Example 3)
FIG. 9 is a circuit diagram showing a portion of a motor driver circuit 200C according to the third embodiment.

Regarding the mask period corresponding to the fall edge of the A-phase drive voltage V _OUTA , the mask generation circuit 280C generates a mask signal when the A-phase drive voltage V _OUTA becomes higher than the third threshold voltage V _TH3 after the mask signal MSKB is asserted. Negate MSKB.

The mask generation circuit 280C includes a third comparator 285 in place of the first comparator 284 of the mask generation circuit 280B in FIG. The third comparator 285 compares the A-phase drive voltage V _OUTA with the third threshold voltage V _TH3 , and asserts the H_DET signal when V _OUTA > V _TH3 .

Note that in the mask generation circuit 280C of FIG. 9, the delay circuit 289 may be omitted.

FIG. 10 is an operational waveform diagram of the motor driver circuit 200C of FIG. 9. When the PWMA signal becomes high at time _t0 , the edge detection signal EDGE is asserted, and the mask signal MSKB becomes asserted (low).

When the PWMA signal becomes high, the gate capacitance of the high-side transistor MH is charged by the high-side predriver 262, and the gate-source voltage _VGS of the high-side transistor MH increases. At time _t1 , when the A-phase drive voltage V _OUTA exceeds the third threshold voltage V _TH3 , the H_DET signal is asserted. The mask signal MSKB is negated at time t _{1 ′} after a first time τ _{1 has elapsed from time t 1} .

The above is the generation of the mask signal MSKB regarding the rising edge of the A-phase drive voltage V _OUTA . The generation of the mask signal MSKB signal regarding the roll edge is similar to that in FIG. 8 .

(Example 4)
FIG. 11 is a circuit diagram showing a portion of a motor driver circuit 200D according to the fourth embodiment. In motor driver circuit 200D, mask signal MSKB from mask generation circuit 280 is input to A/D converter 290D instead of synchronization signal SYNC in FIG. The sample and hold timing of the A/D converter 290D is synchronized with the negation timing of the mask signal MSKB, that is, the positive edge of the mask signal MSKB. For example, the A/D converter 290D is configured to be able to retime the internal timing signal S/H using the negation edge of the mask signal MSKB.

FIG. 12 is a circuit diagram showing a configuration example of A/D converter 290D in FIG. 11. A/D converter 290D includes a timing signal generator 292 and an A/D conversion section 294. The timing signal generator 292 generates a timing signal (sample hold signal) S/H during a period when the mask signal MSKB is negated. The A/D converter 294 converts the analog signal _VERR into a digital signal _DERR based on the S/H signal, and stores it in the memory.

Timing signal generator 292 retimes the S/H signal in response to the positive edge of mask signal MSKB. For example, the timing signal generator 292 is reset by the negation (positive edge) of the mask signal MSKB, and starts generating the S/H signal using the negation of the mask signal MSKB as a start signal.

FIG. 13 is an operational waveform diagram of the motor driver circuit 200D of FIG. 11. The positive edge of mask signal MSK triggers the start of operation of A/D converter 290D.

FIG. 14 is a diagram showing spectra obtained in the motor driver circuit 200 of FIG. 2 and the motor driver circuit 200D of FIG. 11. The spectrum is obtained by converting the time waveform of the drive current _IDRV flowing through the linear motor 102 by fast Fourier transform.

The PWM frequency is 210 kHz, and the spectrum includes the PWM frequency and its harmonics. Referring to the upper part of FIG. 14, in the motor driver circuit 200 of FIG. 2, a spectrum peak is measured at 8.4 kHz and its harmonics in addition to the PWM frequency and its harmonics. Such a peak is undesirable because it is included in a very low frequency band.

On the other hand, referring to the lower part of FIG. 14, in the motor driver circuit 200D of FIG. 11, the peak at 8.4 kHz has disappeared. In motor driver circuit 200D of FIG. 11, undesirable spectral peaks can be suppressed by synchronizing the sampling operation of A/D converter 290 with mask signal MSKB.

Next, configuration examples of the current detection circuit 250 and the error detection amplifier 230 will be explained.

FIG. 15 is a circuit diagram showing a configuration example of the current detection circuit 250 and the error detection amplifier 230.

A voltage drop proportional to the drive current _IDRV occurs across the sense resistor Rs. The voltage drop _VCS of the sense resistor Rs is fed back between the current sense pins ISNS and KSNS (AOUT) of the motor driver circuit 200.
V _CS =R _S ×I _DRV

Current detection circuit 250 generates a current feedback signal V _FB that varies linearly with respect to voltage V _CS and reaches a predetermined level V _CMREF when V _CS =0 (that is, I _DRV =0).

The current detection circuit 250 includes a first operational amplifier OA1, a first resistor R1, a second resistor R2, a third resistor R3, and a fourth resistor R4.

The first resistor R1 is connected between the inverting input (-) of the first operational amplifier OA1 and one end (ISNS pin) of the sense resistor Rs. The second resistor R2 is connected between the inverting input (-) of the first operational amplifier OA1 and the output of the first operational amplifier OA1. The third resistor R3 is connected between the non-inverting input (+) of the first operational amplifier OA1 and the other end (KSNS pin) of the sense resistor Rs. The fourth resistor R4 receives a voltage V _CMREF at a predetermined level at one end thereof, and has the other end connected to the non-inverting input (+) of the first operational amplifier OA1. The current feedback signal V _FB is responsive to the output voltage of the first operational amplifier OA1.

When R1=R3 and R2=R4 hold true, the following equation holds true.
V _FB =R2/R1×V _CS +V _CMREF

The error detection amplifier 230 includes a first input node n1, a second input node n2, an output node n3, a second operational amplifier OA2, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, and a capacitor C1. include. A current feedback signal V _FB is input to the first input node n1, and an analog command signal V _DAC is input to the second input node n2.

The second operational amplifier OA2, the fifth resistor R5, the sixth resistor R6, and the seventh resistor R7 constitute a summing amplifier. The second operational amplifier OA2 receives a reference voltage V _CMREF at its non-inverting input (+). The fifth resistor R5 is connected between the inverting input (-) of the second operational amplifier OA2 and the first input node n1. The sixth resistor R6 is connected between the inverting input (-) of the second operational amplifier OA2 and the second input node n2. The voltage command signal V _EAOUT may be responsive to the voltage of the output of the second operational amplifier OA2. A seventh resistor R7 is connected between the inverting input (-) of the second operational amplifier OA2 and its output.

The gain g of the adder circuit for the feedback voltage V _FB is R7/R5.

Further, an eighth resistor R8 is connected between the output of the second operational amplifier OA2 and the output node n3 of the error detection amplifier 230. A capacitor C1 is connected to the output node n3. The eighth resistor R8 and the capacitor C1 constitute a low-pass filter. This low-pass filter functions as an anti-alias filter for the A/D converter 290 at the subsequent stage.

The above is an example of the configuration of the current detection circuit 250 and the error detection amplifier 230.

(Example 5)
FIG. 16 is a circuit diagram of a motor driver circuit 200E according to the fifth embodiment. The current command generation unit 210E outputs a target code (digital command value) D _REF indicating the target position of the movable element to the feedback controller 220E. The A/D converter 222 of the feedback controller 220A converts the current feedback signal V _FB to a digital current feedback value D _FB . The error detector 232 is a subtracter and generates an error D _ERR between the digital current feedback value D _FB and the target code D _REF . Others are the same as in FIG. 2.

According to the motor driver circuit 200E of FIG. 16, the same effects as the motor driver circuit 200 of FIG. 2 can be obtained.

Note that the motor driver circuit 200 in FIG. 2 has advantages over the motor driver circuit 200E in FIG. 16. This advantage will be explained below.

In the motor driver circuit 200E of FIG. 16, attention is paid to the current feedback signal _VFB , which is the input of the A/D converter 222. In a steady state where the feedback loop is stabilized, the error has converged to D _ERR , so D _REF =D _FB holds true. That is, when the digital command value D _REF is changed, the current feedback signal V _FB that is input to the A/D converter 222 changes so that a digital current feedback value D _FB that matches it is generated. That is, in the motor driver circuit 200E of FIG. 16, the current feedback signal V _FB changes over a wide range in response to changes in the digital command value D _REF . Therefore, it is necessary to select a high-bit A/D converter 222.

The advantages of the motor driver circuit 200 of FIG. 2 over the motor driver circuit 200E of FIG. 16 will be explained. In the motor driver circuit 200 of FIG. 2, attention is paid to the input of the A/D converter 290. The input to A/D converter 290 is an analog error signal _VERR . In steady state, where the feedback loop is stabilized, the analog error signal V _ERR converges to substantially zero, regardless of the target level I _REF of the drive current I _DRV , that is, regardless of the magnitude of the analog command signal V _DAC . ing. Therefore, the variation range of the input voltage of A/D converter 290 is narrower than that of A/D converter 222 in FIG. 16. As a result, the A/D converter 290 in FIG. 2 can be of a lower bit than the A/D converter 222 in FIG. 16. By reducing the bits of the A/D converter 222, the chip cost and power consumption of the motor driver circuit 200 can be reduced.

In addition, in the motor driver circuit 200 of FIG. 2, the gain of the error detection amplifier 230 can be increased. This is because, regardless of the gain, in steady state, the error signal V _ERR , ie, the input of the A/D converter 290, assumes a voltage level corresponding to zero. Increasing the gain of the error detection amplifier 230 produces the same effect as increasing the number of bits (resolution) of the A/D converter 290. Therefore, the motor driver circuit 200 can reduce the number of bits of the A/D converter 290 for this reason as well.

For example, if the motor driver circuit 200E in FIG. 16 requires a 16-bit A/D converter 222, the number of bits in the A/D converter 290 can be reduced to 12 bits in the motor driver circuit 200 in FIG. can. A SAR (successive approximation) DAC can be used as the low-bit A/D converter 290, but other formats may also be used.

(Example 6)
FIG. 17 is a circuit diagram of a motor driver circuit 200F according to the sixth embodiment. Pulse width modulator 240F is composed of a digital circuit. The D/A converter 226 is omitted from the feedback controller 220F, and a digital voltage command value D _CTRL is supplied to the pulse width modulator 240F. The pulse width modulator 240F generates pulse signals PWMA and PWMB having complementary duty cycles according to the digital voltage command value _DCTRL by digital signal processing.

According to the motor driver circuit 200F of FIG. 17, the same effects as the motor driver circuit 200 of FIG. 2 can be obtained.

(Embodiment 2)
FIG. 18 is a block diagram of a positioning device 100G including a motor driver circuit 200G according to the second embodiment.

Feedback controller 220G includes a sample and hold circuit 300 inserted before A/D converter 290. In this embodiment, the mask signal MSKB is supplied to the sample and hold circuit 300 instead of the digital compensator 224.

The sample and hold circuit 300 is a track and hold circuit, and outputs the analog error signal _VERR generated by the error detection amplifier 230 as it is while the mask signal MSKB is negated (track mode). When the mask signal MSKB is asserted, the sample and hold circuit 300 samples the analog error signal _VERR at that time and holds it while the mask signal MSKB is asserted (hold mode).

FIG. 19 is a circuit diagram showing a configuration example of the sample and hold circuit 300. Sample and hold circuit 300 includes a switch 302, a low pass filter 304, and a buffer 306. The low-pass filter 304 can also be used as a pre-filter (anti-alias filter) of the A/D converter 290.

The above is the configuration of the motor driver circuit 200G. Next, the advantages thereof will be explained in comparison with the first embodiment.

In the first embodiment, it can be said that the digital error signal DERR is subjected to hold processing based on the mask signal MSKB. In this case, depending on the timing relationship between the sample and hold timing signal S/H of the A/D converter 290 and the mask signal MSKB, there is a possibility that a beat may occur. On the other hand, in the second embodiment, since the analog error signal _VERR is held using a sample and hold circuit, the occurrence of beats can be suppressed.

(Application)
FIG. 20 is a diagram showing a hard disk device 900 including a motor driver circuit 200. The hard disk drive 900 includes a platter 902, a swing arm 904, a head 906, a spindle motor 910, a seek motor 912, and a motor driver circuit 920. A motor driver circuit 920 drives a spindle motor 910 and a seek motor 912.

Seek motor 912 is a voice coil motor. The motor driver circuit 200 (or 200A) according to the embodiment is included in the motor driver circuit 920 and drives the seek motor 912. Seek motor 912 positions head 906 via swing arm 904.

In the present disclosure, the configuration and type of the linear motor to be driven are not particularly limited. For example, the present disclosure is applicable to driving a spring return type voice coil motor and other linear actuators. Alternatively, the motor to be driven may be a spindle motor.

The use of the positioning device 100 is not limited to hard disk drives, but can also be applied to camera lens positioning mechanisms.

(Additional note)
The following technology is disclosed in this specification.

(Item 1)
a first output terminal to be connected to a first end of a motor to be driven via a current sense resistor;
a second output terminal to be connected to a second end of the motor;
a mask generation circuit that generates a mask signal that is asserted using the start of transition of the first output voltage of the first output terminal as a trigger and is negated after the transition is completed;
an error detector that generates an analog error signal based on an error between a current feedback signal based on a voltage drop across the current sense resistor and a reference signal;
a feedback controller that generates a voltage command value based on the analog error signal generated during the period when the mask signal is negated;
a pulse width modulator that generates a first pulse and a second pulse having complementary duty cycles according to the voltage command value;
a first driver that generates the first output voltage at the first output terminal according to the first pulse;
a second driver that generates a second output voltage at the second output terminal according to the second pulse;
A motor driver circuit comprising:

(Item 2)
The feedback controller is
an A/D converter that converts the analog error signal into a digital error signal;
a compensator that captures the digital error signal during a period in which the mask signal is negated and generates a voltage command value according to the digital error signal;
The motor driver circuit according to claim 1, comprising:

(Item 3)
The feedback controller is
a sample and hold circuit that holds the analog error signal during a period in which the mask signal is asserted;
an A/D converter that converts the output of the sample and hold circuit into a digital error signal;
a compensator that generates a voltage command value according to the digital error signal;
The motor driver circuit according to claim 1, comprising:

(Item 4)
4. The motor driver circuit according to claim 1, wherein the mask generation circuit asserts the mask signal using a transition of the first pulse as a trigger.

(Item 5)
The first driver includes a high-side transistor and a low-side transistor,
Regarding the mask signal corresponding to a rising edge of the first output voltage, the mask generation circuit negates the mask signal when a gate-source voltage of the high-side transistor exceeds a first threshold voltage. The motor driver circuit according to any one of Items 1 to 4.

(Item 6)
The first driver includes a high-side transistor and a low-side transistor,
Regarding the mask signal corresponding to the rising edge of the first output voltage, the mask generation circuit generates a signal after a predetermined first time has elapsed after the gate-source voltage of the high-side transistor exceeds a first threshold voltage. 5. The motor driver circuit according to claim 1, wherein the motor driver circuit negates the mask signal.

(Item 7)
Regarding a mask period corresponding to a fall edge of the first output voltage, the mask generation circuit negates the mask signal when the first output voltage becomes lower than a second threshold voltage after assertion of the mask signal. A motor driver circuit according to any one of claims 1 to 6.

(Item 8)
Regarding the mask period corresponding to the fall edge of the first output voltage, the mask generation circuit is configured to control the mask generation circuit for a predetermined second period of time after the first output voltage becomes lower than a second threshold voltage after the mask signal is asserted. 7. The motor driver circuit according to claim 1, wherein said mask signal is negated after a period of time has elapsed.

(Item 9)
Regarding the mask signal corresponding to a rising edge of the first output voltage, the mask generation circuit negates the mask signal when the first output voltage exceeds a third threshold voltage after assertion of the mask signal. A motor driver circuit according to any one of claims 1 to 4.

(Item 10)
Regarding the mask signal corresponding to a rising edge of the first output voltage, the mask generation circuit generates a predetermined first time period after the first output voltage exceeds a third threshold voltage after assertion of the mask signal. 5. The motor driver circuit according to claim 1, wherein the mask signal is negated after .

(Item 11)
The motor driver circuit according to claim 6 or 10, wherein the predetermined first time can be set from the outside.

(Item 12)
The motor driver circuit according to claim 8, wherein the predetermined second time can be set from the outside.

(Item 13)
3. The motor driver circuit according to claim 2, wherein the A/D converter restarts a sample and hold timing signal using negation of the mask signal as a trigger.

(Item 14)
a first output terminal to be connected to a first end of a motor to be driven via a current sense resistor;
a second output terminal to be connected to a second end of the motor;
a mask generation circuit that generates a mask signal that is asserted using the start of transition of the first output voltage of the first output terminal as a trigger and is negated after the transition is completed;
a current detection circuit that generates a current feedback signal based on a voltage drop across the current sense resistor;
a feedback controller that generates a voltage command value so that the current feedback signal approaches a reference signal;
a pulse width modulator that generates a first pulse and a second pulse having complementary duty cycles according to the voltage command value;
a first driver that generates the first output voltage at the first output terminal according to the first pulse;
a second driver that generates a second output voltage at the second output terminal according to the second pulse;
Equipped with
A motor driver circuit, wherein at least a portion of the feedback controller is configured with a digital circuit, and the digital circuit is configured to convert an analog signal into a digital signal and input the digital signal during a period when the mask signal is negated.

(Item 15)
The motor driver circuit according to claim 14, wherein the analog signal is an analog error signal based on an error between the current feedback signal and a reference signal.

(Item 16)
15. The motor driver circuit of claim 14, wherein the analog signal is the current feedback signal.

(Item 17)
17. The motor driver circuit according to claim 1, wherein the motor is a linear motor.

(Item 18)
The motor driver circuit according to claim 17, wherein the linear motor is a voice coil motor.

(Item 19)
The motor driver circuit according to any one of claims 1 to 18, which is monolithically integrated on one semiconductor substrate.

(Item 20)
linear motor,
The motor driver circuit according to any one of claims 1 to 19, which drives the linear motor;
A positioning device comprising:

(Item 21)
A hard disk device comprising the positioning device according to claim 20.

(Item 22)
A method for driving a motor, the method comprising:
connecting a current sense resistor in series with the motor at a first end of the motor;
generating a current feedback signal based on the voltage drop across the current sense resistor;
asserting a mask signal using the start of transition of the first output voltage applied to the current sense resistor as a trigger;
negating the mask signal using completion of the transition of the first output voltage as a trigger;
generating an analog error signal according to an error between the current feedback signal and a reference signal;
converting the analog error signal into a digital error signal and capturing it while the mask signal is negated;
generating a voltage command value according to the digital error signal;
generating a first pulse and a second pulse having complementary duty cycles according to the voltage command value;
applying the first output voltage responsive to the first pulse to the first end of the motor via the current sense resistor;
applying a second output voltage corresponding to the second pulse to a second end of the motor;
A driving method comprising:

(Item 23)
A method for driving a motor, the method comprising:
connecting a current sense resistor in series with the first end of the motor;
generating a current feedback signal based on the voltage drop across the current sense resistor;
asserting a mask signal using the start of transition of the first output voltage applied to the current sense resistor as a trigger;
negating the mask signal using completion of the transition of the first output voltage as a trigger;
generating a voltage command value such that the current feedback signal approaches a reference signal;
generating a first pulse and a second pulse having complementary duty cycles according to the voltage command value;
applying the first output voltage responsive to the first pulse to the first end of the motor via the current sense resistor;
applying a second output voltage corresponding to the second pulse to a second end of the motor;
Equipped with
The driving method, wherein the step of generating the voltage command value includes the step of converting an analog signal into a digital signal and capturing the digital signal while the mask signal is negated.

100 Positioning device 102 Linear motor 104 Host controller 200 Motor driver circuit 210 Current command generation section 212 Interface circuit 214 Logic circuit 216 D/A converter 220 Feedback controller 222 A/D converter 224 Digital compensator 226 D/A converter 230 Error detection amplifier 240 Pulse Width Modulator 250 Current Detection Circuit 260 First Driver 262 High Side Predriver 264 Low Side Predriver 270 Second Driver 290 A/D Converter 292 Timing Signal Generator 294 A/D Conversion Unit 280 Mask Generation Circuit 282 Edge Detection Circuit 284 First comparator 286 Second comparator 288 Logic circuit

Claims (23)

a first output terminal to be connected to a first end of a motor to be driven via a current sense resistor;
a second output terminal to be connected to a second end of the motor;
a mask generation circuit that generates a mask signal that is asserted using the start of transition of the first output voltage of the first output terminal as a trigger and is negated after the transition is completed;
an error detector that generates an analog error signal based on an error between a current feedback signal based on a voltage drop across the current sense resistor and a reference signal;
a feedback controller that generates a voltage command value based on the analog error signal generated during the period when the mask signal is negated;
a pulse width modulator that generates a first pulse and a second pulse having complementary duty cycles according to the voltage command value;
a first driver that generates the first output voltage at the first output terminal according to the first pulse;
a second driver that generates a second output voltage at the second output terminal according to the second pulse;
A motor driver circuit comprising: The feedback controller is
an A/D converter that converts the analog error signal into a digital error signal;
a compensator that captures the digital error signal during a period in which the mask signal is negated and generates a voltage command value according to the digital error signal;
The motor driver circuit according to claim 1, comprising: The feedback controller is
a sample and hold circuit that holds the analog error signal during a period in which the mask signal is asserted;
an A/D converter that converts the output of the sample and hold circuit into a digital error signal;
a compensator that generates a voltage command value according to the digital error signal;
The motor driver circuit according to claim 1, comprising: 4. The motor driver circuit according to claim 1, wherein the mask generation circuit asserts the mask signal using a transition of the first pulse as a trigger. The first driver includes a high-side transistor and a low-side transistor,
Regarding the mask signal corresponding to a rising edge of the first output voltage, the mask generation circuit negates the mask signal when a gate-source voltage of the high-side transistor exceeds a first threshold voltage. The motor driver circuit according to any one of Items 1 to 3. The first driver includes a high-side transistor and a low-side transistor,
Regarding the mask signal corresponding to the rising edge of the first output voltage, the mask generation circuit generates a signal after a predetermined first time has elapsed after the gate-source voltage of the high-side transistor exceeds a first threshold voltage. 4. The motor driver circuit according to claim 1, wherein the motor driver circuit negates the mask signal. Regarding a mask period corresponding to a fall edge of the first output voltage, the mask generation circuit negates the mask signal when the first output voltage becomes lower than a second threshold voltage after assertion of the mask signal. A motor driver circuit according to any one of claims 1 to 3. Regarding the mask period corresponding to the fall edge of the first output voltage, the mask generation circuit is configured to perform a mask generation circuit for a predetermined second period of time after the first output voltage becomes lower than a second threshold voltage after assertion of the mask signal. 4. The motor driver circuit according to claim 1, wherein said mask signal is negated after a period of time has elapsed. Regarding the mask signal corresponding to a rising edge of the first output voltage, the mask generation circuit negates the mask signal when the first output voltage exceeds a third threshold voltage after assertion of the mask signal. A motor driver circuit according to any one of claims 1 to 3. Regarding the mask signal corresponding to a rising edge of the first output voltage, the mask generation circuit generates a predetermined first time period after the first output voltage exceeds a third threshold voltage after assertion of the mask signal. 4. The motor driver circuit according to claim 1, wherein the mask signal is negated after . The motor driver circuit according to claim 6, wherein the predetermined first time can be set from the outside. The motor driver circuit according to claim 8, wherein the predetermined second time can be set from the outside. 3. The motor driver circuit according to claim 2, wherein the A/D converter restarts a sample and hold timing signal using negation of the mask signal as a trigger. a first output terminal to be connected to a first end of a motor to be driven via a current sense resistor;
a second output terminal to be connected to a second end of the motor;
a mask generation circuit that generates a mask signal that is asserted using the start of transition of the first output voltage of the first output terminal as a trigger and is negated after the transition is completed;
a current detection circuit that generates a current feedback signal based on a voltage drop across the current sense resistor;
a feedback controller that generates a voltage command value so that the current feedback signal approaches a reference signal;
a pulse width modulator that generates a first pulse and a second pulse having complementary duty cycles according to the voltage command value;
a first driver that generates the first output voltage at the first output terminal according to the first pulse;
a second driver that generates a second output voltage at the second output terminal according to the second pulse;
Equipped with
A motor driver circuit, wherein at least a portion of the feedback controller is configured with a digital circuit, and the digital circuit is configured to convert an analog signal into a digital signal and input the digital signal during a period when the mask signal is negated. The motor driver circuit according to claim 14, wherein the analog signal is an analog error signal based on an error between the current feedback signal and a reference signal. 15. The motor driver circuit of claim 14, wherein the analog signal is the current feedback signal. The motor driver circuit according to any one of claims 1 to 3, wherein the motor is a linear motor. The motor driver circuit according to claim 17, wherein the linear motor is a voice coil motor. The motor driver circuit according to any one of claims 1 to 3, which is integrally integrated on one semiconductor substrate. linear motor,
The motor driver circuit according to any one of claims 1 to 3, which drives the linear motor;
A positioning device comprising: A hard disk device comprising the positioning device according to claim 20. A method for driving a motor, the method comprising:
connecting a current sense resistor in series with the motor at a first end of the motor;
generating a current feedback signal based on the voltage drop across the current sense resistor;
asserting a mask signal using the start of transition of the first output voltage applied to the current sense resistor as a trigger;
negating the mask signal using completion of the transition of the first output voltage as a trigger;
generating an analog error signal according to an error between the current feedback signal and a reference signal;
converting the analog error signal into a digital error signal and capturing it while the mask signal is negated;
generating a voltage command value according to the digital error signal;
generating a first pulse and a second pulse having complementary duty cycles according to the voltage command value;
applying the first output voltage responsive to the first pulse to the first end of the motor via the current sense resistor;
applying a second output voltage corresponding to the second pulse to a second end of the motor;
A driving method comprising: A method for driving a motor, the method comprising:
connecting a current sense resistor in series with the first end of the motor;
generating a current feedback signal based on the voltage drop across the current sense resistor;
asserting a mask signal using the start of transition of the first output voltage applied to the current sense resistor as a trigger;
negating the mask signal using completion of the transition of the first output voltage as a trigger;
generating a voltage command value such that the current feedback signal approaches a reference signal;
generating a first pulse and a second pulse having complementary duty cycles according to the voltage command value;
applying the first output voltage responsive to the first pulse to the first end of the motor via the current sense resistor;
applying a second output voltage corresponding to the second pulse to a second end of the motor;
Equipped with
The driving method, wherein the step of generating the voltage command value includes the step of converting an analog signal into a digital signal and capturing the digital signal while the mask signal is negated.

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