JP2023125275A - Driver circuit, optical switch system, and communication network - Google Patents

Abstract

To provide a driver circuit, an optical switch system, and a communication network that can perform a high-speed bias switching operation while applying an appropriate bias.SOLUTION: A driver circuit 100 is provided in a telecommunication network that connects an optical switch device 30 that converts optical signals transmitted and received in an optical communication network that connects a first control device and a plurality of second control devices 20 in a ring shape, according to electrical signals transmitted and received in the second control devices 20, and the second control devices 20. The driver circuit 100 has a driver unit 101, a normal bias T circuit unit 102, and a burst mode bias T circuit unit 103. The driver unit 101 amplifies the electrical signals transmitted by the second control devices 20. The burst mode bias T circuit unit 103 has a smaller time constant τ related to a bias switching operation than the normal bias T circuit unit 102.SELECTED DRAWING: Figure 3

Description

The present invention relates to driver circuits, optical switch systems, and communication networks.

In recent years, there has been a demand for networks with larger capacity and lower latency. Therefore, a configuration using an optical communication network that is small, lightweight, and can handle a large amount of information communication using silicon photonics technology is being considered. In this case, a gateway device that relays between the optical communication network and the telecommunications network may be used.

A gateway device generally includes an optical switch device and a driver circuit. A gateway device outputs a high-speed, broadband optical signal by driving an optical switch device that uses a material with an electro-optic effect or the electric field absorption effect of a semiconductor, which converts an electrical signal into an optical signal, with a driver circuit. It is a device. Here, the optical signal transmitted and received by the gateway device is realized by a burst signal including data frames and guard times provided between the data frames. The data frame includes a preamble section and a payload section in which information is stored. The preamble section includes an arbitrary bit pattern used to prepare the optical switch device for transmission/reception operations. In order to reliably receive the information stored in the payload section provided next to the preamble section from the first bit, the optical switch device is required to complete preparations for transmitting and receiving operations in the preamble section. The gateway device must be ready for operation in the preamble section before the payload section so that it can transmit and receive signals of information stored in the payload section without loss. The operation preparation is, for example, a bias switching operation of a telecommunications network. Therefore, the gateway device is required to perform a high-speed bias switching operation in preparation for operation.

Here, as one embodiment of realizing the bias switching operation, a technique using a bias T circuit as a driver circuit is known. As a bias T circuit used in a conventional driver circuit, one that is generally composed of a series capacitor that blocks the DC component of the driver circuit and an element that applies an output bias is known (for example, Patent Document 1 ).

As in the bias T circuit of Patent Document 1, an inductor is generally used as an element that applies an output bias. On the other hand, if an inductor is used in the bias T circuit, a large inductance value is required to avoid loss in the low frequency band. Therefore, the size of the inductor increases, and the area occupied by the bias T circuit in the substrate area increases. As a conventional bias T circuit, a configuration is known in which a resistor is used instead of an inductor in order to avoid an increase in the area occupied by the bias T circuit (for example, Patent Document 2).

JP2018-191222A Japanese Patent Application Publication No. 2007-241142

Here, the response time when switching the bias voltage depends on the time constant of the bias T circuit. Therefore, in order to perform a high-speed bias switching operation, it is required to reduce the resistance value of the resistor used in the bias T circuit and the capacitance of the capacitor. On the other hand, in order to apply an appropriate bias, it is necessary to use a resistor having a certain resistance value in the bias T circuit. Furthermore, in order to block the direct current component of the front-stage circuit, it is required to use a capacitor with a certain amount of capacitance in the bias T circuit. Therefore, with the bias T circuit used in the conventional driver circuit, it is difficult to prevent loss in the low frequency band, cut off the direct current component of the front stage circuit, and perform a high-speed bias switching operation.

A driver circuit that achieves the above object includes an optical switch device that converts an optical signal transmitted and received in an optical communication network that connects a plurality of control devices in a ring according to an electrical signal transmitted and received in the control device; a driver circuit provided in a telecommunications network that connects the optical switch device to the optical switch device; and a second line connecting a second terminal of the optical switch device and a second terminal of the control device, and the driver circuit includes a driver section, a normal bias T circuit section, and a burst mode It has a bias T circuit section, the driver section amplifies the electrical signal transmitted by the control device, and the burst mode bias T circuit section is more responsive to bias switching operation than the normal bias T circuit section. The time constant is small.

According to this configuration, the driver circuit can perform a high-speed bias switching operation while applying an appropriate bias.
In the driver circuit, the line of the telecommunications network includes a first line connecting a first terminal of the optical switch device and a first terminal of the control device, and a second terminal of the optical switch device; a second line connecting the second terminal of the control device, and the normal bias T circuit section includes a first capacitor provided on the first line, and one end connected to the first line. , a first resistor to which the control voltage signal is applied to the other end, a second capacitor provided on the second line, one end connected to the second line, and the other end to which the control voltage signal is applied. the burst mode bias T circuit section includes a first transistor and a second transistor connected in series between a first power source and a second power source. , and includes a third transistor and a fourth transistor connected in series between the first power source and the second power source, and a connection point between the first transistor and the second transistor is , is connected to the first line, a connection point between the third transistor and the fourth transistor is connected to the second line, and in the first state, the first transistor, the second transistor The transistor, the third transistor, and the fourth transistor are controlled to be in an off state, and in the second state, the first transistor and the fourth transistor are controlled to be in an on state, and the second transistor and the fourth transistor are controlled to be in an on state. 3 transistors are controlled to be off, and in the third state, the first transistor and the fourth transistor are controlled to be off, and the second transistor and the third transistor are controlled to be on. good.

According to this configuration, the driver circuit can perform high-speed bias switching operation while applying an appropriate bias, preventing loss in a low frequency band, and blocking direct current components to the optical switch device.

An optical switch system that achieves the above object includes an optical switch device that converts an optical signal transmitted and received in an optical communication network that connects a plurality of control devices in a ring according to an electrical signal that is transmitted and received in the control device; A driver circuit provided in a telecommunications network connecting a switch device and the control device, comprising the driver circuit.

According to this configuration, the optical switch system can obtain the same effects as the above driver circuit.
A communication network that achieves the above object includes a plurality of control devices, an optical communication network that connects the plurality of control devices in a ring, and an optical signal transmitted and received in the optical communication network and an electrical signal transmitted and received in the control device. A driver circuit provided in a telecommunications network that connects the optical switch device and the control device, the driver circuit being provided.

According to this configuration, the communication network can obtain the same effects as the driver circuit described above.

According to the present invention, a high-speed bias switching operation can be performed while applying an appropriate bias.

FIG. 1 is a diagram showing an example of a network configuration. 5 is a timing chart showing an example of operation in each state. FIG. 3 is a diagram showing an example of the configuration of a driver circuit. FIG. 3 is a diagram used to explain the operation of the driver circuit in the first state. FIG. 7 is a diagram used to explain the operation of the driver circuit in a second state. FIG. 7 is a diagram used to explain the operation of the driver circuit in a third state. FIG. 6 is a diagram showing an example of the operation of the driver circuit in each state. FIG. 3 is a diagram illustrating an example of a comparison result between the driver circuit of this embodiment and a conventional driver circuit.

<Embodiment>
[overall structure]
Hereinafter, embodiments embodying a bias T circuit will be described with reference to the drawings. As shown in FIG. 1, the network 1 includes a first control device 10, a plurality of second control devices 20, and a number of optical switch devices 30 corresponding to the number of second control devices 20. The first control device 10 is, for example, a main control device that instructs each second control device 20 to perform various operations, and the second control device 20, for example, This is a sub-control device that executes various operations. The optical communication network L1 connects the first control device 10 and the second control device 20 in a ring. Specifically, the optical communication network L1 connects the first control device 10 and the optical switch device 30. The second control device 20 and the optical switch device 30 are each connected by a corresponding telecommunications network L2. Information is transmitted and received between the optical communication network L1 and the telecommunication network L2 using, for example, a communication protocol such as CAN (Controller Area Network) communication.

In the following description, the network 1 includes three second control devices 20-1, 20-2, and 20-3, and optical switch devices 30-1, 30-2, and 30-3. A case in which three optical switch devices 30 are provided will be described. The second control device 20-1 and the optical switch device 30-1 are communicably connected via the telecommunications network L2-1. The second control device 20-2 and the optical switch device 30-2 are communicably connected via a telecommunications network L2-2. The second control device 20-3 and the optical switch device 30-3 are communicably connected via a telecommunications network L2-3. The telecommunications networks L2-1, L2-2, and L2-3 are, for example, two-wire systems that transmit data depending on the presence or absence of a voltage difference between the two communication lines, the first line LN1 and the second line LN2. Information is transmitted and received using a differential voltage method.

Furthermore, the telecommunications network L2-1 is provided with a driver circuit 100-1, the telecommunications network L2-2 is provided with a driver circuit 100-2, and the telecommunications network L2-3 is provided with a driver circuit 100-1. -3 is provided. Details of the configuration of driver circuits 100-1, 100-2, and 100-3 will be described later.

In the following description, if the second control devices 20-1, 20-2, and 20-3 are not distinguished from each other, they will simply be referred to as the second control device 20. When the optical switch devices 30-1, 30-2, and 30-3 are not distinguished from each other, they are simply referred to as an optical switch device 30. When the telecommunications networks L2-1, L2-2, and L2-3 are not distinguished from each other, they are simply referred to as telecommunications network L2. When driver circuits 100-1, 100-2, and 100-3 are not distinguished from each other, they are simply referred to as driver circuit 100. Further, the second control device 20 that is directly connected to the optical switch device 30 via the telecommunications network L2 will also be referred to as “the second control device 20 corresponding to the optical switch device 30.” Specifically, the second control device 20 corresponding to the optical switch device 30-1 is the second control device 20-1. The second control device 20 corresponding to the optical switch device 30-2 is the second control device 20-2. The second control device 20 corresponding to the optical switch device 30-3 is the second control device 20-3.

[About optical communication network L1 and telecommunications network L2]
The first control device 10 performs timing control of communication in the optical communication network L1 and communication in the telecommunication network L2 using synchronization control signals for communication related to the optical communication network L1 and the telecommunication network L2. The first control device 10 transmits various information from the transmission terminal Tx via the optical communication network L1. The first control device 10 also receives various information from the reception terminal Rx via the optical communication network L1.

[About the operation of the optical switch device 30]
The optical switch device 30 is a device that converts an optical signal transmitted and received in the optical communication network L1 according to an electrical signal transmitted and received in the second control device 20 based on the timing control of the first control device 10. The operation of the optical switch device 30 transits to three states, a first state, a second state, and a third state, depending on communication between the first control device 10 and the second control device 20. The details of when the operation of the optical switch device 30 transitions to the first state, the second state, and the third state will be described later. The details of the operation of the optical switch device 30 in FIG.

The first state is a state in which information is transmitted from the second control device 20 to the first control device 10 or another second control device 20. In the first state, the optical switch device 30 converts the electrical signal received from the corresponding second control device 20 via the telecommunications network L2 into an optical signal, and then transmits the converted optical signal via the optical communication network L1. and transmits it to the first control device 10 or another second control device 20. The second state is a state in which the second control device 20 receives information transmitted by the first control device 10 or another second control device 20. In the second state, the optical switch device 30 receives an optical signal received from the first control device 10 or another second control device 20 via the optical communication network L1. The third state is a state in which the optical switch device 30 transmits the optical signal received via the optical communication network L1 as it is to the optical switch device 30 or the first control device 10 downstream of the optical communication network L1. In the following description, transmitting the information received by the optical switch device 30 as it is to the downstream optical switch device 30 or the first control device 10 is also referred to as "passing the optical signal." That is, the third state is a state in which the optical switch device 30 passes the optical signal.

[About optical signals and electrical signals in each state]
Hereinafter, using communication between the first control device 10 and the second control device 20-2 as an example, optical signals transmitted and received by the optical switch device 30-2 and electrical signals received by the optical switch device 30-2 will be explained. The details will be explained below. A waveform W12 shown in FIG. 2 is a waveform showing an example of an optical signal that the optical switch device 30-2 receives via the optical communication network L1. Waveform W13 is a waveform that represents an example of an optical signal received by optical switch device 30-2. The waveform W14 is a waveform that represents an example of an optical signal that the optical switch device 30 transmits via the optical communication network L1. In the graphs of waveforms W12 to W14, the horizontal axis indicates time, and the vertical axis indicates the presence or absence of an optical signal. The waveform W11 is a waveform showing an example of the potential difference that occurs between the lines of the telecommunications network L2-2 that realizes three states. In the graph of waveform W11, the horizontal axis indicates time, and the vertical axis indicates the magnitude of voltage.

In FIG. 2, the operation of the optical switch device 30 is such that it transitions to the first state from time t11 to t12, transitions to the second state from time t13 to t14, and transitions to the second state from time t15 to t16. Transition to the third state. As shown by the waveform W12, during the first state, the optical switch device 30-2 receives a continuous light optical signal that instructs the transmission timing of the second control device 20-2 from the first control device 10. As shown by the waveform W11, the optical switch device 30-2 receives an electrical signal indicating a data frame from the second control device 20 during the first state. As shown by the waveform W14, during the first state, the optical switch device 30-2 converts the received electrical signal into an optical signal, modulates the continuous optical signal with the converted optical signal, and performs optical communication. Send to network L1.

As shown by the waveform W12, the optical switch device 30-2 receives the optical signal transmitted from the second control device 20 other than the first control device 10 or the second control device 20-2 during the second state. do. As waveform W11 shows, during the second state, the telecommunications network L2 is forward biased by the bias switching operation. The forward bias state means that, of the first line LN1 and the second line LN2 that realize the telecommunications network L2, a potential of 0 [V] is applied to the second line LN2, and the first line LN1 is This is a state in which a potential higher than 0 [V] is applied. As shown by waveform W13, optical switch device 30-2 receives the optical signal when telecommunications network L2 is placed in a forward bias condition.

As shown by the waveform W12, the optical switch device 30-2 receives the optical signal transmitted to the second control device 20 other than the second control device 20-2 during the third state. As waveform W11 shows, during the third state, the telecommunications network L2 is brought into a reverse biased state by the bias switching operation. The reverse bias state means that, of the first line LN1 and the second line LN2 that realize the telecommunications network L2, 0 [V] potential is applied to the first line LN1, and the second line LN2 is This is a state in which a potential higher than 0 [V] is applied. As shown by the waveform W13, the optical switch device 30-2 passes the received optical signal during the third state. Therefore, as shown by waveform W14, optical switch device 30-2 passes the received optical signal when telecommunications network L2 is controlled to the reverse bias state. In other words, the optical switch device 30-2 directly transmits the received optical signal to the other second control device 20 and first control device 10 that are located downstream of the optical communication network L1.

[About high-speed bias switching operation]
Here, the optical signals transmitted and received in the optical communication network L1 are realized by burst signals including data frames addressed to each optical switch device 30 and guard times provided between the data frames. The data frame includes a preamble section and a payload section in which information is stored. The preamble section includes an arbitrary bit pattern used to prepare the optical switch device 30 for transmission/reception operations. In order to reliably receive the information stored in the payload section provided next to the preamble section from the first bit, the optical switch device 30 is required to complete preparations for transmitting and receiving operations in the preamble section. . The preparation for the transmission/reception operation is, for example, a bias switching operation of the telecommunications network L2.

If the driver circuit 100 cannot perform the bias switching operation of the telecommunications network L2 at high speed and the preparation for the transmission/reception operation takes place during the payload section, the information stored in the payload section cannot be received or passed. Therefore, the driver circuit 100 is required to perform a high-speed bias switching operation so that preparations for transmitting and receiving operations are completed in the telecommunications network L2. The configuration of the driver circuit 100 that realizes high-speed bias switching operation will be described below.

[About the configuration of the driver circuit 100]
As shown in FIG. 3, the driver circuit 100 is provided between a first line LN1 and a second line LN2 realizing a telecommunications network L2. The first line LN1 connects the first terminal P11 of the second control device 20 and the first terminal P21 of the optical switch device 30, and the second line LN2 connects the second terminal P12 of the second control device 20, It is connected to the second terminal P22 of the optical switch device 30.

The driver circuit 100 includes, for example, a driver section 101, a normal bias T circuit section 102, and a burst mode bias T circuit section 103. The driver unit 101 amplifies the electrical signal received from the second control device 20 to an amplitude that can drive the optical switch device 30. The normal bias T circuit section 102 includes, for example, a first capacitor C1, a second capacitor C2, a first resistor R1, and a second resistor R2. The first capacitor C1 is provided on the first line LN1. A second capacitor C2 is provided on the second line LN2. One end of the first resistor R1 is connected to the first line LN1, and a control voltage signal S2 related to timing control of the first control device 10 is applied to the other end. The control voltage signal S2 is a control signal related to timing control of the first control device 10. One end of the second resistor R2 is connected to the second line LN2, and the control voltage signal S2 is applied to the other end. Hereinafter, it is assumed that the first resistor R1 and the second resistor R2 have the same resistance value, and the first capacitor C1 and the second capacitor C2 have the same capacitance.

The first resistor R1 and the second resistor R2 apply a bias to the first line LN1 and the second line LN2 when the high-level control voltage signal S2 is applied. Further, the first capacitor C1 and the second capacitor C2 block direct current components from the optical switch device 30. That is, the first capacitor C1 and the second capacitor C2 suppress the application of high potential DC voltage to the first terminal P21 and the second terminal P22 of the optical switch device 30. The control voltage signal S2 is, for example, a high level signal.

The burst mode bias T circuit section 103 includes, for example, a first transistor Q1, a second transistor Q2, a third transistor Q3, and a fourth transistor Q4. The first transistor Q1 and the third transistor Q3 are realized by, for example, a P-type MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor), and the second transistor Q2 and the fourth transistor Q4 are realized by, for example, an N-type MOSFET. Realized. In the following description, for example, if the first transistor Q1, the second transistor Q2, the third transistor Q3, and the fourth transistor Q4 are not to be distinguished from each other, they will simply be referred to as a transistor Q.

The first transistor Q1 and the second transistor Q2 are connected in series between a first power source that outputs a drain voltage VDD and a second power source that outputs a source voltage VSS. Further, the third transistor Q3 and the fourth transistor Q4 are connected in series between a first power source that outputs the drain voltage VDD and a second power source that outputs the source voltage VSS. Specifically, the drain voltage VDD is applied to the drain terminal of the first transistor Q1 and the drain terminal of the third transistor Q3. A source voltage VSS is applied to the source terminal of the second transistor Q2 and the source terminal of the fourth transistor Q4.

A connection point between the first transistor Q1 and the second transistor Q2 is connected to the first line LN1. Further, a connection point between the third transistor Q3 and the fourth transistor Q4 is connected to the second line LN2.

A control voltage signal S3 related to timing control of the first control device 10 is input to the gate terminal of the first transistor Q1 via an inverting circuit N1. A control voltage signal S3 is input to the gate terminal of the fourth transistor Q4. A control voltage signal S4 related to timing control of the first control device 10 is input to the gate terminal of the second transistor Q2. A control voltage signal S4 is input to the gate terminal of the third transistor Q3 via an inverting circuit N2.

Here, when the P-type MOSFET (that is, the first transistor Q1 and the third transistor Q3) and the N-type MOSFET (that is, the second transistor Q2 and the fourth transistor Q4) are controlled to be in the on state, The voltage applied to the gate terminal is different. Specifically, the P-type MOSFET is controlled to be in an off state when a predetermined voltage is applied to its gate terminal, and is controlled to be in an on state when a predetermined voltage is not applied to its gate terminal. On the other hand, the N-type MOSFET is controlled to be in an off state when a predetermined voltage is not applied to its gate terminal, and is controlled to be in an on state when a predetermined voltage is applied to its gate terminal. The predetermined voltage is, for example, the voltage required to turn the P-type MOSFET into the off state (i.e., off-state voltage), and the voltage required to turn the N-type MOSFET into the on-state (i.e., on-state voltage). .

Therefore, when the control voltage signal S3 is a signal lower than a predetermined voltage, the first transistor Q1 and the fourth transistor Q4 are controlled to be in an off state. Hereinafter, a voltage lower than a predetermined voltage will also be referred to as a "low level." When the control voltage signal S3 is a high-level signal equal to or higher than a predetermined voltage, the first transistor Q1 and the fourth transistor Q4 are controlled to be in an on state. Hereinafter, a voltage equal to or higher than a predetermined voltage will also be referred to as a "high level." When the control voltage signal S4 is a low level signal, the second transistor Q2 and the third transistor Q3 are controlled to be in an off state. When the control voltage signal S4 is a high level signal, the second transistor Q2 and the third transistor Q3 are controlled to be in an on state.

[About transition to the first state, second state, and third state]
Hereinafter, with reference to FIGS. 4 to 6, the transition of the optical switch device 30 and the driver circuit 100 to the first state, second state, and third state, and details of the operation of the driver circuit 100 in each state will be explained. do.

As shown in FIG. 4, the first state means that the control signal S1 that controls the driver section 101 to be in the on state is input, the high-level control voltage signal S2 is applied to the normal bias T circuit section 102, and the burst mode is set. This is a state in which a low-level control voltage signal S3 and a low-level control voltage signal S4 are input to the bias T circuit section 103. In the normal bias T circuit unit 102, in the first state, the first resistor R1 and the second resistor R2 are connected to the first line LN1 and the second line LN2 by applying a high-level control voltage signal S2. Apply bias. Furthermore, in the first state, the low-level control voltage signal S3 and the low-level control voltage signal S4 are input to the burst mode bias T circuit unit 103, so that the transistor Q is controlled to be in the off state. be done. Therefore, in the first state, the first transistor Q1, the second transistor Q2, the third transistor Q3, and the fourth transistor Q4 operate as high resistance elements. In this case, the electrical signal transmitted by the second control device 20 passes through the driver section 101 and the driver circuit 100, and is applied to the first terminal P11 and the second terminal P12 of the optical switch device 30. The optical switch device 30 modulates the continuous light optical signal transmitted by the first control device 10 based on the applied electrical signal.

In the first state, when a bias is applied to the first line LN1 and the second line LN2 by the normal bias T circuit section 102, the response time at bias switching is determined by the time constant τ of the normal bias T circuit section 102. Dependent. Specifically, the time constant τ is expressed by the following equation (1).

τ=RC[sec]…(1)
τ: Time constant R: Resistance value of the first resistor R1 or second resistor R2 C: Capacitance of the first capacitor C1 or second capacitor C2 As shown in FIG. 5, the second state refers to the driver section 101 is inputted, a low level control voltage signal S2 is applied to the normal bias T circuit section 102, and a high level control voltage signal S3 is applied to the burst mode bias T circuit section 103. This is the state in which the low-bell control voltage signal S4 is input. In the normal bias T circuit unit 102, in the second state, the first resistor R1 and the second resistor R2 are connected to the first line LN1 and the second line LN2 by applying the low-level control voltage signal S2. No bias applied. Furthermore, the burst mode bias T circuit section 103 receives a high level control voltage signal S3 and a low level control voltage signal S4 in the second state. Therefore, the first transistor Q1 and the fourth transistor Q4 are controlled to be in the on state, and the second transistor Q2 and the third transistor Q3 are controlled to be in the off state. As a result, the drain voltage VDD is applied to the first terminal P21 of the optical switch device 30, and the source voltage VSS is applied to the second terminal P22. Therefore, a forward bias voltage is applied between the first terminal P21 and the second terminal P22 of the optical switch device 30, and the optical switch device 30 operates in the second state.

Here, the resistance value between the source and drain of the transistor Q becomes sufficiently low in the on state. Hereinafter, the resistance value between the source and the drain when the transistor Q is controlled to be in the on state will be referred to as on-resistance Ron. Further, hereinafter, it is assumed that the on-resistances Ron of the first transistor Q1, the second transistor Q2, the third transistor Q3, and the fourth transistor Q4 have the same resistance value. In the second state, the combined resistance Rg of the burst mode bias T circuit section 103 is expressed by the following equation (2), and the time constant τ in the second state is expressed by the following equation (3).

Rg=Ron/(Ron+R) [Ω]…(2)
τ=CR(Ron/(Ron+R))[sec]...(3)
Rg: Combined resistance of the burst mode bias T circuit section 103 in the second state Ron: On-resistance of the first transistor Q1 or fourth transistor Q4 τ: Time constant R: Resistance value of the first resistor R1 or second resistor R2 C: Capacitance of the first capacitor C1 or the second capacitor C2 The on-resistance Ron is a resistance value that is sufficiently smaller than the resistance value R of the first resistor R1 or the second resistor R2. Therefore, in the second state, the time constant τ can be made smaller by Ron/(Ron+R) compared to the case where the driver circuit 100 includes only the driver section 101 and the normal bias T circuit section 102. Therefore, in the second state, the driver circuit 100 can realize a high-speed bias switching operation. In addition, since the input impedance of the normal bias T circuit section 102 and the burst mode bias T circuit section 103 seen from the driver section 101 can be lowered, the signal output from the driver section 101 is transmitted to the first terminal P21 and the second terminal P21. It is attenuated at terminal P22. Thereby, the optical switch device 30 realizes a receiving operation.

As shown in FIG. 6, the third state means that the control signal S1 that controls the driver section 101 to the off state is input, the low level control voltage signal S2 is applied to the normal bias T circuit section 102, and the burst mode is set. This is a state in which a low-level control voltage signal S3 and a high-level control voltage signal S4 are input to the bias T circuit section 103. In the normal bias T circuit unit 102, in the third state, the first resistor R1 and the second resistor R2 are connected to the first line LN1 and the second line LN2 by applying the low-level control voltage signal S2. No bias applied. Furthermore, the burst mode bias T circuit section 103 receives a low level control voltage signal S3 and a high level control voltage signal S4 in the third state. Therefore, the first transistor Q1 and the fourth transistor Q4 are controlled to be in the off state, and the second transistor Q2 and the third transistor Q3 are controlled to be in the on state. As a result, the source voltage VSS is applied to the first terminal P21 of the optical switch device 30, and the drain voltage VDD is applied to the second terminal P22. Therefore, a reverse bias voltage is applied between the first terminal P21 and the second terminal P22 of the optical switch device 30, and the optical switch device 30 operates in the third state. In the third state, the combined resistance Rg of the burst mode bias T circuit unit 103 is the same as the combined resistance Rg in the second state, and the time constant τ in the third state is the same as the time constant τ in the second state. .

Therefore, in the third state, the time constant τ can be made smaller by Ron/(Ron+R) compared to the case where the driver circuit 100 includes only the driver section 101 and the normal bias T circuit section 102. Therefore, in the third state, a high-speed bias switching operation can be realized similarly to the second state. In addition, since the input impedance of the normal bias T circuit section 102 and the burst mode bias T circuit section 103 seen from the driver section 101 can be lowered, the signal output from the driver section 101 is transmitted to the first terminal P21 and the second terminal P21. It is attenuated at terminal P22. Thereby, the optical switch device 30 can pass the optical signal.

[About the operation of the driver circuit 100]
The details of the operation of the driver circuit 100 of this embodiment will be described below with reference to FIG. 7. A waveform W21 shown in FIG. 7 is a waveform showing an example of an electric signal applied to the first terminal P11 and the second terminal P12 of the second control device 20. Waveform W22 is a waveform showing an example of control signal S1. Waveform W23 is a waveform showing an example of control voltage signal S3. Waveform W24 is a waveform showing an example of control voltage signal S4. Waveform W25 is a waveform that represents an example of an electrical signal input to optical switch device 30 from telecommunications network L2. In the graphs of waveforms W21 to W25, the horizontal axis represents time, and the vertical axis represents the magnitude of voltage.

The operation of the optical switch device 30 and the operation of the driver circuit 100 are transitioned to the first state for about 0.1 to about 0.4 [μsec]. This is because, as shown by the waveform W22, the high-level control signal S1 is input to the driver section 101 for about 0.1 to about 0.4 [μsec]. As a result, as shown by the waveform W25, the electrical signal transmitted by the second control device 20 appears in the telecommunications network L2 for about 0.1 to about 0.4 [μsec]. Further, as shown by the waveform W23 and the waveform W24, during the first state, the low-level control voltage signal S3 and the low-level control voltage signal S4 are input to the burst mode bias T circuit unit 103. Therefore, the first transistor Q1, the second transistor Q2, the third transistor Q3, and the fourth transistor Q4 are all controlled to be in the off state.

The operation of the optical switch device 30 and the operation of the driver circuit 100 are transitioned to the second state for about 0.6 to about 0.7 [μsec]. Specifically, as shown by waveforms W23 to W24, a high level control voltage signal S3 and a low level control voltage signal S4 are input to the driver circuit 100. As a result, the drain voltage VDD is applied to the first terminal P21 of the optical switch device 30, and the source voltage VSS is applied to the second terminal P22. Therefore, a forward bias voltage is applied to the first terminal P21 and the second terminal P22 of the optical switch device 30, and the operation of the optical switch device 30 is transitioned to the second state. As described above, in the second state, as the combined resistance Rg of the burst mode bias T circuit section 103 becomes smaller, the time constant τ becomes smaller. Therefore, in the second state, the driver circuit 100 can realize a high-speed bias switching operation. Specifically, as shown by the waveform W25, the driver circuit 100 can make the rise associated with the bias switching operation at about 0.6 [μsec] steep.

The operation of the optical switch device 30 and the operation of the driver circuit 100 are transited to the third state for about 1.1 to about 1.4 [μsec]. Specifically, as shown by waveforms W23 to W24, a low level control voltage signal S3 and a high level control voltage signal S4 are input to the driver circuit 100. As a result, the source voltage VSS is applied to the first terminal P21 of the optical switch device 30, and the drain voltage VDD is applied to the second terminal P22. Therefore, a reverse bias voltage is applied to the first terminal P21 and the second terminal P22 of the optical switch device 30, and the operation of the optical switch device 30 is transitioned to the third state. As described above, in the third state, as the combined resistance Rg of the burst mode bias T circuit section 103 becomes smaller, the time constant τ becomes smaller. Therefore, in the third state, the driver circuit 100 can realize a high-speed bias switching operation. Specifically, as shown by the waveform W25, the driver circuit 100 can make the fall associated with the bias switching operation at approximately 1.1 [μsec] steeper.

[Results of comparison between driver circuit 100 and conventional driver circuit]
Hereinafter, with reference to FIG. 8, a comparison result between the driver circuit 100 of this embodiment and a conventional driver circuit will be described. The conventional driver circuit is, for example, a circuit of the driver circuit 100 that includes only the driver section 101 and the normal bias T circuit section 102 and does not include the burst mode bias T circuit section 103. A waveform W31 in FIG. 8 is a waveform representing an example of an electrical signal input from the telecommunications network L2 to the optical switch device 30 in the driver circuit 100. Waveform W32 is a waveform that represents an example of an electrical signal input from telecommunications network L2 to optical switch device 30 in a conventional driver circuit.

As shown by the waveform W31, in the driver circuit 100 of this embodiment, the bias is applied to the first line LN1 and the second line LN2 without delay in approximately 0.6 [μsec] with the bias switching operation, and the bias is applied sharply to the first line LN1 and the second line LN2. The waveform is rising. On the other hand, as waveform W32 shows, in the conventional driver circuit, the bias was applied at about 0.6 [μsec] due to the bias switching operation, and although the waveform started to rise, it did not appear that the bias was properly applied. However, it is approximately 0.75 [μsec]. Therefore, the driver circuit 100 of this embodiment can reduce the response time by about 90% compared to the conventional driver circuit, and can realize high-speed bias switching operation.

[Effects of embodiment]
According to the above embodiment, the following effects can be obtained.
(1) The driver circuit 100 converts optical signals transmitted and received in the optical communication network L1 that connects the first control device 10 and a plurality of second control devices 20 in a ring to electrical signals transmitted and received in the second control device 20. A driver circuit 100 provided in a telecommunications network L2 that connects an optical switch device 30 that converts according to a signal and a second control device 20, and a driver circuit 100 provided in a telecommunications network L2 that connects an optical switch device 30 that converts according to a signal and a second control device 20. The first line LN1 connects the first terminal P21 and the first terminal P11 of the second control device 20, and the second terminal P22 of the optical switch device 30 and the second terminal P12 of the second control device 20 are connected. The driver circuit 100 includes a driver section 101, a normal bias T circuit section 102, and a burst mode bias T circuit section 103. The burst mode bias T circuit unit 103 that amplifies the electrical signal to be transmitted has a smaller time constant τ related to bias switching operation than the normal bias T circuit unit 102.

According to this configuration, the driver circuit 100 can reduce the time constant τ compared to conventional driver circuits while applying an appropriate bias. Therefore, the driver circuit 100 can perform a high-speed bias switching operation while applying an appropriate bias.

(2) In the driver circuit 100, the line of the telecommunications network L2 includes a first line LN1 connecting the first terminal P21 of the optical switch device 30 and the first terminal P11 of the second control device 20, and the optical switch A second line LN2 connecting the second terminal P22 of the device 30 and the second terminal P12 of the second control device 20 is included. The normal bias T circuit unit 102 includes a first capacitor C1 provided on the first line LN1, and a first resistor R1 whose one end is connected to the first line LN1 and whose other end is applied with a control voltage signal S2. , a second capacitor C2 provided on the second line LN2, and a second resistor R2, one end of which is connected to the second line LN2, and the other end of which is applied a control voltage signal S2. The burst mode bias T circuit section 103 includes a first transistor Q1 and a second transistor Q2 connected in series between a first power source that outputs a drain voltage VDD and a second power source that outputs a source voltage VSS. and a third transistor Q3 and a fourth transistor Q4 connected in series between a first power source that outputs a drain voltage VDD and a second power source that outputs a source voltage VSS. A connection point between the first transistor Q1 and the second transistor Q2 is connected to the first line LN1. A connection point between the third transistor Q3 and the fourth transistor Q4 is connected to the second line LN2. In the first state, the first transistor Q1, the second transistor Q2, the third transistor Q3, and the fourth transistor Q4 are controlled to be in the off state. In the second state, the first transistor Q1 and the fourth transistor Q4 are controlled to be in the on state, and the second transistor Q2 and the third transistor Q3 are controlled to be in the off state. In the third state, the first transistor Q1 and the fourth transistor Q4 are controlled to be in the off state, and the second transistor Q2 and the third transistor Q3 are controlled to be in the on state.

According to this configuration, the driver circuit 100 uses the first resistor R1, the second resistor R2, the first capacitor C1, and the second capacitor C2 included in the normal bias T circuit section 102 to prevent loss in the low frequency band. , it is possible to cut off the DC component to the optical switch device 30. Further, the driver circuit 100 applies an appropriate bias using the first resistor R1 and the second resistor R2 included in the normal bias T circuit section 102 and the burst mode bias T circuit section 103, while applying a suitable bias to the conventional driver circuit. In comparison, the time constant τ can be made smaller. Therefore, the driver circuit 100 can perform a high-speed bias switching operation while applying an appropriate bias, preventing loss in a low frequency band, and cutting off a DC component to the optical switch device 30.

Further, the driver circuit 100 uses a first resistor R1 and a second resistor R2 instead of an inductor as elements for applying an appropriate bias. For this reason, the driver circuit 100 can reduce the area occupied by the driver circuit 100 on the board area and can be made smaller than when an inductor is used.

Each of the above embodiments may be modified as follows. Note that the above embodiment and each of the following separate examples may be combined with each other within a technically consistent range.
〇In the above description, a case has been described in which the first transistor Q1 and the third transistor Q3 are realized by P-type MOSFETs, and the second transistor Q2 and the fourth transistor Q4 are realized by N-type MOSFETs. Not limited. The first transistor Q1 and the third transistor Q3 may be realized by a PNP type bipolar transistor, and the second transistor Q2 and the fourth transistor Q4 may be realized by an NPN type bipolar transistor. In this case, in the above description, the drain terminal may be replaced with the collector terminal, the gate terminal may be replaced with the base terminal, and the source terminal may be replaced with the emitter terminal. Further, the first power supply outputs a collector voltage instead of the drain voltage VDD, and the second power supply outputs an emitter voltage instead of the source voltage VSS. Further, the predetermined voltage is, for example, a voltage applied to the base terminal to turn the PNP type bipolar transistor into the off state, and a voltage applied to the base terminal to turn the NPN type bipolar transistor into the on state.

The number of second control devices 20 provided in the network 1 is not limited to three, and may be one or two, or may be more than three.
In the above description, a case has been described in which the first control device 10 controls the timing of communication in the optical communication network L1 and communication in the telecommunication network L2, but the present invention is not limited to this. Instead of (or in addition to) the first control device 10, the network 1 may include another device that controls the timing of communication in the optical communication network L1 and communication in the telecommunications network L2. In this case, the other device outputs the synchronization control signal, the control signal S1, the control voltage signal S2, the control voltage signal S3, and the control voltage signal S4 to each part of the network 1.

In the above description, a case has been described in which the driver circuit 100 is applied to the network 1 including the optical communication network L1 and the telecommunications network L2, but the present invention is not limited to this. The driver circuit 100 can be applied to any network as long as it includes an optical communication network L1 and a telecommunications network L2. For example, the network 1 may be used in an in-vehicle network that connects in-vehicle devices. In this case, the first control device 10 and the second control device 20 are realized by, for example, an ECU (Electronic Control Unit). Specifically, the first control device 10 is, for example, a main ECU, and the second control device 20 is, for example, a sub-ECU that controls each part of the vehicle.

Next, technical ideas that can be understood from the above embodiment and other examples will be additionally described below.
(B) In the driver circuit, the first transistor and the third transistor are realized by a P-type MOSFET, the second transistor and the fourth transistor are realized by an N-type MOSFET, and the first transistor and the third transistor are realized by an N-type MOSFET, and The voltage of the second power source is the drain voltage, and the voltage of the second power source is the source voltage.

(b) In the driver circuit, the first transistor and the third transistor are realized by PNP bipolar transistors, the second transistor and the fourth transistor are realized by NPN bipolar transistors, and the first transistor and the third transistor are realized by NPN bipolar transistors. The voltage of the first power supply is a collector voltage, and the voltage of the second power supply is an emitter voltage.

1... Network, 10... First control device, 20, 20-1, 20-2, 20-3... Second control device, 30, 30-1, 30-2, 30-3... Optical switch device, 100, 100-1, 100-2, 100-3...driver circuit, 101...driver section, 102...normal bias T circuit section, 103...burst mode bias T circuit section, C1...first capacitor, C2...second capacitor, L1 ...Optical communication network, L2, L2-1, L2-2, L2-3... Telecommunication network, LN1... First line, LN2... Second line, N1, N2... Inversion circuit, P11, P21... First terminal, P12, P22...second terminal, Q...transistor, Q1...first transistor, Q2...second transistor, Q3...third transistor, Q4...fourth transistor, R1...first resistor, R2...second resistor, S1... Control signals, S2, S3, S4... control voltage signals.

Claims (4)

An optical switch device that converts optical signals sent and received in an optical communication network that connects a plurality of control devices in a ring according to electrical signals that are sent and received in the control device, and a telecommunications network that connects the control device. A driver circuit provided,
The line of the telecommunications network includes a first line connecting a first terminal of the optical switch device and a first terminal of the control device, a second line of the optical switch device, and a first line of the control device. a second line connecting the two terminals;
The driver circuit includes a driver section, a normal bias T circuit section, and a burst mode bias T circuit section,
The driver section amplifies the electrical signal transmitted by the control device,
The burst mode bias T circuit section has a smaller time constant for bias switching operation than the normal bias T circuit section.
A driver circuit characterized by: The line of the telecommunications network includes a first line connecting a first terminal of the optical switch device and a first terminal of the control device, a second line of the optical switch device, and a first line of the control device. a second line connecting the two terminals;
The normal bias T circuit section includes a first capacitor provided on the first line, a first resistor having one end connected to the first line and a control voltage signal applied to the other end, and the first resistor having one end connected to the first line and a control voltage signal applied to the other end. a second capacitor provided on two lines; and a second resistor, one end of which is connected to the second line, and the other end of which the control voltage signal is applied;
The burst mode bias T circuit section includes a first transistor and a second transistor connected in series between a first power source and a second power source, and has a first transistor and a second transistor connected in series between the first power source and the second power source. a third transistor and a fourth transistor connected in series between the power source and the power source;
A connection point between the first transistor and the second transistor is connected to the first line,
A connection point between the third transistor and the fourth transistor is connected to the second line,
In the first state, the first transistor, the second transistor, the third transistor, and the fourth transistor are controlled to be in an off state,
In the second state, the first transistor and the fourth transistor are controlled to be on, and the second transistor and the third transistor are controlled to be off,
In a third state, the first transistor and the fourth transistor are controlled to be off, and the second transistor and the third transistor are controlled to be on.
The driver circuit according to claim 1. an optical switch device that converts optical signals transmitted and received in an optical communication network that connects a plurality of control devices in a ring according to electrical signals transmitted and received in the control device;
A driver circuit provided in a telecommunications network connecting the optical switch device and the control device, comprising the driver circuit according to claim 1 or 2.
An optical switch system characterized by: a plurality of control devices;
an optical communication network that connects the plurality of control devices in a ring;
an optical switch device that converts optical signals transmitted and received in the optical communication network according to electrical signals transmitted and received in the control device;
A driver circuit provided in a telecommunications network connecting the optical switch device and the control device, comprising the driver circuit according to claim 1 or 2.
A communication network characterized by:

Images