JP2023120945A - Δς modulator and δς a/d converter - Google Patents

Abstract

To provide a ΔΣ modulator capable of operating independent of common voltage of input voltage.SOLUTION: An input sampling circuit 110 is used in a ΔΣ modulator that converts a differential input signal VIN to a digital output signal and samples the differential input signal VIN. The input sampling circuit 110 is a switched-capacitor circuit and includes a first capacitor C1 and a second capacitor C2. A fifth switch SW5 is connected between a connection node of a third switch SW3 and a second capacitor C2 and a first input node IN1. A sixth switch SW6 is connected between a connection node of a first switch SW1 and a first capacitor C1 and a second input node IN2. Therefore, the fifth switch SW5 and sixth switch SW6 make a tied back configuration.SELECTED DRAWING: Figure 5

Description

The present disclosure relates to a delta-sigma A/D converter.

A delta-sigma A/D converter is used for measurement of minute signals requiring high resolution and for audio applications. FIG. 1 is a block diagram showing the basic configuration of a delta-sigma A/D converter. A delta-sigma A/D converter 2 converts an analog input signal _VIN into a digital output signal _DOUT . The delta-sigma A/D converter 2 includes an analog section 4 at the front stage and a digital section 6 at the rear stage.

The preceding analog section 4 is a delta-sigma modulator that oversamples the analog input signal _VIN and converts the oversampled signal into a digital signal S at a rough level of 1 bit or several bits.

The output of the delta-sigma modulator will contain quantization noise. This quantization noise is driven to a high frequency region by a loop filter (integration circuit) inside the ΔΣ modulator (noise shaping).

The post-stage digital unit 6 is a digital filter and has the functions of a band-limiting filter and a decimation filter. Specifically, the digital filter attenuates high-frequency noise contained in the output of the ΔΣ modulator with a low-pass band-limiting filter, and lowers the data rate with a decimation filter (downsampling).

FIG. 2 is a circuit diagram of the delta-sigma modulator 10. As shown in FIG. The delta-sigma modulator 10 mainly includes a subtraction circuit 12, a loop filter 14, a quantizer 16, and a D/A converter 18.

Subtraction circuit 12 produces an error between analog input signal V _IN and output signal V _FB of D/A converter 18 . The loop filter 14 accumulates errors and performs noise shaping.

A quantizer 16 quantizes the output signal of the loop filter 14 . The quantized signal is input to the D/A converter.

FIG. 3 is a circuit diagram of a feedforward type third-order delta-sigma modulator 10A. In the delta-sigma modulator 10A, the subtraction circuit 12 and the tertiary loop filter 14 are integrated.

The block containing subtraction circuit 12 and third-order loop filter 14 includes multiple (three) integrators INT1, INT2, INT3 equal in order, multiple adder-subtractors ADD1, ADD2, ADD3, ADD4, and multiple feedforward paths and Have a feedback path. a ₁ , a ₂ , b ₁ , b ₂ , b ₃ , b ₄ , c ₁ , c ₂ , c ₃ denote the gains of the feedforward and feedback paths.

JP 2011-101247 A

Delta-sigma modulators are classified into time-discrete type and time-continuous type. A time-discrete delta-sigma modulator has a sampling circuit that samples an input signal _VIN . In the case of FIG. 3, sampling circuits are implemented on the paths b ₁ to b ₄ of the input signal V _IN .

Generally, the sampling circuit is configured using a switched capacitor circuit. If the input signal V _IN is a differential signal, the switched capacitor circuit is also composed of a differential circuit. A differential switched-capacitor circuit uses a reference voltage to sample the input signal _VIN .

Generally, the reference voltage is often set to 1/2 of the power supply voltage. Performance degrades when the common voltage of the differential input signal V _IN deviates from the reference voltage of the switched capacitor circuit.

The present disclosure has been made in this context, and one exemplary object of certain aspects thereof is to provide a delta-sigma modulator capable of operation independent of the common voltage of the input voltage.

One aspect of the present disclosure is a delta-sigma modulator that converts a differential input signal to a digital output signal. The delta-sigma modulator includes a switched-capacitor input sampling circuit that samples a differential input signal. The input sampling circuit includes a first input node and a second input node forming a differential input, a first output node and a second output node forming a differential output, a reference voltage node, a first input node and a second input node. a first switch, a first capacitor and a second switch connected in series between one output node; and a third switch, a second capacitor and a second switch connected in series between the second input node and the second output node. 4 switches, a connection node of the third switch and the second capacitor, a fifth switch connected between the first input node, a connection node of the first switch and the first capacitor, and the second input node a sixth switch connected between a connection node of the first capacitor and the second switch; a seventh switch connected between a reference voltage node; a connection node of the second capacitor and the fourth switch; and an eighth switch connected between the voltage node.

Arbitrary combinations of the above constituent elements, and mutually replacing constituent elements and expressions among methods, devices, systems, etc. are also effective as embodiments of the present invention or the present disclosure. Furthermore, the description in this section (Summary of the Invention) does not describe all the essential features of the invention, and thus subcombinations of those described features can also be the invention. .

The delta-sigma modulator according to the present disclosure enables processing independent of the common voltage of the differential input signal.

FIG. 1 is a block diagram showing the basic configuration of a delta-sigma A/D converter. FIG. 2 is a circuit diagram of a delta-sigma modulator. FIG. 3 is a circuit diagram of a feedforward type third-order ΔΣ modulator. FIG. 4 is a block diagram of a delta-sigma modulator according to the embodiment. FIG. 5 is a circuit diagram of an input sampling circuit according to the embodiment. FIG. 6 is a level diagram of the input sampling circuit of FIG. FIG. 7 is a circuit diagram of an input sampling circuit according to the comparison technique. FIG. 8 is a level diagram of the input sampling circuit of FIG. FIG. 9 is a diagram showing gain characteristics of an operational amplifier. FIG. 10 is a circuit diagram showing part of the delta-sigma modulator of FIG. FIG. 11 is a circuit diagram of a delta-sigma modulator according to the embodiment. FIG. 12 is a circuit diagram of a delta-sigma modulator according to the embodiment. FIG. 13 is a circuit diagram of a delta-sigma modulator according to the embodiment. 14 is a circuit diagram showing components of the ΔΣ modulator of FIG. 11. FIG.

(Overview of embodiment)
SUMMARY OF THE INVENTION Several exemplary embodiments of the disclosure are summarized. This summary presents, in simplified form, some concepts of one or more embodiments, as a prelude to the more detailed description that is presented later, and for the purpose of a basic understanding of the embodiments. The size is not limited. This summary is not a comprehensive overview of all possible embodiments, and it is intended to neither identify key elements of all embodiments nor delineate the scope of some or all aspects. For convenience, "one embodiment" may be used to refer to one embodiment (example or variation) or multiple embodiments (examples or variations) disclosed herein.

A delta-sigma modulator according to one embodiment converts a differential input signal into a digital output signal. The delta-sigma modulator includes a switched-capacitor input sampling circuit that samples a differential input signal. The input sampling circuit includes a first input node and a second input node forming a differential input, a first output node and a second output node forming a differential output, a reference voltage node, a first input node and a second input node. a first switch, a first capacitor and a second switch connected in series between one output node; and a third switch, a second capacitor and a second switch connected in series between the second input node and the second output node. 4 switches, a connection node of the third switch and the second capacitor, a fifth switch connected between the first input node, a connection node of the first switch and the first capacitor, and the second input node a sixth switch connected between a connection node of the first capacitor and the second switch; a seventh switch connected between a reference voltage node; a connection node of the second capacitor and the fourth switch; and an eighth switch connected between the voltage node.

In the first state, the first switch, third switch, seventh switch, and eighth switch are turned on. In the second state, the second switch, fourth switch, fifth switch, and sixth switch are turned on. Let Vr be the voltage of the reference voltage line, Vip be the voltage of the first input node, and Vin be the voltage of the second input node. It is also assumed that the first capacitor and the second capacitor have the same capacitance Cs. In the first state, the charge Qp stored in the first capacitor and the charge Qn stored in the second capacitor are respectively
Qp=Cs×(Vip−Vr)
Qn=Cs×(Vin−Vr)
is.

In the second state, the voltage Von generated at the first output node and the voltage Vp generated at the second output node are expressed by the following equations.
Von=Vin-Qp/Cs=Vin-(Vip-Vr)=Vin-Vip+Vr
Vop=Vip-Qn/Cs=Vip-(Vin-Vr)=Vip-Vin+Vr

A signal component (input voltage amplitude) Vp-Vn of the differential input signal is denoted as Vsig. At this time,
Von=-Vsig+Vr
Vop=+Vsig+Vr
becomes. The common voltage of the differential output signals Vop and Von is Vr and does not depend on the common voltage of the differential input signals. That is, according to the above configuration, it is possible to generate a differential output signal that does not depend on the common voltage of the differential input signal.

In one embodiment, the delta-sigma modulator may further comprise an integrating amplifier integrated with the input sampling circuit. The integrating amplifier has a third input node connected to the first output node of the input sampling circuit, a fourth input node connected to the second output node of the input sampling circuit, a third output node, and a fourth output node. a third capacitor connected between the third input node and the third output node; a fourth capacitor connected between the fourth input node and the fourth output node; a fully differential operational amplifier having a second input connected to the fourth input node, a first output connected to the third output node, and a second output connected to the fourth output node It's okay.

Assume that the capacitances of the third capacitor and the fourth capacitor are equal to Ci. At this time, the time constant of the integrating circuit is T×Ci/(2×Cs). T is the switching period of the switched capacitor circuit. The time constant of a typical crawl-type switched-capacitor integration circuit is T×Ci/Cs. Therefore, according to the above configuration, the capacitance of the capacitor Cs for obtaining the same time constant can be reduced to 1/2 compared to a general crawl type integrating circuit, and the chip size can be reduced.

In one embodiment, the delta-sigma modulator may further include an internal sampling circuit that samples internal signals within the delta-sigma modulator other than the input signal. The internal sampling circuit includes a fifth input node and a sixth input node forming a differential input, a fifth output node and a sixth output node forming a differential output, and between the fifth input node and the fifth output node. a ninth switch, a fifth capacitor and a tenth switch serially connected to the , an eleventh switch, a sixth capacitor and a twelfth switch serially connected between the sixth input node and the sixth output node; a thirteenth switch connected between a connection node of the 9th switch and the fifth capacitor and the reference voltage node; and a fourteenth switch connected between the connection node of the eleventh switch and the sixth capacitor and the reference voltage node. A fifteenth switch connected between the switch, a connection node of the fifth capacitor and the tenth switch, and the reference voltage node, and a connection node of the sixth capacitor and the twelfth switch, and the reference voltage node. and a sixteenth switch.

In the first state, the internal sampling circuit turns on the ninth switch, the eleventh switch, the fifteenth switch, and the sixteenth switch. In the second state, the tenth switch, the twelfth switch, the thirteenth switch, and the fourteenth switch are turned on. Let Vr be the voltage of the reference voltage line, Vip be the voltage of the first input node, and Vin be the voltage of the second input node. It is also assumed that the fifth capacitor and the sixth capacitor have the same capacitance Cs. In the first state, the charge Qp stored in the fifth capacitor and the charge Qn stored in the sixth capacitor are respectively
Qp=Cs×(Vip−Vr)
Qn=Cs×(Vin−Vr)
is.

In the second state, the voltage Vop generated at the first output node and the voltage Vn generated at the second output node are represented by the following equations.
Vop=Vr-Qp/Cs=Vr-(Vip-Vr)=2Vr-Vip
Von=Vr-Qn/Cs=Vr-(Vin-Vr)=2Vr-Vin

Since the input of the internal sampling circuit is generated based on the reference voltage Vr, its common voltage is Vr. Therefore, the common voltage Voc of the differential output signals Vop and Von is
Voc=(Vop+Von)/2=2Vr-(Vip+Vin)/2=Vr
becomes. That is, the common voltage is constant for the internal circuit.

In one embodiment, the delta-sigma modulator may further include an integration amplifier that forms an integration circuit together with the input sampling circuit. The integrating amplifier has a third input node connected to the first output node of the input sampling circuit, a fourth input node connected to the second output node of the input sampling circuit, a third output node, and a fourth output node. a third capacitor connected between the third input node and the third output node; a fourth capacitor connected between the fourth input node and the fourth output node; a fully differential operational amplifier having a second input connected to the fourth input node, a first output connected to the third output node, and a second output connected to the fourth output node It's okay.

In one embodiment, the delta-sigma modulator may further comprise an internal sampling circuit that samples an internal signal other than the input signal within the delta-sigma modulator. The internal sampling circuit includes a fifth input node and a sixth input node forming a differential input, a fifth output node and a sixth output node forming a differential output, and between the fifth input node and the fifth output node. a ninth switch, a fifth capacitor and a tenth switch connected in series to ; an eleventh switch, a sixth capacitor and a twelfth switch connected in series between the sixth input node and the sixth output node; a thirteenth switch connected between a connection node of the 9th switch and the fifth capacitor and the reference voltage node; and a fourteenth switch connected between the connection node of the eleventh switch and the sixth capacitor and the reference voltage node. A fifteenth switch connected between the switch, a connection node of the fifth capacitor and the tenth switch, and the reference voltage node, and a connection node of the sixth capacitor and the twelfth switch, and the reference voltage node. and a sixteenth switch. One of the fifth and sixth output nodes of the internal sampling circuit is connected to the third input node of the integrating amplifier, and the other of the fifth and sixth output nodes of the internal sampling circuit is connected to the fourth output node of the integrating amplifier. It may be connected to an input node.

With this configuration, the integration amplifier can integrate the weighted addition of the internal signal and the input signal.

In one embodiment, the order of the delta-sigma modulator may be three. In one embodiment, the order of the delta-sigma modulator may be two. In one embodiment, the order of the delta-sigma modulator may be four.

In one embodiment, the delta-sigma modulator may be integrated on one semiconductor substrate. "Integrated integration" includes cases in which all circuit components are formed on a semiconductor substrate and cases in which the main components of a circuit are integrated. A resistor, capacitor, or the like may be provided outside the semiconductor substrate. By integrating the circuits on one chip, the circuit area can be reduced and the characteristics of the circuit elements can be kept uniform.

In one embodiment, a delta-sigma A/D converter may include any of the above-described delta-sigma modulators and a filter that band-limits and down-samples the output signal of the delta-sigma modulator.

(embodiment)
FIG. 4 is a block diagram of the delta-sigma modulator 100 according to the embodiment. The delta-sigma modulator 100 delta-sigma modulates the differential input signal _VIN to convert it into a digital output signal _SOUT . The differential input signal VIN includes complementary positive signal Vip and negative signal Vin. The delta-sigma modulator 100 is integrated on one semiconductor substrate.

The delta-sigma modulator 100 comprises a subtraction circuit 12, a loop filter 14, a quantizer 16, a D/A converter 18 and an input sampling circuit 110. The delta-sigma modulator 100 is of the time-discrete type, and the input sampling circuit 110 consists of a switched capacitor circuit and samples the differential input signal _VIN .

The D/A converter 18 converts the output signal of the delta-sigma modulator 100, that is, the output signal _SOUT of the quantizer 16, into an analog feedback signal _VFB . The subtraction circuit 12 generates an error between the input signal V _IN sampled by the input sampling circuit 110 and the feedback signal V _FB .

Loop filter 14 includes an integration circuit to filter and noise shape the error signal produced by subtraction circuit 12 . The order of the loop filter 14 is not particularly limited. Also, the configuration of the loop filter 14 is not limited, and may be of a feedforward type or a feedback type. In the feedforward type, the input signal V _IN sampled by the input sampling circuit 110 is fed forward to the loop filter 14 .

A quantizer 16 quantizes the noise-shaped signal generated by the loop filter 14 . The number of bits n of the quantizer 16 may be 1 bit or 2 or more bits (multibit).

FIG. 5 is a circuit diagram of the input sampling circuit 110 according to the embodiment. The input sampling circuit 110 is of a fully differential type, and includes a first input node IN1 and a second input node IN2 forming differential inputs, and a first output node OUT1 and a second output node OUT2 forming differential outputs. , has a reference voltage node REF. Differential input signals Vip and Vin are input to the first input node IN1 and the second input node IN2. A reference voltage Vr is supplied to the reference voltage node REF. Reference voltage Vr is selected to be, for example, half the power supply voltage of ΔΣ modulator 100 .

The input sampling circuit 110 includes a plurality of switches SW1-SW8, a first capacitor C1 and a second capacitor C2. A first switch SW1, a first capacitor C1 and a second switch SW2 are connected in series between a first input node IN1 and a first output node OUT1. A third switch SW3, a second capacitor C2 and a fourth switch SW4 are connected in series between the second input node IN2 and the second output node OUT2. Assume that the first capacitor C1 and the second capacitor C2 have the same capacitance Cs.

The fifth switch SW5 is connected between the connection node of the third switch SW3 and the second capacitor C2 and the first input node IN1. The sixth switch SW6 is connected between a connection node of the first switch SW1 and the first capacitor C1 and the second input node IN2. In other words, the fifth switch SW5 and the sixth switch SW6 provide a crossing configuration.

The seventh switch SW7 is connected between a connection node between the first capacitor C1 and the second switch SW2 and the reference voltage node REF. The eighth switch SW8 is connected between a connection node between the second capacitor C2 and the fourth switch SW4 and the reference voltage node REF.

The configurations of the ΔΣ modulator 100 and the input sampling circuit 110 are as described above. Next, the operation of the input sampling circuit 110 will be explained.

The input sampling circuit 110 alternately repeats the first state φ1 and the second state φ2. In the first state φ1, the first switch SW1, the third switch SW3, the seventh switch SW7, and the eighth switch SW8 are turned on.

In the first state φ1, the charge Qp stored in the first capacitor and the charge Qn stored in the second capacitor are respectively
Qp=Cs×(Vip−Vr)
Qn=Cs×(Vin−Vr)
is.

In the second state φ2, the voltage Von generated at the first output node OUT1 and the voltage Vp generated at the second output node OUT2 are represented by equations (1) and (2), respectively.
Von=Vin-Qp/Cs=Vin-(Vip-Vr)
=Vin-Vip+Vr (1)
Vop=Vip-Qn/Cs=Vip-(Vin-Vr)
=Vip−Vin+Vr (2)

FIG. 6 is a level diagram of the input sampling circuit 110 of FIG. It shows a case where the common voltage Vic (=(Vip+Vin)/2) of the differential input Input deviates from the reference voltage Vr of the input sampling circuit 110 . A signal component (input voltage amplitude) Vp-Vn of the differential input signal is denoted as Vsig.

From the equation (1), the voltage Vop of the second output node OUT2 and the voltage Von of the first output node OUT1 are respectively
Vop=-Vsig+Vr (3)
Von=+Vsig+Vr (4)
becomes. The common voltage Voc of the differential output signals Vop and Von is
Voc=(Vop+Von)/2=Vr
becomes. That is, the common voltage Voc matches the reference voltage Vr of the input sampling circuit 110 and does not depend on the common voltage Vic of the differential input signal. That is, according to the configuration of FIG. 5, the differential output signals Vop and Von can be generated independent of the common voltage Vic of the differential input signals Vip and Vin.

The advantage of the input sampling circuit 110 becomes clear by contrasting it with the input sampling circuit according to the comparison technique. Therefore, the comparison technique will be explained.

FIG. 7 is a circuit diagram of the input sampling circuit 110R according to the comparison technique. The input sampling circuit 110R includes a plurality of switches SW1 to SW8 and capacitors C1 and C2, like the input sampling circuit 110 in FIG. The difference from FIG. 5 is the connection mode of the fifth switch SW5 and the sixth switch SW6, and one end of each of the fifth switch SW5 and the sixth switch SW6 is commonly connected to the reference voltage node REF.

The operation of the input sampling circuit 110R will be described. The input sampling circuit 110R alternately repeats the first state φ1 and the second state φ2. In the first state φ1, the first switch SW1, the third switch SW3, the seventh switch SW7, and the eighth switch SW8 are turned on.

In the first state φ1, the charge Qp stored in the first capacitor and the charge Qn stored in the second capacitor are respectively
Qp=Cs×(Vip−Vr)
Qn=Cs×(Vin−Vr)
and is the same as the input sampling circuit 110 according to the embodiment.

In the second state φ2, the voltage Von generated at the first output node OUT1 and the voltage Vp generated at the second output node OUT2 are represented by equations (5) and (6), respectively.
Von=Vr-Qp/Cs=Vr-(Vip-Vr)
= 2Vr-Vip (5)
Vop=Vr-Qn/Cs=Vr-(Vin-Vr)
= 2Vr-Vin (6)

FIG. 8 is a level diagram of the input sampling circuit 110R of FIG. It shows a case where the common voltage Vic (=(Vip+Vin)/2) of the differential input Input deviates from the reference voltage Vr of the input sampling circuit 110 .

From equations (5) and (6), the common voltage Voc' of the differential outputs Vop and Von is
Voc'=(Vop+Von)/2=2Vr-Vic
becomes. That is, in the input sampling circuit 110R according to the comparison technique, the common voltage Voc' does not match the reference voltage Vr, but depends on the common voltage Vic of the differential input signal.

An operational amplifier may be arranged after the input sampling circuit 110 (110R). FIG. 9 is a diagram showing gain characteristics of an operational amplifier. The operational amplifier has a constant gain in a linear range around the reference voltage Vr, and the gain decreases away from the reference voltage Vr. Further, if the input common voltages of the operational amplifiers are not the same, the gain will not be constant, so it will be impossible to ensure sufficient linearity.

In the comparison technique, the output signal of the input sampling circuit 110R, in other words, the input signal of the operational amplifier changes in a range deviating from Vr. Therefore, it is difficult to operate the operational amplifier within its highly linear range.

On the other hand, the output signal of the input sampling circuit 110 according to the embodiment, in other words, the input signal of the operational amplifier changes around Vr. Therefore, it can be operated within the linear range where the operational amplifier has high linearity. Thereby, the characteristics of the delta-sigma modulator 100 can be improved.

The noises of the input sampling circuit 110 of FIG. 5 and the input sampling circuit 110R of FIG. 7 are compared. Let vnp and vnn be the noise amounts input to the input nodes IN1 and IN2. In the input sampling circuit 110R of FIG. 7, the noise amount is represented by Equation (7).

ただし、ｖｎｈｐ，ｖｎｈｎは、ホールド時の入力のノイズ量を表す。 On the other hand, in the input sampling circuit 110 of FIG. 5, the noise amount when the same noises vnp and vnn are input is expressed by Equation (8).

However, vnhp and vnhn represent the amount of input noise during hold.

That is, according to the embodiment, the noise amount is reduced because the noise at the time of sampling and at the time of holding is taken in and averaged.

FIG. 10 is a circuit diagram showing part of the delta-sigma modulator 100 of FIG. FIG. 10 shows the input sampling circuit 110 and part of the loop filter 14 . Loop filter 14 includes an integrating amplifier 120 .

The integration amplifier 120 constitutes a crawl type integration circuit INT together with the input sampling circuit 110 . It has a third input node IN3 and a fourth input node IN4 forming a differential input, and a third output node OUT3 and a fourth output node OUT4 forming a differential output.

Integrating amplifier 120 includes a third capacitor C3, a fourth capacitor C4 and an operational amplifier OA1. A third capacitor C3 is connected between a third input node IN3 and a third output node OUT3. A fourth capacitor C4 is connected between a fourth input node IN4 and a fourth output node OUT4. The operational amplifier OA1 is of a fully differential type, the first input (-) is connected to the third input node IN3, the second input (+) is connected to the fourth input node IN4, and the first output (+) is connected to the third input node IN3. 3 is connected to the output node OUT3, and the second output (-) is connected to the fourth output node OUT4.

Assume that the capacitances of the third capacitor C3 and the fourth capacitor C4 are equal to Ci. At this time, the time constant of the integrating circuit INT is T×Ci/(2×Cs). T is the switching period of the input sampling circuit 110, which is a switched capacitor circuit.

Note that the time constant of the crawl type switched capacitor integration circuit when the input sampling circuit 110R according to the comparison technique is employed in the preceding stage is T×Ci/Cs. Therefore, according to the above configuration, the capacitance of the capacitor Cs for obtaining the same time constant can be reduced to 1/2 compared to a general crawl type integrating circuit, and the chip size can be reduced.

In the example of FIG. 10, integration circuit INT includes the function of adder/subtractor ADD. Intermediate sampling circuit 130 samples internal signals other than the input signal in ΔΣ modulator 100 . In this example, the internal signal is the feedback signal _VFB . The intermediate sampling circuit 130 may have the same configuration as the input sampling circuit 110 according to the embodiment, or may have the same configuration as the input sampling circuit 110R according to the comparison technique.

The input sampling circuit 110, the intermediate sampling circuit 130 and the integrating amplifier 120 form an adding type integrating circuit. Here, since the output of the intermediate sampling circuit 130 is connected to the integration amplifier 120 with the polarity opposite to the output of the input sampling circuit 110, the output of the intermediate sampling circuit 130 is equal to the output of the input sampling circuit 110. Added in reverse polarity.

The feedback signal _VFB , which is the input of the intermediate sampling circuit 130, is a differential signal generated by the D/A converter 18, and its common voltage can be matched with the reference voltage Vr. Therefore, the intermediate sampling circuit 130 can be composed of the input sampling circuit 110R according to the comparison technique. Alternatively, the intermediate sampling circuit 130 may have the same configuration as the input sampling circuit 110 according to the embodiment.

FIG. 11 is a circuit diagram of the delta-sigma modulator 100A according to the embodiment. The delta-sigma modulator 100A is a third-order delta-sigma modulator and has substantially the same configuration as the delta-sigma modulator 10A in FIG.

An input sampling circuit 110 is incorporated in each of the paths b ₁ , b ₂ , b ₃ , b ₄ that receive the differential input signal V _IN . Intermediate sampling circuits 130 are incorporated in paths c ₁ , c ₂ , c ₃ , a ₁ , a ₂ , g ₁ along which other intermediate signals are transmitted.

FIG. 12 is a circuit diagram of the delta-sigma modulator 100B according to the embodiment. The delta-sigma modulator 100B is a secondary delta-sigma modulator and includes two integration circuits INT1 and INT2. An input sampling circuit 110 is incorporated in each of the paths b ₁ , b ₂ , b ₃ that receive the differential input signal V _IN . Intermediate sampling circuits 130 are incorporated in paths c ₁ , c ₂ , a ₁ , a ₂ , g ₁ along which other intermediate signals are transmitted.

FIG. 13 is a circuit diagram of the delta-sigma modulator 100C according to the embodiment. The delta-sigma modulator 100C is a fourth-order delta-sigma modulator and includes four integration circuits INT1 to INT4. An input sampling circuit 110 is incorporated in each of the paths b ₁ to b ₅ that receive the differential input signal V _IN . Intermediate sampling circuits 130 are incorporated in paths c ₁ to c ₄ , a ₁ to a ₄ , g ₁ and g ₂ along which other intermediate signals are transmitted.

FIG. 14 is a circuit diagram showing component 150 of ΔΣ modulators 100A-100C of FIGS. 11-13. Components 150 include input sampling circuit 110 , m intermediate sampling circuits 130 , adder/subtractor ADD, and integrating amplifier 120 .

Component 150 is a circuit block corresponding to the integrator INT _j (j=1, 2...)) adder/subtractor ADD _j and the sampling circuit included in paths a, b, c, and g in each of FIGS. be.

The input sampling circuit 110 is placed on path _bj in FIGS. 11-13. Intermediate sampling circuit 130_1 is placed on path _cj in FIGS. 11-13. The intermediate sampling circuits 130_2 to 130_m are arranged in paths a and g that are input to the adder/subtractor _ADDj , which are paths other than the path c.

The intermediate sampling circuit 130 connects a fifth input node IN5, a sixth input node IN6, a fifth output node OUT5, a sixth output node OUT6, a ninth switch SW9 to a sixteenth switch SW16, a fifth capacitor C5 and a sixth capacitor C6. include. The configuration of the intermediate sampling circuit 130 is similar to that of the input sampling circuit 110R of FIG. One, a plurality, or all of the intermediate sampling circuits 130_1 to 130_m may have the same configuration as the input sampling circuit 110. FIG.

(Application)
The delta-sigma modulator 100 according to the embodiment can be employed in the analog section of the delta-sigma A/D converter in FIG. However, the use of the delta-sigma modulator 100 is not limited to the A/D converter, and can be used for various other uses.

Those skilled in the art will understand that the embodiments are examples, and that there are various modifications in the combination of each component and each processing process, and that such modifications are also included in the scope of the present disclosure or the present invention. It is about

100 ΔΣ modulator 12 subtraction circuit 14 loop filter 16 quantizer 18 D/A converter 110 input sampling circuit IN1 first input node IN2 second input node OUT1 first output node OUT2 second output node REF reference voltage node C1 first Capacitor C2 Second capacitor SW1 First switch SW2 Second switch SW3 Third switch SW4 Fourth switch SW5 Fifth switch SW6 Sixth switch SW7 Seventh switch SW8 Eighth switch 120 Integration amplifier IN3 Third input node IN4 Fourth input node OUT3 third output node OUT4 fourth output node C3 third capacitor C4 fourth capacitor OA1 operational amplifier 130 intermediate sampling circuit IN5 fifth input node IN6 sixth input node OUT5 fifth output node OUT6 sixth output node SW9 ninth switch SW10 10th switch SW11 11th switch SW12 12th switch C5 5th capacitor C6 6th capacitor

Claims (9)

A delta-sigma modulator that converts a differential input signal into a digital output signal,
comprising a switched capacitor type input sampling circuit for sampling the differential input signal;
The input sampling circuit is
a first input node and a second input node forming a differential input;
a first output node and a second output node forming a differential output;
a reference voltage node;
a first switch, a first capacitor and a second switch connected in series between the first input node and the first output node;
a third switch, a second capacitor and a fourth switch connected in series between the second input node and the second output node;
a fifth switch connected between a connection node of the third switch and the second capacitor and the first input node;
a sixth switch connected between a connection node of the first switch and the first capacitor and the second input node;
a seventh switch connected between a connection node of the first capacitor and the second switch and the reference voltage node;
an eighth switch connected between a connection node of the second capacitor and the fourth switch and the reference voltage node;
A delta-sigma modulator, including further comprising an integration amplifier that forms an integration circuit together with the input sampling circuit;
The integration amplifier is
a third input node connected to the first output node of the input sampling circuit;
a fourth input node connected to the second output node of the input sampling circuit;
a third output node;
a fourth output node;
a third capacitor connected between the third input node and the third output node;
a fourth capacitor connected between the fourth input node and the fourth output node;
A first input is connected to the third input node, a second input is connected to the fourth input node, a first output is connected to the third output node, and a second output is connected to the fourth output node. a fully differential operational amplifier with
The delta-sigma modulator of claim 1, comprising: further comprising an internal sampling circuit for sampling an internal signal other than the input signal in the ΔΣ modulator;
The internal sampling circuit is
a fifth input node and a sixth input node forming a differential input;
a fifth output node and a sixth output node forming a differential output;
a ninth switch, a fifth capacitor and a tenth switch connected in series between the fifth input node and the fifth output node;
an eleventh switch, a sixth capacitor and a twelfth switch connected in series between the sixth input node and the sixth output node;
a thirteenth switch connected between a connection node of the ninth switch and the fifth capacitor and the reference voltage node;
a fourteenth switch connected between a connection node of the eleventh switch and the sixth capacitor and the reference voltage node;
a fifteenth switch connected between a connection node of the fifth capacitor and the tenth switch and the reference voltage node;
a sixteenth switch connected between a connection node of the sixth capacitor and the twelfth switch and the reference voltage node;
3. The delta-sigma modulator according to claim 1, comprising: further comprising an internal sampling circuit for sampling an internal signal other than the input signal in the ΔΣ modulator;
The internal sampling circuit is
a fifth input node and a sixth input node forming a differential input;
a fifth output node and a sixth output node forming a differential output;
a ninth switch, a fifth capacitor and a tenth switch connected in series between the fifth input node and the fifth output node;
an eleventh switch, a sixth capacitor and a twelfth switch connected in series between the sixth input node and the sixth output node;
a thirteenth switch connected between a connection node of the ninth switch and the fifth capacitor and the reference voltage node;
a fourteenth switch connected between a connection node of the eleventh switch and the sixth capacitor and the reference voltage node;
a fifteenth switch connected between a connection node of the fifth capacitor and the tenth switch and the reference voltage node;
a sixteenth switch connected between a connection node of the sixth capacitor and the twelfth switch and the reference voltage node;
including
one of the fifth output node and the sixth output node of the internal sampling circuit is connected to the third input node of the integrating amplifier;
3. The ΔΣ modulator according to claim 2, wherein the other of said fifth output node and said sixth output node of said internal sampling circuit is connected to said fourth input node of said integrating amplifier. 5. The delta-sigma modulator according to claim 1, wherein the order of said delta-sigma modulator is three. 5. The delta-sigma modulator according to claim 1, wherein the order of said delta-sigma modulator is two. 5. The delta-sigma modulator according to claim 1, wherein the order of said delta-sigma modulator is four. 8. The delta-sigma modulator according to claim 1, which is integrated on one semiconductor substrate. A ΔΣ modulator according to any one of claims 1 to 8;
a filter for band-limiting and down-sampling the output signal of the delta-sigma modulator;
A delta-sigma A/D converter.

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