JP2023117731A - ΔΣ modulator and analog/digital converter - Google Patents

Abstract

To reduce a quantization error, while preventing an increase in the circuit area and power consumption.SOLUTION: IN a ΔΣ modulator 10, a quantizer 40 quantizes analog voltage V10 output from an integrating circuit 110 to generate a first digital signal Y10. A capacity DA converter of a successive approximation AD converter 70 samples the analog voltage V10 output from the integrating circuit 110 and performs DA conversion of the first digital signal Y10 to generate differential voltage in which a DA conversion value of the first digital signal Y10 is subtracted from the analog voltage V10. The successive approximation AD converter performs AD conversion of the differential voltage to generate a second digital signal Y20. An adder adds a result of differentiation of the second digital signal Y20 and the first digital Y10 to each other to generate an output digital signal Y.SELECTED DRAWING: Figure 1

Description

The present disclosure relates to delta-sigma modulators and analog-to-digital converters.

ΔΣ modulation is one of the conversion methods of an analog/digital (AD) converter. In delta-sigma modulation, an integrator integrates the difference between an input signal sampled by oversampling and an analog signal generated by DA (Digital to Analog) conversion of an output digital signal. Quantizing the output of the integrator produces the above output digital signal. Analog/digital conversion using such delta-sigma modulation can achieve high resolution that cannot be achieved with other methods.

Japanese Patent No. 4357083 (Patent Document 1) discloses a circuit configuration for further reducing quantization errors. Specifically, the ΔΣ modulator disclosed in this document includes an input terminal, an output terminal, a 1-bit quantizer, a 1-bit DA converter, an input integration circuit string, a delay element, and a second subtractor. , a multi-bit quantizer, a differentiator, and an adder. An input analog signal is input to the input terminal. The output terminal outputs an output digital signal. A 1-bit quantizer is arranged in the signal path between the input terminal and the output terminal to quantize the analog signal and output a quantized digital signal. A 1-bit DA converter converts the quantized digital signal into a quantized analog signal. The input integration circuit array includes one or more sets of subtractors and integrators for integrating their outputs connected in one stage or in multiple stages, and the subtractor in the first stage subtracts the quantized analog signal from the input analog signal. Subtractors in the second and subsequent stages subtract the quantized analog signal from the output signal of the integrator in the preceding stage, and output the output signal of the integrator in the final stage to the 1-bit quantizer. A delay element is arranged in the signal path of the quantized analog signal from the 1-bit DA converter to the input integration circuit row. A second subtractor subtracts the quantized analog signal from the analog signal input to the 1-bit quantizer. A multi-bit quantizer quantizes the analog output of the second subtractor to output a quantized second digital signal. The differentiator differentiates the output of the multi-bit quantizer by the same dimension as the number of stages of the input integration circuit array. The adder adds the output of the differentiator to the quantized digital signal and outputs the result (see paragraph [0008] of Patent Document 1).

Japanese Patent No. 4357083

One of the problems of the ΔΣ modulator described in Japanese Patent No. 4357083 (Patent Document 1) is that the analog signal input to the 1-bit quantizer is DA-converted by a 1-bit DA converter. The point is that an analog subtractor (second subtractor) is required for subtracting the analog signal. Since the analog subtractor is usually configured using an operational amplifier, there is a problem that the circuit area and power consumption increase.

The present disclosure has been made in consideration of the above problems, and one of its purposes is to provide a delta-sigma modulation analog/digital converter that reduces quantization errors while suppressing increases in circuit area and power consumption. to provide.

A delta-sigma modulator of one embodiment includes an integration circuit, a quantizer, a delay device, a DA converter, a successive approximation AD converter, a differentiator, and an adder. The integration circuit performs an integration operation on the difference between the input analog signal and the feedback signal. The quantizer generates an m-bit (m≧1) first digital signal by quantizing the analog voltage that is the integration result of the integration circuit. The delayer delays the first digital signal. The DA converter generates the feedback signal by converting the first digital signal delayed by the delay device into an analog signal. A successive approximation AD converter includes a capacitive DA converter. The capacitive DA converter samples the analog voltage output from the integrating circuit and DA converts the first digital signal to generate a difference voltage obtained by subtracting the DA converted value of the first digital signal from the analog voltage. The successive approximation AD converter generates a second digital signal by AD-converting this differential voltage. A differentiator differentiates the second digital signal. The adder generates an output digital signal by adding the differentiated result of the differentiator and the first digital signal.

According to the above embodiment, the DA conversion value of the first digital signal is subtracted from the analog voltage output from the integrating circuit by the capacitive DA converter of the successive approximation AD converter. As a result, increases in circuit area and power consumption can be suppressed. Furthermore, the successive approximation AD converter generates a second digital signal by AD-converting the subtraction result. Since the output digital signal is generated by adding the differentiation result of the second digital signal to the first digital signal, the quantization error can be reduced.

2 is a block diagram showing the configuration of ΔΣ modulator 10 according to Embodiment 1. FIG. 2 is a block diagram showing the configuration of an analog/digital converter 200 using the ΔΣ modulator 10 of FIG. 1; FIG. FIG. 4 is a diagram for explaining the quantization error reduction effect of the ΔΣ modulator 10 of the first embodiment; FIG. 2 is a diagram showing a detailed configuration of SAR-ADC 70 of FIG. 1; FIG. 5 is a flow chart showing the operation of the SAR-ADC of FIG. 4; FIG. 4 is a diagram for explaining a specific example of a subtraction operation by a capacitive DAC; FIG. 2 is a block diagram showing a configuration of a ΔΣ modulator 300 as a comparative example of FIG. 1; FIG. FIG. 10 is a circuit diagram showing the configuration of a SAR-ADC provided in the ΔΣ modulator of Embodiment 2; 9 is a diagram for explaining the operation of the SAR-ADC in FIG. 8; FIG. FIG. 12 is a diagram for explaining a modification of the second embodiment; FIG. FIG. 11 is a diagram for explaining a first configuration example of a third embodiment; FIG. 12 is a flow chart showing the operation of the SAR-ADC of FIG. 11; FIG. 12 is a diagram for explaining a second configuration example of the third embodiment; FIG. 14 is a flow chart showing the operation of the SAR-ADC of FIG. 13;

Hereinafter, each embodiment will be described in detail with reference to the drawings. The same reference numerals are given to the same or corresponding parts, and the description thereof will not be repeated.

Embodiment 1.
[Configuration of ΔΣ modulator]
FIG. 1 is a block diagram showing the configuration of ΔΣ modulator 10 according to Embodiment 1. As shown in FIG. Referring to FIG. 1, ΔΣ modulator 10 includes integration circuit 110, quantizer 40, delay device 50, digital/analog converter (DAC: Digital to Analog Converter) 60, successive approximation type analog/digital A converter (SAR-ADC: Successive Approximation Register Analog to Digital Converter) 70 , a differentiator 80 , and an adder 81 are provided.

Integrating circuit 110 has a configuration in which a subtractor 30 and an integrator 20 for integrating the subtraction result are used as structural units, and the structural units are connected in series in one or more stages. Hereinafter, the number of stages of structural units included in the integrating circuit 110 is assumed to be n (n≧1). The first-stage subtractor 30_1 subtracts the output signal of the DAC 60 from the input analog signal X of the ΔΣ modulator 10 . Subtractors 30_i (2≦i≦n) in the second and subsequent stages subtract the output signal of the DAC 60 from the integration result of the integrator 20_i−1 in the preceding stage. The n-th stage integrator 20_n, which is the final stage, inputs the analog voltage _V10 to the quantizer 40 as the integration result. In this disclosure, the output signal of DAC 60 is also referred to as the feedback signal.

The quantizer 40 quantizes the analog voltage _V10 output from the integration circuit 110 to generate a 1-bit or multi-bit first digital signal _Y10 . Hereinafter, the number of bits of the quantizer 40 is assumed to be m (m≧1). The first digital signal Y ₁₀ is an m-bit digital signal.

The delay device 50 delays the first digital signal _Y10 by one sampling period. The DAC 60 is an m-bit DA converter (mb-DAC) that digital-to-analog converts the m-bit first digital signal Y ₁₀ delayed by the delay device 50 . The analog signal output from DAC 60 is input to each of one-stage subtractor 30 or n-stage subtractors 30 forming integration circuit 110 .

The SAR-ADC 70 is a successive approximation ADC using a capacitive DAC. The SAR-ADC 70 DA-converts the first digital signal _Y10 in the capacitive DAC. Further, the SAR-ADC 70 samples the analog voltage _V10 output from the integration circuit 110 to a capacitor DAC to generate a differential voltage between the analog voltage _V10 and the DA conversion value of the first digital signal _Y10 . The SAR-ADC 70 generates a second digital signal Y ₂₀ by AD-converting this difference voltage using the binary search principle.

A differentiator 80 differentiates the second digital signal Y ₂₀ output from the SAR-ADC 70 . The order of differentiator 80 is preferably the same as the number of stages n of integration circuit 110 .

The adder 81 adds the first digital signal Y ₁₀ output from the quantizer 40 and the differentiation result of the differentiator 80 to generate the output digital signal Y of the ΔΣ modulator 10 .

[Configuration of AD converter]
FIG. 2 is a block diagram showing the configuration of an analog/digital converter 200 using the ΔΣ modulator 10 of FIG. Referring to FIG. 2 , analog/digital converter (ADC) 200 includes ΔΣ modulator 10 and digital filter 210 .

Generally, in a delta-sigma modulator, the sampling frequency is set sufficiently higher than the frequency of the input signal (oversampling) to suppress the quantization noise in the low-frequency region and emphasize the quantization noise in the high-frequency region. is possible. Digital filter 210 is configured as a low-pass filter to remove quantization noise in the emphasized high-frequency region. Thereby, a highly accurate digital signal Z can be obtained.

[Effect of reducing quantization error]
According to the configuration of the ΔΣ modulator 10 shown in FIG. 1, the quantization error contained in the output digital signal Y of the ΔΣ modulator 10 can be reduced more than conventionally. The principle will be described below.

FIG. 3 is a diagram for explaining the quantization error reduction effect of the ΔΣ modulator 10 of the first embodiment. The ΔΣ modulator 10 shown in FIG. 3 corresponds to the case where the number of stages n of the integrating circuit 110 in FIG. 1 is two and the order of the differentiator 80 is second. Also, the integrator 20, the delay device 50, and the differentiator 80 are represented by transfer functions using Z-transform.

Let the quantization error of the quantizer 40 be _E1 . The first digital signal _Y10 output from the quantizer 40 is represented by the sum of the analog voltage _V10 output from the integration circuit 110 and the quantization error _E1 , as shown in the following equation (1). . The analog voltage _V10 is rewritten using the input analog signal X as follows.

Let E ₂ be the quantization error of the SAR-ADC 70 . The second digital signal Y ₂₀ output from the SAR-ADC 70 is the difference between the analog voltage V ₁₀ output from the integration circuit 110 and the DA conversion value of the first digital signal Y ₁₀ output from the quantizer 40. , AD-converted. Therefore, the second digital signal _Y20 is represented by the following equation (2). In the following equation (2), the first digital signal _Y10 of the above equation (1) is also substituted.

The output digital signal Y of the ΔΣ modulator 10 is a signal obtained by differentiating the first digital signal Y ₁₀ output from the quantizer 40 and the second digital signal Y ₂₀ output from the SAR-ADC 70 by the differentiator 80. is the sum of Therefore, the output digital signal Y is represented by the following equation (3) by using the above equations (1) and (2).

Here, the quantization error E ₂ of the SAR-ADC 70 is smaller than the quantization error E ₁ of the quantizer 40 . Therefore, by comparing equations (1) and (2), it can be seen that the quantization error of the ΔΣ modulator 10 of this embodiment is reduced.

[Configuration and operation of SAR-ADC]
Next, the configuration and operation of the SAR-ADC 70 of FIG. 1 will be described in more detail. As already explained, by using the capacitive DAC provided in the SAR-ADC 70, DA conversion of the analog voltage V ₁₀ output from the integration circuit 110 and the first digital signal Y ₁₀ output from the quantizer 40 Subtraction with a value is possible.

FIG. 4 is a diagram showing the detailed configuration of the SAR-ADC 70 of FIG. Referring to FIG. 4, SAR-ADC 70 receives analog voltage V ₁₀ from integration circuit 110 and first digital signal Y ₁₀ from quantizer 40 and outputs a second digital signal Y ₂₀ .

Specifically, the SAR-ADC 70 includes an input switch S100, a comparator 140, a control circuit 150, and a capacitive DAC130. The analog voltage _V10 is input to the first terminal of the input switch S100, and the second terminal of the input switch S100 is connected to the input node of the comparator 140. FIG. The control circuit 150 controls switching of the switches SW0 to SW7 of the input switch S100 and the capacitor DAC .

Comparator 140 compares the input voltage to a comparison voltage (eg, common voltage). A comparison result by the comparator 140 is input to the control circuit 150 . The control circuit 150 generates the second digital signal Y ₂₀ based on the comparison result by the comparator 140 .

Capacitance DAC 130 includes a capacitor group C110 and a switch group S110. The primary side of each capacitor forming capacitor group C110 is connected to the input node of comparator 140 . A positive reference voltage Vr and a negative reference voltage -Vr are selectively applied to the secondary side of each capacitor through corresponding switches of the switch group S110. In this disclosure, the positive reference voltage Vr and the negative reference voltage −Vr are also referred to as the first reference voltage and the second reference voltage.

The capacitance values of the capacitor group C110 are weighted by binary numbers. The capacitor with the largest capacitance value (capacitance value 64C in the case of FIG. 4) and the corresponding switch (SW7 in the case of FIG. 4) correspond to the binary most significant bit (MSB). The capacitor with the smallest capacitance value (capacitance value C in FIG. 4) and the corresponding switch (SW0 or SW1 in FIG. 4) correspond to the binary least significant bit (LSB).

As shown in FIG. 4, the capacitor group C110 includes a first capacitor group C120 and a second capacitor group C130. The switch group S110 includes a first switch group S120 and a second switch group S130. Here, assuming that the number of bits of the first digital signal _Y10 received from the quantizer 40 is m, the first capacitor group C120 is composed of m (4 in FIG. 4) capacitors from the MSB side. be. The first switch group S120 is composed of m switches (switches SW4 to SW6 in the case of FIG. 4) respectively corresponding to the m capacitors of the first capacitor group C120. The second capacitor group C130 and the second switch group S130 are composed of the remaining LSB-side capacitors and corresponding switches.

The MSB-side capacitor group C120 and switch group S120 are used for DA conversion of the first digital signal _Y10 . The capacitor group C130 and the switch group S130 on the LSB side are used for AD-converting the differential voltage between the analog voltage V10 output from the integration circuit ₁₁₀ and the DA-converted value of the first digital signal _Y10 by the successive approximation method. be done.

FIG. 5 is a flow chart showing the operation of the SAR-ADC of FIG. The operation of the SAR-ADC 70 will be described below with reference to FIGS. 4 and 5. FIG. In the initial state of the flow chart of FIG. 5, the input switch S100 is open.

First, in step ST110, control circuit 150 sets the total value of charges generated on the secondary side of capacitor group C110 to 0 when it is assumed that a comparison voltage (for example, a common voltage) is applied to the primary side of capacitor group C110. The switch group S110 is set so that For example, the control circuit 150 connects the switch SW7 to the terminal supplied with the reference voltage Vr, and connects each of the switches SW0 to SW6 to the terminal supplied with the reference voltage -Vr.

In the next step ST120, the control circuit 150 samples the analog voltage _V10 output from the integrating circuit 110 to the primary side of the capacitor group C110 by switching the input switch S100 to the closed state. Either of steps ST110 and ST120 described above may be executed first, or may be executed simultaneously.

In the next step ST130, the control circuit 150 switches the input switch S100 to the open state. As a result, a charge corresponding to the analog voltage _V10 is stored on the primary side of the capacitor group C110.

In the next step ST140, assuming that a comparison voltage (for example, a common voltage) is applied to the primary side of the second capacitor group C130, which is a part of the LSB side of the capacitor group C110, the second capacitor group C130 The corresponding second switch group S130 is connected so that the total value of the charge on the next side becomes zero. For example, in the case of FIG. 4, the control circuit 150 switches the switch SW3 to the terminal supplied with the reference voltage Vr, and switches each of the switches SW0 to SW2 to the terminal supplied with the reference voltage -Vr.

In the next step ST150, the control circuit 150 switches the connection of the first switch group S120 on the MSB _side based on the first digital signal _Y10 output from the quantizer 40, thereby is subtracted from the analog voltage V10 output from the integration circuit ₁₁₀ to generate a difference voltage on the primary side of the capacitor group C110. Either of steps ST140 and ST150 described above may be executed first, or may be executed simultaneously.

For example, in FIG. 4, when the first digital signal _Y10 , which is a 4-bit binary code signal, is "1111", the control circuit 150 connects each of the switches SW7 to SW4 to the terminal to which the reference voltage -Vr is supplied. Connecting. When the first digital signal _Y10 is "1110", the control circuit 150 connects each of the switches SW5 to SW7 to the terminal supplied with the reference voltage -Vr, and connects the switch SW4 to the terminal supplied with the reference voltage Vr. Connecting.

In the next step ST160, the control circuit 150 switches the second switch group S130 using the binary search principle to bring the voltage value on the primary side of the capacitor group C110 as close as possible to the comparison voltage (for example, common voltage). . Thereby, the AD conversion value of the lower bit corresponding to the second switch group S130 is determined.

For example, in FIG. 4, assume that the current voltage Vc on the primary side of capacitor group C110 is positive (eg, the output of comparator 140 corresponds to a high level). In this case, the control circuit 150 switches the connection of the LSB side switch group S130 so that the DA conversion value of the lower 3 bits "100" is subtracted from the current primary voltage Vc of the capacitor group C110. As a result, if the primary side voltage Vc is still positive, the control circuit 150 controls the LSB side so that the DA conversion value of the lower 3 bits "110" is subtracted from the current primary side voltage Vc of the capacitor group C110. switches the connection of the switch group S130. Conversely, when the primary side voltage Vc changes to negative, the control circuit 150 controls the LSB side so that the DA conversion value of the lower 3 bits "010" is subtracted from the current primary side voltage Vc of the capacitor group C110. Switch the connection of the switch group S130. A similar procedure is subsequently executed to determine the final connection of the second switch group S130 on the LSB side.

On the other hand, in FIG. 4, assume that the current voltage V _C on the primary side of the capacitor group C110 is negative. In this case, the control circuit 150 switches the connection of the LSB side switch group S130 so that the DA conversion value of the lower 3 bits "100" is added to the current primary voltage Vc of the capacitor group C110. As a result, if the primary side voltage Vc is still negative, the control circuit 150 controls the LSB side so that the DA conversion value of the lower 3 bits "110" is added to the current primary side voltage Vc of the capacitor group C110. switches the connection of the switch group S130. Conversely, if the primary side voltage Vc changes to positive, the control circuit 150 sets the lower 3 bits to LSB so that the DA conversion value of "010" is added to the current primary side voltage Vc of the capacitor group C110. switches the connection of the switch group S130 on the side. A similar procedure is subsequently executed to determine the final connection of the second switch group S130 on the LSB side.

In the next step ST170, the control circuit 150 determines the second digital signal _Y20 output from the SAR-ADC 70 based on the final connection of the second switch group S130. As described above, the second digital signal _Y20 is obtained by AD-converting the result of subtracting the DA-converted value of the first digital signal _Y10 from the output analog voltage _V10 of the integration circuit 110. FIG.

[Specific example of subtraction operation by capacitive DAC]
FIG. 6 is a diagram for explaining a specific example of the subtraction operation by the capacitive DAC. The capacitive DAC in FIG. 6 corresponds to a 3-bit binary code. It is assumed that the number of bits of the first digital signal _Y10 output from the quantizer 40 is 2 and its value is "11" (binary code). In this case, a first capacitor group C120 composed of two capacitors from the MBS side and a first switch group S120 composed of first switches SW2 and SW3 are used for the subtraction operation.

FIG. 6A corresponds to steps ST110 and ST120 in FIG. That is, the control circuit 150 turns on the input switch S100, connects the switch SW3 corresponding to the MSB to the positive reference voltage Vr, and connects each of the other switches SW0 to SW2 to the negative reference voltage -Vr. As a result, the voltage Vc of the input node of the comparator 140 becomes equal to the analog voltage _V10 output from the integration circuit 110, and the analog voltage _V10 can be sampled.

FIG. 6B corresponds to steps ST130 to ST150 in FIG. When the first digital signal _Y10 is "11" (binary code), the control circuit 150 connects each of the switches SW3 and SW2 of the first switch group S120 on the MSB side to the negative reference voltage -Vr. The control circuit 150 connects the switch SW1 of the second switch group S130 on the LSB side to the positive reference voltage Vr, and connects the switch SW0 to the negative reference voltage -Vr.

Since the charge leakage from the input switch S100, the switch group S110, the comparator 140, and the capacitor group C110 is so small that it can be ignored, the following equation (4) holds according to the law of conservation of charge. The left side of the following equation (4) is the charge generated on the primary side of the capacitor group C110 in the case of FIG. 6A. The right side of the following equation (4) is the charge generated on the primary side of the capacitor group C110 in the case of FIG. 6B. The voltage of the input node of the comparator 140 in the case of FIG. 6B is _VC .

Solving the above equation (4) for V _C yields the following equation (5). As shown in the following equation (5), the subtraction of the voltage 3×Vr/4, which is the DA conversion value of the first digital signal Y ₁₀ “11”, can be realized from the analog voltage V ₁₀ output from the integration circuit 110. I know there is.

After that, the differential voltage obtained by the above subtraction operation is AD-converted by successive approximation, and the LSB-side bit is determined as a result of the AD conversion. Specifically, in the state of FIG. 3B, the comparator 140 compares the voltage V _C of the above equation (5) with the comparison voltage (common voltage). The comparator 140 outputs "1" to the control circuit 150 when V _C ≧0, and outputs "0" to the control circuit 150 when V _C <0. Therefore, when the output of the comparator 140 is "1", the second digital signal _Y20 output from the SAR-ADC 70 is "1", and when the output of the comparator 140 is "0", the The output second digital signal _Y20 is "0". That is, the SAR-ADC 70 can realize AD conversion.

Here, the first digital signal Y ₁₀ output from the quantizer 40 is the upper 2 bits of the output digital signal Y of the ΔΣ modulator 10 . A second digital signal Y ₂₀ output from the SAR-ADC 70 is a digital signal corresponding to the lower 1 bit of the output digital signal Y of the ΔΣ modulator 10 . Therefore, it can be seen that the quantization error E ₂ of the SAR-ADC 70 is smaller than the quantization error E ₁ of the quantizer 40 .

[Technical effect of the delta-sigma modulator of the first embodiment]
As described above, according to the ΔΣ modulator 10 of Embodiment 1, the differential value of the second digital signal Y ₂₀ output from the SAR-ADC 70 is added to the first digital signal Y ₁₀ output from the quantizer 40. be done. Thereby, the quantization error of the output digital signal Y of the ΔΣ modulator 10 can be reduced.

Furthermore, according to the delta-sigma modulator 10 of the first embodiment, the circuit area and power consumption can be reduced as compared with the prior art. A description will be given below with reference to a comparative example.

FIG. 7 is a block diagram showing the configuration of a ΔΣ modulator 300 as a comparative example of FIG. 1. In FIG. The ΔΣ modulator 300 in FIG. 7 is provided with a digital/analog converter (mb-DAC) 360, a subtractor 390, and an analog/digital converter (ADC) 370 individually instead of the SAR-ADC 70 including the capacitive DAC 130. is different from the ΔΣ modulator 10 in FIG. DAC 360 also functions as DAC 60 in FIG. Since other configurations in FIG. 7 are common to those in FIG. 1, the same or corresponding parts are given the same reference numerals.

In FIG. 7, when the m-bit quantizer 40 is composed of a 1-bit quantizer and the m-bit DAC 360 is composed of a 1-bit DAC, the ΔΣ modulator 300 of FIG. It has the same configuration as the ΔΣ modulator disclosed in Japanese Patent No. 4357083 (Patent Document 1).

Here, the subtractor 390 calculates the difference between the analog voltage _V10 output from the integration circuit 110 and the first digital signal _Y10 output from the quantizer 40 that is DA-converted by the DAC360. Therefore, since the subtractor 390 is an analog signal subtractor, it is normally configured using an operational amplifier. As a result, circuit area and power consumption increase.

On the other hand, in the ΔΣ modulator 10 of the present embodiment, the DAC 360, subtractor 390 and ADC 370 are replaced with the SAR-ADC 70. FIG. In particular, DAC 360 and subtractor 390 are replaced with capacitive DAC 130 built into SAR-ADC 70 . Then, in the capacitive DAC 130, DA conversion of the first digital signal _Y10 output from the quantizer 40 and subtraction of the analog voltage _V10 output from the integration circuit 110 and the DA conversion value of the first digital signal _Y10 is realized. Therefore, according to such a configuration, a subtractor for analog signals using an operational amplifier is not required. As a result, circuit area and power consumption can be suppressed. It should be noted that simply incorporating a conventional successive approximation type AD converter cannot achieve the function of subtracting two input signals, so that the above-described effects of the present embodiment cannot be achieved.

[Modification of Embodiment 1]
In FIG. 1, even if the number n of the integrators 20 and the order of the differentiator 80 constituting the integrating circuit 110 are any number equal to or greater than 1, the above effects can be obtained. It is desirable that the number n of differentiators 80 and the order of the differentiators 80 are equal. In FIG. 3, the case where the number of integrators 20 is two and the order of the differentiator 80 is two has been described, but this is merely an example and the number and order are not limited to this case.

In FIG. 4, the case where the SAR-ADC 70 is a 7-bit AD converter and the number of bits of the quantizer 40, the DAC 60, and the first digital signal Y ₁₀ is 4 bits has been explained. In this case, the capacitance DAC 130 forming the SAR-ADC 70 consists of a 4-bit first capacitor group C120 and a first switch group S120 on the MSB side, and a 3-bit second capacitor group C130 and a second switch group S130 on the LSB side. Consists of These bit numbers are examples and are not intended to be limiting.

Similarly, FIG. 6 describes the case where the SAR-ADC 70 is a 3-bit AD converter, and the number of bits of the quantizer 40, DAC 60, and first digital signal _Y10 is 2 bits. In this case, the capacitance DAC 130 forming the SAR-ADC 70 consists of a 2-bit first capacitor group C120 and a first switch group S120 on the MSB side, and a 1-bit second capacitor group C130 and a second switch group S130 on the LSB side. Consists of These bit numbers are examples and are not intended to be limiting.

4 and 6, the quantizer 40, the first digital signal Y ₁₀ , the SAR-ADC 70, and the DAC 60 correspond to binary code digital signals. These devices and signals can achieve the aforementioned effects even if they correspond to other codes such as thermometer codes. An example of the thermometer code will be described in the second embodiment.

In the capacitive DAC 130 of the SAR-ADC 70 described above, each switch constituting the switch group S110 was selectively connectable to the reference voltage Vr and the reference voltage -Vr. On the other hand, each switch constituting the switch group S110 may be configured to be selectively connectable to the positive reference voltage Vr and the reference voltage, or selectively connectable to the negative reference voltage -Vr and the reference voltage. may be configured to be connectable to Even with such a configuration, the same effect as described above can be obtained. Note that such an example will be described in the third embodiment.

Capacitor group C110 forming capacitance DAC 130 may be configured using a scaling capacitance. Thereby, the capacity ratio can be lowered.

Embodiment 2.
[SAR-ADC configuration]
FIG. 8 is a circuit diagram showing the configuration of the SAR-ADC provided in the ΔΣ modulator of the second embodiment. The capacitive DAC 130 of the SAR-ADC 70 of FIG. 8 is a modified example of the capacitive DAC 130 of the SAR-ADC 70 of FIG. 4, and is configured to correspond to the thermometer code instead of the binary code. In the ΔΣ modulator of the second embodiment, the configuration of SAR-ADC 70 other than capacitance DAC 131 is the same as that of ΔΣ modulator 10 of the first embodiment shown in FIGS. 1, 3, and 4, and description thereof will not be repeated. .

Capacitance DAC 131 of SAR-ADC 70 in FIG. 8 includes capacitor group C110 and switch group S110 as in FIG. The capacitor group C110 is composed of a first capacitor group C120 and a second capacitor group C130. The switch group S110 includes a first switch group S120 corresponding to the first capacitor group C120 and a second switch group S130 corresponding to the second capacitor group C130. The first capacitor group C120 and the first switch group S120 are used for DA conversion of the first digital signal _Y10 output from the quantizer 40 . The second capacitor group C130 and the second switch group S130 are used to AD-convert a differential voltage obtained by subtracting the DA-converted value of the first digital signal _Y10 from the analog voltage _V10 by successive approximation.

In the second embodiment, the m-bit first digital signal _Y10 output from the quantizer 40 is represented by a thermometer code. Therefore, the first capacitor group C120 corresponds to the thermometer code, and each capacitor has the same capacity. The second capacitor group C130 includes two capacitors each having half the capacity of each capacitor forming the first capacitor group C120.

Here, the first capacitor group C120 and the first switch group S120 include more capacitors and switches than m capacitors and corresponding m switches required for DA conversion of the m-bit first digital signal _Y10 . It is characterized by having For example, in FIG. 8, if the number of bits of the first digital signal _Y10 is 3 bits, the first capacitor group C120 and the first switch group S120 have one switch SW2 corresponding to one extra capacitor. are doing. Advantages of such a configuration will be described later.

[Operation of SAR-ADC]
Next, the operation of the ΔΣ modulator provided with the SAR-ADC 70 of FIG. 8 will be described. The basic procedure is the same as the flowchart of FIG. 5 of Embodiment 1, but there is a partial change in step ST150.

9 is a diagram for explaining the operation of the SAR-ADC in FIG. 8. FIG. 9A corresponds to steps ST110 and ST120 in FIG. 5, and FIG. 9B corresponds to steps ST130 to ST150 in FIG.

First, the control circuit 150 sets the switch so that the total value of charges generated on the secondary side of the capacitor group C110 becomes zero when it is assumed that a comparison voltage (common voltage) is applied to the primary side of the capacitor group C110. A group S110 is set (ST110). For example, as shown in FIG. 9A, half of the switches SW4 and SW5 in the first switch group S120 are connected to the positive reference voltage Vr, and the remaining half of the switches SW2 and SW3 in the first switch group S120 are connected to the negative voltage. is connected to the reference voltage -Vr of . Furthermore, half of the switches SW1 in the second switch group S130 are connected to the positive reference voltage Vr, and the remaining half of the switches SW0 in the second switch group S130 are connected to the negative reference voltage Vr.

Furthermore, the control circuit 150 switches the input switch S100 to the closed state (ST120). As a result, the analog voltage _V10 output from the integrating circuit 110 is sampled to the primary side of the capacitor group C110. Either of steps ST110 and ST120 described above may be executed first, or may be executed simultaneously.

Next, as shown in FIG. 9B, the control circuit 150 switches the input switch S100 to the open state (step ST130). After that, the control circuit 150 controls the total value of the charges on the secondary side of the second capacitor group C130 to be zero when it is assumed that the comparison voltage (common voltage) is applied to the primary side of the second capacitor group C130. , connect the corresponding second switch group S130 (ST140). As shown in FIG. 9A, the switch SW1 is already connected to the positive reference voltage Vr, and the switch SW0 is already connected to the negative reference voltage -Vr. Therefore, in FIG. 9B, there is no need to change the connections of the switches SW0 and SW1 that constitute the second switch group S130.

Next, control circuit 150 switches connection of m switches in first switch group S120 based on m-bit first digital signal _Y10 output from quantizer 40 (ST150). In the case of FIG. 9B, since the first digital signal _Y10 is a 3-bit signal "111" in the thermometer code, the control circuit 150 connects each of the switches SW3 to SW5 to the negative reference voltage -Vr. do. Furthermore, the control circuit 150 sets the remaining switches SW2 that constitute the first switch group S120 to an open state, that is, to a state that they are connected neither to the positive reference voltage Vr nor to the negative reference voltage -Vr. In this respect, the control procedure of this embodiment differs from step ST150 in FIG. 5 of the first embodiment.

By switching the connection of the first switch group S120, a difference voltage V _C obtained by subtracting the DA conversion value of the first digital signal _Y10 from the analog voltage V10, which is the output of the integrating circuit ₁₁₀ , is applied to the primary side of the capacitor group C110. is generated.

Specifically, in the case of FIG. 9, the following equation (6) holds according to the law of conservation of charge. The left side of the following equation (6) is the charge generated on the primary side of the capacitor group C110 (C120, C130) in the case of FIG. 9A. The right side of the following equation (6) is the charge generated on the primary side of the capacitor group C110 (C120, C130) in the case of FIG. 9B. In FIG. 9B, the voltage of the input node of comparator 140 is _VC . In FIG. 9B, since the switch SW2 is open, the charge accumulated on the primary side of the capacitor corresponding to the switch SW2 remains 2C(V ₁₀ +Vr) and does not change.

Solving the above equation (6) for V _C yields the following equation (7). As shown in the following equation (7), the subtraction of the voltage Vr, which is the DA conversion value of "11" as the first digital signal _Y10 , from the analog voltage V10 output from the integrating circuit ₁₁₀ is realized. I understand.

Comparing the above equation (7) with the equation (5) in the case of the first embodiment, in the case of the first embodiment, the voltage value corresponding to the case where the first digital signal Y ₁₀ is "11" is referred to. While it could not be equal to the voltage Vr, in the case of the second embodiment, the voltage value corresponding to "11" can be equal to the reference voltage Vr. This is the advantage of providing extra capacitors and switches in the first capacitor group C120 and the first switch group S120 as described above and opening the extra switches during DA conversion of the first digital signal _Y10 . . In other words, in both the first and second embodiments, it is necessary to increase the reference voltage Vr as the absolute value of the input analog signal X increases. There is an advantage that it can be handled even if it is left as it is.

After the above subtraction operation, the differential voltage obtained by the subtraction is AD-converted by successive approximation method. Bits on the LSB side are determined as a result of AD conversion (ST160, ST170). This AD conversion operation is the same as in the case of the first embodiment, and description thereof will not be repeated.

[Technical effect of the second embodiment]
In the second embodiment, the case where the first digital signal _Y10 output from the quantizer 40 is a digital value expressed in thermometer code has been described. In this case, the first capacitor group C120 and the second capacitor group C130 of the capacitive DAC 131 forming the SAR-ADC 70 are also formed of capacitors having the same capacitance value according to the thermometer code. Even with such a configuration, as in the case of the first embodiment, subtraction of the DA conversion value of the first digital signal _Y10 from the analog voltage _V10 output from the integrating circuit 110 can be realized in the capacitive DAC 131. FIG. Thereby, the circuit area and power consumption can be suppressed.

Furthermore, in the second embodiment, extra capacitors and switches are provided in the first capacitor group C120 and the first switch group S120, and the extra switches are controlled to be open during DA conversion of the first digital signal _Y10 . . The advantages of this are as follows. By modifying the above equation (1), the analog voltage _V10 output from the integration circuit 110 is expressed by the following equation (8).

According to the above equation (8), as the absolute value of the input analog signal X increases, the absolute value of the analog voltage _V10 increases. As a result, the absolute value of the reference voltage Vr or -Vr used for DA conversion of the first digital signal _Y10 in the SAR-ADC 70 also needs to be increased. However, in the case of the first embodiment, the DA conversion value of the first digital signal _Y10 is at most a factor times the reference voltage Vr (this factor is smaller than 1), and the reference voltage Vr can be used as it is. could not. On the other hand, in the case of the second embodiment, there is an advantage that the maximum value of the DA conversion value of the first digital signal _Y10 can be made equal to the reference voltage Vr.

[Modification of Embodiment 2]
8 and 9, the first digital signal _Y10 is described as a 3-bit signal, but the number of bits of the first digital signal _Y10 may be arbitrary. Therefore, the number of capacitors and switches in first capacitor group C120 and first switch group S120 that make up capacitance DAC 131 and the number of capacitors and switches that make up second capacitor group C130 and second switch group S130 can also be set arbitrarily. .

Further, the effect of providing the extra capacitors and switches in the first capacitor group C120 and the first switch group S120 can also be obtained in the binary code configuration described in the first embodiment. Specific examples will be described below.

FIG. 10 is a diagram for explaining a modification of the second embodiment. The configuration of capacitive DAC 130 shown in FIG. 10 is the same as the configuration of capacitive DAC 130 of FIG. In FIG. 10, the number of bits of the first digital signal _Y10 output from the quantizer 40 is 1 and its value is "1".

FIG. 10A corresponds to FIG. 6A. In FIG. 10A, analog voltage _V10 output from integration circuit 110 is sampled.

Referring to FIG. 10B, when first digital signal _Y10 is "1" (binary code), control circuit 150 sets switch SW3 of first switch group S120 on the MSB side to negative reference voltage -Vr. connect to. Also, the control circuit 150 opens the extra switch SW2 of the first switch group S120. The connections of the switches SW0 and SW1 of the second switch group S130 on the LSB side are the same as in the case of FIG. 6B.

In the cases of FIGS. 10A and 10B, the following equation (9) holds according to the law of conservation of electric charge. The left side of the following equation (9) is the charge generated on the primary side of the capacitor group C110 (C120, C130) in the case of FIG. 10(A). The right side of the following equation (9) is the charge generated on the primary side of the capacitor group C110 (C120, C130) in the case of FIG. 10(B). The voltage of the input node of the comparator 140 in the case of FIG. 10B is _VC . Also, in FIG. 10B, the switch SW2 is in an open state, so the charge accumulated on the primary side of the capacitor corresponding to the switch SW2 remains 2C (V ₁₀ +Vr) and does not change.

Solving the above equation (9) for V _C yields equation (7) above. 9A and 9B, from the analog voltage _V10 output from the integrating circuit 110, the voltage which is the DA conversion value of " ₁ " which is the value of the first digital signal Y10 Subtraction of Vr has been realized.

Embodiment 3.
In the first and second embodiments, each switch SW that constitutes the capacitive DACs 130 and 131 can be selectively connected to a positive reference voltage Vr higher than the reference voltage (ground voltage) and a negative reference voltage −Vr lower than the reference voltage. was configured as In the third embodiment, a case where each switch SW can be selectively connected to the reference voltage and the negative reference voltage -Vr and a case where it can be selectively connected to the reference voltage and the positive reference voltage Vr will be described.

[When each switch SW can be selectively connected to the reference voltage and the negative reference voltage -Vr]
FIG. 11 is a diagram for explaining the first configuration example of the third embodiment. Specifically, in the capacitive DAC 132 shown in FIG. 11, each switch SW that constitutes the first switch group S120 and the second switch group S130 can be selectively connected to the reference voltage (ground voltage) and the negative reference voltage -Vr. . The configuration of ΔΣ modulator 10 other than capacitance DAC 132 of SAR-ADC 70 is the same as that described with reference to FIGS. 1, 3 and 4 of the first embodiment, and description thereof will not be repeated.

FIG. 12 is a flow chart showing the operation of the SAR-ADC of FIG. Steps ST210 and ST220 in FIG. 12 correspond to FIG. 11A, and step ST240 in FIG. 12 corresponds to FIG. 11B. The operation of the SAR-ADC in the first configuration example of the third embodiment will be described below with reference to FIGS. 11 and 12. FIG.

First, in step ST210, the control circuit 150 of the SAR-ADC 70 connects the switches SW0 to SW3 of the first switch group S120 and the second switch group S130 to the reference voltage (ground voltage).

In the next step ST220, the control circuit 150 samples the analog voltage _V10 output from the integrating circuit 110 to the primary side of the capacitor group C110 by switching the input switch S100 to the closed state. Either of steps ST210 and ST220 described above may be executed first, or both may be executed simultaneously.

In the next step ST230, the control circuit 150 switches the input switch S100 to the open state. As a result, a charge corresponding to the analog voltage _V10 is stored on the primary side of the capacitor group C110.

In the next step ST240, the control circuit 150 switches connection of each switch SW of the first switch group S120 according to the first digital signal _Y10 output from the quantizer 40. FIG. In the case of FIG. 11B, the first digital signal _Y10 is a 2-bit binary code signal and is "11". In this case, the control circuit 150 connects each of the switches SW2 and SW3 forming the first switch group S120 to the negative reference voltage -Vr. The switches SW0 and SW1 constituting the second switch group S130 remain connected to the reference voltage (ground voltage) and are not changed in connection. By switching the connection of the first switch group S120, a differential voltage obtained by subtracting the DA conversion value of the first digital signal _Y10 from the analog voltage _V10 output from the integrating circuit 110 is applied to the primary side of the capacitor group C110. generated.

In the cases of FIGS. 11A and 11B, the following equation (10) holds according to the law of conservation of electric charge. The left side of the following equation (10) is the charge generated on the primary side of the capacitor group C110 in the case of FIG. 11(A). The right side of the following equation (10) is the charge generated on the primary side of the capacitor group C110 in the case of FIG. 11(B). The voltage of the input node of the comparator 140 in the case of FIG. 11B is _VC .

Solving the above equation (10) for V _C yields equation (5) above. As shown in equation (5), subtraction of the voltage 3×Vr/4, which is the DA conversion value of “11” as the first digital signal Y ₁₀ , can be realized from the analog voltage V ₁₀ output from the integration circuit 110. It can be seen that

In subsequent step S250, the control circuit 150 brings the voltage value on the primary side of the capacitor group C110 as close as possible to the reference voltage by switching the second switch group S130 using the binary search principle. Thereby, the AD conversion value of the lower bit corresponding to the second switch group S130 is determined.

Specifically, in FIG. 11B, assume that the current voltage Vc on the primary side of capacitor group C110 is positive (for example, the output of comparator 140 corresponds to high level). In this case, the control circuit 150 connects the switch SW1 to the reference voltage -Vr to further subtract the DA conversion value of "1", which is the lower 1 bit, from the current voltage value on the primary side of the capacitor group C110. . As a result, if the voltage Vc on the primary side is still positive, "1" is determined as the lower 1 bit, and if the voltage Vc on the primary side changes to negative, "0" is determined as the lower 1 bit.

On the other hand, in FIG. 11B, assume that the current voltage Vc on the primary side of the capacitor group C110 is negative. In this case, the control circuit 150 switches the connection of the switch SW2 corresponding to the least significant bit in the first switch group S120 to "0" and connects the switch SW1 to the reference voltage -Vr. As a result, if the voltage Vc on the primary side is still negative, the lower 1 bit is minus "1", and if the voltage Vc on the primary side changes to positive, "0" is determined as the lower 1 bit. .

After that, in step ST260, the control circuit 150 determines the second digital signal _Y20 output from the SAR-ADC 70 based on the final connection of the switch group S110. As described above, the second digital signal _Y20 is a value obtained by AD-converting the difference voltage obtained by subtracting the DA-converted value of the first digital signal _Y10 from the analog voltage _V10 output from the integration circuit 110 .

[When each switch SW can be selectively connected to the reference voltage and the positive reference voltage Vr]
FIG. 13 is a diagram for explaining a second configuration example of the third embodiment. Specifically, in the capacitive DAC 133 shown in FIG. 13, each switch SW that constitutes the first switch group S120 and the second switch group S130 can be selectively connected to the reference voltage (ground voltage) and the positive reference voltage Vr. The configuration of ΔΣ modulator 10 other than capacitance DAC 133 of SAR-ADC 70 is the same as that described with reference to FIGS. 1, 3 and 4 of the first embodiment, and description thereof will not be repeated.

FIG. 14 is a flow chart showing the operation of the SAR-ADC of FIG. Steps ST310 to ST330 in FIG. 14 correspond to FIG. 13A, and step ST350 in FIG. 14 corresponds to FIG. 13B. The operation of the SAR-ADC in the second configuration example of the third embodiment will be described below with reference to FIGS. 13 and 14. FIG.

First, in step ST310, the control circuit 150 of the SAR-ADC 70 connects the switches SW0 and SW1 of the second switch group S130 to the reference voltage (ground voltage).

In the next step ST320, the control circuit 150 switches connection of each switch SW of the first switch group S120 according to the first digital signal _Y10 output from the quantizer 40. FIG. In the case of FIG. 13A, the first digital signal _Y10 is a 2-bit binary code signal and is "11". In this case, the control circuit 150 connects each of the switches SW2 and SW3 forming the first switch group S120 to the positive reference voltage Vr.

In the next step ST330, the control circuit 150 samples the analog voltage _V10 output from the integrating circuit 110 to the primary side of the capacitor group C110 by switching the input switch S100 to the closed state. The above steps ST310 to ST330 may be executed in any order, and at least two steps may be executed simultaneously.

In the next step ST340, the control circuit 150 switches the input switch S100 to the open state. This preserves the charge on the primary side of capacitor group C110.

In the next step ST350, the control circuit 150 switches each switch SW of the first switch group S120 to the reference voltage (ground voltage). The switches SW0 and SW1 constituting the second switch group S130 remain connected to the reference voltage (ground voltage) and are not changed in connection. By switching the connection of the first switch group S120, a differential voltage obtained by subtracting the DA conversion value of the first digital signal _Y10 from the analog voltage _V10 output from the integrating circuit 110 is applied to the primary side of the capacitor group C110. generated.

In the cases of FIGS. 13A and 13B, the following equation (11) holds according to the law of conservation of charge. The left side of the following equation (11) is the charge generated on the primary side of the capacitor group C110 in the case of FIG. 13(A). The right side of the following equation (11) is the charge generated on the primary side of the capacitor group C110 in the case of FIG. 13(B). The voltage of the input node of the comparator 140 in the case of FIG. 13B is _VC .

Solving the above equation (11) for V _C yields equation (5) above. As shown in equation (5), subtraction of the voltage 3×Vr/4, which is the DA conversion value of “11” as the first digital signal Y ₁₀ , can be realized from the analog voltage V ₁₀ output from the integration circuit 110. It can be seen that

In the next step S250, the control circuit 150 brings the voltage value on the primary side of the capacitor group C110 as close as possible to the reference voltage by switching the second switch group S130 using the binary search principle. Thereby, the AD conversion value of the lower bit corresponding to the second switch group S130 is determined.

Specifically, in FIG. 13B, assume that the current voltage Vc on the primary side of the capacitor group C110 is negative (for example, the output of the comparator 140 corresponds to low level). In this case, the control circuit 150 connects the switch SW1 to the reference voltage Vr to add the DA conversion value of "1", which is the lower 1 bit, to the current voltage value on the primary side of the capacitor group C110. As a result, if the voltage Vc on the primary side is still negative, "1" is determined as the lower 1 bit, and if the voltage Vc on the primary side changes to positive, "0" is determined as the lower 1 bit.

On the other hand, in FIG. 13B, it is assumed that the current voltage Vc on the primary side of the capacitor group C110 is positive. In this case, the control circuit 150 returns to step ST320 and switches the connection of the switch SW2 corresponding to the least significant bit in the first switch group S120 to "0". Furthermore, in step S360, the switch SW1 is connected to the reference voltage Vr. As a result, if the voltage Vc on the primary side is still positive, the lower 1 bit is minus "1", and if the voltage Vc on the primary side changes to negative, "0" is determined as the lower 1 bit. .

After that, in step ST360, the control circuit 150 determines the second digital signal _Y20 output from the SAR-ADC 70 based on the final connection of the switch group S110. As described above, the second digital signal _Y20 is a value obtained by AD-converting the difference voltage obtained by subtracting the DA-converted value of the first digital signal _Y10 from the analog voltage _V10 output from the integration circuit 110 .

[Technical effect of the third embodiment]
In the third embodiment, each switch SW forming the capacitive DAC 132 can be selectively connected to the reference voltage and the negative reference voltage −Vr, and each switch SW forming the capacitive DAC 133 can be connected to the reference voltage and the positive reference voltage Vr. A case where it is possible to selectively connect to Even with such a configuration, as in the case of the first embodiment, subtraction of the DA conversion value of the first digital signal _Y10 from the analog voltage _V10 output from the integrating circuit 110 is realized in the capacitor DACs 132 and 133. can. Thereby, the circuit area and power consumption can be suppressed.

[Modification of Embodiment 3]
11 and 13, the second switch group S130 is configured to be selectively connectable to one of the positive reference voltage Vr, the negative reference voltage -Vr, and the reference voltage (ground voltage). good too. This allows voltage to be added or subtracted from the current primary of capacitor group C110.

The embodiments disclosed this time should be considered as examples and not restrictive in all respects. The scope of this application is indicated by the scope of claims rather than the above description, and is intended to include all changes within the meaning and scope of equivalence to the scope of claims.

10 ΔΣ modulator, 20 integrator, 30 subtractor, 40 quantizer, 50 delay device, 60, 130 to 133 DAC, 70 SAR ADC, 80 differentiator, 81 adder, 110 integration circuit, 140 comparator, 150 control circuit , 200 analog/digital converter, 210 digital filter, C110 capacitor group, C120 first capacitor group, C130 second capacitor group, S100 input switch, S110 switch group, S120 first switch group, S130 second switch group, SW, SW to SW7 switch, V ₁₀ analog voltage, V _C difference voltage, Vr, -Vr reference voltage, X input analog signal, Y output digital signal, Y ₁₀ first digital signal, Y ₂₀ second digital signal.

Claims (10)

A delta-sigma modulator,
an integration circuit that performs an integration operation on the difference between the input analog signal and the feedback signal;
a quantizer that generates an m-bit (m≧1) first digital signal by quantizing the analog voltage that is the integration result of the integration circuit;
a delayer for delaying the first digital signal;
a DA (Digital to Analog) converter that generates the feedback signal by converting the first digital signal delayed by the delay device into an analog signal;
A successive approximation AD (Analog to Digital) converter including a capacitance DA converter,
The capacitive DA converter samples the analog voltage output from the integration circuit and DA converts the first digital signal, thereby subtracting the DA conversion value of the first digital signal from the analog voltage. generating a differential voltage, wherein the successive approximation AD converter AD-converts the differential voltage to generate a second digital signal;
The ΔΣ modulator further
a differentiator that differentiates the second digital signal;
A delta-sigma modulator comprising an adder that generates an output digital signal by adding the differentiation result of the differentiator and the first digital signal. The capacitive DA converter is
a plurality of capacitors in number greater than m;
a plurality of switches individually connected to one end of each of the plurality of capacitors;
each of the plurality of switches configured to selectively connect the one end of the corresponding capacitor to one of a plurality of different reference voltages;
The capacitive DA converter performs DA conversion of the first digital signal using m capacitors out of the plurality of capacitors and corresponding m switches out of the plurality of switches. The delta-sigma modulator according to claim 1. The first digital signal is a digital signal represented by a binary code,
the capacities of the plurality of capacitors are binary weighted;
3. The delta-sigma modulator according to claim 2, wherein m-th capacitors counted from the larger one of said plurality of capacitors are used for DA conversion of said first digital signal. The successive approximation type AD converter uses the remaining capacitors excluding m capacitors used for DA conversion of the first digital signal and the corresponding switches among the plurality of capacitors, and calculates the difference by a successive approximation method. 4. The delta-sigma modulator according to claim 2, which AD-converts a voltage. The plurality of reference voltages include a first reference voltage higher than a common voltage and a second reference voltage lower than the common voltage,
The capacitive DA converter converts the one end of each of the plurality of capacitors to the first reference voltage or the second voltage via a corresponding switch when sampling the analog voltage output from the integration circuit. A ΔΣ modulator according to any one of claims 2 to 4, connected to a reference voltage. The successive approximation AD converter, when DA-converting the first digital signal, among the plurality of switches excluding m switches used for DA-converting the first digital signal, 6. The ΔΣ modulator according to claim 5, wherein at least one of is opened. The delta-sigma modulator according to any one of claims 2 to 4, wherein said plurality of reference voltages include a ground voltage. The integration circuit has a configuration unit including a subtractor and an integrator for integrating the subtraction result, and the configuration units are connected in series in one or more stages,
the subtractor in the first stage subtracts the feedback signal from the input analog signal;
the subtractor in the second and subsequent stages subtracts the feedback signal from the integration result of the integrator in the previous stage;
8. The ΔΣ modulator according to any one of claims 1 to 7, wherein the integration result of said final stage integrator is input to said quantizer as said analog voltage. 9. The ΔΣ modulator according to claim 8, wherein the number of stages of said building blocks in said integration circuit is equal to the order of said differentiator. A ΔΣ modulator according to any one of claims 1 to 9;
and a digital filter that cuts off a high frequency band of the output digital signal of the ΔΣ modulator.

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