JP2023114211A - wiring board - Google Patents

Abstract

To provide wiring boards with excellent signal transmission quality.SOLUTION: A wiring board 1 of the embodiment has a plurality of alternately stacked insulating layers 11a, 11b, 11c and conductor layers 12a, 12b, 12c, a plurality of sub-substrates 10A, 10B, 10C, which are spaced apart from each other in the planar direction, and a sealing layer 100 filling a gap between the plurality of sub-substrates 10A, 10B, 10C and bonding the plurality of sub-substrates 10A, 10B, 10C together. At least two of the plurality of sub-substrates 10A, 10B, 10C have conductor layers of different thicknesses from each other.SELECTED DRAWING: Figure 1

Description

The present invention relates to wiring boards.

The semiconductor package disclosed in Patent Document 1 has a plurality of connection structures. A plurality of connection structures form an integrated semiconductor package by filling the gaps between them with a passivation layer. The connection structure includes insulating layers and redistribution layers (conductor layers) that are alternately laminated, and the insulating layers and redistribution layers of each of the plurality of connection structures have approximately the same thickness.

U.S. Patent Application Publication No. 2020/0185357

The conductor layers (redistribution layers) included in each of the plurality of connection structures included in the semiconductor package disclosed in Patent Document 1 have approximately the same thickness. Since the conductor thickness is substantially uniform within the semiconductor package, it may be difficult to form wiring having different characteristics within the same semiconductor package.

A wiring board of the present invention comprises a plurality of insulating layers and conductor layers that are alternately laminated, a plurality of sub-boards spaced apart from each other in a plane direction, and filling the gaps between the plurality of sub-boards, and a sealing layer that bonds the plurality of sub-substrates. At least two sub-boards among the plurality of sub-boards have the conductor layers with different thicknesses.

According to embodiments of the present invention, a wiring board includes multiple sub-boards having different conductor thicknesses. A plurality of wiring patterns having characteristics matching the signals to be transmitted can be provided in the same wiring board. A wiring board with excellent signal transmission quality can be provided.

1 is a cross-sectional view showing an example of a wiring board according to an embodiment of the present invention; FIG. FIG. 4 is a cross-sectional view showing another example of the wiring board according to the embodiment of the present invention; FIG. 4 is a cross-sectional view showing a method for manufacturing a wiring board according to one embodiment of the present invention; FIG. 4 is a cross-sectional view showing a method for manufacturing a wiring board according to one embodiment of the present invention; FIG. 4 is a cross-sectional view showing a method for manufacturing a wiring board according to one embodiment of the present invention; FIG. 4 is a cross-sectional view showing a method for manufacturing a wiring board according to one embodiment of the present invention; FIG. 4 is a cross-sectional view showing a method for manufacturing a wiring board according to one embodiment of the present invention;

A wiring board according to one embodiment of the present invention will be described with reference to the drawings. It should be noted that the drawings referred to hereinafter are not intended to show the exact proportions of the constituent elements, but are drawn so that the features of the present invention can be easily understood. FIG. 1 shows a cross-sectional view of a wiring board 1 as an example of a structure that the wiring board of one embodiment can have.

As shown in FIG. 1, the wiring board 1 has two surfaces, an F surface FS and a B surface BS opposite to the F surface FS, which are two surfaces extending in a direction perpendicular to the thickness direction. are doing. The wiring board 1 has a plurality of laminates 10A, 10B, and 10C. The laminate 10A has a plurality of conductor layers 12a and insulating layers 11a. The laminate 10B has a plurality of conductor layers 12b and insulating layers 11b. The laminate 10C has a plurality of conductor layers 12c and insulating layers 11c. A plurality of laminates 10A, 10B, and 10C each have a laminate structure similar to a so-called buildup portion in a buildup wiring board.

The plurality of laminates 10A, 10B, and 10C integrally constitute the wiring substrate 1 by being joined together. The multiple laminates 10A, 10B, 10C are also referred to as sub-substrates 10A, 10B, 10C. The sub-board 10A is also called the first sub-board 10A, the sub-board 10B is also called the second sub-board 10B, and the sub-board 10C is also called the third sub-board 10C.

The plurality of sub-boards 10A, 10B, 10C are arranged apart from each other in the planar direction. Note that the “planar direction” means the horizontal direction in the drawing in which the insulating layers 11a, 11b, 11c and the conductor layers 12a, 12b, 12c extend, that is, the thickness direction of the wiring board 1. means a direction substantially orthogonal to A sealing layer 100 fills the gaps between the sub-substrates 10A, 10B, and 10C. The sealing layer 100 bonds the sub-substrates 10A, 10B and 10C together, thereby integrating the sub-substrates 10A, 10B and 10C.

Each of the plurality of sub-boards 10A, 10B, and 10C has first surfaces 10AF, 10BF, and 10CF as two surfaces extending in the plane direction, and a second surface 10AS opposite to the first surfaces 10AF, 10BF, and 10CF. , 10BS, 10CS. The conductor layers 12a, 12b, 12c forming the first surfaces 10AF, 10BF, 10CF of the plurality of sub-boards 10A, 10B, 10C include conductor pads 12ap, 12bp, 12cp as their conductor patterns. The conductor layers 12a, 12b, 12c forming the second surfaces 10AS, 10BS, 10CS of the plurality of sub-boards 10A, 10B, 10C include conductor pads 12ac, 12bc, 12cc as their conductor patterns.

In the illustrated example, the sealing layer 100 fills the gaps between the plurality of sub-substrates 10A, 10B and 10C and covers the upper surfaces (first surfaces) 10AF, 10BF and 10CF of the plurality of sub-substrates 10A, 10B and 10C. is also covered. Openings 100a, 100b, 100c corresponding to the positions of the conductor pads 12ap, 12bp, 12cp are formed in the sealing layer 100 covering the first surfaces 10AF, 10BF, 10CF. The upper surfaces of the conductor pads 12ap, 12bp and 12cp are exposed at the bottoms of the openings 100a, 100b and 100c.

The F surface FS of the wiring board 1 includes the surface (upper surface) of the sealing layer 100, the inner surfaces of the openings 100a, 100b, and 100c formed in the sealing layer 100, and the conductor pads 12ap exposed from the openings 100a, 100b, and 100c. , 12 bp, and 12 cp. The F surface FS is a component mounting surface on which external electronic components EDa, EDb, EDc1, and EDc2 can be mounted. function as component connection pads that can be connected to the connection pads of EDa, EDb, EDc1, and EDc2.

In the illustrated example, the B surface BS is composed of the surface (lower surface) of the sealing layer 100 and the surfaces (second surfaces) 10AS, 10BS and 10CS of the sub-substrates 10A, 10B and 10C. Conductive pads 12ac, 12bc and 12cc of the sub-boards 10A, 10B and 10C are exposed on the B side BS. The B surface BS of the wiring board 1 can be a connection surface that is connected to an external element when the wiring board 1 itself is mounted on an external element such as an external wiring board (for example, a motherboard of any electrical device). . The contact pads 12ac, 12bc, 12cc can be connected with any substrate, electrical component, mechanical component, or the like.

In the description of the wiring board of the present embodiment, the side closer to the B-side BS where the conductor pads 12ac, 12bc, and 12cc of each component of the wiring board 1 are exposed is referred to as "lower", "downward", or "lower side". , and the side far from the B-side BS, that is, the F-side FS with respect to the B-side BS is referred to as "upper", "upper", or "upper". Therefore, in the description of each element constituting the wiring board 1, the outward surface of the B surface BS in the thickness direction of the wiring substrate 1 is also referred to as the "lower surface", and the outward surface of the F surface FS is also referred to as the "upper surface". Also called

A plurality of sub-boards 10A, 10B, and 10C forming the wiring board 1 have component mounting areas EDAa, EDAb, and EDAc, respectively. The component connection pads 12ap forming the component mounting area EDAa of the first sub-board 10A are connected to the external electronic component EDa. The component connection pads 12bp forming the component mounting area EDAb of the second sub-board 10B are connected to the external electronic component EDb. The component connection pads 12cp forming the component mounting area EDAc of the third sub-board 10C are connected to the external electronic components EDc1 and EDc2. That is, the component connection pads 12ap, 12bp, and 12cp of the sub-boards 10A, 10B, and 10C respectively have individual component mounting areas EDAa, EDAb, and EDAc for each of the sub-boards 10A, 10B, and 10C.

Examples of the electronic components EDa, EDb, EDc1, and EDc2 that can be mounted on the wiring board 1 include electronic components such as semiconductor integrated circuit devices and active components such as transistors. In the drawing, the electronic component EDa that can be mounted on the first sub-board 10A can be, for example, a memory element such as HBM (High Bandwidth Memory) or DRAM (Dynamic Random Access Memory). Also, the electronic component EDb that can be mounted on the second sub-board 10B can be, for example, a communication component such as an integrated circuit for high-speed communication. Also, the electronic components EDc1 and EDc2 that can be mounted on the third sub-board 10c can be, for example, integrated circuits such as logic chips incorporating logic circuits, or processors such as MPUs (Micro Processor Units).

The sub-board 10A is formed by alternately laminating a plurality of insulating layers 11a and conductor layers 12a, and the two conductor layers 12a formed on both sides in the thickness direction of one insulating layer 11a separate the via conductors 13a. connected through The sub-board 10B is formed by alternately laminating a plurality of insulating layers 11b and conductor layers 12b. connected through The sub-board 10C is formed by alternately laminating a plurality of insulating layers 11c and conductor layers 12c. connected through

The plurality of sub-boards 10A, 10B, and 10C have approximately the same thickness. In the illustrated example, the first sub-board 10A and the second sub-board 10B are composed of five insulating layers 11a and 11b and six conductor layers 12a and 12b, respectively. It is composed of six insulating layers 11c and seven conductive layers 12c. That is, in the wiring board of the embodiment, the thicknesses of the insulating layers and the conductor layers forming each of the plurality of sub-boards can be different. In particular, regarding the conductor layer, the thickness (conductor thickness) of the conductor layer is different in at least two sub-boards among the plurality of sub-boards. As a result, it is possible to form a circuit having characteristics corresponding to the electronic components that can be mounted on each of the plurality of sub-boards, for each sub-board.

In the wiring board 1 of the example shown in FIG. 1, the thicknesses of the conductor layers 12a, 12b, 12c are different in all the sub-boards 10A, 10B, 10C. Specifically, the minimum thicknesses of the conductor layers 12a, 12b and 12c of the first, second and third sub-boards 10A, 10B and 10C are different from each other.

More specifically, the conductor layer 12a of the first sub-board 10A on which the memory element can be mounted includes wiring patterns for power supply and has a relatively large thickness. , has a value of less than 25 μm. The conductor layer 12b of the second sub-board 10B on which an integrated circuit for high-speed communication can be mounted includes a conductor pattern for high-speed communication, and the minimum conductor thickness is the conductor thickness of the conductor layer 12a of the first sub-board 10A. and the minimum value of the conductor thickness is, for example, 15 μm or more and less than 20 μm. The conductor layer 12c of the third sub-board 10C on which the processor can be mounted has a relatively fine conductor pattern, and the minimum conductor thickness is greater than the minimum conductor thickness of the conductor layer 12b of the second sub-board 10B. The minimum value is, for example, 5 μm or more and less than 15 μm.

The conductor layer 12c included in the third sub-board 10C has the smallest conductor thickness among the conductor layers 12a, 12b, and 12c of the plurality of sub-boards 10A, 10B, and 10C. It can contain patterns. For example, in the third sub-board 10C, the minimum line width of the wiring pattern of the conductor layer 12c is 10 μm or less, and the minimum line-to-line distance is 10 μm or less. In the illustrated example, the minimum line width of the wiring patterns of the conductor layers 12a and 12b on the first sub-board 10A and the second sub-board 10B is 15 μm or more, and the minimum line-to-line distance is 15 μm or more. be. That is, the third sub-board 10C can have the finest wiring pattern in the wiring board 1 as the wiring pattern of the conductor layer 12c.

That is, among the plurality of illustrated sub-boards 10A, 10B, and 10C, the minimum conductor thickness of the second sub-board 10B is smaller than the minimum conductor thickness of the first sub-board 10A. The minimum conductor thickness of 10C is smaller than the minimum conductor thickness of second sub-board 10B. As a result, wiring patterns having characteristics suitable for the electronic components EDa, EDb, EDc1, and EDc2 that can be mounted may be formed on the first, second, and third sub-boards 10A, 10B, and 10C, respectively. . Signal transmission characteristics in each conductor layer of the first, second, and third sub-boards 10A, 10B, and 10C can be improved.

In the illustrated example, among the plurality of sub-boards 10A, 10B, and 10C, the first sub-board 10A is adjacent to the third sub-board 10C on one side in the planar direction. The second sub-board 10B is adjacent to the third sub-board 10C on the side opposite to the first sub-board 10A in the plane direction. That is, the third sub-board 10C is interposed between the first sub-board 10A having the conductor layer 12a that can include the power supply pattern and the second sub-board 10B that can include the circuit pattern for high-speed communication.

As illustrated, each of the plurality of sub-boards 10A, 10B, 10C has two surfaces (first surfaces 10AF, 10BF, 10CF and second surfaces 10AS, 10BS, 10CS) extending in the plane direction. At least one of the surfaces has a concave portion. A part of the adjacent sub-boards is fitted into the concave portions 10Ar, 10Br, 10Cr1 and 10Cr2 of each of the plurality of sub-boards 10A, 10B and 10C.

Specifically, the first sub-substrate 10A has a recess 10Ar on its first surface 10AF, and a part of the third sub-substrate 10C enters the recess 10Ar. The second sub-board 10B has a recess 10Br on its first surface 10BF, and a portion of the third sub-board 10C enters the recess 10Br. The third sub-board 10C has recesses 10Cr1 and 10Cr2 on its second surface 10CS. A part of the first sub-board 10A enters the recess 10Cr1, and a part of the second sub-board 10B enters the recess 10Cr2. is entering.

Undesirable deformation of the wiring board 1 may be suppressed by having such a configuration in the arrangement of the plurality of sub-boards 10A, 10B, and 10C. Specifically, for example, an external force applied along the thickness direction to an arbitrary sub-board of the wiring board 1 is effectively applied to the adjacent sub-board via the inner surface of the concave portion of the adjacent sub-board. can be stress distributed. By effectively dispersing the stress among the plurality of sub-boards 10A, 10B, and 10C, the occurrence of undesirable deformation such as warpage in the wiring board 1 may be suppressed.

The insulating layers 11a, 11b, 11c forming the sub-boards 10A, 10B, 10C, respectively, can be formed using an insulating resin such as epoxy resin, bismaleimide triazine resin (BT resin), or phenol resin. Each insulating layer 11a, 11b, 11c may contain a reinforcing material (core material) such as glass fiber and/or an inorganic filler such as silica or alumina.

Moreover, the insulating layers 11a, 11b, and 11c may contain a thermoplastic resin. In particular, the insulating layer 11b constituting the second sub-board 10B, which includes wiring patterns for high-speed communication and is capable of transmitting relatively high-frequency signals, contains a thermoplastic resin having a relatively low dielectric constant and dielectric loss tangent. is preferred. Specifically, among thermoplastic resins, relatively low dielectric constant and dielectric loss tangent, fluororesin, liquid crystal polymer (LCP), fluoroethylene resin (PTFE), polyester resin (PE), modified polyimide resin (MPI ). The dielectric loss of high frequency signals carried through the conductor layer 12b can be kept relatively small.

The sealing layer 100 that fills the gaps between the sub-boards 10A, 10B, 10C may contain, for example, a photosensitive epoxy resin. As with the insulating layers 11a, 11b, and 11c, the sealing layer 100 is made of heat-resistant resin such as fluororesin, liquid crystal polymer (LCP), fluoroethylene resin (PTFE), polyester resin (PE), and modified polyimide resin (MPI). It may contain a plastic resin.

Conductor layers 12a, 12b, 12c and via conductors 13a, 13b, 13c included in sub-boards 10A, 10B, 10C are formed using any metal such as copper or nickel. and/or a metal film formed by plating, sputtering, or the like. Conductive layers 12a, 12b, 12c and via conductors 13a, 13b, 13c are shown in FIG. 1 as having a single layer structure, but may have a multilayer structure having two or more metal layers. Conductive layers (12a, 12b, 12c) and via conductors (13a, 13b, 13c) may have, for example, a two-layer structure including a metal foil or electroless plated film and an electrolytic plated film.

FIG. 2 shows a wiring board 2 as another example of the wiring board of the embodiment. Wiring board 2 is different from wiring board 1 described above with reference to FIG. It has the same structure except that it is formed on the opposite side in the thickness direction of the substrate.

Specifically, in the wiring board 1 described with reference to FIG. 1, the recesses 10Cr1 and 10Cr2 of the third sub-board 10C are formed only on the second surface 10CS, and the recess 10Br of the second sub-board 10B is formed only on the second surface 10CS. It is formed on the first surface 10BF. On the other hand, in the wiring board 2, the recess 10Cr1 of the third sub-board 10C is formed on the second surface 10CS, and the recess 10Cr2 is formed on the first surface 10CF. Also, the recess 10Br of the second sub-board 10B is formed on the second surface 10BS.

That is, in the third sub-board 10C, recesses 10Cr1 and 10Cr2 are formed on both the first surface 10CF and the second surface 10CS, and the recesses 10Cr1 and 10Cr2 are formed on the adjacent sub-substrates 10A and 10B, respectively. Some are stuck. With such a configuration, in particular, an external force that may be applied along the thickness direction of the third sub-board 10C may be more effectively distributed to the adjacent sub-boards 10B and 10A. Specifically, the external force applied to the third sub-board 10C from the upper side (first surface 10CF side) is dispersed to the first sub-board 10A via the recess 10Cr1 into which the first sub-board 10A enters, An external force that may be applied to the third sub-substrate 10C from the surface 10CS side) may be effectively dispersed to the second sub-substrate 10B via the recess 10Cr2. Undesirable deformation such as warping of the wiring board 1 may be effectively suppressed.

Next, a method of manufacturing a wiring board will be described with reference to FIGS. 3A to 3E, taking the case of manufacturing the wiring board 1 shown in FIG. 1 as an example. First, as shown in FIG. 3A, a support plate SB is prepared. An adhesive layer BL is provided on one surface in the thickness direction of the support plate SB. For the support plate SB, for example, a prepreg obtained by impregnating a core material such as glass fiber with a resin material such as epoxy resin, a metal plate containing copper, or a plate-like body such as ceramics or glass can be used.

As will be described later with reference to FIG. 3C, the second surfaces 10AS, 10BS, and 10CS of the sub-substrates 10A, 10B, and 10C and the sealing layer 100 are in close contact with the adhesive layer BL on the opposite side of the support plate SB. . The adhesive layer BL exhibits a stronger adhesive force with the support plate SB than with the second surfaces 10AS, 10BS, and 10CS of the sub-substrates 10A, 10B, and 10C and the sealing layer 100. A material that can be used is preferably used. The material forming the adhesive layer BL should not lose adhesiveness between the second surfaces 10AS, 10BS, 10CS of the sub-substrates 10A, 10B, 10C and the sealing layer 100 by any treatment such as heating. may For example, an acrylic resin adhesive may be included as the material of the adhesive layer BL.

Next, as shown in FIG. 3B, the sub-substrates 10A, 10B, and 10C are arranged on the support plate SB via the adhesive layer BL. The sub-boards 10A, 10B, 10C are arranged with the second surfaces 10AS, 10BS, 10CS having their contact pads 12ac, 12bc, 12cc facing the support plate SB. The sub-boards 10A, 10B, and 10C are arranged such that the third sub-board 10C is adjacent to the first sub-board 10A, and the second sub-board 10B is adjacent to the third sub-board 10C on the opposite side of the first sub-board 10A. are arranged so as to have a gap between them.

For example, first, the first sub-substrate 10A and the second sub-substrate 10B are arranged at desired positions on the adhesive layer BL. Next, a part of the third sub-board 10C on the side of the first sub-board 10A enters the concave portion 10Ar formed in the first surface 10AF of the first sub-board 10A, and the first surface 10BF of the second sub-board 10B is formed. The third sub-substrate 10C is arranged on the adhesive layer BL such that a part of the third sub-substrate 10C on the second sub-substrate 10B side enters the formed recess 10Br.

The first, second, and third sub-boards 10A, 10B, and 10C can be separately formed by, for example, a general build-up wiring board manufacturing method. The first, second, and third sub-boards 10A, 10B, and 10C, for example, form conductor layers 12a, 12b, and 12c including conductor pads 12ac, 12bc, and 12cc on the base plate, and It can be formed by stacking insulating layers 11a, 11b, 11c and conductor layers 12a, 12b, 12c. After lamination is completed, the sub-boards 10A, 10B, 10C are removed from the base plate, and recesses 10Ar, 10Br, 10Cr1, 10Cr2 are formed in the sub-boards 10A, 10B, 10C, respectively. For example, recesses 10Ar, 10Br, 10Cr1, and 10Cr2 can be formed by cutting a part of the sub-board by router processing.

An encapsulation layer 100 is then formed, as shown in FIG. 3C. For example, a frame (not shown) is formed on the support plate SB to enclose a desired space including the regions where the sub-substrates 10A, 10B, and 10C are arranged, and the sealing layer 100 is placed inside the frame. A constituent resin material (for example, epoxy resin) is injected in a fluid state. The injected resin material fills the gaps between the sub-boards 10A, 10B and 10C and completely covers the first surfaces 10AF, 10BF and 10CF. After the injected resin material hardens, the frame body is removed, resulting in the state shown in FIG. 3B. A sealing layer 100 fills the gaps between the first, second, and third sub-substrates 10A, 10B, 10C, respectively, and bonds the sub-substrates 10A, 10B, 10C together. The top surface of the cured encapsulation layer 100 can be polished by any method, such as chemical-mechanical polishing, if desired.

Openings 100a, 100b, 100c are then formed in the sealing layer 100, as shown in FIG. 3D. The openings 100a, 100b, 100c can be formed by photolithography, for example. Openings 100a exposing the upper surfaces of the component connection pads 12ap, 12bp, 12cp on the bottom by exposure and development using a mask having an opening pattern corresponding to the component connection pads 12ap, 12bp, 12cp of the sub-boards 10A, 10B, 10C. , 100b, 100c are formed.

Next, as shown in FIG. 3E, the adhesive layer BL and the sub-substrates 10A, 10B, 10C are separated, and the support plate SB is removed. By removing the support plate SB, the B surface BS composed of the second surfaces 10AS, 10BS, and 10CS of the sub-substrates 10A, 10B, and 10C and the surface (lower surface) of the sealing layer 100 is exposed. The exposed surfaces of the component connection pads 12ap, 12bp, 12cp and the conductor pads 12ac, 12bc, 12cc are coated with Au, Ni/Au, Ni/Pd/Au by electroless plating, solder leveler, spray coating, or the like. , solder, or a heat-resistant preflux may be formed as a surface protective film (not shown). The wiring board 1 shown in FIG. 1 is completed through the above steps.

The wiring substrates of the embodiments are not limited to those having the structures illustrated in each drawing, and the structures, shapes, and materials illustrated in this specification. For example, the number of sub-boards that a wiring board can have is not limited to three. A wiring board may have four or more sub-boards. Also, each sub-board may have any number of resin insulating layers and wiring layers. All the sub-boards constituting the wiring board may each have different numbers of insulating layers and conductor layers.

1, 2 wiring board 10A sub-board (first sub-board)
10B sub-board (second sub-board)
10C sub-board (third sub-board)
10AF, 10BF, 10CF First surface 10AS, 10BS, 10CS Second surface 11a, 11b, 11c Insulating layers 12a, 12b, 12c Conductive layers 12ap, 12bp, 12cp Conductive pads (component connection pads)
12ac, 12bc, 12cc Conductor pad 100 Sealing layer 100a, 100b, 100c Opening 10Ar, 10Br, 10Cr1, 10Cr2 Concave portion FS F surface BS B surface SB Support plate BL Adhesive layer EDAa, EDAb, EDAc Component mounting area

Claims (9)

a plurality of sub-boards comprising a plurality of alternately laminated insulating layers and conductor layers, the sub-boards being spaced apart from each other in a planar direction;
a sealing layer that fills gaps between the plurality of sub-substrates and bonds the plurality of sub-substrates;
A wiring board having
At least two sub-boards among the plurality of sub-boards have the conductor layers with different thicknesses. 2. The wiring board according to claim 1, wherein at least two of said plurality of sub-boards have different minimum thicknesses of said conductor layers. 3. The wiring board according to claim 2, wherein the minimum value of the thickness of the conductor layer is different for each of the plurality of sub-boards. 2. The wiring board according to claim 1, wherein each of said plurality of sub-boards has a component connection pad, and said component connection pads possessed by each of said sub-boards are separate component mounting areas for each of said sub-boards. constitutes 2. The wiring board according to claim 1, wherein each of two adjacent sub-boards among the plurality of sub-boards has a portion of the adjacent sub-board on at least one of the two surfaces extending in the planar direction. has a recess into which the 6. The wiring board according to claim 5, wherein a sub-board adjacent to two of said plurality of sub-boards has said recesses on each of said two surfaces. 3. The wiring board according to claim 2, wherein the plurality of sub-boards includes a first sub-board, a second sub-board, and a third sub-board, and the conductor layer included in the second sub-board is The minimum thickness of the conductor layer included in the first sub-board is smaller than the minimum thickness of the conductor layer included in the first sub-board, and the minimum thickness of the conductor layer included in the third sub-board is the second sub-board. is smaller than the minimum value of the thickness of the conductor layer included in the 8. The wiring board according to claim 7, wherein said first sub-board and said third sub-board are adjacent to each other, and said third sub-board and said second sub-board are adjacent to each other. 8. The wiring board according to claim 7, wherein said insulating layer included in said second sub-board contains a thermoplastic resin.

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