JP2023111047A - regulator circuit - Google Patents

Abstract

To provide a regulator circuit that detects generation of a reverse current with high accuracy to suppress the reverse current.SOLUTION: A regulator circuit 100 comprises a reverse current preventing transistor MP2 connected in series with an output transistor MP1, and a reverse current prevention controlling circuit 111. In the reverse current prevention controlling circuit 111, a first voltage drop circuit 108 generates a first voltage VLV1 by subtracting a first drop voltage from a supply voltage VI supplied to an input node NIN. A second voltage drop circuit 109 generates a second voltage VLV2 by subtracting from an output voltage VO a second drop voltage which is equal to a voltage drop generated across the output transistor MP1 when a reverse current flows. A comparison circuit 110 compares a differential voltage between the second voltage VLV2 and the first voltage VLV1 with a threshold. The first drop voltage is set equal to the threshold. The reverse current preventing transistor MP2 is turned on and off based on a comparison result of the comparison circuit 110.SELECTED DRAWING: Figure 1

Description

The present disclosure relates to regulator circuits.

A regulator circuit is known as a circuit that outputs a desired DC voltage required by a system or the like from an externally supplied DC voltage. When a regulator circuit generates an output voltage lower than a supply voltage, a linear regulator typified by an LDO (Low Drop Out) circuit is used.

A linear regulator uses an active device in the output section to produce an output voltage and an output current. Bipolar transistors or MOS (Metal Oxide Semiconductor) transistors, for example, are used as the active elements. These transistors are formed on a semiconductor substrate.

During normal operation of the linear regulator, the output voltage is lower than the supply voltage. However, if the supply voltage becomes lower than the output voltage due to usage conditions or a sudden drop in the supply voltage, current flows back from the output terminal to the power supply. In order to prevent this backflow, the output section of the regulator circuit is provided with a backflow prevention circuit that switches the output section to an off state when it is detected that the supply voltage is lower than the output voltage.

Japanese Patent Laying-Open No. 2019-125082 (Patent Document 1) provides a regulator circuit including a backflow prevention circuit that suppresses the influence of fluctuations in process conditions and fluctuations in operating temperature to enable highly accurate backflow determination. With the goal. Specifically, the regulator circuit of this document includes a backflow prevention transistor connected between an input terminal and an output stage transistor, and a backflow prevention control unit that controls the backflow prevention transistor. The backflow prevention controller includes a first transistor and a second transistor, which are depletion type P-type MOS transistors. The source of the first transistor is connected to the output terminal of the regulator circuit, and the gate of the first transistor is connected to the input terminal of the regulator circuit. The source of the second transistor is connected to its gate and the drain of the first transistor, and the drain of the second transistor is grounded. The on/off of the backflow prevention transistor is controlled by the drain voltage of the first transistor.

JP 2019-125082 A

In the regulator circuit disclosed in Patent Document 1, it is necessary to provide depletion type first and second transistors. For this reason, a process for manufacturing the depletion-type transistor is required in addition to the process for manufacturing the enhancement-type transistor, resulting in a long manufacturing period. As a result, manufacturing costs increase and production efficiency deteriorates.

The present disclosure has been made in consideration of the above problems. One of the objects of the present disclosure is to provide a regulator circuit that can be configured with ordinary enhancement-type transistors without using depletion-type transistors and that has a backflow prevention circuit that is less susceptible to fluctuations in process conditions and operating temperature. is to provide

The regulator circuit of one embodiment includes an input node, an output node, a reference node, an output transistor, an error amplifier, a backflow prevention transistor, a first constant current source, a second constant current source, A first voltage drop circuit, a second voltage drop circuit, and a comparison circuit are provided. The input node receives an externally supplied voltage. The output node outputs an output voltage. A reference node receives a reference voltage. The output transistor is connected between the input node and the output node. The error amplifier controls the amount of current passing through the output transistor based on the voltage difference between the reference voltage and the output voltage or its divided voltage. The backflow prevention transistor is connected in series with the output transistor between the input node and the output node. A first constant current source generates a first constant current. A second constant current source generates a second constant current. The first voltage drop circuit is connected in series with the first constant current source between the input node and the reference node, and provides a first voltage drop corresponding to the first constant current from the supply voltage. to generate a voltage of The second voltage drop circuit generates a second voltage by subtracting from the output voltage a second drop voltage equal to the voltage drop across the output transistor when a reverse current flows from the output node to the input node. The comparison circuit is connected in series with the second constant current source and the second voltage drop circuit between the output node and the reference node, and converts the difference voltage between the second voltage and the first voltage into a second voltage. It is compared with a threshold corresponding to constant current. The backflow prevention transistor is controlled to be opened or closed based on the comparison result of the comparison circuit. The values of the first constant current and the second constant current are determined so that the first voltage drop equals the threshold.

According to the above embodiment, the control circuit comprising the first constant current source, the second constant current source, the first voltage drop circuit, the second voltage drop circuit, and the comparison circuit controls the reverse current flow. The opening and closing of the prevention transistor is controlled. The above control circuit can be configured using normal enhancement-type transistors without using depletion-type transistors, and can be configured to be less susceptible to fluctuations in process conditions and operating temperature.

1 is a circuit diagram showing a configuration of a regulator circuit including a backflow prevention circuit according to Embodiment 1; FIG. FIG. 2 is a diagram showing a voltage dividing circuit extracted from FIG. 1; FIG. 10 is a diagram showing the configuration of an output circuit without a backflow prevention transistor MP2; 3 is a diagram showing the configuration of an output circuit of the present embodiment provided with a backflow prevention transistor MP2; FIG. FIG. 10 is a diagram showing a configuration of a regulator circuit including a backflow prevention circuit according to Embodiment 2; FIG. 10 is a diagram showing the configuration of a regulator circuit including a backflow prevention circuit according to Embodiment 3; FIG. 10 is a diagram showing the configuration of a regulator circuit including a backflow prevention circuit according to Embodiment 4;

Hereinafter, each embodiment will be described in detail with reference to the drawings. The same reference numerals are given to the same or corresponding parts, and the description thereof will not be repeated.

Embodiment 1.
[Schematic configuration of regulator circuit]
FIG. 1 is a circuit diagram showing the configuration of a regulator circuit 100 having a backflow prevention circuit according to the first embodiment. Referring to FIG. 1, regulator circuit 100 includes constant voltage source 101, error amplifier 102, output circuit 103, voltage dividing circuit 104, output capacitance C1, input node (Node) NIN, output node NOUT, ground node GND, and A backflow prevention control circuit 111 is provided. The backflow prevention circuit 120 is composed of the backflow prevention transistor MP<b>2 of the output circuit 103 and the backflow prevention control circuit 111 .

As shown in FIG. 1, an input node NIN is supplied with a voltage VI from the outside, and this supply voltage VI is input to an output circuit 103 . Output circuit 103 receives supply voltage VI, generates desired output voltage VO according to the voltage output from constant voltage source 101, and outputs generated output voltage VO to output node NOUT. The generated output voltage VO is input to the voltage dividing circuit 104 and also to the backflow prevention control circuit 111 .

Ground node GND receives a ground voltage as a reference voltage. The ground node GND is also called a reference node. Output capacitor C1 is connected between output node NOUT and ground node GND.

The output circuit 103 includes an output transistor MP1 that drives the output voltage VO, and a backflow prevention transistor MP2. In the case of FIG. 1, the output transistor MP1 and the backflow prevention transistor MP2 are formed of P-type MOS transistors and are connected in series between the input node NIN and the output node NOUT. The output voltage of the error amplifier 102 is input to the gate of the output transistor MP1. This controls the output voltage and output current of the output transistor MP1. A control voltage from the backflow prevention control circuit 111 is input to the gate of the backflow prevention transistor MP2. This control voltage controls opening and closing of the backflow prevention transistor MP2. Details of the operation of output circuit 103 will be described later with reference to FIGS.

FIG. 2 is a diagram showing the voltage dividing circuit 104 extracted from FIG. The voltage dividing circuit 104 divides the output voltage VO to generate a divided voltage, and outputs the generated divided voltage as a feedback voltage VFB used for gate voltage control of the output transistor MP1. Voltage dividing circuit 104 in FIG. 2 is shown as an example of a voltage dividing circuit, and includes resistance elements R1 and R2 connected in series between output node NOUT and ground node GND. Assuming that the resistance values of the resistance elements R1 and R2 are r1 and r2, respectively, the feedback voltage VFB is
VFB=VO×r2/(r1+r2) (1)
is represented by

Returning to FIG. 1, the connection and function of error amplifier 102 will be described. A reference voltage VREF generated by the constant voltage source 101 is input to the inverting input terminal (− side) of the error amplifier 102 . A feedback voltage VFB is input to the non-inverting input terminal (+ side) of the error amplifier 102 . That is, the non-inverting input terminal (+ side) of the error amplifier 102 is connected to the connection node N2 between the resistance elements R1 and R2. The output terminal of the error amplifier 102 is connected to the gate of the output transistor MP1 forming the output circuit 103 . As a result, the output voltage VO of the output circuit 103 is adjusted so that the reference voltage VREF and the feedback voltage VFB are equal. By performing feedback control on the output voltage VO as described above, even if the load current output from the output node NOUT increases or decreases, the current supply capability of the output circuit 103 is adjusted to keep the output voltage VO constant. drool. That is, the constant voltage output function of regulator circuit 100 is realized.

[Configuration and Operation of Output Circuit]
Next, the configuration and operation of output circuit 103 will be described in more detail. FIG. 3 is a diagram showing the configuration of the output circuit 203 when the backflow prevention transistor MP2 is not provided.

Referring to FIG. 3, output transistor MP1 forming output circuit 203 is formed of a P-type MOS transistor. The source S of the output transistor MP1 is connected to the input node NIN, and the drain D is connected to the output node NOUT. Also, the control voltage VGMP1 output from the error amplifier 102 is input to the gate G of the output transistor MP1. In the case of a MOS transistor, a source S and a back gate B (also called body, substrate, or bulk) are directly connected. Also, the parasitic diode D1 is formed such that the direction from the drain D to the back gate B is the forward direction.

In normal use, the output voltage VO output from the output node NOUT is lower than the voltage VI externally supplied to the input node NIN. Therefore, the parasitic diode D1 existing between the drain D and the back gate B of the output transistor MP1 is in a reverse bias state. As a result, no reverse current flows from the output node NOUT to the input node NIN via the parasitic diode D1.

However, when the voltage VI externally supplied to the input node NIN drops, a reverse current may occur. Specifically, when the voltage difference between the output voltage VO and the supply voltage VI is greater than the forward voltage Vfd1 of the parasitic diode D1 (VO−VI>Vfd1), the parasitic diode D1 becomes forward biased. As a result, a reverse current flows from the output node NOUT to the input node NIN.

FIG. 4 is a diagram showing the configuration of the output circuit 103 of this embodiment provided with the backflow prevention transistor MP2.

The backflow prevention transistor MP2 is composed of a P-type transistor and is connected in series with the output transistor MP1 between the input node NIN and the output node NOUT. As shown in FIG. 4, the source S of the backflow prevention transistor MP2 is connected to the output node NOUT side, and the drain D is connected to the input node NIN side. A control voltage VGMP2 output from the backflow prevention control circuit 111 is input to the gate G of the backflow prevention transistor MP2. Generally, in the case of a MOS transistor, the source S and the back gate B are directly connected. Also, the parasitic diode D2 is formed so that the direction from the drain D to the back gate B is the forward direction.

In normal use, the output voltage VO output from the output node NOUT is lower than the voltage VI externally supplied to the input node NIN. In this case, the backflow prevention transistor MP2 is controlled to be always on. Therefore, the drain current flowing between the source S and the drain D of the output transistor MP1 according to the output voltage VGMP1 of the error amplifier 102 flows from the input node NIN to the output node NOUT via the anti-backflow transistor MP2.

On the other hand, when the voltage VI externally supplied to the input node NIN drops and the voltage difference between the supply voltage VI and the output voltage VO exceeds the forward voltage Vfd1 of the parasitic diode D1, a reverse current occurs. Therefore, before this voltage difference is reached, the backflow prevention transistor MP2 is controlled to be turned off by the output signal from the backflow prevention control circuit. This cuts off the current flowing between the source S and the drain D of the output transistor MP1. Here, since the parasitic diode D2 of the backflow prevention transistor MP2 is connected in the opposite direction to the parasitic diode D1 of the output transistor MP1, both the parasitic diodes D1 and D2 are not forward-biased. Therefore, when the backflow prevention transistor MP2 is controlled to be turned off, no current path occurs between the input node NIN and the output node NOUT.

1 and 3, the output transistor MP1 and the backflow prevention transistor MP2 are connected so that the source S of the output transistor MP1 and the source S of the backflow prevention transistor MP2 are directly connected. Conversely, the output transistor MP1 and the backflow prevention transistor MP2 may be connected so that the drain D of the output transistor MP1 and the drain D of the backflow prevention transistor MP2 are directly connected. In this case, the source S of the output transistor MP1 is connected to the input node NIN, and the source of the backflow prevention transistor MP2 is connected to the output node NOUT.

As described above, the output transistor MP1 is connected between the output node NOUT and the input node NIN such that the direction from the output node NOUT to the input node NIN is the forward direction of the parasitic diode D1. The backflow prevention transistor MP2 is connected in series with the output transistor MP1 between the output node NOUT and the input node NIN such that the direction from the input node NIN to NOUT is the forward direction of the parasitic diode D2. Thus, by controlling the backflow prevention transistor MP2 to be turned off, it is possible to prevent the current from flowing back from the output node NOUT to the input node NIN.

[Configuration of backflow prevention control circuit]
Next, the configuration of the backflow prevention control circuit 111 will be described. Referring to FIG. 1, backflow prevention control circuit 111 includes first constant current source 106 that generates first constant current I1, second constant current source 105 that generates second constant current I2, and first constant current source 105 that generates second constant current I2. voltage drop circuit 108, a second voltage drop circuit 109, and a comparison circuit 110.

In FIG. 1, the connection node of the output circuit 103, the voltage dividing circuit 104 and the output node NOUT is assumed to be a node N3. Voltage drop circuit 108 and constant current source 106 are connected in series between input node NIN and ground node GND in this order. Voltage drop circuit 109, comparison circuit 110 and constant current source 105 are connected in series between node N3 and ground node GND in this order. A connection node N4 between the comparison circuit 110 and the constant current source 105 is connected to the gate of the backflow prevention transistor MP2.

A voltage drop circuit 108 subtracts a first drop voltage ΔV1 corresponding to the current value generated by the constant current source 106 from the supply voltage VI to generate a first voltage VLV1. In the case of FIG. 1, the voltage drop circuit 108 is composed of a diode-connected P-type MOS transistor MP5 (third field effect transistor). As shown in FIG. 1, the source S of the P-type MOS transistor MP5 is connected to the input node NIN. The drain D of the P-type MOS transistor MP5 is connected to the constant current source 106 and its own gate G.

The voltage between the source S and the drain D of the P-type MOS transistor MP5 constituting the voltage drop circuit 108 (equal to the voltage between the source S and the gate G) is equal to the drop voltage ΔV1. Therefore, voltage drop ΔV1 has a value corresponding to current value I1 generated by constant current source 106 . In the diode-connected P-type MOS transistor MP5, when the drain-source voltage (that is, the gate-source voltage) exceeds the threshold voltage Vth of the P-type MOS transistor MP5, current flows through

The voltage drop circuit 109 generates a second voltage VLV2 by subtracting the second drop voltage ΔV2 from the output voltage VO. The voltage drop ΔV2 is set to be equal to the voltage drop across the output transistor MP1 when a reverse current flows from the output node NOUT to the input node NIN.

In the case of FIG. 1, the voltage drop circuit 109 is composed of a diode-connected P-type MOS transistor MP3 (first field effect transistor). As shown in FIG. 1, the drain D of the P-type MOS transistor MP3 is connected to the node N3 and its own gate G. As shown in FIG. The source S of the P-type MOS transistor MP3 is connected to the source S of the P-type MOS transistor MP4 forming the comparison circuit 110. FIG. According to the specific configuration example of the voltage drop circuit 109, the P-type MOS transistor MP3 is always in an off state, so that the forward current of the parasitic diode D3 of the P-type MOS transistor MP3 flows through the voltage drop circuit 109. Therefore, the voltage drop ΔV2 is equal to the forward voltage of the parasitic diode D3.

The comparison circuit 110 compares the differential voltage between the second voltage VLV2 and the first voltage VLV1 with a threshold Vth corresponding to the current value of the constant current source 105 . The anti-backflow transistor MP2 is controlled to be turned off when the differential voltage (VLV2-VLV1) is greater than or equal to the threshold value Vth. Here, by setting the current values of the constant current sources 105 and 106 so that the voltage drop ΔV1 of the voltage drop circuit 108 is equal to the threshold value Vth, when a reverse current occurs in the output circuit 103, the backflow prevention transistor MP2 can be controlled to be off.

In the case of FIG. 1, the comparison circuit 110 is composed of a P-type MOS transistor MP4 (fourth field effect transistor). As shown in FIG. 1, the source S of the P-type MOS transistor MP4 forming the comparison circuit 110 is connected to the source S of the P-type MOS transistor MP3 forming the voltage drop circuit 109. FIG. The drain D of the P-type MOS transistor MP4 is connected to the constant current source 105 and to the gate of the anti-backflow transistor MP2. The gate G of the P-type MOS transistor MP4 is connected to the drain D of the P-type MOS transistor MP5 forming the voltage drop circuit 108, that is, the connection node N5 between the voltage drop circuit 108 and the constant current source 106.

According to the specific configuration example of the comparison circuit 110 described above, when the voltage between the source S and the gate G of the P-type MOS transistor MP4 becomes equal to or higher than the threshold voltage of the P-type MOS transistor MP4, the P-type MOS transistor MP4 is turned on. . As a result, the voltage of the drain D of the P-type MOS transistor MP4 forming the comparison circuit 110 rises, so that the anti-backflow transistor MP2 is turned off. Therefore, the above threshold Vth is equal to the threshold voltage of the P-type MOS transistor MP4.

[Operation of backflow prevention control circuit]
Next, the operation of the backflow prevention control circuit 111 will be described in more detail.

First, as described above, a reverse current is generated in the output circuit 103 because the voltage difference between the supply voltage VI applied to the input node NIN and the output voltage VO output from the output node NOUT is the output of the output circuit 103. This is when the forward voltage Vfd1 of the parasitic diode D1 of the transistor MP1 is exceeded. That is, the voltage drop that occurs in the output transistor MP1 when the reverse current occurs is equal to the forward voltage Vfd1 of the parasitic diode D1 in the case of the first embodiment. Specifically, the conditions under which backflow occurs are:
VO−VI>Vfd1 (2)
is represented by In the above equation (2), when VI and Vfd1 are transposed and rearranged, the conditional expression for occurrence of backflow is:
VO−Vfd1>VI (3)
is obtained. The left side of the above equation (3) represents the voltage obtained by subtracting the forward voltage Vfd1 of the parasitic diode D1 of the output transistor MP1 from the output voltage VO. On the other hand, the right side of the above equation (3) indicates the supply voltage VI input from the input node NIN.

Here, the configuration of the comparison circuit for performing the comparison of the above equation (3) is considered. If the supply voltage VI is used as the power supply voltage of the comparison circuit, the power supply voltage of the comparison circuit and the input voltage to be compared become the same voltage, so the input stage of the comparison circuit needs to be configured as a rail-to-rail type. , the circuit scale of the comparison circuit becomes large. In order to avoid this problem, a voltage drop circuit 108 using the gate-source voltage of the MOS transistor is used to make the input voltage to the comparison circuit less than the supply voltage VI. Specifically, in the configuration of the voltage drop circuit 108 of FIG. 1, the gate-source voltage VGSP5 of the P-type transistor MP5 is subtracted from both sides of the backflow generation conditional expression (3) above. Then, the backflow occurrence conditional expression of the above equation (3) is
VO-Vfd1-VGSP5>VI-VGSP5 (4)
is rewritten as

As described above, in the P-type MOS transistor MP5 forming the voltage drop circuit 108, the gate G and the drain D are connected to each other. equal to voltage VLV1. i.e.
VLV1=VI-VGSP5 (5)
holds.

On the other hand, a method of realizing the voltage on the left side of the backflow occurrence conditional expression (4) will be described. The source voltage of the P-type MOS transistor MP4 forming the comparison circuit 110 is assumed to be VLV2. The P-type MOS transistor MP4 turns on when the gate-source voltage VGSP4 exceeds the threshold voltage of the P-type MOS transistor MP4. In this case, the current generated by the constant current source 105 flows through the P-type MOS transistor MP3 forming the voltage drop circuit 109 via the P-type MOS transistor MP4. Since the P-type MOS transistor MP3 is off as described above, a current path is formed through the parasitic diode D3 of the P-type MOS transistor MP3. Assuming that the forward bias voltage of the parasitic diode D3 of the P-type MOS transistor MP3 is Vfd3, the source voltage VLV2 of the P-type MOS transistor MP4 is
VLV2=VO-Vfd3 (6)
is represented by

Here, the condition for turning on the P-type MOS transistor MP4 constituting the comparison circuit 110 is obtained by using the absolute value of the threshold voltage VGSP4(th) of the P-type MOS transistor MP4.
VLV2−VLV1>|VGSP4(th)| (7)
is represented by In the above equation (7), VLV2 represents the source voltage of the P-type MOS transistor MP4, and VLV1 represents the gate voltage of the P-type MOS transistor MP4. Therefore, the left side of the above equation (7) is equal to the gate-source voltage VGSP4 of the P-type MOS transistor MP4.

By substituting VLV1 of the above formula (5) and VLV2 of the above formula (6) into the above formula (7),
VO−Vfd3−VI+VGSP5>|VGSP4(th)| (8)
is obtained. By transforming the above equation (8),
VO−Vfd3−|VGSP4(th)|>VI−VGSP5 (9)
is obtained.

The above formula (9) is compared with the backflow generation conditional formula (4). The output transistor MP1 and the P-type MOS transistor MP3 forming the voltage drop circuit 109 have the same configuration. That is, the dimensions, materials, device manufacturing processes, etc. are all the same. In this case, the forward voltage Vfd1 of the parasitic diode D1 of the output transistor MP1 in the above equation (4) is equal to the forward voltage Vfd3 of the parasitic diode D3 of the P-type MOS transistor MP3 in the above equation (9). In addition, the effect of the element manufacturing process and the effect of the operating temperature act similarly on the output transistor MP1 and the P-type MOS transistor MP3. Therefore, these influences can be suppressed.

Further, the P-type MOS transistor MP5 forming the voltage drop circuit 108 and the P-type MOS transistor MP4 forming the comparison circuit 110 have the same structure. That is, the dimensions, materials, device manufacturing processes, etc. are all the same. In this case, the threshold voltage of the P-type MOS transistor MP5 and the threshold voltage of the P-type MOS transistor MP4 are equal. Therefore, the current generated by each of constant current sources 105 and 106 is equal to the absolute value of gate-source voltage VGSP5 of P-type MOS transistor MP5 and threshold voltage VGSP4(th) of P-type MOS transistor MP4. You can adjust the value. In addition, the effect of the device manufacturing process and the effect of the operating temperature act similarly on the P-type MOS transistor MP5 and the P-type MOS transistor MP4. Therefore, these influences can be suppressed.

As described above, with the configuration of the backflow prevention control circuit 111, the backflow generation condition can be determined with high accuracy. In the above description, the P-type MOS transistor MP5 and the P-type MOS transistor MP4 do not necessarily have the same configuration. When the two transistors have different configurations, the constant current source 105 is adjusted so that the gate-source voltage VGSP5 of the P-type MOS transistor MP5 and the threshold voltage VGSP4(th) of the P-type MOS transistor MP4 have the same absolute value. , 106 has the same effect.

[Effect of Embodiment 1]
As described above, according to the regulator circuit 100 including the backflow prevention circuit of the first embodiment, unlike the case of Patent Document 1, the backflow generation condition is determined with high accuracy without using a depletion type P-type MOS transistor. can. Therefore, it is not necessary to add a manufacturing process for forming a depletion type P-type MOS transistor, and it is possible to prevent a decrease in production efficiency without prolonging the manufacturing period.

Embodiment 2.
In the second embodiment, a modification of the configuration of the voltage drop circuit 109A forming the backflow prevention control circuit 111A will be described.

FIG. 5 is a diagram showing the configuration of a regulator circuit 100A including a backflow prevention circuit according to the second embodiment. The voltage drop circuit 109A of the backflow prevention control circuit 111A of FIG. Differs from drop circuit 109 . Specifically, the source S of the P-type MOS transistor MP6 is connected to the drain D of the P-type MOS transistor MP3. The drain D of the P-type MOS transistor MP6 is connected to its own gate G and to the source S of the P-type MOS transistor MP3. Therefore, the P-type MOS transistor MP6 is also a diode-connected transistor. 5 are otherwise the same as those in FIG. 1, the same or corresponding parts are denoted by the same reference numerals and the description thereof will not be repeated.

Next, the operation of the regulator circuit 100A of FIG. 5 will be described. Since the operation of regulator circuit 100A when no backflow occurs in output circuit 103 is the same as in the first embodiment, description thereof will not be repeated.

In the first embodiment, the reverse current generation condition of the output circuit 103 is described as the case where the voltage difference between the output voltage VO and the supply voltage VI becomes larger than the forward voltage of the parasitic diode D1 of the output transistor MP1. However, in this case, it should be noted that the forward voltage of the parasitic diode D1 of the output transistor MP1 is limited to a case where it is smaller than the absolute value of the threshold voltage of the output transistor MP1. When the forward voltage of the parasitic diode D1 of the output transistor MP1 that constitutes the output circuit 103 is larger than the absolute value of the threshold voltage of the output transistor MP1, before the reverse current through the parasitic diode D1 occurs, the output transistor Since the gate-source voltage of MP1 becomes equal to or higher than the absolute value of the threshold voltage, the output transistor MP1 is turned on. As a result, a reverse current flows between the source S and the drain D of the output transistor MP1.

Here, in the voltage drop circuit 109A of FIG. 5, the P-type MOS transistor MP3 and the P-type MOS transistor MP6 are connected in parallel. Therefore, the forward voltage of the parasitic diode D3 of the P-type MOS transistor MP3 and the absolute value of the threshold voltage between the gate and source of the P-type MOS transistor MP6 are compared, and the transistor having the smaller voltage is used. current path is enabled. Therefore, the formula described in Embodiment 1 is modified as follows.

First, equations (3) and (4) representing the conditions for the generation of backflow are expressed as ,
VO−|VGSP1(th)|>VI (3A)
VO−|VGSP1(th)|−VGSP5>VI−VGSP5 (4A)
is rewritten to

When |VGSP1(th)|<Vfd1, the source voltage VLV2' of the P-type MOS transistor MP4 is obtained using the gate-source voltage VGSP6 of the P-type MOS transistor MP6 as follows:
VLV2'=VO-VGSP6 (6A)
is represented by Furthermore, the condition for turning on the P-type MOS transistor MP4 constituting the comparison circuit 110 is
VLV2′−VLV1>|VGSP4(th)| …(7A)
is represented by By substituting VLV1 of the above formula (5) and VLV2′ of the formula (6A) into the above formula (7A),
VO−VGSP6−VI+VGSP5>|VGSP4(th)| …(8A)
is obtained. By transforming the above formula (8A),
VO−VGSP6−|VGSP4(th)|>VI−VGSP5 (9A)
is obtained.

Here, the absolute value of the threshold voltage VGSP1(th) of the output transistor MP1 in the above equation (4A) is equal to the gate-source voltage VGSP6 of the P-type MOS transistor MP6 in the above equation (9A). , and the transistor size of the P-type MOS transistor MP6. Furthermore, the transistor size and the current values of constant current sources 105 and 106 are adjusted so that the gate-source voltage VGSP5 of P-type MOS transistor MP5 and the absolute value of threshold voltage VGSP4(th) of P-type MOS transistor MP4 are equal. set. As a result, the above formula (9A) becomes equivalent to the backflow occurrence conditional formula (4A).

As described above, according to the configuration of the backflow prevention control circuit 111A in FIG. 5, the absolute value of the threshold voltage of the output transistor MP1 becomes smaller than the forward voltage of the parasitic diode D1 of the output transistor MP1 that constitutes the output circuit 103. Even in such a case, the backflow generation condition can be determined with high accuracy.

Embodiment 3.
FIG. 6 is a diagram showing the configuration of a regulator circuit 100B having a backflow prevention circuit according to the third embodiment. The backflow prevention control circuit 111B of FIG. 6 differs from the backflow prevention control circuit 111 of FIG. . The current mirror circuit 112 includes N-type MOS transistors MN1, MN2 and MN3 (fifth to seventh field effect transistors). N-type MOS transistor MN2 corresponds to constant current source 106, and N-type MOS transistor MN3 corresponds to constant current source 105. FIG.

The connection of each component described above will be described. Constant current source 107 and N-type MOS transistor MN1 are connected in series between input node NIN and ground node GND in this order. The gate G of the N-type MOS transistor MN1 is connected to its own drain D and also to the gates G of the N-type MOS transistors MN2 and MN3. Each source S of the N-type MOS transistors MN1, MN2, MN3 is connected to a common ground node GND. The drain D of the N-type MOS transistor MN2 is connected to the drain D of the P-type MOS transistor MP5 forming the voltage drop circuit . The drain D of the N-type MOS transistor MN3 is connected to the drain D of the P-type MOS transistor MP4 forming the comparison circuit 110. FIG.

6 are the same as those in FIG. 1, so the same or corresponding parts are denoted by the same reference numerals and the description thereof will not be repeated.

Next, operation of the regulator circuit 100B of FIG. 6 will be described. Operations other than constant current source 107 and current mirror circuit 112 forming backflow prevention control circuit 111B are the same as those in the first embodiment, and description thereof will not be repeated.

A current generated by constant current source 107 is input to N-type MOS transistor MN1 of current mirror circuit 112 . The current flowing through N-type MOS transistor MN1 is copied to N-type MOS transistor MN2 and N-type MOS transistor MN3. Here, by configuring the N-type MOS transistors MN2 and MN3 with the same size, the currents flowing through the N-type MOS transistors MN2 and MN3 can be made equal.

When both the P-type transistor MP5 forming the voltage drop circuit 108 and the P-type MOS transistor MP4 forming the comparison circuit 110 operate in the saturation region, the gate-source voltage of the P-type MOS transistor is equal to the drain current. Proportional to the square root. Therefore, in order to equalize the gate-source voltages of the P-type MOS transistors MP4 and MP5, it is necessary to equalize the sizes of both transistors and to equalize the drain currents of both transistors. According to the configuration of the backflow prevention control circuit 111B in FIG. 6, the same drain current can be supplied from the current mirror circuit 112 to the P-type MOS transistors MP4 and MP5.

Further, when the transistor sizes of the P-type MOS transistors MP4 and MP5 are different, by making the transistor size ratio of the N-type transistors MN1 to MN3 in the current mirror circuit 112 different from each other, an arbitrary drain current can be applied to the P-type MOS transistor MP4. and MP5. This allows the gate-source voltages of the P-type MOS transistors MP4 and MP5 to be equal to each other.

As described above, the same effect as in the case of the first embodiment can be achieved. Note that the current mirror circuit 112 is not limited to the configuration shown in FIG. For example, the current mirror circuit 112 may be composed of a cascode current mirror circuit in order to improve the accuracy of the output current.

Embodiment 4.
FIG. 7 is a diagram showing the configuration of a regulator circuit including a backflow prevention circuit according to the fourth embodiment. 100C of the fourth embodiment is a combination of the second and third embodiments. That is, in the backflow prevention control circuit 111C of FIG. 7, the voltage drop circuit 109A differs from the voltage drop circuit 109 of FIG. 6 in that the voltage drop circuit 109A further includes a P-type MOS transistor MP6 connected in anti-parallel with the P-type MOS transistor MP3.

In regulator circuit 100C of FIG. 7, the operations and effects of constant current source 107 and current mirror circuit 112 are the same as in regulator circuit 100B of FIG. Operations and effects other than the constant current source 107 and the current mirror circuit 112 are the same as those of the regulator circuit 100A of FIG. Therefore, the description will not be repeated for either case.

The embodiments disclosed this time should be considered as examples and not restrictive in all respects. The scope of this application is indicated by the scope of claims rather than the above description, and is intended to include all changes within the meaning and scope of equivalence to the scope of claims.

100, 100A, 100B, 100C regulator circuit, 101 constant voltage source, 102 error amplifier, 103 output circuit, 104 voltage dividing circuit, 105 second constant current source, 106 first constant current source, 107 constant current source, 108 first voltage drop circuit 109, 109A second voltage drop circuit 110 comparison circuit 111, 111A, 111B, 111C backflow prevention control circuit 112 current mirror circuit 120, 120A, 120B, 120C backflow prevention circuit C1 Output capacitance D1 to D5 Parasitic diode GND Ground node I0 Reference current I1 First constant current I2 Second constant current VLV1 First voltage VLV2 Second voltage MN1 Transistor MN1 N-type MOS transistor (fifth field effect transistor), MN2 N-type MOS transistor (sixth field effect transistor), MN3 N-type MOS transistor (seventh field effect transistor), MP1 output transistor, MP2 backflow prevention transistor, MP3 P type MOS transistor (first field effect transistor), MP4 P-type MOS transistor (fourth field effect transistor), MP5 P-type MOS transistor (third field effect transistor), MP6 P-type MOS transistor (second field effect transistor) effect transistor), N2, N4, N5 connection node, N3 node, NIN input node, NOUT output node, R1, R2 resistive element, VO output voltage, VI supply voltage.

Claims (7)

an input node for receiving an external supply voltage;
an output node for outputting an output voltage;
a reference node for receiving a reference voltage;
an output transistor connected between the input node and the output node;
an error amplifier that controls the amount of current passing through the output transistor based on the voltage difference between the reference voltage and the output voltage or its divided voltage;
a backflow prevention transistor connected in series with the output transistor between the input node and the output node;
a first constant current source that generates a first constant current;
a second constant current source that generates a second constant current;
A first voltage, which is connected in series with the first constant current source between the input node and the reference node, is obtained by subtracting a first voltage drop corresponding to the first constant current from the supply voltage. a first voltage drop circuit to generate;
a second voltage drop generating a second voltage obtained by subtracting from the output voltage a second voltage drop equal to a voltage drop across the output transistor when a reverse current flows from the output node to the input node; a circuit;
The second constant current source and the second voltage drop circuit are connected in series between the output node and the reference node, and the differential voltage between the second voltage and the first voltage is reduced to the a comparison circuit that compares with a threshold corresponding to the second constant current,
The backflow prevention transistor is open/close controlled based on the comparison result of the comparison circuit,
A regulator circuit, wherein values of the first constant current and the second constant current are determined such that the first voltage drop and the threshold are equal. the output transistor is a field effect transistor having a parasitic diode whose forward direction is from the output node to the input node;
2. The regulator circuit according to claim 1, wherein said backflow prevention transistor is a field effect transistor having a parasitic diode whose forward direction is from said input node to said output node. the second voltage drop circuit includes a diode-connected first field effect transistor;
the first field effect transistor has a parasitic diode having a forward direction from the output node to the reference node;
3. The regulator circuit of claim 2, wherein the forward voltage of the parasitic diode of the first field effect transistor is equal to the forward voltage of the parasitic diode of the output transistor. the second voltage drop circuit further includes a diode-connected second field effect transistor;
the second field effect transistor has a parasitic diode connected in parallel with the first field effect transistor and having a forward direction from the reference node to the output node;
When the threshold voltage of the output transistor is greater than or equal to the forward voltage of the parasitic diode of the output transistor, the second drop voltage is equal to the forward voltage of the parasitic diode of the first field effect transistor. ,
wherein the second voltage drop is equal to the gate-to-source voltage of the second field effect transistor when the threshold voltage of the output transistor is less than the forward voltage of the parasitic diode of the output transistor; Item 4. The regulator circuit according to item 3. the first voltage drop circuit includes a diode-connected third field effect transistor connected between the input node and the first constant current source;
the third field effect transistor has a parasitic diode having a forward direction from the reference node to the input node;
5. The regulator circuit according to claim 3, wherein said first drop voltage is equal to the gate-source voltage of said third field effect transistor. the comparison circuit includes a fourth field effect transistor connected between the second voltage drop circuit and the second constant current source;
a gate of the fourth field effect transistor is connected to a connection node between the third field effect transistor and the first constant current source;
a connection node between the fourth field effect transistor and the second constant current source is connected to the gate of the backflow prevention transistor;
6. The regulator circuit of claim 5, wherein said threshold is equal to the absolute value of the threshold voltage of said fourth field effect transistor. the regulator circuit further comprising a fifth field effect transistor receiving a reference current;
The first constant current source includes a sixth field effect transistor forming a current mirror with the fifth field effect transistor,
the second constant current source includes a seventh field effect transistor forming a current mirror with the fifth field effect transistor,
A transistor size of each of the fifth field effect transistor, the sixth field effect transistor, and the seventh field effect transistor is determined according to the values of the first constant current and the second constant current. The regulator circuit according to any one of claims 1 to 6, wherein the regulator circuit is

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