JP2023103840A - Surface processing method for semiconductor wafer - Google Patents

Abstract

To realize reduction of a process-affected layer in a planarizing process method of a surface of a semiconductor wafer using anodic oxidation.SOLUTION: A surface processing method for planarizing a surface (W1) for a semiconductor wafer (W) includes: a first type of planarization process in which an oxide is generated on the surface by anodic oxidation and such an oxide is removed, and a second type of planarization process different from the first type of planarization process. The first type of planarization process is performed under processing conditions where an oxidation rate by anodic oxidation is equal to or greater than an oxide removal rate. The second type of planarization process is a process which is performed before the first type of planarization process to remove an oxide generated on the surface by the anodic oxidation under processing conditions where the oxide removal rate is equal to or greater than the oxidation rate. Alternatively, the second type of planarization process is a process which is performed after the first type of planarization process to further planarize the surface than the first type of planarization process.SELECTED DRAWING: Figure 1

Description

The present invention relates to a surface processing method for a semiconductor wafer.

Patent Literature 1 discloses a polishing method using anodization. In such a polishing method, the anodizing process and the polishing process are performed simultaneously or alternately in the presence of an electrolytic solution, and the surface of the workpiece is polished under the condition that the polishing rate by the polishing process is higher than the oxidation rate by the anodizing process. polishing. In the anodizing process, a voltage is applied using the workpiece as an anode to oxidize the surface of the workpiece. In the polishing process, a fixed-abrasive polishing body in which abrasive grains having a predetermined hardness and grain size are fixed to a base material is used to polish and remove oxides formed on the surface of the workpiece. Specifically, in this polishing method, a high-speed polishing process and a low-speed polishing process are sequentially performed. The high speed polishing process has a high material removal rate from the workpiece, removing even scratches and deep subsurface damage introduced during manufacturing. The high speed polishing process also includes damage introducing means for introducing uniform shallow damage under the surface of the workpiece. The slow polish process has a low material removal rate from the workpiece and planarizes by removing oxides resulting from shallow damage. As a result, it is possible to realize a high-speed polishing process that can replace the grinding process and the lapping process used in the process of slicing an ingot into wafers.

JP 2021-27359 A

The lead time in the semiconductor wafer manufacturing process is rate-determined by the processing time in surface flattening processing (that is, grinding and polishing). Such processing time depends on the amount of the work-affected layer, which is the machining allowance. A work-affected layer is a surface layer having crystal distortion, scratches, etc., caused by slicing or grinding. Therefore, in order to shorten the lead time in the semiconductor wafer manufacturing process by speeding up the surface flattening process, it is necessary to reduce the process-affected layer. In this regard, the polishing method described in Patent Literature 1 introduces uniform shallow damage under the surface of the workpiece in the high-speed polishing process, and such "shallow damage" corresponds to a work-affected layer. That is, the polishing method described in Patent Document 1 rather increases the work-affected layer in the high-speed polishing step. In this regard, there has been no proposal for a surface flattening processing method focusing on reduction of a work-affected layer.

The present invention has been made in view of the circumstances exemplified above. That is, the present invention provides a technique for reducing a process-affected layer in, for example, a method for flattening the surface of a semiconductor wafer using anodization.

The surface processing method according to claim 1 is a method for planarizing a surface (W1) of a semiconductor wafer (W),
a first type of planarization process in which an oxide is formed on the surface by anodization and the oxide is removed;
a second type of planarization processing different from the first type of planarization processing;
has
The first type of planarization processing is performed under processing conditions such that the oxidation rate by anodization is equal to or higher than the oxide removal rate,
The second type of flattening process is
A process performed before the first type planarization process to remove oxides generated on the surface by anodic oxidation under processing conditions where the oxide removal rate is equal to or higher than the oxidation rate, or the first type planarization process It is a processing for flattening the surface more than the flattening processing of the first type, which is performed later.
A surface processing method according to claim 6 is a method for planarizing a surface (W1) of a semiconductor wafer (W),
a first type of planarization process in which an oxide is formed on the surface by anodization and the oxide is removed;
a second type of planarization processing different from the first type of planarization processing;
has
As the first type of flattening process,
A surface oxidation process for generating an oxide on the surface by anodization after the grinding process as the second type flattening process;
an oxide removal process for removing oxides generated by the surface oxidation process;
I do.
A surface processing method according to claim 7 is a method for planarizing a surface (W1) of a semiconductor wafer (W),
a first type of planarization process in which an oxide is formed on the surface by anodization and the oxide is removed;
a second type of planarization processing different from the first type of planarization processing;
has
As the first type of flattening process,
A surface oxidation process for generating an oxide on the surface by anodization after the polishing process as the second type planarization process;
an oxide removal process for removing oxides generated by the surface oxidation process;
I do.

In addition, in each column of the application documents, each element may be given a reference sign with parentheses. In this case, the reference numerals indicate only one example of the corresponding relationship between the same element and the specific configuration described in the embodiment described later. Therefore, the present invention is not limited in any way by the description of the reference numerals.

1 is a schematic configuration diagram of a surface processing apparatus for carrying out a surface processing method according to an embodiment of the present invention; FIG. FIG. 2 is a diagram showing an example of a schematic manufacturing process of a semiconductor wafer that can be realized by using the surface processing apparatus shown in FIG. 1; 2 is a diagram showing another example of a schematic manufacturing process of a semiconductor wafer that can be realized by using the surface processing apparatus shown in FIG. 1; FIG. FIG. 4 is a diagram showing still another example of a schematic manufacturing process of a semiconductor wafer that can be realized by using the surface processing apparatus shown in FIG. 1; FIG. 4 is a diagram showing still another example of a schematic manufacturing process of a semiconductor wafer that can be realized by using the surface processing apparatus shown in FIG. 1; FIG. 4 is a diagram showing still another example of a schematic manufacturing process of a semiconductor wafer that can be realized by using the surface processing apparatus shown in FIG. 1; FIG. 4 is a diagram showing still another example of a schematic manufacturing process of a semiconductor wafer that can be realized by using the surface processing apparatus shown in FIG. 1; FIG. 4 is a diagram showing another example of flattening processing of a semiconductor wafer that can be realized by using the surface processing apparatus shown in FIG. 1; FIG. 8 is a diagram showing another example of flattening processing of a semiconductor wafer that can be realized by using the surface processing apparatus shown in FIG. 1;

(embodiment)
BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention will be described based on the drawings. It should be noted that if various modifications applicable to one embodiment are inserted in the middle of a series of explanations related to the embodiment, there is a risk that the understanding of the embodiment will be hindered. For this reason, the modification will not be inserted in the middle of the series of descriptions regarding the embodiment, and will be described collectively after that.

(Surface processing equipment)
Referring to FIG. 1, a surface processing apparatus 1 is a processing apparatus that uses a semiconductor wafer W, which is a SiC wafer, as a work piece. It is configured to be polishable. The "principal surface" is a surface orthogonal to the thickness direction of a layered or plate-like material, and is also referred to as a "plate surface". Specifically, in the present embodiment, the surface processing apparatus 1 is configured to be capable of polishing or grinding the surface W1 of the semiconductor wafer W to be processed using anodization. That is, the surface processing apparatus 1 has a configuration as an ECMP apparatus or an ECMG apparatus. ECMP is an abbreviation for Electro-Chemical Mechanical Polishing. ECMG is an abbreviation for Electro-Chemical Mechanical Grinding.

A surface processing apparatus 1 includes a container 2 , a surface processing pad 3 , a driving device 4 and a power supply device 5 . As will be described later, FIG. 1 and the following description using this are simplified solely for describing the schematic configuration and function of the surface processing apparatus 1 according to the present embodiment. , does not necessarily match the specific device configuration that is actually manufactured and sold. Also, for simplification of explanation, a right-handed XYZ coordinate system is set as illustrated. In the present embodiment, the Z-axis positive direction indicates the vertically upward direction, that is, the direction opposite to the direction of weight action. Both the X-axis direction and the Y-axis direction, which are orthogonal to each other, indicate the horizontal direction. Hereinafter, for convenience of explanation, the Z-axis positive direction side corresponding to vertically upward may be simply referred to as "upper", and the reverse may simply be referred to as "lower".

The container 2 is formed in the shape of a bathtub that opens upward. The container 2 is configured to hold the semiconductor wafer W at its bottom and accommodate the semiconductor wafer W while being immersed in the electrolytic solution S containing no etchant component. The etchant component is a component that constitutes a dissolving solution that has the ability to dissolve the oxide film (that is, SiC oxide that is formed in the form of a film) produced on the surface to be processed W1 by anodization (i.e., hydrofluoric acid, etc.). ). The electrolytic solution S is, for example, an aqueous solution of sodium chloride, potassium chloride, sodium nitrate, or the like. A surface treatment pad 3 and a drive device 4 are arranged above the container 2 . The container 2, the surface processing pad 3, and the driving device 4 are provided so as to be vertically movable relative to each other by an elevating mechanism (not shown). In addition, the container 2, the surface processing pad 3, and the driving device 4 are relatively movable in the in-plane direction along the surface to be processed W1 (that is, the horizontal direction perpendicular to the rotation axis) by a slide mechanism (not shown). is provided.

The surface processing pad 3 has an electrode 31 and a grindstone layer 32 . The electrode 31 is a plate-shaped member made of a good conductor such as metal, and is formed of, for example, a copper plate. The grindstone layer 32 is joined to the electrode 31 . That is, the surface processing pad 3 has a structure in which the electrode 31 and the grindstone layer 32 are joined together in the thickness direction of the surface processing pad 3 . The whetstone layer 32 is formed of a whetstone (such as a diamond whetstone) that is an abrasive or an abrasive. The surface processing pad 3 is provided so that the grindstone layer 32 faces the processing surface W1 of the semiconductor wafer W with the electrolytic solution S interposed therebetween. The surface processing pad 3 is formed on the surface to be processed W1 by anodic oxidation by driving the driving device 4 to rotate while the grindstone layer 32 is disposed opposite to the surface to be processed W1 with the electrolytic solution S interposed therebetween. The oxide film is provided so that it can be selectively removed by polishing or grinding.

The driving device 4 is configured to rotationally drive the surface processing pad 3 around a rotation axis extending in the vertical direction. The power supply device 5 applies a voltage with the semiconductor wafer W as the workpiece being processed in the presence of the electrolytic solution S as an anode and the electrode 31 of the surface processing pad 3 as a cathode, thereby applying a voltage to the workpiece being processed by the grindstone layer 32 . It is arranged to pass a current for anodizing the surface W1.

(Surface processing method)
A surface processing method according to the present disclosure is a method of planarizing a surface to be processed W<b>1 , which is the surface of a semiconductor wafer W obtained from an ingot, using a surface processing apparatus 1 . The surface processing method according to this embodiment includes a first type planarization process and a second type planarization process. The first type of flattening process uses anodic oxidation under processing conditions such that an oxide film is formed on the surface W1 to be processed by anodic oxidation, and the removal of the oxide film does not overtake the formation of this oxide film. It is a flattening process. The second type of flattening processing is different from the first type of flattening processing, and is performed before or after the first type of flattening processing.

(First embodiment)
A surface processing method according to the first embodiment will be described below. In the present embodiment, the first type of flattening processing is processing for removing oxides generated on the surface to be processed W1 by anodization under processing conditions in which the oxidation rate by anodization is equal to or higher than the oxide removal rate. . Further, in the present embodiment, as the second type of planarization processing, an oxide is generated on the processing surface W1 by anodization under processing conditions in which the oxide removal rate is equal to or higher than the oxidation rate, which is performed before the first type of planarization processing. includes an anodizing grinding process (ie, ECMG process), which removes the oxidized oxide by grinding. Furthermore, the present embodiment includes, as the second type of flattening processing, a polishing processing that flattens the surface to be processed W1 more than the first type of flattening processing, which is performed after the first type of flattening processing.

FIG. 2 shows an outline of a method for manufacturing a semiconductor wafer W including a surface processing method according to this embodiment. An outline of a method for manufacturing a semiconductor wafer W, which is a SiC wafer, will be described below with reference to FIGS. 1 and 2. FIG.

As shown in FIG. 2, the method for manufacturing a semiconductor wafer W according to this embodiment includes an ingot forming process, a wafer slicing process, a grinding process, and a polishing process in this order. Further, the grinding process includes a high-speed ECMG machining process, which is a high-speed grinding process, and a finish ECMG machining process, which is a low-speed grinding process or a finish grinding process. The polishing process is a CMP process. CMP is an abbreviation for Chemical Mechanical Polishing. In order to briefly explain the contents of the present invention, the process flow chart shown in FIG. shows an overview of the series of finishing steps. Therefore, the specific process flow chart for planarizing both surfaces of the semiconductor wafer W does not match that shown in FIG. The same applies to other embodiments after FIG. Details such as beveling, reversing, and transporting of the outer edge of the semiconductor wafer W, which are actually necessary for the manufacturing process of the semiconductor wafer W but have little relevance to the content of the present invention, will not be described here. Since the specification would be redundant, the description is omitted in this specification.

The ingot forming step is a step of processing a crystal-grown single-crystal SiC mass into a columnar ingot. The wafer slicing step is a step of obtaining a semiconductor wafer W, which is a thin disc-shaped SiC wafer, from an ingot by a well-known wafer slicing method such as wire slicing or laser slicing. The grinding process is a first-stage flattening process for the surface W1 of the semiconductor wafer W to be processed, which is performed prior to the subsequent polishing process. As a result, the thickness of the semiconductor wafer W is adjusted within a predetermined range, and "undulations" and relatively large irregularities generated on the surface W1 to be processed in the wafer slicing process are removed. The polishing process is the second stage, that is, the final stage of the planarization process for the surface W1 of the semiconductor wafer W to be processed, which is performed after the grinding process. As a result, the surface W1 to be processed of the semiconductor wafer W is finished to an epi-ready mirror surface, which is a preferable surface condition for the semiconductor device manufacturing process.

The lead time in the manufacturing process of the semiconductor wafer W is rate-determined by the processing time in surface flattening processing (that is, grinding and polishing). Here, in the wafer slicing process and the grinding process, a work-affected layer is generated on the surface W1 of the semiconductor wafer W to be processed. The work-affected layer includes damage such as scratches, crystal strain, cracks, residual stress, etc. on the SiC surface and its neighboring regions. Such a work-affected layer becomes a "cutting allowance" in a grinding process or a polishing process. Therefore, in order to shorten the lead time in the manufacturing process of the semiconductor wafer W, it is necessary to reduce the work-affected layer.

Therefore, in the present embodiment, ECMG processing, which is damage-free or low-damage grinding, is employed in the grinding process. ECMG processing is an anodizing grinding process in which oxides generated on the surface W1 to be processed by anodization are selectively removed by grinding. Specifically, in the ECMG processing, in the presence of the electrolytic solution S, current is applied with the semiconductor wafer W as the anode and the electrode 31 as the cathode, and the surface processing pad 3 is driven to rotate. The surface W1 is ground while being anodized. Anodizing and grinding can be done simultaneously or alternately. A comparatively soft oxide is generated on the surface to be processed W1 by anodization, and the generated oxide is selectively removed by grinding, thereby satisfactorily removing the work-affected layer generated in the wafer slicing process while grinding. It is possible to satisfactorily suppress the generation of a work-affected layer due to In particular, in the present embodiment, ECMG processing is performed under processing conditions such that the oxidation rate by anodization is equal to or higher than the oxide removal rate by grinding. As a result, the surface W1 to be processed after the ECMG processing has no oxide film, or a small amount of the oxide film remains. Even if a small amount of the oxide film remains on the surface W1 to be processed, the oxide film is relatively soft and can be easily removed in a later step.

As shown in FIG. 2 , in this embodiment, as grinding processes using ECMG, high-speed ECMG processing, which is the first stage of high-speed grinding, and finish ECMG processing, which is the second stage of finish grinding and High-speed ECMG processing, which is rough grinding, uses an abrasive material having a hardness higher than that of the semiconductor wafer W before finishing ECMG processing, which is finish grinding, so that the surface is polished under processing conditions in which the grinding speed is equal to or higher than the oxidation speed. It is a surface flattening process that grinds. Finish ECMG processing is finish grinding processing performed between high-speed ECMG processing and polishing processing under processing conditions in which the oxidation speed is equal to or higher than the grinding speed. Further, in this embodiment, CMP processing is used as the polishing processing for polishing the surface W1 to be processed, which is a post-process of the finishing ECMG processing. Finishing ECMG processing corresponds to "first type planarization processing", and high-speed ECMG processing and polishing processing correspond to "second type planarization processing". According to the present embodiment, the surface to be processed W1 is roughly ground at relatively high speed with low damage by high-speed ECMG processing. After that, the surface to be processed W1 is finish-ground by finishing ECMG processing so as to be damage-free or extremely low-damage. At this time, on the surface W1 to be processed, the residual work-affected layer is suppressed satisfactorily. Then, the surface to be processed W1 is finished to a good epi-ready surface by the subsequent polishing. In this way, by using three wafer flattening processes, it is possible to achieve both high-speed flattening and good quality. The high-speed ECMG machining and the finish ECMG machining may use a common surface machining device 1 or may use different surface machining devices 1 . That is, for example, a common surface processing apparatus 1 may be used, and the surface processing pad 3 may be exchanged between high-speed ECMG processing and finish ECMG processing. Alternatively, the semiconductor wafer W may be transferred from the surface processing apparatus 1 for high-speed ECMG processing to the surface processing apparatus 1 for finish ECMG processing.

In high-speed ECMG processing and finish ECMG processing, a grindstone layer 32 as an abrasive material in the surface processing pad 3 is arranged opposite to the surface W1 to be processed, and oxides generated on the surface W1 to be processed by anodization are selectively removed by the grindstone layer 32. It is a process that removes to Here, the grindstone layer 32 in high-speed ECMG and finish ECMG processing can be formed of well-known grindstone materials. When the grindstone layer 32 for high-speed ECMG processing and finish ECMG processing are both made of a diamond grindstone, the grain size of the grindstone layer 32 for finish ECMG processing can be made equal to or greater than the grain size of the grindstone layer 32 for high-speed ECMG processing. Specifically, for example, the grit of the grindstone layer 32 in the finishing ECMG processing is selected within the range of No. 400 to No. 30000, and the combination can be appropriately selected according to the object to be processed. For example, using a diamond grindstone of No. 30000 as the grindstone layer 32, high-speed ECMG processing is performed at a processing speed of 1.6 μm/min, and then finish ECMG processing is performed at a processing speed of 0.5 μm/min. It was flattened to TTV=3.7 μm. TTV is an abbreviation for Total Thickness Variation. At this time, the surface W1 to be processed after processing by the high-speed ECMG processing had a surface roughness Ra of 1.0 nm, and a work-affected layer of about 100 to 500 nm remained. On the other hand, the processing time of the finish ECMG processing is 1 minute, and the processed surface W1 after the finish ECMG processing is hardly confirmed to have a residual work-affected layer, and the processed surface W1 has an oxide film of about 10 to 20 nm. occurred, but no distortion of the atomic arrangement occurred. The surface W1 to be processed after processing by the finishing ECMG processing had a surface roughness Ra of 3.2 nm due to the formation of an oxide film, and the surface roughness was lower than after the high-speed ECMG processing. By satisfactorily removing the film, it was possible to satisfactorily planarize the substrate.

(Second embodiment)
Other embodiments will be described below. In addition, in the following description of other embodiments, mainly the parts different from the first embodiment will be described. Moreover, in the first embodiment and other embodiments, the same or equivalent portions are denoted by the same reference numerals. Therefore, in the following description of the other embodiments, the description in the first embodiment is appropriately used for the components denoted by the same reference numerals as in the first embodiment, unless there is a technical contradiction or special additional description. can be

This embodiment includes, as the second type of planarization processing, anodizing grinding processing (that is, ECMG processing) under processing conditions in which the oxide removal rate is equal to or higher than the oxidation rate, which is performed before the first type of planarization processing. . Further, the second type planarization processing includes polishing processing performed after the first type planarization processing.

FIG. 3 shows an outline of a method for manufacturing a semiconductor wafer W including a surface processing method according to this embodiment. In this embodiment, the polishing process in the first embodiment is replaced with the ECMP process from the CMP process. The ECMP process is an anodizing polishing process that selectively removes oxides generated on the surface W1 to be processed by anodizing by polishing. Anodizing and polishing can be performed simultaneously or alternately. In the ECMP process, a soft grindstone containing relatively soft abrasive grains (for example, ceria abrasive grains) may be used as the grindstone layer 32 . According to this embodiment, by replacing the CMP process with the ECMP process, which is a less damaging polishing process, high-speed and damage-free polishing of the surface to be processed W1 can be realized. Specifically, for example, a No. 30000 diamond grindstone is used as the grindstone layer 32, high-speed ECMG processing is performed at a processing speed of 1.6 μm/min, and then finish ECMG processing is performed at a processing speed of 0.5 μm/min. rice field. Subsequently, using a grindstone layer 32 containing ceria abrasive grains, ECMP processing was performed at a processing speed of 0.2 μm/min. The TTV of the semiconductor wafer W after processing was 3.7 μm, and the processing time of the ECMP processing was 2.5 minutes. The surface to be processed W1 after processing had a surface roughness Ra of 0.5 nm, and no distortion of the atomic arrangement occurred. For the high-speed ECMG machining, the finish ECMG machining, and the ECMP machining, the common surface machining device 1 may be used, or different surface machining devices 1 may be used.

(Third embodiment)
FIG. 4 shows an outline of a method for manufacturing a semiconductor wafer W including a surface processing method according to this embodiment. In the present embodiment, the ECMP processing in the second embodiment is divided into two stages: a first stage of high-speed ECMP processing, that is, rough ECMP processing, and a second stage of finishing ECMP processing. The high-speed ECMP machining quickly mirror-finishes the surface W1 to be machined. The subsequent finishing ECMP process removes the work-affected layer almost completely. In this case, processing conditions are set such that the polishing speed is higher than the oxidation speed in high-speed ECMP processing, and processing conditions are set such that the polishing speed is approximately equal to the oxidation speed in rough ECMP processing. It is possible to achieve both the surface quality of the machined surface W1. The high-speed ECMP processing and the finish ECMP processing may use a common surface processing device 1 or may use different surface processing devices 1 .

(Fourth embodiment)
By reducing the number of processes and the number of devices used in the wafer flattening process, it is possible to reduce the manufacturing cost. In this regard, the method for manufacturing a semiconductor wafer W according to the present embodiment shown in FIG. 5 is obtained by replacing the polishing processing in the first to third embodiments with an oxide film removing processing using an etchant component. is. That is, in the present embodiment, the first type of planarization processing is finish ECMG processing performed under processing conditions in which the oxidation rate is equal to or higher than the grinding speed, and the second type of planarization processing is performed after the finish ECMG processing. , is an oxide film removal process that is different from grinding and polishing. As a result, it is possible to form an epi-ready work surface W1 on which there is almost no residual work-affected layer at low cost.

(Fifth embodiment)
In the manufacturing method of the semiconductor wafer W according to the present embodiment shown in FIGS. 6 and 7, the two-step ECMG processing in the second embodiment is integrated into one-step ECMG processing corresponding to the finishing ECMG processing. It is. That is, in the present embodiment, the first type of planarization processing is ECMG processing performed under processing conditions in which the oxidation rate is equal to or higher than the grinding speed, and the second type of planarization processing is polishing processing performed after ECMG processing. That is, ECMP processing or CMP processing. As a result, it is possible to form an epi-ready work surface W1 on which there is almost no residual work-affected layer at low cost. In the example of FIG. 6, the ECMG processing and the ECMP processing may use a common surface processing device 1 or may use different surface processing devices 1 .

(Sixth embodiment)
The manufacturing method according to the first embodiment shown in FIG. 2 includes high-speed ECMG processing, which is rough grinding, and finish ECMG processing, which is finish grinding, as grinding processes. In the finishing ECMG processing, the processing conditions are set so that the oxidation speed is equal to or higher than the grinding speed. However, it may be difficult to adjust the oxidation rate and the oxide removal rate, that is, the grinding rate, in ECMG processing depending on the type of the semiconductor wafer W, which is the workpiece, and the type of the surface processing pad 3 .

Therefore, in such a case, only anodic oxidation is performed after the completion of grinding by ECMG processing as rough grinding processing, leaving a fine oxide film on the surface W1 to be processed, and polishing and cleaning in the subsequent process. By removing the film, it is possible to form the surface to be processed W1 on which there is almost no residual work-affected layer. FIG. 8 shows an example of such a surface processing method. That is, in the present embodiment, after the grinding process as the second type of flattening process, the first type of planarizing process is anodized to form an oxide on the surface W1 to be processed by anodizing, which is surface oxidation. and an oxide removing process for removing oxides generated on the surface W1 to be processed by the surface oxidation process. The surface oxidation process can be performed by the surface processing apparatus 1 by using the surface processing pad 3 that does not have the grindstone layer 32 . Alternatively, the surface processing pad 3 may not be rotationally driven by the driving device 4 during the surface oxidation processing. The oxide removal process is a surface flattening process other than grinding, and may be, for example, polishing, oxide dissolution, cleaning, or the like. As a result, it is possible to reduce the work-affected layer on the surface W1 to be processed of the semiconductor wafer W to be polished. In this case, the relationship between the oxidation rate in the surface oxidation process and the oxide removal rate in the subsequent oxide removal process may be such that oxidation rate≧oxide removal rate, but there is no particular limitation. Also, ECMG machining as a rough grinding process can be replaced by other types of grinding processes.

Similarly, the manufacturing method according to the third embodiment shown in FIG. 4 has high-speed ECMP processing, which is rough polishing processing, and finish ECMP processing, which is finish polishing processing, as polishing processing. In this regard, it may be difficult to adjust the oxidation rate and the oxide removal rate, that is, the polishing rate, in ECMP processing depending on the type of the semiconductor wafer W, which is the object to be processed, or the type of the surface processing pad 3 . Therefore, in such a case, only anodization is performed after the completion of polishing by ECMP processing as rough polishing processing, leaving a minute oxide film on the surface W1 to be processed, and removing the oxide film in a post-process. As a result, it is possible to form the surface to be processed W1 on which there is almost no residual work-affected layer. FIG. 9 shows an example of such a surface processing method. That is, in the present embodiment, after the polishing process as the second type planarization process, as the first type planarization process, a surface oxidation process that is an anodization process for generating an oxide on the surface by anodization, An oxide removal process is performed to remove oxides generated by the surface oxidation process. In this case, there is no particular limitation on the magnitude relationship between the oxidation rate in the surface oxidation process and the oxide removal rate in the subsequent oxide removal process. Also, the ECMP process as a rough polishing process can be replaced with other types of polishing processes.

(Summary of embodiment)
As described above, in each of the above-described embodiments, an oxide film is formed on the surface to be processed W1 by anodization, and anodization is performed under processing conditions such that the removal of the oxide film does not overtake the formation of the oxide film. At least an assisted planarization process is included. Therefore, according to each of the above-described embodiments, there is provided a technique for reducing the process-affected layer in the planarization processing method of the surface W1 to be processed of the semiconductor wafer W using anodization.

(Modification)
The present invention is not limited to the above embodiments. Therefore, the above embodiment can be modified as appropriate. A representative modified example will be described below. In the following description of the modified example, differences from the above embodiment will be mainly described. Moreover, in the above-described embodiment and modifications, the same reference numerals are given to parts that are the same or equivalent to each other. Therefore, in the description of the modification below, the description in the above embodiment can be used as appropriate for components having the same reference numerals as those in the above embodiment, unless there is a technical contradiction or special additional description.

The present invention is not limited to the specific device configurations shown in the above embodiments. That is, FIG. 1 and the following description using it are simplified solely for describing the schematic configuration and function of the surface processing apparatus 1 according to the present embodiment, and are not actually manufactured and sold. It does not necessarily match the specific device configuration provided. Specifically, for example, in the above embodiment, while the semiconductor wafer W is held on the side of the container 2, the surface processing pad 3 is rotatably held above the semiconductor wafer W. . However, the invention is not limited to such aspects. That is, a configuration is possible in which the semiconductor wafer W is held by a chuck arranged above the container 2 and rotationally driven by the driving device 4 while the surface processing pad 3 is held on the container 2 side.

The electrolytic solution S may contain an etchant component. That is, the surface processing apparatus 1 according to the present invention and the surface processing method practicable thereby selectively remove the oxide film produced by the anodization using both the etchant and the surface processing pad 3. , the surface to be processed W1 may be polished or ground.

There are no particular restrictions on the count or material of the grindstone layer 32 . That is, the count and material of the grindstone layer 32 can be appropriately selected within the range in which the effects of the present invention can be satisfactorily exhibited.

Needless to say, the elements constituting the above-described embodiments are not necessarily essential, unless explicitly stated as essential or clearly considered essential in principle. In addition, when numerical values such as the number, amount, range, etc. of a constituent element are mentioned, unless it is explicitly stated that it is particularly essential, or when it is clearly limited to a specific numerical value in principle, the specific numerical value The present invention is not limited to Similarly, when the shape, direction, positional relationship, etc. of the constituent elements, etc. are mentioned, unless it is explicitly stated that it is particularly essential, or when it is limited to a specific shape, direction, positional relationship, etc. in principle , the shape, direction, positional relationship, etc., of which the present invention is not limited.

Modifications are also not limited to the above examples. That is, for example, a plurality of embodiments other than those exemplified above can be combined with each other as long as they are not technically inconsistent. Likewise, multiple variants may be combined with each other unless technically inconsistent.

REFERENCE SIGNS LIST 1 surface processing device 2 container 3 surface processing pad 31 electrode 32 grindstone layer 4 drive device 5 power supply device S electrolyte solution W semiconductor wafer W1 surface to be processed (surface)

Claims (8)

A surface processing method for planarizing a surface (W1) of a semiconductor wafer (W),
a first type of planarization process in which an oxide is formed on the surface by anodization and the oxide is removed;
a second type of planarization processing different from the first type of planarization processing;
has
The first type of planarization processing is performed under processing conditions such that the oxidation rate by anodization is equal to or higher than the oxide removal rate,
The second type of flattening process is
A process performed before the first type planarization process to remove oxides generated on the surface by anodic oxidation under processing conditions where the oxide removal rate is equal to or higher than the oxidation rate, or the first type planarization process A process to flatten the surface further than the first type flattening process performed later,
surface treatment method. The first type of flattening process is an anodizing grinding process performed under processing conditions in which the oxidation speed is equal to or higher than the grinding speed,
The second type planarization process is a polishing process or an oxide film removal process performed after the first type planarization process,
The surface processing method according to claim 1. As the second type of flattening process,
A high-speed grinding process in which, before the first type of flattening process, the surface is ground under processing conditions in which the grinding speed is equal to or higher than the oxidation speed by using an abrasive material having a hardness higher than that of the semiconductor wafer;
A polishing process for polishing the surface after the first type of flattening process;
and
The first type of flattening process is a finish grinding process performed under processing conditions in which the oxidation rate is equal to or higher than the grinding rate between the high-speed grinding process and the polishing process.
The surface processing method according to claim 1. The polishing process is an anodizing polishing process that selectively removes oxides generated on the surface by anodizing by polishing.
The surface processing method according to claim 3. The high-speed grinding process and the finish grinding process are performed by arranging the grindstone layer in the surface processing pad (3) having the grindstone layer (32) as the abrasive so as to face the surface, and anodic oxidation generated on the surface. A process for selectively removing an object with the grindstone layer,
The grindstone layer in the high-speed grinding process and the finish grinding process is formed of a diamond grindstone,
The number of the grindstone layer in the finish grinding process is equal to or higher than the number of the grindstone layer in the high-speed grinding process.
The surface processing method according to claim 3 or 4. A surface processing method for planarizing a surface (W1) of a semiconductor wafer (W),
a first type of planarization process in which an oxide is formed on the surface by anodization and the oxide is removed;
a second type of planarization processing different from the first type of planarization processing;
has
As the first type of flattening process,
A surface oxidation process for generating an oxide on the surface by anodization after the grinding process as the second type flattening process;
an oxide removal process for removing oxides generated by the surface oxidation process;
I do,
surface treatment method. A surface processing method for planarizing a surface (W1) of a semiconductor wafer (W),
a first type of planarization process in which an oxide is formed on the surface by anodization and the oxide is removed;
a second type of planarization processing different from the first type of planarization processing;
has
As the first type of flattening process,
A surface oxidation process for generating an oxide on the surface by anodization after the polishing process as the second type planarization process;
an oxide removal process for removing oxides generated by the surface oxidation process;
I do,
surface treatment method. The semiconductor wafer is a SiC wafer,
The surface processing method according to any one of claims 1 to 7.

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